Display substrate and preparation method therefor, and display device

Abstract

A display substrate and a preparation method therefor, and a display device. The display substrate has a display area (AA) and a border area (BB). The display substrate comprises a base (10), a circuit structure layer (20) and a first electrode layer (204) that are sequentially arranged in a first direction, the first direction being perpendicular to the base (10), wherein the edge of the first electrode layer (204) away from the display area (AA) is located on the side of a wiring structure (202) away from the base (10) and is located between an isolation dam (203) and a peripheral circuit structure (201), or the edge of the first electrode layer (204) away from the display area (AA) is located on the end face of the isolation dam (203) away from the base (10).

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the field of display devices, and in particular, to a display substrate, a preparation method thereof, and a display device. BACKGROUND

[0002] Organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become mainstream products in the current display field.

[0003] A tandem OLED display substrate is a stacked device formed by connecting multiple stacked light emitting layers together through a connecting layer. Currently, there is a peeling-off situation between the wire and the connecting electrode, which affects the yield of the product.

[0004] SUMMARY

[0005] The following is a summary of the subject matter detailed herein. This summary is not intended to limit the scope of the claims.

[0006] The display substrate provided by the embodiments of the present disclosure has a display area and a frame area.

[0007] The display substrate includes a substrate, a circuit structure layer, and a first electrode layer arranged in the first direction in sequence, and the first direction is perpendicular to the substrate.

[0008] The circuit structure layer includes a peripheral circuit structure located in the frame area, a wire structure, and an isolation dam, the wire structure and the isolation dam are both located on a side of the peripheral circuit structure away from the display area, and the isolation dam is located on a side of the wire structure away from the substrate in the first direction.

[0009] The edge of the first electrode layer away from the display area is located on a side of the wire structure away from the substrate and between the isolation dam and the peripheral circuit structure, or the edge of the first electrode layer away from the display area extends to an end surface of the isolation dam away from the substrate.

[0010] The first electrode layer comprises a first edge and a second edge away from the edges of the display area, and the peripheral circuit structure comprises a first side and a second side away from the edges of the display area;

[0011] The first edge and the first side are located on the same side of the display area in a direction parallel to the substrate, and the minimum distance between the first edge and the first side is set as a first distance;

[0012] The second edge and the second side are located on the same side of the display area in a direction parallel to the substrate, and the minimum distance between the second edge and the second side is set as a second distance, and the first distance is greater than the second distance.

[0013] In some example embodiments, the frame area comprises a first frame area, and the first frame area is located on one side of the display area in a second direction parallel to the substrate;

[0014] The first edge and the first side are both located in the first frame area, and the second edge and the second side are not located in the first frame area.

[0015] In some example embodiments, the frame area further comprises a second frame area, a third frame area and a fourth frame area, the second frame area is located on one side of the display area away from the first frame area in the second direction, and the third frame area and the fourth frame area are located on both sides of the display area in a third direction, the third direction is perpendicular to the first direction and intersects with the second direction;

[0016] The second edge and the second side are located in one of the second frame area, the third frame area and the fourth frame area.

[0017] In some example embodiments, the frame area comprises a corner area, a second frame area, a third frame area and a fourth frame area;

[0018] The second frame area is located on one side of the display area away from the first frame area in the second direction, and the third frame area and the fourth frame area are located on both sides of the display area in a third direction, the third direction is perpendicular to the first direction and intersects with the second direction;

[0019] The corner area is located at the joint position of the first frame area and the third frame area, or at the joint position of the first frame area and the fourth frame area, or at the joint position of the second frame area and the third frame area, or at the joint position of the second frame area and the fourth frame area;

[0020] The second edge and the second side are located in the corner area.

[0021] In some exemplary embodiments, the edge of the first electrode layer away from the display area further includes a third edge and a fourth edge, and the edge of the peripheral circuit structure away from the display area includes a third side and a fourth side;

[0022] The second edge and the second side are located within the second border area;

[0023] The third edge and the third side are located in the third border area, and the minimum distance between the third edge and the third side is set as the third distance;

[0024] The second edge and the second side are located in the fourth border area, and the minimum distance between the fourth edge and the fourth side is set as the fourth distance;

[0025] The values ​​of any two of the first distance, the second distance, the third distance, and the fourth distance are not equal.

[0026] In some exemplary embodiments, the first electrode layer is provided with at least one first through hole, the first through hole penetrating the first electrode layer in the first direction, and the orthographic projection of the first through hole on the substrate is located within the orthographic projection of the wiring structure on the substrate.

[0027] In some exemplary embodiments, the wiring structure includes a first metal layer, and the peripheral circuit structure includes a first planarization layer;

[0028] The first metal layer extends from one end near the display area to between the first planarization layer and the substrate;

[0029] The first electrode layer is provided with at least one second through hole, and the second through hole penetrates the first electrode layer in the first direction;

[0030] The first planarization layer is provided with at least one third through hole, which penetrates the first planarization layer in the first direction;

[0031] The orthographic projection of the second through hole on the substrate lies within the orthographic projection of the first planar layer on the substrate and does not overlap with the orthographic projection of the third through hole on the substrate.

[0032] In some exemplary embodiments, the trace structure includes a first metal layer, and the peripheral circuit structure includes a first planarization layer and a second planarization layer, wherein the second planarization layer is located on the side of the first planarization layer closer to the substrate;

[0033] The first planarization layer has a notch at one end away from the display area to expose the second planarization layer;

[0034] The first metal layer extends into the notch at one end near the display area. The first metal layer is provided with a third through hole that penetrates the first metal layer in the first direction. The orthographic projection of the third through hole on the substrate is located within the orthographic projection of the second planar layer on the substrate.

[0035] The first electrode layer is provided with a second through hole that penetrates the first electrode layer in the first direction, and the orthographic projection of the second through hole on the substrate overlaps with the orthographic projection of the third through hole on the substrate.

[0036] In some exemplary embodiments, the orthographic projection of the second through hole on the substrate is configured to overlap with the orthographic projection of the third through hole on the substrate.

[0037] In some exemplary embodiments, a first filling layer, a second filling layer, and a third filling layer are also included, wherein the first filling layer fills the first through-hole, the second filling layer fills the second through-hole, and the third filling layer fills the third through-hole.

[0038] In some exemplary embodiments, the first filling layer protrudes from the first through-hole and covers the edge of the first through-hole away from the substrate, and the second filling layer protrudes from the second through-hole and covers the edge of the second through-hole away from the substrate;

[0039] The first filling layer and the second filling layer are disposed in the same layer, and the maximum size of the first filling layer in the first direction is set to be greater than the maximum size of the second filling layer in the first direction.

[0040] In some exemplary embodiments, the third filling layer and the first planarization layer are disposed in the same layer, and the third filling layer and the first planarization layer are made of the same material.

[0041] In some exemplary embodiments, the first through hole is provided in multiple ways, including a fourth through hole and a fifth through hole, wherein the fourth through hole is located in the first frame area and the fifth through hole is not located in the first frame area.

[0042] In some exemplary embodiments, the fourth through hole and the fifth through hole are configured with different hole types, or the opening area of ​​the fourth through hole is not equal to the opening area of ​​the fifth through hole.

[0043] In some exemplary embodiments, a first organic layer is also included, the first organic layer being located on the side of the wiring structure away from the substrate, the first organic layer being configured to cover the edge of the first electrode layer away from the display area.

[0044] In some exemplary embodiments, the end of the first organic layer away from the first organic layer is configured to extend toward the side away from the display area, and the first organic layer is configured to cover the isolation dam.

[0045] In some exemplary embodiments, the minimum distance between the edge of the first electrode layer away from the display area and the peripheral circuit structure in a direction parallel to the substrate is set to 20 micrometers to 100 micrometers.

[0046] In some exemplary embodiments, the isolation dam includes a first isolation dam and a second isolation dam, wherein the first isolation dam is located on the side of the second isolation dam closer to the display area;

[0047] The edge of the first electrode layer away from the display area is located between the first isolation dam and the peripheral circuit structure.

[0048] This disclosure provides a method for preparing a display substrate, comprising:

[0049] A circuit structure layer and a first electrode layer are sequentially formed on a substrate. The circuit structure layer includes a peripheral circuit structure, a trace structure, and an isolation dam located in the border area. The trace structure and the isolation dam are both located on the side of the peripheral circuit structure away from the display area. The isolation dam is located on the side of the trace structure away from the substrate in a first direction, which is perpendicular to the substrate. The edge of the first electrode layer away from the display area is located on the side of the trace structure away from the substrate and between the isolation dam and the peripheral circuit structure. Alternatively, the edge of the first electrode layer away from the display area extends to the end face of the isolation dam away from the substrate. The edge of the first electrode layer away from the display area includes a first edge and a second edge. The edge of the peripheral circuit structure away from the display area includes a first side and a second side. The first edge and the first side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the first edge and the first side is set as a first distance. The second edge and the second side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the second edge and the second side is set as a second distance. The first distance is greater than the second distance.

[0050] This disclosure provides a display device, which includes the display substrate described above.

[0051] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0052] Overview of the attached figures

[0053] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0054] Figure 1 is a schematic diagram of a display device;

[0055] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0056] Figure 3 is a schematic cross-sectional view of a display substrate;

[0057] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention;

[0058] Figure 5 is a magnified view of part A in Figure 4;

[0059] Figure 6 is a magnified view of part B in Figure 4;

[0060] Figure 7 is a schematic diagram of the CC-direction section in Figure 5;

[0061] Figure 8 is a schematic diagram of the EE-direction section in Figure 6;

[0062] Figure 9 is a magnified view of part D in Figure 5;

[0063] Figure 10 is a magnified view of part F in Figure 8;

[0064] Figure 11 is a cross-sectional schematic diagram of another display panel of this exemplary embodiment;

[0065] Figure 12 is a cross-sectional schematic diagram of another display panel according to this exemplary embodiment;

[0066] Figure 13 is a cross-sectional schematic diagram of another display panel of this exemplary embodiment;

[0067] Figure 14 is a magnified view of part G in Figure 13;

[0068] Figure 15 is a cross-sectional schematic diagram of another display panel of this exemplary embodiment;

[0069] Figure 16 is a magnified view of part H in Figure 15.

[0070] Detailed Explanation

[0071] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0072] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0073] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0074] Tandem OLED display substrates are stacked devices formed by connecting multiple stacked light-emitting layers together through a charge-generating layer. However, the added charge-generating layer has strong conductivity, which can cause crosstalk between pixels, thus affecting the display effect. To achieve a normal display effect, the light-emitting structure layer needs to be designed with T-shaped isolation pillars in the display area to block the charge-generating layer material between pixels. The inventors of this application have discovered that during the fabrication of tandem OLED display substrates, especially during the processing of the T-shaped isolation pillars, two water washing processes are required. This leaves organic matter and moisture residue at the edge. Subsequent processes cover this residue, making it difficult for the organic matter and moisture to release. Furthermore, subsequent high-temperature / vacuum / oven processes cause moisture to rise, which, when combined with the connecting electrode layer, prevents moisture release, leading to the electrode layer being lifted by the moisture and peeling off.

[0075] This disclosure provides a display substrate having a display area and a border area;

[0076] The display substrate includes a substrate, a circuit structure layer and a first electrode layer arranged sequentially in a first direction, wherein the first direction is perpendicular to the substrate;

[0077] The circuit structure layer includes a peripheral circuit structure, a wiring structure, and an isolation dam located in the border area. The wiring structure and the isolation dam are both located on the side of the peripheral circuit structure away from the display area, and the isolation dam is located on the side of the wiring structure away from the substrate in the first direction.

[0078] The edge of the first electrode layer away from the display area is located on the side of the trace structure away from the substrate and between the isolation dam and the peripheral circuit structure; or, the edge of the first electrode layer away from the display area extends to the end face of the isolation dam away from the substrate;

[0079] The first electrode layer has a first edge and a second edge at its edge away from the display area, and the peripheral circuit structure has a first side and a second side at its edge away from the display area.

[0080] The first edge and the first side are located on the same side of the display area in the direction parallel to the substrate, and the minimum distance between the first edge and the first side is set as a first distance;

[0081] The second edge and the second side are located on the same side of the display area in the direction parallel to the substrate, and the minimum distance between the second edge and the second side is set as the second distance, wherein the first distance is greater than the second distance.

[0082] The technical solutions of the embodiments of the present invention will be described in detail below through specific examples.

[0083] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0084] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0085] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0086] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0087] Figure 3 is a schematic cross-sectional view of a display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a circuit structure layer 20 disposed on a substrate 10, a light-emitting structure layer 30 disposed on the side of the circuit structure layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0088] In an exemplary embodiment, the substrate 10 can be a flexible substrate or a rigid substrate. The circuit structure layer 20 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 30 can include multiple light-emitting devices, each of which can include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The organic light-emitting layer can be a series OLED structure. The encapsulation structure layer 40 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to form an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 30, but is not limited thereto. For example, the first, second, and third encapsulation layers can all be inorganic materials or all be organic materials.

[0089] In an exemplary embodiment, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0090] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention. Figure 5 is a partially enlarged schematic diagram of point A in Figure 4. Figure 6 is a partially enlarged schematic diagram of point B in Figure 4. Figure 7 is a cross-sectional view along the CC direction in Figure 5. Figure 8 is a cross-sectional view along the EE direction in Figure 6. In some exemplary embodiments, as shown in Figures 3 to 8, the display substrate may have a display area AA and a border area BB. The display substrate may include a substrate 10, a circuit structure layer 20, and a first electrode layer 204 arranged sequentially in a first direction, the first direction being perpendicular to the substrate 10. The circuit structure layer 20 may include a peripheral circuit structure 201, a wiring structure 202, and an isolation dam 203 located in the border area BB. The wiring structure 202 and the isolation dam 203 may both be located on the side of the peripheral circuit structure 201 away from the display area AA, and the isolation dam 203 may be located on the side of the wiring structure 202 away from the substrate 10. The edge of the first electrode layer 204 away from the display area AA (i.e., the outer edge 206) may be located on the side of the wiring structure 202 away from the substrate 10 and between the isolation dam 203 and the peripheral circuit structure 201; or, the edge of the first electrode layer 204 away from the display area AA (i.e., the outer edge 206) may extend to the end face of the isolation dam 203 away from the substrate 10. The edge of the first electrode layer 204 away from the display area AA (i.e., the outer edge 206) may include a first edge 206-1 and a second edge 206-2, and the edge of the peripheral circuit structure 201 away from the display area AA may include a first side edge 201-5 and a second side edge 201-6. The first edge 206-1 and the first side edge 201-5 are located on the same side of the display area AA in the direction parallel to the substrate 10, and the minimum distance between the first edge 206-1 and the first side edge 201-5 is set as a first distance (L1). The second edge 206-2 and the second side edge 201-6 are located on the same side of the display area AA in the direction parallel to the substrate 10. The minimum distance between the second edge 206-2 and the second side edge 201-6 is set as the second distance (L2), and the first distance (L1) is greater than the second distance (L2). As a result, the area of ​​the first electrode layer 204 covering the wiring structure 202 is reduced, which can correspondingly reduce the area of ​​the first electrode layer 204 in areas prone to water accumulation and reduce the risk of peeling.

[0091] In some exemplary embodiments, as shown in Figures 4 to 8, the display substrate may include a display area AA and a border area BB surrounding the display area AA. In some exemplary embodiments, the display area AA may include a plurality of sub-pixels arranged in a matrix, and the sub-pixels may include pixel driving circuits and light-emitting devices. The border area BB may have an isolation dam 203, a gate driver on array (GOA) circuit, and power lines for transmitting voltage signals to the plurality of sub-pixels. The isolation dam 203 of the border area BB forms a ring structure surrounding the display area AA. For example, the border area BB may include: a first border area B1 located on one side of the display area AA in a second direction, a second border area B2 located on the other side of the second direction, a third border area B3 located on one side of the display area AA in a third direction, and a fourth border area B4 located on the other side of the third direction. The second direction and the third direction are both perpendicular to the first direction, and the second direction and the third direction are perpendicular to each other. The fourth border area B4 may be the lower border of the display substrate, the third border area B3 may be the upper border of the display substrate, the first border area B1 may be the left border of the display substrate, and the second border area B2 may be the right border of the display substrate. In some exemplary embodiments, the intersection of the first border area B1 and the fourth border area B4 can be a corner area B5, which can be arc-shaped. The corner area B5 can also be located at the intersections of the first border area B1 and the third border area B3, the second border area B2 and the fourth border area B4, and the second border area B2 and the third border area B3. However, this is not a limitation. For example, the border area BB is located on the outer periphery of the display area AA, and the border area BB can be circular, semi-circular, L-shaped, or linear, etc.

[0092] In some exemplary embodiments, as shown in Figures 4 to 8, the trace structure 202 may be a power line (VSS). The low voltage required by the pixel driving circuit in the display area AA can be introduced from the bonding pads. The trace structure 202 can deliver the low voltage to each pixel driving circuit. The first electrode layer 204 can serve as a connecting electrode, acting as a bridge for the trace structure 202 to deliver the voltage to the pixel driving circuit. The trace structure 202 includes at least one of a conductive first metal layer 202-1, a second metal layer 202-2, and a third metal layer 202-3. The first metal layer 202-1, the second metal layer 202-2, and the third metal layer 202-3 may be stacked sequentially in a first direction, i.e., sequentially arranged in the direction close to the substrate 10. The third metal layer 202-3 may be disposed on the substrate 10. The second metal layer 202-2 covers the surface of the third metal layer 202-3 away from the substrate 10, and the first metal layer 202-1 covers the surface of the second metal layer 202-2 away from the substrate 10.

[0093] In some exemplary embodiments, as shown in Figures 4 to 8, the peripheral circuit structure 201 may include a first planarization layer 201-1, a second planarization layer 201-2, and a third planarization layer 201-3, which may be sequentially stacked in the direction close to the substrate 10. The third planarization layer 201-3 may be disposed on the substrate 10, the second planarization layer 201-2 covers the surface of the third planarization layer 201-3 away from the substrate 10, and the first planarization layer 201-1 covers the surface of the second planarization layer 201-2 away from the substrate 10. The materials of the first planarization layer 201-1, the second planarization layer 201-2, and the third planarization layer 201-3 may all be organic insulating materials, such as resin.

[0094] In some exemplary embodiments, as shown in Figures 4 to 8, the isolation dam 203 may extend along the edge of the display area AA and form a ring structure surrounding the display area AA. The isolation dam 203 may include a first isolation dam 203-1 and a second isolation dam 203-2, both of which may extend along the edge of the display area AA and are parallel to each other. The first isolation dam 203-1 and the second isolation dam 203-2 can block moisture from entering the display area AA from the border area BB. The first isolation dam 203-1 may be located on the side of the second isolation dam 203-2 closer to the display area AA.

[0095] In some exemplary embodiments, as shown in Figures 4 to 8, the material of the first electrode layer 204 may include a conductive metallic material. The first electrode layer 204 may be arranged in the same layer as the anode of the light-emitting device in the display area AA. The first electrode layer 204 may surround the display area AA. The edge of the first electrode layer 204 away from the display area AA may be an outer edge 206, and the edge of the first electrode layer 204 away from the display area AA may be an inner edge. The outer edge 206 of the first electrode layer 204 is located in the border area BB, and the inner edge is located in the display area AA. The first electrode layer 204 may cover a portion of the surface of the first metal layer 202-1 away from the substrate 10, such that the first electrode layer 204 contacts the wiring structure 202. The contact area between the first electrode layer 204 and the first metal layer 202-1 is the same as the contact area between the first electrode layer 204 and the wiring structure 202. The first electrode layer 204 may also cover the end face of the peripheral circuit structure 201 of the circuit structure layer 20 away from the substrate 10 and the end face of the circuit structure layer 20 located in the display area AA and away from the substrate 10. Currently, the coverage area of ​​the first electrode layer 204 is relatively large. The outer edge 206 of the first electrode layer 204 usually extends to the space between the first isolation dam 203-1 and the second isolation dam 203-2. In this example, the first electrode layer 204 extends to the side of the first isolation dam 203-1 near the display area AA, so that the first electrode layer 204 will not cover the first metal layer 202-1 between the first isolation dam 203-1 and the second isolation dam 203-2. This reduces the coverage area of ​​the first electrode layer 204 and reduces the risk of water accumulation being sealed by the first electrode layer 204.

[0096] In some exemplary embodiments, as shown in Figures 4 to 8, the first electrode layer 204 is provided with at least one first through-hole 204-1. The orthographic projection of the first through-hole 204-1 on the substrate 10 lies within the orthographic projection of the wiring structure 202 on the substrate 10, and the first through-hole 204-1 is located between the first isolation dam 203-1 and the peripheral circuit structure 201. The first through-hole 204-1 penetrates the first electrode layer 204 in a first direction, and extends along the first direction to the first metal layer 202-1 near one end of the substrate 10. The first through-hole 204-1 provides an upward path for water vapor, allowing it to be promptly discharged from the first through-hole 204-1, preventing peeling.

[0097] In some exemplary embodiments, as shown in Figures 4 to 8, multiple first through holes 204-1 may be provided. The multiple first through holes 204-1 have the same hole shape and size, and their cross-sections parallel to the substrate 10 are set as rectangles, making the first through holes 204-1 rectangular holes. However, this is not limited to this; for example, the first through holes 204-1 may be circular holes, trapezoidal holes, triangular holes, rhomboid holes, polygonal holes, irregular holes, etc. The multiple first through holes 204-1 are arranged linearly, or evenly spaced along the edge of the display area AA. However, this is not limited to this; for example, the multiple first through holes 204-1 may be non-equally spaced along the edge of the display area AA, or arranged in an array or irregularly. Furthermore, the first through holes 204-1 may be circular holes, rhomboid holes, polygonal holes, etc.

[0098] In some exemplary embodiments, as shown in Figures 4 to 8, the first through holes 204-1 in different regions of the border area BB are different. The hole type, number, and opening area of ​​the first through holes 204-1 in different regions are different. For example, the first through hole 204-1 in the first border area B1 may be the fourth through hole, and the first through hole 204-1 in the corner area B5 may be the fifth through hole. The fourth through hole and the fifth through hole are located in different regions, have different numbers, or have different hole types, or the opening area of ​​the fourth through hole is not equal to the opening area of ​​the fifth through hole. In some exemplary embodiments, the minimum distance between the first edge 206-1 and the first side 201-5 in the first border area B1 is set as a first distance (L1), and the minimum distance between the second edge 206-2 and the second side 201-6 in the corner area B5 is set as a second distance (L2), where L1 > L2. The number of first through holes 204-1 in the first border area B1 is greater than the number of first through holes 204-1 in the corner area B5. For example, the first through holes 204-1 in the first border area B1 can be arranged in two columns parallel to the edge of the display area AA, and the first through holes 204-1 in the corner area B5 can be arranged in one column parallel to the edge of the display area AA. In some exemplary embodiments, the first through-hole 204-1 located in the first border region B1 may be a fourth through-hole, and the first through-hole 204-1 located in the third border region B3 may be a fifth through-hole. The fourth and fifth through-holes are located in different regions, have different numbers, or have different hole shapes, or the opening area of ​​the fourth through-hole is not equal to the opening area of ​​the fifth through-hole. In some exemplary embodiments, the hole shape, number, and opening area of ​​the first through-hole 204-1 can be adjusted according to the difference in the area of ​​the wiring structure covered by the first electrode layer 204 in the third border region B3 and the first border region B1, thereby ensuring that the contact area between the wiring structure and the first electrode layer 204 is large enough, reducing the impedance of the first electrode layer 204, and improving the uniformity of display brightness. For example, the area of ​​the wiring structure covered by the first electrode layer 204 in the third border area B3 is smaller than the area of ​​the wiring structure covered by the first electrode layer 204 in the first border area B1, and the opening area of ​​the first through hole 204-1 in the third border area B3 is smaller than the opening area of ​​the first through hole 204-1 in the first border area B1.

[0099] In some exemplary embodiments, as shown in Figures 4 to 8, the first edge 206-1 and the first side edge 201-5 may be located in the first frame area B1, and the second side edge 201-6 and the second edge 206-2 may be located in the corner area B5. That is, the edge of the first electrode layer 204 in the first frame area B1 away from the display area AA may be the first edge 206-1, and the edge of the peripheral circuit structure 201 in the first frame area B1 away from the display area AA may be the first side edge 201-5; the edge of the first electrode layer 204 in the corner area B5 away from the display area AA may be the second edge 206-2, and the edge of the peripheral circuit structure 201 in the corner area B5 away from the display area AA may be the second side edge 201-6. The minimum distance between the first edge 206-1 and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be L1, and the minimum distance between the second edge 206-2 and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be L2, where L1 > L2. The first planarization layer 201-1, the second planarization layer 201-2, and the third planarization layer 201-3 are basically flush with the edges away from the display area AA. The minimum distance between the edge of the first electrode layer 204 away from the display area AA and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be the minimum distance between the edge of the first electrode layer 204 away from the display area AA and the first planarization layer 201-1 in the direction parallel to the substrate 10. Therefore, based on the same extension length along the edge of the display area AA, the contact area of ​​the first electrode layer 204 and the wiring structure 202 in the first frame area B1 is greater than the contact area of ​​the first electrode layer 204 and the wiring structure 202 in the corner area B5. That is, the area of ​​the wiring structure 202 in the corner area B5 is reduced relative to the first frame area B1, which can correspondingly reduce the area of ​​the first electrode layer 204 in the water-prone position and reduce the risk of peeling.

[0100] In some exemplary embodiments, as shown in Figures 4 to 8, the first edge 206-1 and the first side edge 201-5 may be located in the fourth frame area B4, and the second side edge 201-6 and the second edge 206-2 may be located in the first frame area B1. The edge of the first electrode layer 204 in the fourth frame area B4 away from the display area AA (i.e., the outer edge 206) may be the first edge 206-1, and the edge of the peripheral circuit structure 201 in the fourth frame area B4 away from the display area AA may be the first side edge 201-5. The edge of the first electrode layer 204 in the first frame area B1 away from the display area AA (i.e., the outer edge 206) may be the second edge 206-2, and the edge of the peripheral circuit structure 201 in the fourth frame area B4 away from the display area AA may be the second side edge 201-6. The first edge 206-1 extends to the first isolation dam 203-1, and the second edge 206-2 does not extend to the second isolation dam 203-2. The minimum distance between the first edge 206-1 and the surrounding circuit structure 201 in the direction parallel to the substrate 10 can be L1, and the minimum distance between the second edge 206-2 and the surrounding circuit structure 201 in the direction parallel to the substrate 10 can be L2, where L1 > L2. However, this is not the only possibility. The first edge 206-1 and the first side edge 201-5 may be located in other areas of the border area BB. For example, the first edge 206-1 and the first side edge 201-5 may be located in the first border area B1, and the second side edge 201-6 and the second edge 206-2 may be located in the second border area B2. For another example, the first edge 206-1 and the first side edge 201-5 may be located in the third border area B3, and the second side edge 201-6 and the second edge 206-2 may be located in the fourth border area B4. For yet another example, the first edge 206-1 and the first side edge 201-5 may be located in the first border area B1, and the second side edge 201-6 and the second edge 206-2 may be located in the third border area B3. For yet another example, the first edge 206-1 and the first side edge 201-5 may be located in the fourth border area B4, and the second side edge 201-6 and the second edge 206-2 may be located in the first border area B1.

[0101] In some exemplary embodiments, the edge of the first electrode layer 204 away from the display area AA further includes a third edge (not shown) and a fourth edge (not shown), and the edge of the peripheral circuit structure 201 away from the display area AA may include a third side edge (not shown) and a fourth side edge (not shown). The first edge 206-1 and the first side edge 201-5 may be located in the first border area B1, and the second side edge 201-6 and the second edge 206-2 may be located in the second border area B2. The third edge and the third side edge are located in the third border area B3, and the minimum distance between the third edge and the third side edge is set as a third distance. The fourth edge and the fourth side edge are located in the fourth border area B4, and the minimum distance between the fourth edge and the fourth side edge is set as a fourth distance. The values ​​of any two of the first distance, second distance, third distance, and fourth distance are not equal, so that the distance by which the outer edge of the first electrode layer 204 protrudes from the peripheral circuit structure 201 in the direction parallel to the substrate 10 is not the same. This makes the first distance, second distance, third distance, and fourth distance match the corresponding border area. A narrower border area can correspond to a smaller spacing. For example, the third border area B3 is relatively narrower than other areas, and the contact area between the trace structure in the third border area B3 and the first electrode layer 204-1 is relatively small. The third distance is smaller than the first distance, second distance, and fourth distance.

[0102] Figure 9 is a partially enlarged schematic diagram of point D in Figure 5, and Figure 10 is a partially enlarged schematic diagram of point F in Figure 8. In some exemplary embodiments, as shown in Figures 5 to 10, the minimum distance between the edge of the first electrode layer 204 away from the display area AA (i.e., the outer edge 206) and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be 20 micrometers to 100 micrometers. At least two rows of first through holes 204-1 can be arranged in the portion of the first electrode layer 204 between the first edge 206-1 and the first side edge 201-5. The minimum distance (L1) between the first edge 206-1 and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be 85 micrometers, and the minimum distance (L2) between the second edge 206-2 and the peripheral circuit structure 201 in the direction parallel to the substrate 10 can be 40 micrometers.

[0103] In some exemplary embodiments, as shown in Figures 5 and 9, the first electrode layer 204 has two rows of rectangular first through holes 204-1 arranged between the first edge 206-1 and the peripheral circuit structure 201. The first through holes 204-1 can be square holes, and the side length of the first through holes 204-1 can be from 5 micrometers to 20 micrometers. In this example, the side length of the first through holes 204-1 can be 8.5 micrometers, i.e., L3 = L4 = 8.5 μm. The spacing between the two rows of rectangular first through holes 204-1 can be L5, the spacing between the first through holes 204-1 in the same row can be L8, the minimum distance between the first through holes 204-1 and the first edge 206-1 can be L6, and the minimum distance between the first through holes 204-1 and the peripheral circuit structure 201 can be L7. To ensure breathability, L5 can be 10 to 20 micrometers, L6 can be 0 to 20 micrometers, L7 can be 10 to 20 micrometers, and L8 can be 10 to 20 micrometers.

[0104] In some exemplary embodiments, as shown in Figures 6, 8, and 10, a row of rectangular first through-holes 204-1 are arranged between the second edge 206-2 and the peripheral circuit structure 201 in the first electrode layer 204. The first through-holes 204-1 can be square holes, and their side length can be from 5 micrometers to 20 micrometers. In this example, the side length L3 of the first through-hole 204-1 can be 8.5 μm. The minimum distance between the first through-hole 204-1 and the second edge 206-2 can be L9, and the minimum distance between the first through-hole 204-1 and the peripheral circuit structure 201 can be L10. In some exemplary embodiments, L10 is greater than L9 to ensure sufficient space between the first through-hole 204-1 and the arc portion near the display first electrode layer 204 (i.e., between the projection of the first through-hole 204-1 and the peripheral circuit structure 201 near the display area), thus avoiding damage to the peripheral circuit structure 201 when the first through-hole 204-1 is installed. In some exemplary embodiments, in order to ensure breathability, L9 can be 0 to 20 micrometers and L10 can be 10 to 20 micrometers.

[0105] In some exemplary embodiments, as shown in Figures 7, 8, 10, and 11, the display substrate further includes a first filling layer 205. The first filling layer 205 may be an organic insulating material and may be breathable. The first filling layer 205 fills and completely fills the first through-hole 204-1, protruding from the first through-hole 204-1, so that the first filling layer 205 covers the edge of the first through-hole 204-1 away from the substrate 10, making it less likely for the first electrode layer 204 to lift off the edge of the first through-hole 204-1. Moreover, the first filling layer 205 covering the edge of the first through-hole 204-1 can reduce corrosion caused by the exposed boundary of the first through-hole 204-1. The first filling layer 205 may be made of the same material as the pixel definition layer located in the display area AA of the light-emitting structure layer, and is disposed in the same layer as the pixel definition layer. The first filling layer 205 may be fabricated using the patterning process of the pixel definition layer. In some exemplary embodiments, the minimum distance between the first through hole 204-1 and the second edge 206-2 can be L9, and the minimum distance between the first through hole 204-1 and the peripheral circuit structure 201 can be L10. L10 is greater than L9, which can ensure that there is sufficient space between the first filling layer 205 and the arc portion near the first display electrode layer 204 (i.e., between the projection of the first filling layer 205 and the peripheral circuit structure 201 near the display area), and can avoid poor overlap of the first filling layer 205 near the arc portion of the first display electrode layer 204, which makes it easy to peel off.

[0106] Figure 11 is a cross-sectional schematic diagram of another display panel according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 11, the display substrate further includes a first organic layer 207, which may be an organic insulating material. The first organic layer 207 may cover the isolation dam 203, that is, the first organic layer 207 may cover the first isolation dam 203-1 and the second isolation dam 203-2, as well as the portion between the first isolation dam 203-1 and the second isolation dam 203-2. The first organic layer 207 also covers the edge (outer edge 206) of the first electrode layer 204 away from the display area AA. The edge (outer edge 206) of the first electrode layer 204 away from the display area AA may be a first edge or a second edge. The boundary of the first electrode layer 204 is covered, which can reduce the intrusion of moisture into the organic channel between the first isolation dam 203-1 and the second isolation dam 203-2. In some exemplary embodiments, the distance between the first filling layer 205 and the first organic layer 207 covering the first isolation dam 203-1 is less than the distance between the first filling layer 205 and the surrounding circuit structure 201, which can ensure sufficient buffer distance and improve the effect of isolating water and oxygen.

[0107] Figure 12 is a cross-sectional schematic diagram of another display panel according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 12, the edge (outer edge 206) of the first electrode layer 204 away from the display area AA extends onto the first isolation dam 203-1 and is located on the end face of the first isolation dam 203-1 away from the substrate 10. The first electrode layer 204 does not cover the wiring structure 202 between the first isolation dam 203-1 and the second isolation dam 203-2. Water may easily accumulate between the first isolation dam 203-1 and the second isolation dam 203-2. Since the first electrode layer 204 does not cover the area between the first isolation dam 203-1 and the second isolation dam 203-2, the risk of peeling off the first electrode layer 204 can be greatly reduced.

[0108] Figure 13 is a cross-sectional schematic diagram of another display panel according to this exemplary embodiment, and Figure 14 is a partially enlarged schematic diagram of point G in Figure 13. In some exemplary embodiments, as shown in Figures 13 and 14, the first metal layer 202-1 extends from one end near the display area AA to between the first planarization layer 201-1 and the substrate 10, such that the first metal layer 202-1 is inserted between the first planarization layer 201-1 and the second planarization layer 201-2, and the orthographic projection of the first metal layer 202-1 on the substrate 10 overlaps with the orthographic projection of the first planarization layer 201-1 on the substrate 10. The first electrode layer 204 is provided with at least one second through hole 204-2, which penetrates the first electrode layer 204 in a first direction. The second through hole 204-2 can be a rectangular hole, a circular hole, etc., and the orthographic projection of the second through hole 204-2 on the substrate 10 is located within the orthographic projection of the first planarization layer 201-1 on the substrate 10. The first metal layer 202-1 is provided with at least one third through hole 202-4, which penetrates the first metal layer 202-1 in a first direction. The third through hole 202-4 can be a rectangular hole, a circular hole, etc. The orthographic projection of the third through hole 202-4 on the substrate 10 lies within the orthographic projection of the first planarization layer 201-1 on the substrate 10. The second through hole 204-2 and the third through hole 202-4 provide an upward path for water vapor in the surrounding circuit structure, facilitating water vapor discharge and preventing the first electrode layer 204 covering the surrounding circuit structure from peeling off.

[0109] In some exemplary embodiments, as shown in Figures 13 and 14, the orthographic projection of the second through-hole 204-2 onto the substrate 10 does not overlap with the orthographic projection of the third through-hole 202-4 onto the substrate 10, such that the second through-hole 204-2 and the third through-hole 202-4 are staggered in a first direction. The third through-hole 202-4 is filled by a first planarization layer 201-1 covering the first metal layer 202-1. The display substrate further includes a second filling layer 208, which may be an organic insulating material and may be breathable. The second filling layer 208 can fill and completely fill the second through-hole 204-2. The second filling layer 208 protrudes from the second through-hole 204-2, such that the second filling layer 208 covers the edge of the second through-hole 204-2 away from the substrate 10, making it less likely for the edge of the first electrode layer 204 at the second through-hole 204-2 to lift up. The second filling layer 208 can be made of the same material as the pixel definition layer located in the display area AA of the light-emitting structure layer, and can be set in the same layer as the pixel definition layer. The second filling layer 208 can be made by the patterning process of the pixel definition layer.

[0110] Figure 15 is a cross-sectional schematic diagram of another display panel according to this exemplary embodiment, and Figure 16 is a partially enlarged schematic diagram of point G in Figure 15. In some exemplary embodiments, as shown in Figures 15 and 16, a notch 201-4 is provided at the end of the first planarization layer 201-1 away from the display area AA. The notch 201-4 can be formed by hollowing out the material of the first planarization layer 201-1, that is, the end of the first planarization layer 201-1 away from the display area AA shrinks towards the display area AA to expose the second planarization layer 201-2. The end of the first metal layer 202-1 near the display area AA extends into the notch 201-4, thereby increasing the contact area between the first metal layer 202-1 and the first electrode layer 204, reducing the impedance of the first electrode layer 204, and improving the uniformity of display brightness. The first metal layer 202-1 has a third through hole 202-4 penetrating through the first metal layer 202-1 in a first direction. The third through hole 202-4 can be a rectangular hole, a circular hole, etc. The orthographic projection of the third through hole 202-4 on the substrate 10 lies within the orthographic projection of the second planarization layer on the substrate 10. The first electrode layer 204 has at least one first through hole 204-1 and at least one second through hole 204-2. Both the first through hole 204-1 and the second through hole 204-2 penetrate the first electrode layer 204 in the first direction. The hole shapes of the first through hole 204-1 and the second through hole 204-2 can be the same for easy processing, for example, they can be rectangular holes, circular holes, etc. The orthographic projection of the first through-hole 204-1 on the substrate 10 is not the same as the orthographic projection of the first planarization layer 201-1 on the substrate 10 and is located within the orthographic projection of the second metal layer 202-2 on the substrate 10. The orthographic projection of the second through-hole 204-2 on the substrate 10 is located within the orthographic projection of the first planarization layer 201-1 on the substrate 10.

[0111] In some exemplary embodiments, as shown in Figures 15 and 16, the orthographic projection of the second through hole 204-2 on the substrate 10 overlaps with the orthographic projection of the third through hole 202-4 on the substrate 10. In this example, the hole shapes of the second through hole 204-2 and the third through hole 202-4 are the same and the hole positions are also the same, so that the orthographic projection of the second through hole 204-2 on the substrate 10 overlaps with the orthographic projection of the third through hole 202-4 on the substrate 10, providing a straight upward path for water vapor and accelerating the water vapor removal speed.

[0112] In some exemplary embodiments, as shown in Figures 15 and 16, the display substrate further includes a second filling layer 208 and a third filling layer 209. Both the second filling layer 208 and the third filling layer 209 may be organic insulating materials and be breathable. The second filling layer 208 may fill and protrude from the second through-hole 204-2, and the third filling layer 209 may fill the third through-hole 202-4. The second filling layer 208 may be made of the same material as the pixel definition layer located in the display area AA of the light-emitting structure layer and may be disposed on the same layer as the pixel definition layer. The third filling layer 209 may be made of the same material as the first planarization layer 201-1 and may be disposed on the same layer.

[0113] In some exemplary embodiments, as shown in Figures 15 and 16, the maximum dimension of the second filling layer 208 in the first direction may be H2, and the maximum dimension of the second filling layer 205 in the first direction may be H1, wherein H2 > H1.

[0114] In some exemplary embodiments, a fabrication method can be applied to the aforementioned display substrate. The fabrication method may include sequentially fabricating a circuit structure layer and a first electrode layer on the substrate. During the fabrication of the circuit structure layer on the substrate, a first planarization layer, a second planarization layer, a third planarization layer, a wiring structure, and an isolation dam need to be fabricated on the substrate through processes such as coating, deposition, and etching. During the fabrication of the first electrode layer on the circuit structure layer, an electrode thin film needs to be deposited on the circuit structure layer first, and an electrode layer pattern needs to be etched. The electrode layer pattern has a first through-hole. The pre-baking, post-baking, and etching processes in the patterning process of the first electrode layer all require a high-temperature environment. Under this environment, moisture can be promptly removed through the first through-hole, preventing peeling. Finally, a breathable insulating material is used to fill the first through-hole.

[0115] In some exemplary embodiments, a method for fabricating a display substrate includes:

[0116] A circuit structure layer and a first electrode layer are sequentially formed on a substrate. The circuit structure layer includes a peripheral circuit structure, a trace structure, and an isolation dam located in the border area. The trace structure and the isolation dam are both located on the side of the peripheral circuit structure away from the display area. The isolation dam is located on the side of the trace structure away from the substrate in a first direction, which is perpendicular to the substrate. The edge of the first electrode layer away from the display area is located on the side of the trace structure away from the substrate and between the isolation dam and the peripheral circuit structure. Alternatively, the edge of the first electrode layer away from the display area extends to the end face of the isolation dam away from the substrate. The edge of the first electrode layer away from the display area includes a first edge and a second edge. The edge of the peripheral circuit structure away from the display area includes a first side and a second side. The first edge and the first side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the first edge and the first side is set as a first distance. The second edge and the second side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the second edge and the second side is set as a second distance. The first distance is greater than the second distance.

[0117] In some exemplary embodiments, a display device is provided, comprising the aforementioned display substrate, and may be an OLED display device. The display device provided in this disclosure can be applied to electronic devices, which may include mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, in-vehicle displays, and any product or component with display functionality, such as wearable devices, smartwatches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc. In this example, the display device is a mobile phone.

[0118] In conjunction with the above embodiments, the display substrate of this example, by allowing the first electrode layer to retract to the side of the first isolation dam near the display area and opening a first through-hole, reduces moisture confinement and allows moisture to be released promptly through the first through-hole, thereby preventing the first electrode layer from peeling off. The first metal layer extends towards the display area, increasing the overlap between the wiring structure and the first electrode layer across the entire surface. This reduces the risk of peeling while ensuring that the overlap area between the wiring structure and the first electrode layer does not decrease, achieving a good display effect.

[0119] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0120] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0121] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0122] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0123] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0124] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0125] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, wherein, The display substrate has a display area and a bezel area; The display substrate includes a substrate, a circuit structure layer and a first electrode layer arranged sequentially in a first direction, wherein the first direction is perpendicular to the substrate; The circuit structure layer includes a peripheral circuit structure, a wiring structure, and an isolation dam located in the border area. The wiring structure and the isolation dam are both located on the side of the peripheral circuit structure away from the display area, and the isolation dam is located on the side of the wiring structure away from the substrate in the first direction. The edge of the first electrode layer away from the display area is located on the side of the trace structure away from the substrate and between the isolation dam and the peripheral circuit structure; or, the edge of the first electrode layer away from the display area extends to the end face of the isolation dam away from the substrate; The first electrode layer has a first edge and a second edge at its edge away from the display area, and the peripheral circuit structure has a first side and a second side at its edge away from the display area. The first edge and the first side are located on the same side of the display area in the direction parallel to the substrate, and the minimum distance between the first edge and the first side is set as a first distance; The second edge and the second side are located on the same side of the display area in the direction parallel to the substrate, and the minimum distance between the second edge and the second side is set as the second distance, wherein the first distance is greater than the second distance.

2. The display substrate according to claim 1, wherein, The border area includes a first border area, which is located on one side of the display area in a second direction, and the second direction is parallel to the substrate; The first edge and the first side are both located in the first border area, while the second edge and the second side are not located in the first border area.

3. The display substrate according to claim 2, wherein, The border area further includes a second border area, a third border area, and a fourth border area. The second border area is located on the side of the display area away from the first border area in the second direction. The third border area and the fourth border area are located on both sides of the display area in a third direction. The third direction is perpendicular to the first direction and intersects with the second direction. The second edge and the second side are located in one of the second border area, the third border area and the fourth border area.

4. The display substrate according to claim 2, wherein, The border area includes a corner area, a second border area, a third border area, and a fourth border area; The second border is located on the side of the display area away from the first border area in the second direction. The third border area and the fourth border area are located on both sides of the display area in the third direction, which is perpendicular to the first direction and intersects with the second direction. The corner area is located at the junction of the first border area and the third border area, or at the junction of the first border area and the fourth border area, or at the junction of the second border area and the third border area, or at the junction of the second border area and the fourth border area. The second edge and the second side are located in the corner region.

5. The display substrate according to claim 3, wherein, The first electrode layer further includes a third edge and a fourth edge at the edge away from the display area, and the peripheral circuit structure includes a third side and a fourth side at the edge away from the display area; The second edge and the second side are located within the second border area; The third edge and the third side are located in the third border area, and the minimum distance between the third edge and the third side is set as the third distance; The second edge and the second side are located in the fourth border area, and the minimum distance between the fourth edge and the fourth side is set as the fourth distance; The values ​​of any two of the first distance, the second distance, the third distance, and the fourth distance are not equal.

6. The display substrate according to claim 2, wherein, The first electrode layer is provided with at least one first through hole, the first through hole penetrates the first electrode layer in the first direction, and the orthographic projection of the first through hole on the substrate is located within the orthographic projection of the wiring structure on the substrate.

7. The display substrate according to claim 6, wherein, The wiring structure includes a first metal layer, and the peripheral circuit structure includes a first planarization layer; The first metal layer extends from one end near the display area to between the first planarization layer and the substrate; The first electrode layer is provided with at least one second through hole, and the second through hole penetrates the first electrode layer in the first direction; The first planarization layer is provided with at least one third through hole, which penetrates the first planarization layer in the first direction; The orthographic projection of the second through hole on the substrate lies within the orthographic projection of the first planar layer on the substrate and does not overlap with the orthographic projection of the third through hole on the substrate.

8. The display substrate according to claim 6, wherein, The trace structure includes a first metal layer, and the peripheral circuit structure includes a first planarization layer and a second planarization layer, wherein the second planarization layer is located on the side of the first planarization layer closer to the substrate. The first planarization layer has a notch at one end away from the display area to expose the second planarization layer; The first metal layer extends into the notch at one end near the display area. The first metal layer is provided with a third through hole that penetrates the first metal layer in the first direction. The orthographic projection of the third through hole on the substrate is located within the orthographic projection of the second planar layer on the substrate. The first electrode layer is provided with a second through hole that penetrates the first electrode layer in the first direction, and the orthographic projection of the second through hole on the substrate overlaps with the orthographic projection of the third through hole on the substrate.

9. The display substrate according to claim 8, wherein, The orthographic projection of the second through hole on the substrate is configured to overlap with the orthographic projection of the third through hole on the substrate.

10. The display substrate according to claim 7 or 8, wherein, It also includes a first filling layer, a second filling layer, and a third filling layer, wherein the first filling layer fills the first through hole, the second filling layer fills the second through hole, and the third filling layer fills the third through hole.

11. The display substrate according to claim 10, wherein, The first filling layer protrudes from the first through hole and covers the edge of the first through hole away from the substrate, and the second filling layer protrudes from the second through hole and covers the edge of the second through hole away from the substrate; The first filling layer and the second filling layer are disposed in the same layer, and the maximum size of the first filling layer in the first direction is set to be greater than the maximum size of the second filling layer in the first direction.

12. The display substrate according to claim 10, wherein, The third filling layer and the first planarization layer are disposed in the same layer, and the third filling layer and the first planarization layer are made of the same material.

13. The display substrate according to claim 6, wherein, The first through hole is provided in multiple ways, including a fourth through hole and a fifth through hole. The fourth through hole is located in the first frame area, and the fifth through hole is not located in the first frame area.

14. The display substrate according to claim 13, wherein, The fourth through hole and the fifth through hole are configured with different hole types, or the opening area of ​​the fourth through hole is not equal to the opening area of ​​the fifth through hole.

15. The display substrate according to any one of claims 1 to 9, wherein, It also includes a first organic layer, which is located on the side of the wiring structure away from the substrate, and the first organic layer is configured to cover the edge of the first electrode layer away from the display area.

16. The display substrate according to claim 15, wherein, The end of the first organic layer away from the first organic layer is configured to extend toward the side away from the display area, and the first organic layer is configured to cover the isolation dam.

17. The display substrate according to any one of claims 1 to 9, wherein, The minimum distance between the edge of the first electrode layer away from the display area and the peripheral circuit structure in the direction parallel to the substrate is set to 20 micrometers to 100 micrometers.

18. The display substrate according to any one of claims 1 to 9, wherein, The isolation dam includes a first isolation dam and a second isolation dam, with the first isolation dam located on the side of the second isolation dam closer to the display area; The edge of the first electrode layer away from the display area is located between the first isolation dam and the peripheral circuit structure.

19. A method for preparing a display substrate, wherein, include: A circuit structure layer and a first electrode layer are sequentially formed on a substrate. The circuit structure layer includes a peripheral circuit structure, a trace structure, and an isolation dam located in the border area. The trace structure and the isolation dam are both located on the side of the peripheral circuit structure away from the display area. The isolation dam is located on the side of the trace structure away from the substrate in a first direction, which is perpendicular to the substrate. The edge of the first electrode layer away from the display area is located on the side of the trace structure away from the substrate and between the isolation dam and the peripheral circuit structure. Alternatively, the edge of the first electrode layer away from the display area extends to the end face of the isolation dam away from the substrate. The edge of the first electrode layer away from the display area includes a first edge and a second edge. The edge of the peripheral circuit structure away from the display area includes a first side and a second side. The first edge and the first side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the first edge and the first side is set as a first distance. The second edge and the second side are located on the same side of the display area in a direction parallel to the substrate. The minimum distance between the second edge and the second side is set as a second distance. The first distance is greater than the second distance.

20. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 18.

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