Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises at least one constant-voltage signal line. The constant-voltage signal line comprises a horizontal constant-voltage signal sub-line extending in a first direction and a vertical constant-voltage signal sub-line extending in a second direction. The horizontal constant-voltage signal sub-line is configured to provide a constant-voltage signal to a plurality of pixel units in one pixel unit row. A plurality of data lines comprise a plurality of data line pairs. Each data line pair comprises a first data line and a second data line which are adjacent in the first direction. The vertical constant-voltage signal sub-line is located between a first data line and a second data line in one data line pair. The display substrate further comprises a first fanout wire and a second fanout wire, wherein the first fanout wire is connected to data lines in a second display region and extends from the second display region to a first display region; and the second fanout wire is located in the first display region, is connected to the first fanout wire and extends from the first display region to a peripheral region, and the second fanout wire is located between two adjacent data line pairs. The display substrate has an optimized layout design.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, Organic Light Emitting Diode (OLED) displays have gradually become a research hotspot for major manufacturers due to their advantages such as active light emission, high contrast, wide color gamut, wide viewing angle, fast response, low power consumption, thinness, and flexibility. They are increasingly being applied to various electronic products. A typical OLED display device includes a display substrate, which comprises pixel driving circuitry and organic light-emitting elements electrically connected to the pixel driving circuitry. The organic light-emitting elements include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. Holes and electrons are injected into the organic light-emitting layer from the anode and cathode, respectively, forming excitons and emitting light within the organic light-emitting layer.

[0003] On the other hand, consumers are increasingly demanding narrow bezels for smartphones and other electronic products. In typical display substrates, the data lines of each pixel unit need to be led out from the display area and electrically connected to bonding pads in the bonding area located in the peripheral area. The line leading out the data line and connecting it to the bonding area is called a fanout wire. Since placing the fanout wire in the peripheral area outside the rounded corners of the display area occupies a large space, it results in a larger bezel width in that area of ​​the display substrate. FIP (Fanout In Pixel) is a good way to reduce the bezel width. It effectively reduces the bezel width by placing the fanout wire inside the display area, instead of in the peripheral area outside the rounded corners.

[0004] Summary of the Invention

[0005] This disclosure provides a display substrate and a display device. By providing a first lead and a second lead in the display area to connect data lines in the second display area to the peripheral area, the display substrate does not need to provide lead lines in the peripheral area outside the second display area, thereby reducing the bezel width. By providing a vertical sub-constant voltage signal line between the first data line and the second data line in a data line pair, the display substrate can not only utilize the space between the first data line and the second data line to arrange the vertical sub-constant voltage signal line extending in a second direction, but also utilize the vertical sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line. Furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead between the first data line and the second data line in a data line pair, thus avoiding interference between the first data line and the second data line on the signals on the second lead. On the other hand, to reduce ESD (electrostatic discharge) risks, the second lead extending along the second direction requires a jumper design, i.e., jumpering via two planarization vias. These two planarization vias affect the flatness of the effective light-emitting area of ​​the anode above it. In the area where the data line pairs are located, the two data lines themselves are connected to the pixel driving circuit through two planarization vias. Therefore, at least two planarization vias already exist in the area where the data line pairs are located. If the second lead is placed between the first and second data lines in the data line pair, it will be difficult for the effective light-emitting area of ​​the anode to completely avoid these four planarization vias, thus adversely affecting the flatness of the effective light-emitting area of ​​the anode, leading to defects such as color shift. Therefore, by placing the second lead in the area between two adjacent data line pairs, rather than in the area between the first and second data lines in a single data line pair, this display substrate also avoids the jumper design of the second lead affecting the flatness of the anode, thereby improving the flatness of the anode and reducing defects such as color shift. In summary, this display substrate not only reduces the bezel width but also optimizes the layout design on the display substrate and improves display quality.

[0006] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a plurality of pixel units arrayed on the substrate along a first direction and a second direction; and a plurality of data lines located on the substrate and arranged along the first direction, each data line extending along the second direction; the plurality of pixel units are divided into a plurality of pixel unit columns arranged along the first direction, each pixel unit column including a plurality of pixel units arranged along the second direction, each data line being configured to provide a data signal to at least a portion of the plurality of pixel units in a pixel unit column; the plurality of pixel units are divided into a plurality of pixel unit rows arranged along the second direction, each pixel unit row including a plurality of pixel units arranged along the first direction, the display substrate further comprising at least one constant voltage signal line, the constant voltage signal line including a lateral sub-constant voltage signal line extending along the first direction and a longitudinal sub-constant voltage signal line extending along the second direction, the lateral sub-constant voltage signal line being configured to provide a data signal to a plurality of pixel units in a pixel unit row. A constant voltage signal is provided, wherein the longitudinal sub-constant voltage signal line is electrically connected to the transverse sub-constant voltage signal line; the plurality of data lines include a plurality of data line pairs, each data line pair including a first data line and a second data line adjacent in the first direction, a first distance between the first data line and the second data line in a data line pair being less than a second distance between two adjacent data line pairs, the longitudinal sub-constant voltage signal line being located between the first data line and the second data line in a data line pair, the display substrate including a display area and a peripheral area, the display area including a first display area and two second display areas located on both sides of the first display area, the display substrate further including a first lead and a second lead, the first lead being connected to the data line in the second display area and extending from the second display area to the first display area, the second lead being located in the first display area, electrically connected to the first lead, and extending from the first display area along the second direction to the peripheral area, the second lead being located between two adjacent data line pairs.

[0007] For example, in one embodiment of this disclosure, the display substrate further includes: a first semiconductor layer located on the substrate; a second semiconductor layer located on the side of the first semiconductor layer away from the substrate; each pixel unit includes a pixel driving circuit and a light-emitting element; the pixel driving circuit is electrically connected to the light-emitting element and configured to drive the light-emitting element to emit light; each pixel driving circuit includes a plurality of transistors; in each pixel driving circuit, a portion of the active layer of the plurality of transistors is located on the first semiconductor layer, and another portion of the active layer of the plurality of transistors is located on the second semiconductor layer, forming a semiconductor block in the second semiconductor layer; the second lead is located between two semiconductor blocks of two adjacent pixel driving circuits; the pixel driving circuit includes a compensation transistor and a first initialization transistor; the active layers of the compensation transistor and the first initialization transistor are connected and form the semiconductor block in the second semiconductor layer.

[0008] For example, in a display substrate provided in one embodiment of this disclosure, the constant voltage signal line is configured to provide an initialization signal to the plurality of pixel units.

[0009] For example, in a display substrate provided in one embodiment of this disclosure, the longitudinal sub-constant voltage signal line and the first data line and the second data line are disposed on the same layer.

[0010] For example, a display substrate provided in one embodiment of this disclosure further includes: a first lead-out adapter wire, a first end of the first lead-out adapter wire being connected to the first lead wire, and a second end of the first lead-out adapter wire being connected to the second lead wire; the orthographic projection of the first lead-out adapter wire on the substrate is covered by the orthographic projection of the second lead wire on the substrate.

[0011] For example, a display substrate provided in one embodiment of this disclosure further includes: a second lead-out adapter wire, a first end of the second lead-out adapter wire being connected to the first lead wire, and a second end of the second lead-out adapter wire being connected to the data line; the orthographic projection of the second lead-out adapter wire on the substrate is covered by the orthographic projection of the data line on the substrate.

[0012] For example, in one embodiment of this disclosure, the display substrate further includes: a first source / drain metal layer located on the substrate; a planarization layer located on the side of the first source / drain metal layer away from the substrate; and a second source / drain metal layer located on the side of the planarization layer away from the first source / drain metal layer, wherein the second lead includes a first conductive portion located in the first source / drain metal layer and a second conductive portion located in the second source / drain metal layer, and the first conductive portion and the second conductive portion are electrically connected through a planarization layer via in the planarization layer.

[0013] For example, in a display substrate provided in one embodiment of this disclosure, the pixel driving circuit includes a storage capacitor, a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The first electrode of the storage capacitor and the gate of the driving transistor are connected to a first node. The second electrode of the first light-emitting control transistor and the first electrode of the driving transistor are connected to a second node. The second electrode of the driving transistor and the first electrode of the second light-emitting control transistor are connected to a third node. The second electrode of the second light-emitting control transistor and the light-emitting element are connected to a fourth node. The at least one constant voltage signal line includes a first constant voltage signal line, which includes a first lateral sub-constant voltage signal line extending along the first direction and a first longitudinal sub-constant voltage signal line extending along the second direction. The first lateral sub-constant voltage signal line is configured to provide a first initialization signal to the first node of a plurality of pixel units in a pixel unit row. The at least one constant voltage signal line includes a second constant voltage signal line, which includes a second lateral sub-constant voltage signal line extending along the first direction and a second longitudinal sub-constant voltage signal line extending along the second direction. The second lateral sub-constant voltage signal line is configured to provide a second initialization signal to the fourth node of a plurality of pixel units in a pixel unit row.

[0014] For example, in a display substrate provided in an embodiment of this disclosure, the plurality of data line pairs include a first data line pair and a second data line pair, wherein the first vertical sub-constant voltage signal line is located between the first data line and the second data line in the first data line pair, and the second vertical sub-constant voltage signal line is located between the first data line and the second data line in the second data line pair.

[0015] For example, in a display substrate provided in an embodiment of this disclosure, the at least one constant voltage signal line includes a third constant voltage signal line, the third constant voltage signal line including a third lateral sub-constant voltage signal line extending along the first direction and a third longitudinal sub-constant voltage signal line extending along the second direction, the third lateral sub-constant voltage signal line being configured to provide a third initialization signal to the second node in a plurality of pixel units in a pixel unit row.

[0016] For example, in a display substrate provided in an embodiment of this disclosure, the plurality of data line pairs include a first data line pair, a second data line pair, and a third data line pair. The first vertical sub-constant voltage signal line is located between the first data line and the second data line in the first data line pair, the second vertical sub-constant voltage signal line is located between the first data line and the second data line in the second data line pair, and the third vertical sub-constant voltage signal line is located between the first data line and the second data line in the third data line pair.

[0017] For example, in a display substrate provided in an embodiment of this disclosure, the first longitudinal sub-constant voltage signal line, the second longitudinal sub-constant voltage signal line, and the third longitudinal sub-constant voltage signal line are arranged sequentially in the first direction.

[0018] For example, in a display substrate provided in one embodiment of this disclosure, at least two of the number of the first vertical sub-constant voltage signal lines, the number of the second vertical sub-constant voltage signal lines, and the number of the third vertical sub-constant voltage signal lines are not equal throughout the entire display substrate.

[0019] For example, in a display substrate provided in one embodiment of this disclosure, the number of the second vertical sub-constant voltage signal lines is greater than the number of the first vertical sub-constant voltage signal lines and the number of the third vertical sub-constant voltage signal lines throughout the entire display substrate.

[0020] For example, in a display substrate provided in one embodiment of this disclosure, a second lead is provided between two adjacent data pairs in the first display area in the first direction; or, two second leads are provided between two adjacent data pairs in the first display area in the first direction.

[0021] For example, in a display substrate provided in one embodiment of this disclosure, the first terminal of the compensation transistor is connected to the first node, the second terminal of the compensation transistor is connected to the third node, the first terminal of the first initialization transistor is connected to the first constant voltage signal line, the second terminal of the first initialization transistor is connected to the first node, and the second lead is located between the two compensation transistors of two adjacent pixel driving circuits.

[0022] For example, in a display substrate provided in one embodiment of this disclosure, the pixel driving circuit further includes an isolation transistor, and the compensation transistor is connected to the first node through the isolation transistor.

[0023] For example, a display substrate provided in one embodiment of this disclosure further includes: the material of the first semiconductor layer includes a silicon-based semiconductor, and the material of the second semiconductor includes a metal oxide semiconductor.

[0024] At least one embodiment of this disclosure also provides a display device, which includes a display substrate according to any one of the preceding claims and a power supply component for providing electrical power to the display substrate. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 is a partial planar schematic diagram of a display substrate;

[0027] Figure 2 shows the way the data lines are led out in the display substrate shown in Figure 1;

[0028] Figure 3 shows the connection structure between the data lines and the lead-out lines in the display substrate shown in Figure 1;

[0029] Figure 4 is a partial planar schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0030] Figure 5 shows the lead-out method of the data lines in the display substrate shown in Figure 4;

[0031] Figure 6 shows the connection structure between the data lines and the lead-out lines in the display substrate shown in Figure 4;

[0032] Figure 7 is a cross-sectional schematic diagram of a pixel unit in a display substrate according to an embodiment of the present disclosure;

[0033] Figure 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0034] Figure 9 is a plan view of different constant voltage signal lines in a display substrate according to an embodiment of the present disclosure;

[0035] Figure 10 is a plan view of a display substrate provided in an embodiment of the present disclosure;

[0036] Figures 11-21 are schematic planar views of multiple film layers in the display substrate shown in Figure 10;

[0037] Figure 22 is a plan view of another display substrate provided in an embodiment of the present disclosure;

[0038] Figure 23 is a plan view of another display substrate provided in an embodiment of this disclosure; and

[0039] Figure 24 is a schematic diagram of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0042] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain errors. Considering measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two. In the embodiments of this disclosure, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). Here, "same layer" does not always mean that multiple film layers have the same thickness or that multiple film layers have the same height in a cross-sectional view.

[0043] Unless otherwise defined, a transistor as described in this disclosure refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor also includes a channel region located between the source (source terminal, source region, or source electrode) and the drain (drain terminal, drain region, or drain electrode); this channel region can be switched between an on state and a non-conducting state by controlling the gate, thereby enabling the transistor to function as a switching element. The source can be the first terminal of the transistor, and the drain can be the second terminal, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the source and drain can sometimes be interchanged. Therefore, in this disclosure, the source and drain can be interchanged.

[0044] To reduce the bezel width, FIP (Fanout In Pixel) technology can be used to set a second lead-out line in the display area. The data line corresponding to the rounded corner of the display substrate is first transferred to the middle area of ​​the display area, and then led out from the middle area to the bonding area.

[0045] Figure 1 is a partial planar schematic diagram of a display substrate; Figure 2 shows the lead-out method of the data lines in the display substrate shown in Figure 1; Figure 3 shows the connection structure between the data lines and the lead-out lines in the display substrate shown in Figure 1. It should be noted that the different colored patterns in Figure 3 represent different film layers.

[0046] As shown in Figures 1 and 2, the display substrate 10 includes multiple pixel units 20. Each pixel unit 20 includes a pixel driving circuit 22 and a light-emitting element (not shown) electrically connected to the pixel driving circuit 22. The pixel driving circuit 22 can drive the light-emitting element to emit light for display. The display substrate 10 also includes a data line 12 that provides data signals to the pixel driving circuit 22. The data line 12 extends generally in a vertical direction. Since the data line 12 requires a source driving circuit (Source IC) to provide data signals, the data line needs to be connected to a bonding area in the peripheral area outside the display area of ​​the display substrate and electrically connected to the source driving circuit located in the bonding area. For example, the pixel driving circuit 22 can output currents of different magnitudes, and the light-emitting element can emit light of corresponding brightness in response to the current output by the pixel driving circuit.

[0047] As shown in Figures 1 and 2, the display substrate 10 also includes a first lead 14 and a second lead 16. The first lead 14 extends laterally, and the second lead 16 extends longitudinally. One end of the first lead 14 is connected to the data line 12, and the other end is connected to the second lead 16. Thus, the first lead 14 and the second lead 16 can connect the data line 12 in the edge area of ​​the display area of ​​the display substrate 10 to the bonding area, thereby eliminating the need to occupy space in the peripheral area outside the edge area of ​​the display area and reducing the bezel width.

[0048] As shown in Figures 1 and 2, the display substrate 10 also includes an initialization signal line 18 for providing an initialization signal to the pixel driving circuit. This initialization signal line 18 typically includes a laterally extending portion and a vertically extending portion, which are electrically connected to form a mesh-like conductive structure, thereby reducing resistance and voltage drop. It should be noted that the aforementioned initialization signal is a constant voltage signal, thus enabling the formation of the mesh-like conductive structure and increasing the uniformity of the initialization signal for each pixel unit on the entire display substrate. Similarly, the display substrate may also include other constant voltage signal lines for transmitting constant voltage signals. It should be noted that in Figure 2, except for the first lead, the second lead, and the connection structure between the first and second leads, the other structures are simplified.

[0049] As shown in Figures 1 and 2, in LTPO (Low Temperature Polysilicon Oxide) products, due to layout space limitations, adjacent pixel driving circuits in the horizontal direction are designed symmetrically, resulting in the two data lines connected to these two pixel driving circuits being relatively close together. In this case, to facilitate connection with data line 12 and reduce the length of the first lead 14, the second lead 16 is placed between adjacent data lines 12. It should be noted that the aforementioned LTPO product refers to a display substrate where the pixel driving circuit uses both low temperature polysilicon transistors and oxide transistors.

[0050] However, since data line 12 transmits a transition signal, not a constant voltage signal, the first lead 14 and the second lead 16 connected to data line 12 also transmit transition signals. These transition signals can easily cause interference or crosstalk to signals on adjacent signal lines. The first lead 14, extending laterally, can be shielded and blocked by other laterally extending signal lines transmitting constant voltage signals, thus reducing the risk of crosstalk. However, the second lead 16 is located between adjacent data lines 12, and the distance between these two data lines 12 is relatively short. The signal on the second lead 16 can easily cause crosstalk to the signals on these two data lines 12. Furthermore, the second lead 16 typically requires a via connection structure to electrically connect portions located on different conductive layers, and this via connection structure increases the unevenness of the anode above it. In addition, to reduce the risk of ESD (electrostatic discharge), the second lead 16 needs to be jumpered, i.e., jumpered through two planarization vias 17. However, these two planarization vias 17 will affect the flatness of the effective light-emitting area of ​​the anode above it. In the area where the adjacent data lines 12 are located, the two data lines 12 themselves are connected to the pixel driving circuit through two planarization vias 19. Therefore, there are already at least two planarization vias 19 in the area where these two data lines 12 are located. If the second lead 16 is placed between these two data lines 12, it will be difficult for the effective light-emitting area of ​​the anode to completely avoid these four planarization vias 17 and 19, thereby adversely affecting the flatness of the effective light-emitting area of ​​the anode and causing defects such as color shift.

[0051] On the other hand, as shown in Figures 2 and 3, due to the limited space between adjacent data lines 12, the position selection of the two planar layer vias 19 of the second lead 16 is also limited. Therefore, in order to electrically connect the second lead 16 with the first lead 14, a connection structure 33 needs to be set in the first source-drain metal layer. Some connection structures 33 are too long, which will not only affect the resistance of the lead, but also cause the pixel unit 20 with the connection structure 33 to differ from other pixel units 20 without the connection structure 33, which can easily lead to visual defects.

[0052] In this embodiment, a display substrate is provided, comprising a substrate, a plurality of pixel units, and a plurality of data lines; the plurality of pixel units are arrayed on the substrate along a first direction and a second direction; the plurality of data lines are located on the substrate and arranged along the first direction, and each data line extends along the second direction; the plurality of pixel units are divided into a plurality of pixel unit columns arranged along the first direction, each pixel unit column including a plurality of pixel units arranged along the second direction, and each data line is configured to provide a data signal to the plurality of pixel units in a pixel unit column; the plurality of pixel units are divided into a plurality of pixel unit rows arranged along the second direction, each pixel unit row including a plurality of pixel units arranged along the first direction; the display substrate further includes at least one constant voltage signal line, the constant voltage signal line including a transverse sub-constant voltage signal line extending along the first direction and a longitudinal sub-constant voltage signal line extending along the second direction, the transverse sub-constant voltage signal line... It is configured to provide a constant voltage signal to multiple pixel units in a pixel unit row; multiple data lines include multiple data line pairs, each data line pair including a first data line and a second data line adjacent in a first direction, a first distance between the first data line and the second data line in a data line pair is less than a second distance between two adjacent data line pairs, and a longitudinal sub-constant voltage signal line is located between the first data line and the second data line in a data line pair; the display substrate includes a display area and a peripheral area, the display area includes a first display area and two second display areas located on both sides of the first display area, the display substrate also includes a first lead and a second lead, the first lead is connected to the data lines in the second display areas and extends from the second display areas to the first display areas, the second lead is located in the first display area, connected to the first lead and extends from the first display area to the peripheral area, and the second lead is located between two adjacent data line pairs.

[0053] In the display substrate provided in this embodiment, by providing the aforementioned first and second leads to connect the data lines in the second display area to the peripheral area, the display substrate does not need to provide leads in the peripheral area outside the second display area, thereby reducing the bezel width. By providing a vertical sub-constant voltage signal line between the first and second data lines in a data line pair, the display substrate can not only utilize the space between the first and second data lines to arrange the vertical sub-constant voltage signal line extending along the second direction, but also utilize the vertical sub-constant voltage signal line to reduce signal crosstalk between the first and second data lines. Furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead between the first and second data lines in a data line pair, thus avoiding interference between the first and second data lines on the signals on the second lead. On the other hand, to reduce ESD (electrostatic discharge) risks, the second lead extending along the second direction requires a jumper design, i.e., jumpering via two planarization vias. These two planarization vias affect the flatness of the effective light-emitting area of ​​the anode above it. In the area where the data line pairs are located, the two data lines themselves are connected to the pixel driving circuit through two planarization vias. Therefore, at least two planarization vias already exist in the area where the data line pairs are located. If the second lead is placed between the first and second data lines in the data line pair, it will be difficult for the effective light-emitting area of ​​the anode to completely avoid these four planarization vias, thus adversely affecting the flatness of the effective light-emitting area of ​​the anode, leading to defects such as color shift. Therefore, by placing the second lead in the area between two adjacent data line pairs, rather than in the area between the first and second data lines in a single data line pair, this display substrate also avoids the jumper design of the second lead affecting the flatness of the anode, thereby improving the flatness of the anode and reducing defects such as color shift. In summary, this display substrate not only reduces the bezel width but also optimizes the layout design on the display substrate and improves display quality.

[0054] This disclosure also provides a display device including the aforementioned display substrate. Therefore, this display device can also reduce signal crosstalk between the first and second data lines in a data line pair and improve the flatness of the anode, thereby reducing color shift.

[0055] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0056] Figure 4 is a partial planar schematic diagram of a display substrate according to an embodiment of this disclosure. Figure 5 shows the lead-out method of the data lines in the display substrate shown in Figure 4; Figure 6 shows the connection structure between the data lines and the lead-out lines in the display substrate shown in Figure 4. It should be noted that the different colored patterns in Figures 4 to 6 represent different film layers.

[0057] As shown in Figures 4 and 5, the display substrate 100 includes a substrate 110, a plurality of pixel units 120, and a plurality of data lines 130. The plurality of pixel units 120 are arrayed on the substrate 110 along a first direction X and a second direction Y. The plurality of data lines 130 are located on the substrate 110 and arranged along the first direction X, and each data line 130 extends along the second direction Y. Since the plurality of pixel units 120 are arrayed, the plurality of pixel units 120 are divided into a plurality of pixel unit columns 141 arranged along the first direction X. Each pixel unit column 141 includes a plurality of pixel units 120 arranged along the second direction Y. Each data line 130 is configured to provide a data signal to at least a portion of the plurality of pixel units 120 in a pixel unit column 141.

[0058] For example, multiple data lines 130 and multiple pixel unit columns 141 can be configured in a one-to-one correspondence, with one data line 130 providing a data signal for one pixel unit column 141. Of course, embodiments of this disclosure include, but are not limited to, multiple data lines 130 may provide data signals for one pixel unit column 141, or one data line 130 may provide data signals for multiple pixel unit columns 141.

[0059] As shown in Figures 4 and 5, since the multiple pixel units 120 are arrayed, the multiple pixel units 120 can also be divided into multiple pixel unit rows 142 arranged along the second direction Y. Each pixel unit row 142 includes multiple pixel units 120 arranged along the first direction X. The display substrate 100 also includes at least one constant voltage signal line 150. The constant voltage signal line 150 includes a horizontal sub-constant voltage signal line 151 extending along the first direction X and a vertical sub-constant voltage signal line 152 extending along the second direction Y. The horizontal sub-constant voltage signal line 151 is configured to provide a constant voltage signal to the multiple pixel units 120 in a pixel unit row 142. The vertical sub-constant voltage signal line 152 is electrically connected to the horizontal sub-constant voltage signal line 151. It should be noted that the horizontal sub-constant voltage signal line 151 and the vertical sub-constant voltage signal line 152 can form a mesh conductive structure, thereby reducing the overall resistance and voltage drop of the constant voltage signal line 151, making the constant voltage signal provided to each pixel unit 120 on the display substrate 100 more uniform, thereby improving the display quality.

[0060] As shown in Figures 4 and 5, in the display substrate 100, the plurality of data lines 130 include a plurality of data line pairs 170. Each data line pair 170 includes a first data line 131 and a second data line 132 that are adjacent in the first direction X. The first distance D1 between the first data line 131 and the second data line 132 in a data line pair 170 is less than the second distance D2 between two adjacent data line pairs 170. The first distance D1 between the first data line 131 and the second data line 132 can be the distance between the edge of the first data line 131 and the edge of the second data line 132. The second distance D2 between two adjacent data line pairs 170 can be the distance between the oppositely arranged edges of two adjacent data line pairs 170. That is, the distance between two data lines in a data line pair is less than the distance between adjacent data line pairs.

[0061] For example, as shown in Figures 4 and 5, the second distance D2 mentioned above is three times greater than the first distance D1.

[0062] As shown in Figures 4 and 5, the longitudinal sub-constant voltage signal line 152 is located between the first data line 131 and the second data line 132 in a data line pair 170; that is, the orthogonal projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 is located between the orthogonal projections of the first data line 131 and the second data line 132 on the substrate 110 in a data line pair 170.

[0063] As shown in Figures 4 and 5, the display substrate 100 includes a display area 210 and a peripheral area 220. The display area 210 includes a first display area 210A and two second display areas 210B located on both sides of the first display area 210A (Figures 4 and 5 only show one side of the second display area 210B). The display substrate 100 also includes a first lead 161 and a second lead 162. The first lead 161 is connected to the data line 130 in the second display area 210B and extends from the second display area 210B to the first display area 210A. The second lead 162 is located in the first display area 210A, is electrically connected to the first lead 161, and extends from the first display area 210 along the second direction Y to the peripheral area 220. The second lead 162 is located between two adjacent data line pairs 170.

[0064] As shown in Figure 5, the second data line 132 in the data line pair 170 closest to the first display area 210A in the second display area 210B can be connected to the second data line 162 closest to the second display area 210B in the first display area 210A via a first lead 161. This allows data signals to be applied to the second data line 132 in the data line pair 170 closest to the first display area 210A in the second display area 210B by applying a data signal to the second lead 162. Similarly, the first data line 131 in the data line pair 170 closest to the first display area 210A in the second display area 210B can be connected to another second lead 162 in the first display area 210A via another first lead 161. This allows data signals to be applied to the first data line 131 in the data line pair 170 closest to the first display area 210A in the second display area 210B by applying a data signal to the second lead 162.

[0065] In the display substrate provided in this embodiment, by providing the aforementioned first and second leads to connect the data lines in the second display area to the peripheral area, the display substrate does not need to provide leads in the peripheral area outside the second display area, thereby reducing the bezel width. By providing a vertical sub-constant voltage signal line between the first and second data lines in a data line pair, the display substrate can not only utilize the space between the first and second data lines to arrange the vertical sub-constant voltage signal line extending along the second direction, but also utilize the vertical sub-constant voltage signal line to reduce signal crosstalk between the first and second data lines. Furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead between the first and second data lines in a data line pair, thus avoiding interference between the first and second data lines on the signals on the second lead.

[0066] On the other hand, to reduce ESD (electrostatic discharge) risks, the second lead extending along the second direction requires a jumper design, i.e., jumpering via two planarization vias. These two planarization vias affect the flatness of the effective light-emitting area of ​​the anode above it. In the area where the data line pairs are located, the two data lines themselves are connected to the pixel driving circuit through two planarization vias. Therefore, at least two planarization vias already exist in the area where the data line pairs are located. If the second lead is placed between the first and second data lines in the data line pair, it will be difficult for the effective light-emitting area of ​​the anode to completely avoid these four planarization vias, thus adversely affecting the flatness of the effective light-emitting area of ​​the anode, leading to defects such as color shift. Therefore, by placing the second lead in the area between two adjacent data line pairs, rather than the area between the first and second data lines in a single data line pair, the display substrate can also avoid the jumper design of the second lead affecting the flatness of the anode, thereby improving the flatness of the anode and reducing defects such as color shift. It should be noted that the effective light-emitting area of ​​the anode mentioned above refers to the area where the anode contacts the light-emitting layer, i.e., the opening area of ​​the anode.

[0067] In summary, this display substrate not only reduces the bezel width but also optimizes the layout design on the display substrate and improves the display quality.

[0068] It should be noted that the red, green, and blue wiring patterns in Figure 5 can represent different signal transmission paths, and wiring patterns of the same color connect to the same signal. For example, a red wiring pattern can represent a data signal in one data line 130 of the second display area 210B, which is introduced from the first display area 210A, transmitted through the second lead-out line 162 and the first lead-out line 161, and loaded onto the data line 130; a blue wiring pattern can represent a data signal in another data line 130 of the second display area 210B, which is introduced from the first display area 210A, transmitted through another second lead-out line 162 and another first lead-out line 161, and loaded onto the other data line 130.

[0069] For example, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments disclosed herein include, but are not limited to, the first direction X and the second direction Y may also intersect and not be perpendicular.

[0070] In some examples, the constant voltage signal line 150 is configured to provide an initialization signal to a plurality of pixel units 120. That is, the constant voltage signal line 150 is an initialization signal line. On the one hand, since the initialization signal is a constant voltage signal, by setting the initialization signal line between the first data line and the second data line in a data line pair, the display substrate can not only utilize the space between the first data line and the second data line to arrange the initialization signal line, but also utilize the initialization signal line to reduce signal crosstalk between the first data line and the second data line. Of course, embodiments of this disclosure include, but are not limited to, the aforementioned constant voltage signal line can also be other constant voltage signal lines.

[0071] In some examples, as shown in Figure 4, the vertical sub-constant voltage signal line 152 is arranged on the same layer as the first data line 131 and the second data line 132. That is, the vertical sub-constant voltage signal line 152, located between the first data line 131 and the second data line 132 in a data line pair 170, is arranged on the same layer as the first data line 131 and the second data line 132. Therefore, the display substrate can better reduce signal crosstalk between the first data line and the second data line.

[0072] In some examples, as shown in Figures 5 and 6, the display substrate 100 further includes a first lead-out adapter 163, a first end of which is connected to a first lead 161, and a second end of which is connected to a second lead 162. The orthographic projection of the first lead-out adapter 163 on the substrate 110 is covered by the orthographic projection of the second lead 162 on the substrate 110. It should be noted that the aforementioned coverage refers to the fact that more than 90% of the area of ​​the orthographic projection of the first lead-out adapter on the substrate is covered by the orthographic projection of the second lead on the substrate.

[0073] In the display substrate provided in this example, since there is ample space for wiring between the pixel driving circuits of two adjacent pixel unit columns, there are many possible locations for the two planarization layer vias of the second lead. Therefore, they can be positioned close to the first lead, thereby shortening the length of the first lead adapter. Furthermore, in the direction perpendicular to the substrate, the first lead adapter can be positioned below the second lead, meaning that the orthographic projection of the first lead adapter on the substrate is covered by the orthographic projection of the second lead on the substrate. This prevents the first lead adapter from being observed, avoids inconsistencies in patterns across different areas of the display substrate, and ultimately improves the display quality of the display substrate.

[0074] In some examples, as shown in Figures 5 and 6, the display substrate 100 further includes a second lead-out adapter 164; a first end of the second lead-out adapter 164 is connected to the first lead-out line 161, and a second end of the second lead-out adapter 164 is connected to the data line 130; the orthographic projection of the second lead-out adapter 164 on the substrate 110 is covered by the orthographic projection of the data line 130 on the substrate 110. It should be noted that the aforementioned coverage means that more than 90% of the area of ​​the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate.

[0075] In the display substrate provided in this example, since the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate, the second lead-out adapter can be avoided from being observed, thus avoiding different patterns in different areas of the display substrate and improving the display quality of the display substrate.

[0076] In some examples, as shown in Figures 5 and 6, the display substrate 100 further includes a first source / drain metal layer 230, a planarization layer, and a second source / drain metal layer 250; the first source / drain metal layer 230 is located on the substrate 110; the planarization layer is located on the side of the first source / drain metal layer 230 away from the substrate 110; and the second source / drain metal layer 250 is located on the side of the planarization layer away from the first source / drain metal layer 230. It should be noted that the planarization layer is an insulating film layer located between the first and second source / drain metal layers, and this planarization layer is transparent in Figures 4 and 5.

[0077] In some examples, as shown in Figures 5 and 6, the second lead 162 includes a first conductive portion 162A located in the first source / drain metal layer 230 and a second conductive portion 162B located in the second source / drain metal layer 250. The first conductive portion 162A and the second conductive portion 162B are electrically connected through a planarization via 242 in the planarization layer. Thus, this second lead, through a jumper design, avoids forming a continuously extending long straight conductive structure, thereby reducing the risk of electrostatic discharge.

[0078] It should be noted that the first and second source / drain metal layers here are used to define the film layer relationship between the two conductive portions of the second lead, and do not limit the display substrate to having only two source / drain metal layers. For example, the display substrate may include two or three source / drain metal layers; when the display substrate includes two source / drain metal layers, the first and second source / drain metal layers mentioned above may be two source / drain metal layers stacked sequentially in a direction perpendicular to the substrate; when the display substrate includes three source / drain metal layers, the first and second source / drain metal layers mentioned above may be any two of the three source / drain metal layers stacked sequentially in a direction perpendicular to the substrate, as long as the above positional relationship is satisfied.

[0079] In some examples, as shown in Figures 5 and 6, the first lead 161 is located in the first source / drain metal layer 230, and the first lead-out adapter 163 can also be located in the first source / drain metal layer 230, so that it can be directly connected to the first lead 161 without the need for vias. Of course, embodiments of this disclosure include, but are not limited to, the first lead 161 and the first lead-out adapter 163 can also be located in the second source / drain metal layer 250.

[0080] In some examples, as shown in Figures 5 and 6, a first lead 161 extends along a first direction X, and a first lead adapter 163 extends outward from the first lead 161 along a second direction Y at the location where the second lead 162 intersects with the first lead 161, and is covered by the second lead 162. One end of the first lead adapter 163 is electrically connected to the second lead 162 through a planarization via 244 in the planarization layer.

[0081] In some examples, the substrate described above can be a rigid substrate or a flexible substrate, and this disclosure does not impose any limitations. When the substrate is a rigid substrate, it can be a glass substrate, a quartz substrate, a sapphire substrate, a plastic substrate, etc. When the substrate is a flexible substrate, it can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen; the first and second inorganic material layers can also be referred to as barrier layers.

[0082] In some examples, the materials of the first and second source / drain metal layers described above can be conductive metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first and second source / drain metal layers described above can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo or Ti / Al / Ti, etc.

[0083] In some examples, as shown in Figures 4 and 5, a second lead 162 is provided between two adjacent data pairs 170 in the first direction X in the first display area 210A. That is, the display substrate adopts a 2-in-1 design. Of course, embodiments of this disclosure include, but are not limited to, the display substrate may also have two second leads between two adjacent data pairs in the first direction, i.e., a 1-in-1 design.

[0084] Figure 7 is a cross-sectional schematic diagram of a pixel unit in a display substrate according to an embodiment of the present disclosure;

[0085] Figure 8 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0086] Figure 9 is a plan view of different constant voltage signal lines in a display substrate according to an embodiment of this disclosure. It should be noted that the different colored patterns in Figure 9 represent different film layers.

[0087] As shown in Figure 7, each pixel unit 120 includes a pixel driving circuit 122 and a light-emitting element 124. The pixel driving circuit 122 and the light-emitting element 124 are electrically connected and configured to drive the light-emitting element 124 to emit light. Each light-emitting element 124 includes an anode 1241, a cathode 1242, and an organic light-emitting functional layer 1243 located between the anode 1241 and the cathode 1242. The organic light-emitting functional layer 1243 may include an organic light-emitting layer for emitting light and an auxiliary functional layer for assisting in emitting light. It should be noted that the above-mentioned auxiliary functional layer may include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc. Of course, the disclosed embodiments are not limited to this, and the above-mentioned light-emitting element may also be other types of light-emitting elements.

[0088] For example, as shown in FIG7, the display substrate 100 further includes a pixel defining layer 290, and each pixel unit 120 further includes a pixel opening 295 located in the pixel defining layer 290. The pixel opening 295 exposes a portion of the anode 1241, and the organic light-emitting functional layer 1243 is in contact with the portion of the anode 1241 exposed by the pixel opening 295. In this case, the area corresponding to the pixel opening 295 can be the effective light-emitting area of ​​the pixel unit or the anode.

[0089] As shown in Figure 8, the pixel driving circuit 122 includes a storage capacitor Cst, a driving transistor T3, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. The first electrode of the storage capacitor Cst and the gate of the driving transistor T3 are connected to a first node N1. The second electrode of the first light-emitting control transistor T5 and the first electrode of the driving transistor T3 are connected to a second node N2. The second electrode of the driving transistor T3 and the first electrode of the second light-emitting control transistor T6 are connected to a third node N3. The second electrode of the second light-emitting control transistor T6 and the light-emitting element 124 are connected to a fourth node N4. It should be noted that although Figure 8 shows a pixel driving circuit with a 9T1C structure, the embodiments of this disclosure include, but are not limited to, this pixel driving circuit, which can also adopt a 7T1C structure and an 8T1C structure.

[0090] As shown in Figures 8 and 9, the aforementioned at least one constant voltage signal line 150 includes a first constant voltage signal line 150A. The first constant voltage signal line 150A includes a first lateral sub-constant voltage signal line 151A extending along a first direction X and a first longitudinal sub-constant voltage signal line 152A extending along a second direction Y. The first lateral sub-constant voltage signal line 151A is configured to provide a first initialization signal Vinit1 to a first node N1 in a plurality of pixel units in a pixel unit row, thereby initializing the first node N1. That is, the aforementioned first constant voltage signal line 150A is a first initialization signal line INIT1. Thus, the display substrate can place the longitudinal extension portion of the first initialization signal line INIT1, which transmits the first initialization signal Vinit1, i.e., the first longitudinal sub-constant voltage signal line, between the first data line and the second data line in a data line pair. This allows the space between the first data line and the second data line to be used to arrange the first longitudinal sub-constant voltage signal line extending along the second direction, and also allows the first longitudinal sub-constant voltage signal line to be used to reduce signal crosstalk between the first data line and the second data line. It should be noted that, in order to clearly show the connection methods of different constant voltage signal lines, Figure 9 does not show all the film layers.

[0091] In some examples, as shown in Figures 8 and 9, at least one constant voltage signal line 150 described above includes a second constant voltage signal line 150B. The second constant voltage signal line 150B includes a second lateral sub-constant voltage signal line 151B extending along a first direction X and a second longitudinal sub-constant voltage signal line 152B extending along a second direction Y. The second lateral sub-constant voltage signal line 152B is configured to provide a second initialization signal Vinit2 to a fourth node N4 in a plurality of pixel units 120 in a pixel unit row 142, thereby initializing the fourth node N4. That is, the second constant voltage signal line 150B is the second initialization signal line INIT2. Thus, the display substrate can place the longitudinal extension portion of the second initialization signal line INIT2, which transmits the second initialization signal Vinit2, i.e., the second longitudinal sub-constant voltage signal line, between the first data line and the second data line in a data line pair. This allows the space between the first data line and the second data line to be used to arrange the second longitudinal sub-constant voltage signal line extending along the second direction, and also allows the use of the second longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line.

[0092] As shown in Figure 9, the multiple data line pairs 170 include a first data line pair 170A and a second data line pair 170B. The first longitudinal sub-constant voltage signal line 152A is located between the first data line 131 and the second data line 132 in the first data line pair 170A, and the second longitudinal sub-constant voltage signal line 152B is located between the first data line 131 and the second data line 132 in the second data line pair 170B. That is, the longitudinal extensions of different initialization signal lines are located in different data line pairs.

[0093] As shown in Figures 8 and 9, the aforementioned at least one constant voltage signal line 150 includes a third constant voltage signal line 150C. The third constant voltage signal line 150C includes a third lateral sub-constant voltage signal line 151C extending along a first direction X and a third longitudinal sub-constant voltage signal line 152C extending along a second direction Y. The third lateral sub-constant voltage signal line 151C is configured to provide a third initialization signal Vinit3 to a second node N2 in a plurality of pixel units 120 in a pixel unit row 142. In other words, the aforementioned third constant voltage signal line 150C is the third initialization signal line INIT3. Therefore, the display substrate can place the longitudinal extension portion of the third initialization signal line INIT3, which transmits the third initialization signal Vinit3, i.e., the third longitudinal sub-constant voltage signal line, between the first data line and the second data line in a data line pair. This allows the space between the first and second data lines to be used to arrange the third longitudinal sub-constant voltage signal line extending along the second direction, and also allows the use of the third longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first and second data lines.

[0094] In some examples, as shown in Figures 8 and 9, multiple data line pairs 170 include a first data line pair 170A, a second data line pair 170B, and a third data line pair 170C. A first longitudinal sub-constant voltage signal line 152A is located between the first data line 131 and the second data line 132 in the first data line pair 170A. A second longitudinal sub-constant voltage signal line 152B is located between the first data line 131 and the second data line 132 in the second data line pair 170B. A third longitudinal sub-constant voltage signal line 152C is located between the first data line 131 and the second data line 132 in the third data line pair 170C.

[0095] It should be noted that the first constant voltage signal line, the second constant voltage signal line, and the third constant voltage signal line transmit different constant voltage signals, therefore the first constant voltage signal line, the second constant voltage signal line, and the third constant voltage signal line are not electrically connected to each other.

[0096] In some examples, at least two of the numbers of the second, first, and third vertical sub-constant voltage signal lines are different in the display substrate. As mentioned above, the first, second, and third constant voltage signal lines transmit different constant voltage signals and are not electrically connected to each other. Since the number of data line pairs on the display substrate is limited, the more vertical sub-constant voltage signal lines there are, the smaller the resistance and voltage drop of the constant voltage signal lines will be. Therefore, the number of vertical sub-constant voltage signal lines can be set as needed.

[0097] In some examples, the number of second vertical sub-constant voltage signal lines in the display substrate is greater than the number of first and third vertical sub-constant voltage signal lines. Since the second constant voltage signal lines are configured to provide a second initialization signal to the fourth node, which is used to initialize the anode of the light-emitting element, having a greater number of second vertical sub-constant voltage signal lines than the first and third vertical sub-constant voltage signal lines can significantly improve the display quality of the display substrate. It should be noted that the embodiments disclosed herein include, but are not limited to, this; the number of first, second, and third vertical sub-constant voltage signal lines can be set according to actual conditions.

[0098] In some examples, as shown in FIG9, the first longitudinal sub-constant voltage signal line 152A, the second longitudinal sub-constant voltage signal line 152B, and the third longitudinal sub-constant voltage signal line 152C are arranged sequentially along the first direction X. Thus, the display can substantially better arrange the first longitudinal sub-constant voltage signal line 152A, the second longitudinal sub-constant voltage signal line 152B, and the third longitudinal sub-constant voltage signal line 152C. Of course, embodiments of this disclosure include, but are not limited to, this.

[0099] In some examples, as shown in FIG8, the pixel driving circuit 122 further includes a compensation transistor T2 and a first initialization transistor T1. The first terminal of the compensation transistor T2 is connected to the first node N1, for example, it can be connected to the first node N1 through an isolation transistor T9; the second terminal of the compensation transistor T2 is connected to the third node N3. The first terminal of the first initialization transistor T1 is connected to the first constant voltage signal line 150A, and the second terminal of the first initialization transistor T1 is connected to the first node N1, for example, it can be connected to the first node N1 through an isolation transistor T9. It should be noted that the pixel driving circuit shown in FIG8 is provided with an isolation transistor, but the embodiments of this disclosure include, but are not limited to, this, and the pixel driving circuit may also not be provided with the above-mentioned isolation transistor.

[0100] In some examples, as shown in Figure 9, the second lead 162 is located between two compensation transistors T2 of two adjacent pixel driving circuits 122. Thus, the display substrate can make full use of the space on the display substrate, improving the compactness of the layout.

[0101] In some examples, as shown in Figure 9, the two pixel driving circuits 122 located on both sides of the second lead 162 are mirror symmetrical, so that the two data lines of the two pixel driving circuits 122 are close to each other to form the above-mentioned data line pair.

[0102] In some examples, as shown in FIG9, the active layers of the compensation transistor T2 and the first initialization transistor T1 are connected to form a semiconductor block 2625 located in the second semiconductor layer 262, and the second lead 162 is located between the two semiconductor blocks 2625 of two adjacent pixel driving circuits 122. Thus, the display substrate can fully utilize the space on the display substrate, improving the compactness of the layout. It should be noted that the aforementioned semiconductor block refers to a block made of semiconductor material, which may include a conductive portion after a conductor-forming process. In some examples, as shown in FIG8, the first initialization signal line INIT1 is connected to the first terminal of the first initialization transistor T1. The pixel driving circuit 122 also includes a second initialization transistor T7, the first terminal of which is connected to the second initialization signal line INIT2, and the second terminal of which is connected to the fourth node N4. That is, the second terminal of the second initialization transistor T7 and the second terminal of the second light-emitting control transistor T6 are connected to the light-emitting element 124 and connected to the fourth node N4. Thus, when the second initialization transistor T7 is turned on, the second initialization signal line INIT2 can initialize the fourth node N4.

[0103] In some examples, as shown in Figure 8, the pixel driving circuit 122 further includes a third initialization transistor T8. The first terminal of the third initialization transistor T8 is connected to the third constant voltage signal line 150C, and the second terminal of the third initialization transistor T8 is connected to the second node N2. That is, the second terminal of the first light-emitting control transistor T5, the first terminal of the driving transistor T3, and the second terminal of the third initialization transistor T8 are connected and then connected to the second node N2. Thus, when the third initialization transistor T8 is turned on, the third constant voltage signal line 150C can initialize the second node N2.

[0104] In some examples, as shown in Figure 8, the pixel driving circuit 122 further includes a data writing transistor T4, the first terminal of which is configured to be connected to a data line, and the second terminal of which is connected to the second node N2. The first plate of the storage capacitor Cst and the first terminal of the first light-emitting control transistor T5 are both connected to the power supply line VDD.

[0105] In some examples, the transistors in the pixel driving circuit can be P-type transistors, N-type transistors, or a combination of both.

[0106] In some examples, the aforementioned driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, third initialization transistor T8, and isolation transistor T9 can be low-temperature polycrystalline silicon transistors. That is, the active layer material of the aforementioned driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, third initialization transistor T8, and isolation transistor T9 is low-temperature polycrystalline silicon. The aforementioned first initialization transistor T1 and compensation transistor T2 can be oxide transistors; that is, the active layer of the aforementioned first initialization transistor T1 and compensation transistor T2 can be a metal-oxide-semiconductor, such as indium gallium tin oxide or indium gallium zinc oxide.

[0107] In some examples, in this pixel driving circuit, the first initialization transistor T1 and the compensation transistor T2 can be N-type transistors; the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second initialization transistor T7, the third initialization transistor T8, and the isolation transistor T9 can be P-type transistors.

[0108] In some examples, as shown in Figure 8, the display substrate further includes a first scan signal line 181, a second scan signal line 182, a third scan signal line 183, a fourth scan signal line 184, a fifth scan signal line 185, a first light emission control signal line EM1, a second light emission control signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data line DATA, and a first power supply line VDD. It should be noted that the aforementioned first constant voltage signal line 150A can be the first initialization signal line INIT1, the second constant voltage signal line 150B can be the second initialization signal line INIT2, and the third constant voltage signal line 150C can be the third initialization signal line INIT3.

[0109] As shown in Figure 8, the first scan signal line 181 is connected to the gate of the compensation transistor T2; the second scan signal line 182 is connected to the gate of the isolation transistor T9 and the gate of the data writing transistor T4; the third scan signal line 183 is connected to the gate of the first initialization transistor T1; the fourth scan signal line 184 is connected to the gate of the second initialization transistor T7; the fifth scan signal line 185 is connected to the gate of the third initialization transistor T8; the first light emission control signal line EM1 is connected to the gate of the first light emission control transistor T5; and the second light emission control signal line EM2 is connected to the gate of the second light emission control transistor T6.

[0110] The first initial signal line INIT1 is connected to the first terminal of the first initialization transistor T1, the second initial signal line INIT2 is connected to the first terminal of the second initialization transistor T7, the third initial signal line INIT3 is connected to the first terminal of the third initialization transistor T8, the data line DATA is connected to the first terminal of the data writing transistor T4, and the first power supply line VDD is connected to the first terminal of the first light-emitting control transistor T5.

[0111] The following describes an exemplary operation of the pixel driving circuit. This exemplary operation may include seven stages, as follows:

[0112] The first stage, S1, can be referred to as the reset stage of the second node N2 and the fourth node N4. The signals of the first scan signal line 181, the third scan signal line 183, the fourth scan signal line 184, and the fifth scan signal line 185 are low-level signals, while the signals of the second scan signal line 182, the first light emission control signal line EM1, and the second light emission control signal line EM2 are high-level signals, which turns on the second initialization transistor T7 and the third initialization transistor T8, and turns off the other transistors.

[0113] The second initialization transistor T7 is turned on, providing the signal of the second initial signal line INIT2 to the fourth node N4, initializing (resetting) the first terminal of the light-emitting element 124, clearing the original charge in the first terminal of the light-emitting element 124, and setting the potential of the fourth node N4 to Vinit2. The third initialization transistor T8 is turned on, providing the signal of the third initial signal line INIT3 to the second node N2, initializing (resetting) the second node N2, and setting the potential of the second node N2 to Vinit3.

[0114] The second stage, S2, can be called the first node N1 reset stage. The signal of the first scan signal line 181 is a low-level signal, the signal of the second scan signal line 182 appears a low-level signal twice, and a high-level signal the rest of the time, and the signals of the third scan signal line 183, the fourth scan signal line 184, the fifth scan signal line 185, the first light emission control signal line EM1 and the second light emission control signal line EM2 are high-level signals, which turns on the first initialization transistor T1, turns on the data writing transistor T4 and the isolation transistor T9 twice each, and turns off the other transistors.

[0115] The first initialization transistor T1 is turned on, providing the signal of the first initial signal line INIT1 to the fifth node N5. When the data write transistor T4 and the isolation transistor T9 are turned on, the signal of the first initial signal line INIT1 is provided to the first node N1 to initialize (reset) the first node N1, clearing the original charge in the first node N1. The potential of the first node N1 is Vinit1. Since the isolation transistor T9 is a low-temperature polysilicon transistor, before the isolation transistor T9 is turned on for the first time, it is affected by the potential of the first node N1 and the gate bias voltage. The potential of the first node N1 is related to the data voltage of the previous stage, so the characteristics of the isolation transistor T9 are affected by the previous stage. After the isolation transistor T9 is turned on for the first time, the potential of the first node N1 is reset to Vinit1. The gate voltage of the isolation transistor T9 is relatively fixed whether it is high or low level. Therefore, after the first turn-on and turn-off, the influence of the previous stage data on the characteristics of the isolation transistor T9 can be cleared. When the isolation transistor T9 is turned on for the second time, the potential of the first node N1 is reset to Vinit1 again. This disclosure, by resetting the first node N1 twice consecutively, can better eliminate the influence of the data voltage from the previous stage on the characteristics of the isolation transistor T9, thereby improving image retention and low grayscale image quality. Furthermore, because the data writing transistor T4 is turned on twice in this stage, the data line DATA writes the data voltage of the first few cell rows to the second node N2. This changes the potential of the second node N2, thus changing the gate-source voltage of the driving transistor T3. The characteristics of the driving transistor T3 are reset, which can further improve image retention.

[0116] The third stage, S3, can be called the third node N3 reset stage. The signals of the first scan signal line 181, the second scan signal line 182, the third scan signal line 183, the fourth scan signal line 184, the fifth scan signal line 185, the first light emission control signal line EM1, and the second light emission control signal line EM2 are high-level signals, which turns on the first initialization transistor T1 and the compensation transistor T2, and turns off the other transistors.

[0117] The compensation transistor T2 is turned on, which turns on the third node N3 and the fifth node N5. The first initialization transistor T1 is turned on, which provides the signal of the first initial signal line INIT1 to the third node N3, initializes (resets) the third node N3, clears the original charge in the third node N3, and makes the potential of the third node N3 Vinit1.

[0118] The fourth stage, S4, can be called the data writing stage. The signal on the third scan signal line 183 is a low-level signal, the signal on the second scan signal line 182 is a low-level signal for a short period of time, and the signals on the first scan signal line 181, the fourth scan signal line 184, the fifth scan signal line 185, the first light emission control signal line EM1, and the second light emission control signal line EM2 are high-level signals, which turns on the compensation transistor T2, the data writing transistor T4, and the isolation transistor T9, while turning off the other transistors.

[0119] When compensation transistor T2 is turned on, nodes N3 and N5 are turned on. When isolation transistor T9 is turned on, nodes N1 and N5 are turned on. Since driver transistor T3 remains on during this stage, data write transistor T4 is turned on, allowing the data signal output from the data line DATA to be supplied to node N1 via node N2, the turned-on driver transistor T3, node N3, the turned-on compensation transistor T2, node N5, and the turned-on isolation transistor T9. The difference between the data voltage output from the data line DATA and the threshold voltage of driver transistor T3 is charged into storage capacitor Cst. The voltage at node N1 is Vd - |Vth|, where Vd is the data voltage output from the data line DATA and Vth is the threshold voltage of driver transistor T3. When isolation transistor T9 is turned off, storage capacitor Cst maintains the data voltage.

[0120] The fifth stage, S5, can be referred to as the reset stage for the second node N2, the third node N3, and the fourth node N4. The signals on the first scan signal line 181 and the third scan signal line 183 are low-level signals, and the signals on the fourth scan signal line 184 and the fifth scan signal line 185 are successively low-level signals for a short period. The signals on the second scan signal line 182, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are high-level signals, turning on the second initialization transistor T7 and the third initialization transistor T8, while turning off the other transistors.

[0121] The second initialization transistor T7 is turned on, providing the signal of the second initial signal line INIT2 to the fourth node N4. Since the driving transistor T3 remains on during this stage, the third initialization transistor T8 is turned on, providing the signal of the third initial signal line INIT3 to the second node N2 and the third node N3, resetting the second node N2, the third node N3, and the fourth node N4 respectively. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. This stage of resetting the second node N2, the third node N3, and the fourth node N4 can improve the hysteresis deviation caused by grayscale differences between adjacent pixels, and can also periodically reset the OLED anode, improving low-frequency flicker.

[0122] The sixth stage, S6, can be referred to as the reset stage of the second node N2 and the third node N3. The signals of the first scan signal line 181, the third scan signal line 183, and the first light-emitting control signal line EM1 are low-level signals, while the signals of the second scan signal line 182, the fourth scan signal line 184, the fifth scan signal line 185, and the second light-emitting control signal line EM2 are high-level signals, turning on the first light-emitting control transistor T5 and turning off the other transistors.

[0123] The first light-emitting control transistor T5 is turned on, so that the power supply voltage Vdd output from the first power supply line VDD is provided to the second node N2 and the third node N3, resetting the second node N2 and the third node N3, that is, resetting the first and second terminals of the driving transistor T3.

[0124] The seventh stage, A7, can be called the light-emitting stage. The signals of the first scan signal line 181, the third scan signal line 183, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are low-level signals, while the signals of the second scan signal line 182, the fourth scan signal line 184, and the fifth scan signal line 185 are high-level signals, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, while the other transistors are turned off.

[0125] The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, so that the power supply voltage output from the first power line VDD provides a driving voltage to the first terminal of the light-emitting element 124 through the turned-on first light-emitting control transistor T5, driving transistor T3 and the second light-emitting control transistor T6, thereby driving the light-emitting element 124 to emit light.

[0126] During the pixel driving circuit operation, the driving current flowing through the driving transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the driving transistor T3 is:

[0127] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[Vdd-Vd] 2

[0128] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element 124, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor T3.

[0129] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the driving transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0130] It should be noted that the operation process of the pixel driving circuit provided in this embodiment is not limited to this, and other operation processes may also be used for the pixel driving circuit.

[0131] Figure 10 is a planar schematic diagram of a display substrate according to an embodiment of the present disclosure; Figures 11-21 are planar schematic diagrams of multiple film layers in the display substrate shown in Figure 10. It should be noted that the different colored patterns in Figure 10 represent different film layers. As shown in Figure 10, the display substrate 100 includes a substrate 110, a plurality of pixel units 120, and a plurality of data lines 130; the plurality of pixel units 120 are arrayed on the substrate 110 along a first direction X and a second direction Y; the plurality of data lines 130 are located on the substrate 110 and arranged along the first direction X, and each data line 130 extends along the second direction Y. Since the plurality of pixel units 120 are arrayed, the plurality of pixel units 120 are divided into a plurality of pixel unit columns 141 arranged along the first direction X, each pixel unit column 141 includes a plurality of pixel units 120 arranged along the second direction Y, and each data line 130 is configured to provide data signals to at least a portion of the plurality of pixel units 120 in a pixel unit column 141.

[0132] As shown in Figure 10, due to the array arrangement of multiple pixel units 120, the multiple pixel units 120 can also be divided into multiple pixel unit rows 142 arranged along the second direction Y. Each pixel unit row 142 includes multiple pixel units 120 arranged along the first direction X. The display substrate 100 also includes at least one constant voltage signal line 150. The constant voltage signal line 150 includes a horizontal sub-constant voltage signal line 151 extending along the first direction X and a vertical sub-constant voltage signal line 152 extending along the second direction Y. The horizontal sub-constant voltage signal line 151 is configured to provide a constant voltage signal to the multiple pixel units 120 in a pixel unit row 142. The vertical sub-constant voltage signal line 152 is electrically connected to the horizontal sub-constant voltage signal line 151. It should be noted that the horizontal sub-constant voltage signal line 151 and the vertical sub-constant voltage signal line 152 can form a mesh conductive structure, thereby reducing the overall resistance and voltage drop of the constant voltage signal line 151, making the constant voltage signal provided to each pixel unit 120 on the display substrate 100 more uniform, thereby improving the display quality.

[0133] As shown in Figure 10, in the display substrate 100, a plurality of data lines 130 include a plurality of data line pairs 170. Each data line pair 170 includes a first data line 131 and a second data line 132 that are adjacent in the first direction X. The first distance between the first data line 131 and the second data line 132 in a data line pair 170 is less than the second distance between two adjacent data line pairs 170. The first distance between the first data line 131 and the second data line 132 can be the distance between the edge of the first data line 131 and the edge of the second data line 132. The second distance between two adjacent data line pairs 170 can be the distance between the oppositely arranged edges of two adjacent data line pairs 170. That is, the distance between two data lines in a data line pair is less than the distance between adjacent data line pairs.

[0134] As shown in Figure 10, the longitudinal sub-constant voltage signal line 152 is located between the first data line 131 and the second data line 132 in a data line pair 170; that is, the orthogonal projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 is located between the orthogonal projections of the first data line 131 and the second data line 132 on the substrate 110 in a data line pair 170.

[0135] As shown in Figure 10, the display substrate 100 further includes a first lead (not shown) and a second lead 162, the second lead 162 being located between two adjacent data line pairs 170. It should be noted that the first lead and the second lead here have the same function as those in the embodiments shown in Figures 4 and 5, and the relevant descriptions can be found in the relevant descriptions of Figures 4 and 5.

[0136] In the display substrate provided in this embodiment, by providing a longitudinal sub-constant voltage signal line between the first data line and the second data line in a data line pair, the display substrate can not only utilize the space between the first data line and the second data line to arrange the longitudinal sub-constant voltage signal line extending along the second direction, but also utilize the longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line; furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead line between the first data line and the second data line in a data line pair, and can also avoid interference between the first data line and the second data line on the signal on the second lead line.

[0137] On the other hand, to reduce the risk of ESD (electrostatic discharge), the second lead extending along the second direction includes a first conductive portion and a second conductive portion. The first and second conductive portions need to be electrically connected through two planarization vias, which affect the flatness of the effective light-emitting area of ​​the anode above them. In the area where the data line pairs are located, the two data lines themselves are connected to the pixel driving circuit through two planarization vias. Therefore, at least two planarization vias already exist in the area where the data line pairs are located. If the second lead is placed between the first and second data lines in the data line pair, it will be difficult for the effective light-emitting area of ​​the anode to completely avoid these four planarization vias, thus adversely affecting the flatness of the effective light-emitting area of ​​the anode and causing defects such as color shift. Therefore, by placing the second lead in the area between two adjacent data line pairs, rather than in the area between the first and second data lines in a single data line pair, the display substrate can also avoid the jumper design of the second lead affecting the flatness of the anode, thereby improving the flatness of the anode and reducing defects such as color shift.

[0138] In summary, this display substrate not only reduces the bezel width but also optimizes the layout design on the display substrate and improves the display quality.

[0139] For example, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments disclosed herein include, but are not limited to, the first direction X and the second direction Y may also intersect and not be perpendicular.

[0140] In the display substrate provided in this example, each pixel driving circuit 122 adopts the pixel driving circuit shown in FIG8. As shown in Figures 8 and 10, each pixel driving circuit 122 includes a storage capacitor Cst, a first initialization transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, and an isolation transistor T9. The first plate of the storage capacitor Cst, the gate of the driving transistor T3, and the second terminal of the isolation transistor T9 are connected to the first node N1. The second terminals of the data writing transistor T4, the first light-emitting control transistor T5, and the first terminal of the driving transistor T3 are connected to the second node N2. The second terminals of the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6 are connected to the third node N3. The second terminals of the second light-emitting control transistor T6, the second terminals of the second initialization transistor T7, and the light-emitting element 124 are connected to the fourth node N4. The first terminals of the compensation transistor T2, the first initialization transistor T1, and the isolation transistor T9 are connected to the fifth node N5. At this time, the first terminal of the compensation transistor T2 is connected to the first node N1 through the isolation transistor T9. It should be noted that the embodiments disclosed herein include, but are not limited to, the pixel driving circuit may also adopt a 7T1C structure or an 8T1C structure.

[0141] In some examples, as shown in Figures 8 and 10, the first terminal of isolation transistor T9, the second terminal of first initialization transistor T1, and the first terminal of compensation transistor T2 are connected to the fifth node N5, while the second terminal of isolation transistor T9, the gate of driving transistor T3, and the first plate of storage capacitor Cst are connected to the first node N1. The first terminal of first initialization transistor T1 is connected to the first constant voltage signal line 150A. When isolation transistor T9 is turned on, the first initialization signal Vinit1 on the first constant voltage signal line 150A can initialize the first node N1. Furthermore, by setting the aforementioned isolation transistor T9, the display substrate can effectively avoid potential fluctuations at the gate electrode of driving transistor T3 caused by changes in the characteristics of compensation transistor T2, thereby improving or eliminating horizontal stripe defects.

[0142] In some examples, as shown in Figures 8 and 10, the display substrate further includes a first scan signal line 181, a second scan signal line 182, a third scan signal line 183, a fourth scan signal line 184, a fifth scan signal line 185, a first light emission control signal line EM1, a second light emission control signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data line DATA, and a first power supply line VDD. The first scan signal line 181 is connected to the gate of the compensation transistor T2, the second scan signal line 182 is connected to the gate of the isolation transistor T9, the third scan signal line 183 is connected to the gate of the first initialization transistor T1, the fourth scan signal line 184 is connected to the gate of the second initialization transistor T7, the fifth scan signal line 185 is connected to the gate of the third initialization transistor T8, the first light emission control signal line EM1 is connected to the gate of the first light emission control transistor T5, the second light emission control signal line EM2 is connected to the gate of the second light emission control transistor T6, the first initialization signal line INIT1 is connected to the first terminal of the first initialization transistor T1, the second initialization signal line INIT2 is connected to the first terminal of the second initialization transistor T7, and the third initialization signal line INIT3 is connected to the first terminal of the third initialization transistor T8.

[0143] It should be noted that the first constant voltage signal line 150A mentioned above can be the first initialization signal line INIT1, the second constant voltage signal line 150B can be the second initialization signal line INIT2, and the third constant voltage signal line 150C can be the third initialization signal line INIT3.

[0144] In some examples, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 mentioned above may be the same light-emitting control signal line.

[0145] In some examples, as shown in Figures 8 and 10, the first initialization signal line INIT1 is configured to provide a first initialization signal Vinit1 to a first node N1 in a plurality of pixel units 120 in a pixel unit row 142, thereby initializing the first node N1. In this case, the aforementioned first constant voltage signal line 150A can be the first initialization signal line INIT1. Thus, the display substrate can place the longitudinal extension of the first initialization signal line INIT1, which transmits the first initialization signal Vinit1—that is, the first longitudinal sub-constant voltage signal line—between the first data line and the second data line in a data line pair. This allows the space between the first data line and the second data line to be used to arrange the first longitudinal sub-constant voltage signal line extending in the second direction, and also allows the use of the first longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line.

[0146] In some examples, as shown in Figures 8 and 10, the second initialization signal line INIT2 is configured to provide a second initialization signal Vinit2 to the fourth node N4 in a plurality of pixel units 120 in a pixel unit row 142, thereby initializing the fourth node N4. In this case, the second constant voltage signal line 150B can be this second initialization signal line INIT2. Thus, the display substrate can place the longitudinal extension of the second initialization signal line INIT2, which transmits the second initialization signal Vinit2—that is, the second longitudinal sub-constant voltage signal line—between the first and second data lines in a data line pair. This allows the space between the first and second data lines to be utilized to arrange the second longitudinal sub-constant voltage signal line extending along the second direction, and also allows the use of the second longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first and second data lines.

[0147] In some examples, as shown in Figures 8 and 10, the third initialization signal line INIT3 is configured to provide a third initialization signal Vinit3 to the second node N2 of a plurality of pixel units 120 in a pixel unit row 142. In this case, the aforementioned third constant voltage signal line 150C can be the third initialization signal line INIT3. Thus, the display substrate can place the longitudinal extension of the third initialization signal line INIT3, which transmits the third initialization signal Vinit3—that is, the third longitudinal sub-constant voltage signal line—between the first and second data lines in a data line pair. This allows the space between the first and second data lines to be utilized to arrange the third longitudinal sub-constant voltage signal line extending in the second direction, and also reduces signal crosstalk between the first and second data lines.

[0148] In some examples, as shown in Figure 10, the lateral extension of the first initialization signal line INIT1 (i.e., the first lateral sub-constant voltage signal line of the first constant voltage signal line) is connected to the first terminal of the first initialization transistor T1; the lateral extension of the second initialization signal line INIT2 (i.e., the second lateral sub-constant voltage signal line of the second constant voltage signal line) is connected to the first terminal of the second initialization transistor T7; and the lateral extension of the third initialization signal line INIT3 (i.e., the third lateral sub-constant voltage signal line of the third constant voltage signal line) is connected to the first terminal of the third initialization transistor T8.

[0149] In some examples, as shown in Figure 10, the second lead 162 is located between two compensation transistors T2 of two adjacent pixel driving circuits 122. Thus, the display substrate can make full use of the space on the display substrate, improving the compactness of the layout.

[0150] In some examples, as shown in Figure 10, the two pixel driving circuits 122 located on both sides of the second lead 162 are mirror symmetrical, so that the two data lines of the two pixel driving circuits 122 are close to each other to form the above-mentioned data line pair.

[0151] In some examples, as shown in Figures 8 and 10, the display substrate 100 further includes a first semiconductor layer 261 and a second semiconductor layer 262; the first semiconductor layer 261 is located on the substrate 110, and the second semiconductor layer 262 is located on the side of the first semiconductor layer 261 away from the substrate 110; in this case, the active layers of the aforementioned driving transistor T3, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are located on the first semiconductor layer 261, and the active layers of the aforementioned compensation transistor T2 and the first initialization transistor T1 are located on the second semiconductor layer 262. The material of the first semiconductor layer 261 includes silicon-based semiconductors, and the material of the second semiconductor layer 260 includes metal-oxide-semiconductor semiconductors. That is, the aforementioned driving transistor T3, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are silicon-based semiconductor transistors, and the aforementioned compensation transistor T2 and the first initialization transistor T1 are oxide transistors. Silicon-based semiconductor transistors, especially low-temperature polysilicon transistors (LTPS), have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. By using both LTPS and oxide transistors to construct the pixel driving circuit, the display substrate can leverage the advantages of both types of transistors to achieve low-frequency driving, reduce power consumption, and improve display quality. Furthermore, since the aforementioned compensation transistor and first initialization transistor are both oxide transistors, they both have low leakage current, thus ensuring the stability of the voltage at the gate of the first node N1, i.e., the driving transistor T3.

[0152] In some examples, as shown in Figures 8 and 10, the active layers of the compensation transistor T2 and the first initialization transistor T1 are connected to form a semiconductor block 2625 located in the second semiconductor layer 262, and the second lead 162 is located between the two semiconductor blocks 2625 of two adjacent pixel driving circuits 122. Thus, the display substrate can make full use of the space on the display substrate, improving the compactness of the layout.

[0153] In some examples, the material of the first semiconductor layer 261 mentioned above includes low-temperature polycrystalline silicon, and the material of the second semiconductor layer 262 includes indium gallium zinc oxide (IGZO). As described above, low-temperature polycrystalline silicon transistors have advantages such as high mobility and fast charging, while IGZO transistors have advantages such as low leakage current. By using both low-temperature polycrystalline silicon transistors and IGZO transistors to construct the pixel driving circuit, the display substrate can utilize the advantages of both types of transistors, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0154] In some examples, the transistors in the pixel driving circuit can be P-type transistors, N-type transistors, or a combination of both.

[0155] In some examples, the aforementioned driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, third initialization transistor T8, and isolation transistor T9 can be low-temperature polycrystalline silicon transistors. That is, the active layer material of the aforementioned driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, third initialization transistor T8, and isolation transistor T9 is low-temperature polycrystalline silicon. The aforementioned first initialization transistor T1 and compensation transistor T2 can be oxide transistors; that is, the active layer of the aforementioned first initialization transistor T1 and compensation transistor T2 can be a metal-oxide-semiconductor, such as indium gallium zinc oxide.

[0156] In some examples, in this pixel driving circuit, the first initialization transistor T1 and the compensation transistor T2 can be N-type transistors; the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second initialization transistor T7, the third initialization transistor T8, and the isolation transistor T9 can be P-type transistors.

[0157] In some examples, as shown in Figures 10 and 11, the display substrate 100 includes a first semiconductor layer 261, which may include an active layer of a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, and an isolation transistor T9.

[0158] In some examples, as shown in Figures 10 and 11, the active layers of the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second initialization transistor T7 are interconnected as a single structure, while the active layers of the third initialization transistor T8 and the isolation transistor T9 are set separately.

[0159] For example, the first semiconductor layer 261 can be made of silicon-based semiconductors, such as low-temperature polycrystalline silicon. Therefore, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second initialization transistor T7, the third initialization transistor T8, and the isolation transistor T9 can have advantages such as high mobility and fast charging.

[0160] In some examples, as shown in Figures 10 and 12, the display substrate 100 includes a first gate layer 281 located on the side of the first semiconductor layer 261 away from the substrate 110. The first gate layer 281 may include a first light emission control signal line EM1, a second scan signal line 182, a fourth scan signal line 184, a fifth scan signal line 185, a first electrode CE1 of a storage capacitor Cst, a second light emission control signal line EM2, and a lateral extension of a first initialization signal line INIT1. The first light emission control signal line EM1, the fifth scan signal line 185, the first initialization signal line INIT1, the second scan signal line 182, the second light emission control signal line EM2, and the fourth scan signal line 184 corresponding to a pixel unit row are sequentially arranged along the second direction Y.

[0161] It should be noted that an insulating layer is also provided between the first semiconductor layer and the first gate layer of the display substrate. The insulating layer is provided throughout and is used to insulate the first semiconductor layer and the first gate layer. Therefore, the insulating layer is also the gate insulating layer.

[0162] In some examples, as shown in Figures 10 and 12, the orthographic projection of the first electrode CE1 of the storage capacitor Cst onto the substrate 110 can be a rectangle with chamfers; the orthographic projection of the first light-emitting control signal line EM1 onto the substrate 110 can be a straight line or a broken line extending along the first direction X of the main body; the first light-emitting signal line EM1 has a recessed structure corresponding to the first electrode CE1.

[0163] In some examples, as shown in Figures 10 and 13, the display substrate 100 includes a second gate layer 282 located on the side of the first gate layer 281 away from the substrate 110; the second gate layer 282 includes a second electrode CE2 of the storage capacitor Cst, a first shielding line 282A and a second shielding line 282B.

[0164] In some examples, as shown in Figures 10 and 13, the shape of the first shielding line 282A can be a straight line or a broken line extending along the first direction X of the main body. The orthographic projection of the first shielding line 282A on the substrate 110 can be located between the second scan signal line 182 and the first initialization signal line INIT1. The first shielding line 282A has a portion overlapping with the active layer of the first initialization transistor T1, which is used to shield the channel region of the first initialization transistor T1, thereby ensuring the electrical performance of the first initialization transistor T1. It can also serve as the bottom gate electrode of the first initialization transistor T1. It should be noted that the width of the portion of the first shielding line 282A overlapping with the active layer of the first initialization transistor T1 can be greater than the width of other portions, thereby reducing the parasitic capacitance between the first shielding line and other structures.

[0165] In some examples, as shown in Figures 10 and 13, the shape of the second shielding line 282B can be a straight line or a broken line extending along the first direction X of the main body. The orthogonal projection of the second shielding line 282B on the substrate 110 can be located between the first electrode CE1 and the second scan signal line 182. The second shielding line 282B has a portion overlapping with the active layer of the compensation transistor T2, which is used to shield the channel region of the compensation transistor T2, thereby ensuring the electrical performance of the compensation transistor T2. It can also serve as the bottom gate electrode of the compensation transistor T2. It should be noted that the width of the portion of the second shielding line 282B overlapping with the active layer of the compensation transistor T2 can be greater than the width of other portions, thereby reducing the parasitic capacitance between the second shielding line and other structures.

[0166] In some examples, as shown in Figures 10 and 13, the orthographic projection of the second electrode CE2 on the substrate 110 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode CE2 on the substrate 110 at least partially overlaps with the orthographic projection of the first electrode CE1 on the substrate 110, thereby forming a storage capacitor Cst.

[0167] In some examples, as shown in Figures 10 and 13, since the second plate CE2 of the storage capacitor Cst is connected to the power line VDD, the second plates CE2 of the same pixel cell row are interconnected, thereby improving the uniformity of the voltage on the second substrate CE2.

[0168] In some examples, as shown in Figures 10 and 13, the second electrode CE2 has an opening 2820. The opening 2820 can be rectangular in shape and can be located in the central region of the second electrode CE2, making the second electrode CE2 form a ring structure. The orthographic projection of the opening 2820 on the substrate 110 overlaps with the orthographic projection of the first electrode CE1 on the substrate 110, so that other conductive structures can be connected to the first electrode CE1 through the opening 2820.

[0169] In some examples, as shown in Figures 10 and 14, the display substrate 100 further includes a second semiconductor layer 262 located on the side of the second gate layer 282 away from the substrate 110. The second semiconductor layer 262 includes the active layer of the first initialization transistor T1 and the active layer of the compensation transistor T2.

[0170] In some examples, as shown in Figures 10 and 14, the material of the first semiconductor layer 261 includes silicon-based semiconductors, and the material of the second semiconductor 270 includes metal-oxide-semiconductor (MODS). That is, the aforementioned driving transistor T3, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are silicon-based semiconductor transistors, while the aforementioned compensation transistor T2 and the first initialization transistor T1 are MODS transistors. Since silicon-based semiconductor transistors, especially low-temperature polysilicon transistors (LTPS), have advantages such as high mobility and fast charging, while MODS transistors have advantages such as low leakage current, by simultaneously using LPS transistors and MODS transistors to construct the pixel driving circuit, the display substrate can utilize the advantages of both types of transistors, achieving low-frequency driving, reducing power consumption, and improving display quality. Furthermore, since the aforementioned compensation transistor and first initialization transistor are MODS transistors, they both have low leakage current, thereby ensuring the voltage stability at the first node N1, i.e., the gate of the driving transistor T3.

[0171] In some examples, as shown in Figures 10 and 14, the active layers of the compensation transistor T2 and the first initialization transistor T1 are connected to form a semiconductor block 2625 located in the second semiconductor layer 262. The second lead 162 is located between the two semiconductor blocks 2625 of two adjacent pixel driving circuits 122. Thus, the display substrate can fully utilize the space on the display substrate, improving the compactness of the layout. It should be noted that the aforementioned semiconductor block refers to a block made of semiconductor material, which may include a conductive portion after a conductor-forming process. In some examples, as shown in Figures 10 and 14, the orthographic projection of the semiconductor block 2625 on the substrate 110 can be an elongated strip extending along the second direction Y. The orthographic projection of the semiconductor block 2625 on the substrate 110 can overlap with the orthographic projections of the first blocking line 282A and the second blocking line 282B on the substrate 110, respectively.

[0172] In some examples, as shown in Figures 10 and 15, the display substrate 100 further includes a third gate layer 283 located on the side of the second semiconductor layer 262 away from the substrate 110. The third gate layer 283 includes a third initialization signal line INIT3, a second initialization signal line INIT2, a third scan signal line 183, and a first scan signal line 181.

[0173] In some examples, as shown in Figures 10 and 15, the shape of the first scan signal line 181 can be a straight line or a broken line extending along the first direction X of the main body. The orthographic projection of the first scan signal line 181 on the substrate 110 can be located between the orthographic projections of the first electrode plate CE1 and the second scan signal line 182 on the substrate 110. The first scan signal line 181 overlaps with the active layer of the compensation transistor T2, thereby serving as the gate of the compensation transistor T2.

[0174] In some examples, as shown in Figures 10 and 15, the orthographic projection of the first scan signal line 181 on the substrate 110 at least partially overlaps with the orthographic projection of the first blocking line 282A on the substrate 110. The first scan signal line 181 and the first blocking line 282A can be connected to the same signal source, so that the first blocking line 282A can serve as the bottom gate electrode of the compensation transistor T2, and the first scan signal line 181 can serve as the top gate electrode of the first blocking line 282A, forming a compensation transistor T2 with a dual-gate structure.

[0175] In some examples, as shown in Figures 10 and 15, the shape of the third scan signal line 183 can be a straight line or a broken line extending along the first direction X of the main body. The third scan signal line 183 can be located between the second scan signal line 182 and the first initial signal line INIT1. The area where the third scan signal line 183 overlaps with the active layer of the first initialization transistor T1 can be used as the gate of the first initialization transistor T1.

[0176] In some examples, as shown in Figures 10 and 15, the orthographic projection of the third scan signal line 183 on the substrate 110 at least partially overlaps with the orthographic projection of the second blocking line 282B on the substrate 110. The third scan signal line 183 and the second blocking line 282B can be connected to the same signal source, so that the second blocking line 282B can serve as the bottom gate electrode of the first initialization transistor T1, and the third scan signal line 183 can serve as the top gate electrode of the first initialization transistor T1, forming a first initialization transistor T1 with a dual-gate structure.

[0177] In some examples, as shown in Figures 10 and 15, the shape of the second initial signal line INIT2 can be a straight line or a broken line extending along the first direction X of the main body. The second initial signal line INIT2 can be located on the side where the orthogonal projection of the second light emission control signal line EM2 on the substrate 110 is far away from the orthogonal projection of the second electrode CE2 on the substrate 110.

[0178] In some examples, as shown in Figures 10 and 15, the orthographic projection of the second initial signal line INIT2 on the substrate 110 at least partially overlaps with the orthographic projection of the fourth scan signal line 184 on the substrate, so that the second initial signal line INIT2 with a constant potential can effectively shield the voltage jump of the fourth scan signal line 184 from the influence on the pixel driving circuit.

[0179] In some examples, as shown in Figures 10 and 15, the shape of the third initial signal line INIT3 can be a straight line or a broken line extending along the first direction X of the main body, and the third initial signal line INIT3 can be located between the second electrode plate CE2 and the second initial signal line INIT2.

[0180] In some examples, as shown in Figures 10 and 15, the orthographic projection of the third initial signal line INIT3 on the substrate 110 at least partially overlaps with the orthographic projection of the first light emission control signal line EM1 on the substrate 110, so that the third initial signal line INIT3 with a constant potential can effectively shield the influence of the voltage jump of the first light emission control signal line EM1 on the pixel driving circuit.

[0181] In some examples, as shown in Figures 10 and 16, the display substrate 100 further includes a first interlayer insulating layer 310 located on the side of the third gate layer 283 away from the substrate 110. The first interlayer insulating layer 310 includes a plurality of via structures 315 for electrical connections between different film layers of the pixel driving circuit 122.

[0182] In some examples, as shown in Figures 10 and 17, the display substrate 100 further includes a second interlayer insulating layer 320 located on the side of the first interlayer insulating layer 310 away from the substrate 110. The second interlayer insulating layer 320 includes a plurality of via structures 325 for electrical connections between different film layers of the pixel driving circuit 122.

[0183] In some examples, as shown in Figures 10 and 18, the display substrate 100 further includes a first source / drain metal layer 230 located on the side of the second interlayer insulating layer 320 away from the substrate 110. The first source / drain metal layer 230 includes a first conductive portion 162A of the second lead 162, a first lead 161, and a plurality of conductive blocks 235, which can be used for electrical connections between different components of the pixel driving circuit.

[0184] In some examples, as shown in Figures 10 and 19, the display substrate 100 further includes a first planarization layer 241 located on the side of the first source / drain metal layer 230 away from the substrate 110. The first planarization layer 241 includes a plurality of first planarization vias 2415, which can be used for electrical connections between conductive structures in the first source / drain metal layer 230 and the second source / drain metal layer 250.

[0185] In some examples, as shown in Figures 10 and 20, the display substrate 100 further includes a second source / drain metal layer 250 located on the side of the first planarization layer 241 away from the substrate 110. The second source / drain metal layer 250 includes a data line 130, a power line 190, a second conductive portion 162B of a second lead 162, and a longitudinal constant voltage signal line 152.

[0186] In some examples, as shown in Figures 10 and 20, the plurality of data lines 130 includes a plurality of data line pairs 170. Each data line pair 170 includes a first data line 131 and a second data line 132 adjacent in a first direction X. A first distance between the first data line 131 and the second data line 132 in a data line pair 170 is less than a second distance between two adjacent data line pairs 170. A longitudinal sub-constant voltage signal line 152 is located between the first data line 131 and the second data line 132 in a data line pair 170; that is, the orthographic projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 is located between the orthographic projections of the first data line 131 and the second data line 132 in a data line pair 170 on the substrate 110, thereby reducing signal crosstalk between the first data line 131 and the second data line 132.

[0187] In some examples, as shown in Figures 10 and 20, the power line 190 can be a straight line or a broken line extending along the second direction Y. The power line 190 is electrically connected to the first light-emitting control transistor T5 and the second plate CE2 of the first electrode and storage capacitor Cst. The power line 190 can be a broken line of non-uniform width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0188] In some examples, as shown in Figures 10 and 20, the orthographic projection of the power line 190 on the substrate 110 at least partially overlaps with the orthographic projection of the active layer of the compensation transistor T2 on the substrate 110, and the orthographic projection of the power line 190 on the substrate 110 at least partially overlaps with the orthographic projection of the active layer of the first initialization transistor T1 on the substrate 110. This allows the power line 190 to block the active layers of the first initialization transistor T1 and the compensation transistor T2, thereby preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the first initialization transistor T1 and the compensation transistor T2. This also prevents the oxide transistor from experiencing characteristic drift due to light exposure, thus improving the electrical characteristics of the oxide transistor.

[0189] In some examples, as shown in Figures 10 and 20, the shape of the data line 130 can be a straight line or a broken line extending along the second direction Y of the main body.

[0190] In some examples, as shown in Figures 10 and 20, the second source / drain metal layer 250 may further include an anode connection electrode 254. The anode connection electrode 254 may be block-shaped (e.g., rectangular) and is configured to connect to a subsequently formed anode.

[0191] In some examples, as shown in Figures 10 and 21, the display substrate 100 further includes a second planarization layer 242 located on the side of the second source / drain metal layer 250 away from the substrate 110. The second planarization layer 242 includes a second planarization layer via 2425 for connecting the anode to the anode connection electrode 254.

[0192] Figure 22 is a planar schematic diagram of another display substrate provided in an embodiment of this disclosure. As shown in Figure 22, the display substrate 100 includes a substrate 110, a plurality of pixel units, and a plurality of data lines 130; the plurality of pixel units are arrayed on the substrate 110 along a first direction X and a second direction Y; the plurality of data lines 130 are located on the substrate 110 and arranged along the first direction X, and each data line 130 extends along the second direction Y. Due to the array arrangement of the plurality of pixel units, the plurality of pixel units are divided into a plurality of pixel unit columns arranged along the first direction X, each pixel unit column including a plurality of pixel units arranged along the second direction Y, and each data line 130 is configured to provide data signals to at least a portion of the plurality of pixel units in a pixel unit column. It should be noted that, in order to clearly show the three source and drain metal layers, other film layers in Figure 22 are omitted; in addition, the arrangement of pixel units in this display substrate can be referred to the relevant descriptions in Figures 4 and 10. Furthermore, the different colored patterns in Figure 22 represent different film layers.

[0193] As shown in Figure 22, due to the arrangement of multiple pixel unit arrays, the multiple pixel units can also be divided into multiple pixel unit rows arranged along the second direction Y. Each pixel unit row includes multiple pixel units arranged along the first direction X. The display substrate 100 also includes at least one constant voltage signal line 150. The constant voltage signal line 150 includes a horizontal sub-constant voltage signal line (not shown) extending along the first direction X and a vertical sub-constant voltage signal line 152 extending along the second direction Y. The horizontal sub-constant voltage signal line is configured to provide a constant voltage signal to multiple pixel units 120 in a pixel unit row; the vertical sub-constant voltage signal line 152 is electrically connected to the horizontal sub-constant voltage signal line. It should be noted that the horizontal sub-constant voltage signal line and the vertical sub-constant voltage signal line 152 can form a mesh conductive structure, thereby reducing the overall resistance and voltage drop of the constant voltage signal line, making the constant voltage signal provided to each pixel unit on the display substrate 100 more uniform, thereby improving the display quality. It should be noted that the above-mentioned horizontal sub-constant voltage signal line configuration can be referred to the relevant descriptions in Figures 4 and 10.

[0194] As shown in Figure 22, in the display substrate 100, the plurality of data lines 130 include a plurality of data line pairs 170. Each data line pair 170 includes a first data line 131 and a second data line 132 that are adjacent in the first direction X. The first distance between the first data line 131 and the second data line 132 in a data line pair 170 is less than the second distance between two adjacent data line pairs 170. The first distance between the first data line 131 and the second data line 132 can be the distance between the edge of the first data line 131 and the edge of the second data line 132. The second distance between two adjacent data line pairs 170 can be the distance between the oppositely arranged edges of two adjacent data line pairs 170. That is, the distance between two data lines in a data line pair is less than the distance between adjacent data line pairs.

[0195] As shown in Figure 22, the longitudinal sub-constant voltage signal line 152 is located between the first data line 131 and the second data line 132 in a data line pair 170; that is, the orthogonal projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 is located between the orthogonal projections of the first data line 131 and the second data line 132 on the substrate 110 in a data line pair 170.

[0196] As shown in Figure 22, the display substrate 100 also includes a first lead 161 and a second lead 162, with the second lead 162 located between two adjacent data line pairs 170. It should be noted that the first and second leads here function the same as those in the embodiments shown in Figures 4 and 5, and related descriptions can be found in the relevant descriptions of Figures 4 and 5.

[0197] As shown in Figure 22, the display substrate 100 further includes a first source / drain metal layer 230, a second source / drain metal layer 250, and a third source / drain metal layer 270. The first source / drain metal layer 230 is located on the substrate 110, the second source / drain metal layer 250 is located on the side of the first source / drain metal layer 230 away from the substrate 110, and the third source / drain metal layer 270 is located on the side of the second source / drain metal layer 250 away from the substrate 110. It should be noted that a planarization layer is disposed between adjacent source / drain metal layers in this display substrate.

[0198] In the display substrate provided in this embodiment, by providing a longitudinal sub-constant voltage signal line between the first data line and the second data line in a data line pair, the display substrate can not only utilize the space between the first data line and the second data line to arrange the longitudinal sub-constant voltage signal line extending along the second direction, but also utilize the longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line; furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead line between the first data line and the second data line in a data line pair, and can also avoid interference between the first data line and the second data line on the signal on the second lead line.

[0199] For example, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments disclosed herein include, but are not limited to, the first direction X and the second direction Y may also intersect and not be perpendicular.

[0200] In some examples, as shown in Figure 22, the longitudinal sub-constant voltage signal line 152 and the first data line 131 and the second data line 132 are all located in the third source / drain metal layer 270. Therefore, the display substrate can better reduce signal crosstalk between the first data line and the second data line.

[0201] In some examples, as shown in Figure 22, the first lead 161 is located in the second source / drain metal layer 250. This makes it easier to connect the first lead 161 to the data line 130, and also makes it easier to connect the first lead 161 to the second lead 162.

[0202] In some examples, as shown in FIG22, the display substrate 100 further includes a first lead-out adapter 163, a first end of which is connected to a first lead 161, and a second end of which is connected to a second lead 162; the orthographic projection of the first lead-out adapter 163 on the substrate 110 is covered by the orthographic projection of the second lead 162 on the substrate 110. It should be noted that the aforementioned coverage means that more than 90% of the area of ​​the orthographic projection of the first lead-out adapter on the substrate is covered by the orthographic projection of the second lead on the substrate.

[0203] In the display substrate provided in this example, since no planarization vias are provided between the pixel driving circuits of two adjacent pixel unit columns, the wiring space is relatively ample. There are many possible locations for the two planarization vias of the second lead, allowing them to be positioned close to the first lead, thereby shortening the length of the first lead adapter. Furthermore, in the direction perpendicular to the substrate, the first lead adapter can be positioned below the second lead, meaning the orthographic projection of the first lead adapter onto the substrate is covered by the orthographic projection of the second lead onto the substrate. This prevents the first lead adapter from being observed, avoids inconsistencies in patterns across different areas of the display substrate, and ultimately improves the display quality of the display substrate.

[0204] In some examples, as shown in FIG22, the display substrate 100 further includes a second lead-out adapter 164; a first end of the second lead-out adapter 164 is connected to the first lead-out line 161, and a second end of the second lead-out adapter 164 is connected to the data line 130; the orthographic projection of the second lead-out adapter 164 on the substrate 110 is covered by the orthographic projection of the data line 130 on the substrate 110. It should be noted that the above-mentioned coverage means that more than 90% of the area of ​​the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate.

[0205] In the display substrate provided in this example, since the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate, the second lead-out adapter can be avoided from being observed, thus avoiding different patterns in different areas of the display substrate and improving the display quality of the display substrate.

[0206] In some examples, as shown in Figure 22, the first lead-out adapter 163 may also be located in the second source / drain metal layer 250, so that it can be directly connected to the first lead-out 161 without the need for a via.

[0207] In some examples, as shown in Figure 22, the first lead 161 extends along the first direction X, and the first lead adapter 163 extends outward from the first lead 161 along the second direction Y at the location where the second lead 162 intersects with the first lead 161, and is covered by the second lead 162.

[0208] Figure 23 is a planar schematic diagram of another display substrate provided in an embodiment of the present disclosure. As shown in Figure 23, the display substrate 100 includes a substrate 110, a plurality of pixel units, a plurality of data lines 130, and a plurality of power lines 190; the plurality of pixel units are arrayed on the substrate 110 along a first direction X and a second direction Y; the plurality of data lines 130 are located on the substrate 110 and arranged along the first direction X, and each data line 130 extends along the second direction Y; the plurality of power lines 190 are located on the substrate 110 and arranged along the first direction X, and each power line 190 also extends along the second direction Y. Due to the array arrangement of the plurality of pixel units, the plurality of pixel units are divided into a plurality of pixel unit columns arranged along the first direction X, each pixel unit column includes a plurality of pixel units arranged along the second direction Y, each data line 130 is configured to provide a data signal to at least a portion of the plurality of pixel units in a pixel unit column, and each power line 190 is configured to provide a power signal, such as a VDD signal, to at least a portion of the plurality of pixel units in a pixel unit column. It should be noted that, in order to clearly show the three source and drain metal layers, the other film layers in Figure 23 are omitted; in addition, the arrangement of pixel units in this display substrate can be found in the relevant descriptions in Figures 4 and 10. Furthermore, the different colored patterns in Figure 23 represent different film layers.

[0209] As shown in Figure 23, due to the arrangement of multiple pixel unit arrays, the multiple pixel units can also be divided into multiple pixel unit rows arranged along the second direction Y. Each pixel unit row includes multiple pixel units arranged along the first direction X. The display substrate 100 also includes at least one constant voltage signal line 150. The constant voltage signal line 150 includes a horizontal sub-constant voltage signal line (not shown) extending along the first direction X and a vertical sub-constant voltage signal line 152 extending along the second direction Y. The horizontal sub-constant voltage signal line is configured to provide a constant voltage signal to multiple pixel units 120 in a pixel unit row 142; the vertical sub-constant voltage signal line 152 is electrically connected to the horizontal sub-constant voltage signal line. It should be noted that the horizontal sub-constant voltage signal line and the vertical sub-constant voltage signal line 152 can form a mesh conductive structure, thereby reducing the overall resistance and voltage drop of the constant voltage signal line, making the constant voltage signal provided to each pixel unit 120 on the display substrate 100 more uniform, thereby improving the display quality. It should be noted that the above-mentioned horizontal sub-constant voltage signal line configuration can be referred to the relevant descriptions in Figures 4 and 10.

[0210] As shown in Figure 23, in the display substrate 100, the plurality of data lines 130 include a plurality of data line pairs 170. Each data line pair 170 includes a first data line 131 and a second data line 132 that are adjacent in the first direction X. The first distance between the first data line 131 and the second data line 132 in a data line pair 170 is less than the second distance between two adjacent data line pairs 170. The first distance between the first data line 131 and the second data line 132 can be the distance between the edge of the first data line 131 and the edge of the second data line 132. The second distance between two adjacent data line pairs 170 can be the distance between the oppositely arranged edges of two adjacent data line pairs 170. That is, the distance between two data lines in a data line pair is less than the distance between adjacent data line pairs.

[0211] As shown in Figure 23, the longitudinal sub-constant voltage signal line 152 is located between the first data line 131 and the second data line 132 in a data line pair 170; that is, the orthogonal projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 is located between the orthogonal projections of the first data line 131 and the second data line 132 on the substrate 110 in a data line pair 170.

[0212] As shown in Figure 23, the display substrate 100 further includes a first lead 161 and a second lead 162, with the second lead 162 located between two adjacent data line pairs 170. It should be noted that the first and second leads here function the same as those in the embodiments shown in Figures 4 and 5, and related descriptions can be found in the relevant descriptions of Figures 4 and 5.

[0213] As shown in Figure 23, the display substrate 100 further includes a first source / drain metal layer 230, a second source / drain metal layer 250, and a third source / drain metal layer 270. The first source / drain metal layer 230 is located on the substrate 110, the second source / drain metal layer 250 is located on the side of the first source / drain metal layer 230 away from the substrate 110, and the third source / drain metal layer 270 is located on the side of the second source / drain metal layer 250 away from the substrate 110. It should be noted that a planarization layer is provided between adjacent source / drain metal layers in this display substrate. The second lead 162 includes a lead located on the first source / drain metal layer 230.

[0214] In the display substrate provided in this embodiment, by providing a longitudinal sub-constant voltage signal line between the first data line and the second data line in a data line pair, the display substrate can not only utilize the space between the first data line and the second data line to arrange the longitudinal sub-constant voltage signal line extending along the second direction, but also utilize the longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first data line and the second data line; furthermore, compared to a conventional display substrate, this display substrate does not provide a second lead line between the first data line and the second data line in a data line pair, and can also avoid interference between the first data line and the second data line on the signal on the second lead line.

[0215] For example, the first direction X and the second direction Y are perpendicular to each other. Of course, the embodiments disclosed herein include, but are not limited to, the first direction X and the second direction Y may also intersect and not be perpendicular.

[0216] In some examples, as shown in Figure 23, the distance between the orthographic projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 and the orthographic projection of the adjacent first data line 131 on the substrate 110 is approximately equal to the distance between the orthographic projection of the longitudinal sub-constant voltage signal line 152 on the substrate 110 and the orthographic projection of the adjacent second data line 132 on the substrate 110.

[0217] In some examples, as shown in FIG23, two power lines 190 are respectively located on both sides of the aforementioned data line pair 170 in the first direction. The power lines 190 may include portions located in the second source / drain metal layer 250 and portions located in the third source / drain metal layer 270. In the display substrate provided in this example, the second lead 162 is located in the first source / drain metal layer 230 and does not occupy the third source / drain metal layer 270. Therefore, the portion of the power line 190 located in the third source / drain metal layer 270 does not need to be partially removed for the second lead 162, thereby reducing the resistance of the power line 190.

[0218] In some examples, as shown in Figure 23, the longitudinal sub-constant voltage signal line 152 and the first data line 131 and the second data line 132 are both located in the third source / drain metal layer 270. Therefore, the display substrate can better reduce signal crosstalk between the first data line and the second data line.

[0219] In some examples, as shown in Figure 23, the first lead 161 is located in the second source / drain metal layer 250. This makes it easier to connect the first lead 161 to the data line 130, and also makes it easier to connect the first lead 161 to the second lead 162.

[0220] In some examples, as shown in FIG23, the display substrate 100 further includes a first lead-out adapter 163, a first end of the first lead-out adapter 163 being connected to a first lead 161, and a second end of the first lead-out adapter 163 being connected to a second lead 162; the orthographic projection of the first lead-out adapter 163 on the substrate 110 is covered by the orthographic projection of the second lead 162 on the substrate 110.

[0221] In the display substrate provided in this example, since no planarization vias are provided between the pixel driving circuits of two adjacent pixel unit columns, the wiring space is relatively ample. There are many possible locations for the two planarization vias of the second lead, allowing them to be positioned close to the first lead, thereby shortening the length of the first lead adapter. Furthermore, in the direction perpendicular to the substrate, the first lead adapter can be positioned below the second lead, meaning the orthographic projection of the first lead adapter onto the substrate is covered by the orthographic projection of the second lead onto the substrate. This prevents the first lead adapter from being observed, avoids inconsistencies in patterns across different areas of the display substrate, and ultimately improves the display quality of the display substrate.

[0222] In some examples, as shown in FIG23, the display substrate 100 further includes a second lead-out adapter 164; a first end of the second lead-out adapter 164 is connected to the first lead-out line 161, and a second end of the second lead-out adapter 164 is connected to the data line 130; the orthographic projection of the second lead-out adapter 164 on the substrate 110 is covered by the orthographic projection of the data line 130 on the substrate 110.

[0223] In the display substrate provided in this example, since the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate, the second lead-out adapter can be avoided from being observed, thus avoiding different patterns in different areas of the display substrate and improving the display quality of the display substrate.

[0224] In some examples, as shown in Figure 23, the first lead-out adapter 163 may also be located in the second source / drain metal layer 250, so that it can be directly connected to the first lead-out 161 without the need for a via.

[0225] In some examples, as shown in Figure 23, the first lead 161 extends along the first direction X, and the first lead adapter 163 extends outward from the first lead 161 along the second direction Y at the location where the second lead 162 intersects with the first lead 161, and is covered by the second lead 162.

[0226] At least one embodiment of this disclosure also provides a display device. FIG24 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in FIG24, the display device 500 includes the above-described display substrate 100. Thus, the display device 500 has the technical effects corresponding to the beneficial effects of the included display substrate 100, which will not be described in detail here.

[0227] For example, with a smaller bezel width, the display substrate can utilize the space between the first and second data lines in a data line pair to arrange the longitudinal sub-constant voltage signal line extending along the second direction, and can also use the longitudinal sub-constant voltage signal line to reduce signal crosstalk between the first and second data lines. Therefore, the display device not only has a smaller bezel width, but also prevents signal crosstalk between the first and second data lines, thus having better display quality.

[0228] In some examples, the aforementioned display device may be an electronic device with display function, such as a television, laptop computer, desktop computer, tablet computer, navigator, electronic picture frame, or smartphone.

[0229] In some examples, the display device 500 also includes a power supply component 400 that provides power to the display substrate 100. For example, when the display device is a mobile phone or tablet computer, the power supply component may be the battery in the mobile phone or tablet product; when the display device is a television or desktop computer, the power supply component may also be the power input component of the television or desktop computer.

[0230] The following points need to be explained:

[0231] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0232] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0233] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple pixel units are arrayed on the substrate along a first direction and a second direction; as well as Multiple data lines are located on the substrate and arranged along the first direction, with each data line extending along the second direction; The plurality of pixel units are divided into a plurality of pixel unit columns arranged along the first direction, each pixel unit column includes a plurality of pixel units arranged along the second direction, and each data line is configured to provide a data signal to at least a portion of the plurality of pixel units in a pixel unit column; The plurality of pixel units are divided into a plurality of pixel unit rows arranged along the second direction, each pixel unit row including a plurality of pixel units arranged along the first direction. The display substrate further includes at least one constant voltage signal line, the constant voltage signal line including a lateral sub-constant voltage signal line extending along the first direction and a longitudinal sub-constant voltage signal line extending along the second direction. The lateral sub-constant voltage signal line is configured to provide a constant voltage signal to a plurality of pixel units in one pixel unit row, and the longitudinal sub-constant voltage signal line is electrically connected to the lateral sub-constant voltage signal line. The plurality of data lines includes a plurality of data line pairs, each data line pair including a first data line and a second data line adjacent in the first direction, wherein a first distance between the first data line and the second data line in a data line pair is less than a second distance between two adjacent data line pairs, and the longitudinal sub-constant voltage signal line is located between the first data line and the second data line in a data line pair. The display substrate includes a display area and a peripheral area. The display area includes a first display area and two second display areas located on both sides of the first display area. The display substrate also includes a first lead and a second lead. The first lead is connected to the data line in the second display area and extends from the second display area to the first display area. The second lead is located in the first display area, electrically connected to the first lead, and extends from the first display area along the second direction to the peripheral area. The second lead is located between two adjacent pairs of data lines.

2. The display substrate according to claim 1, further comprising: A first semiconductor layer is located on the substrate. The second semiconductor layer is located on the side of the first semiconductor layer away from the substrate. Each pixel unit includes a pixel driving circuit and a light-emitting element. The pixel driving circuit is electrically connected to the light-emitting element and is configured to drive the light-emitting element to emit light. Each pixel driving circuit includes a plurality of transistors. In each of the pixel driving circuits, a portion of the active layer of the plurality of transistors is located in the first semiconductor layer, and another portion of the active layer of the plurality of transistors is located in the second semiconductor layer, forming a semiconductor block in the second semiconductor layer. The second lead is located between two semiconductor blocks of two adjacent pixel driving circuits. The pixel driving circuit includes a compensation transistor and a first initialization transistor, the compensation transistor and the first initialization transistor being connected to an active layer and forming the semiconductor block located in the second semiconductor layer.

3. The display substrate according to claim 1 or 2, wherein, The constant voltage signal line is configured to provide an initialization signal to the plurality of pixel units.

4. The display substrate according to claim 1 or 2, wherein, The longitudinal sub-constant voltage signal line is arranged on the same layer as the first data line and the second data line.

5. The display substrate according to claim 1 or 2, further comprising: First lead-out adapter cable, Wherein, the first end of the first lead-out adapter is connected to the first lead, and the second end of the first lead-out adapter is connected to the second lead; the orthographic projection of the first lead-out adapter on the substrate is covered by the orthographic projection of the second lead on the substrate.

6. The display substrate according to claim 5, further comprising: Second lead-out adapter cable, Wherein, the first end of the second lead-out adapter is connected to the first lead-out line, and the second end of the second lead-out adapter is connected to the data line; the orthographic projection of the second lead-out adapter on the substrate is covered by the orthographic projection of the data line on the substrate.

7. The display substrate according to any one of claims 1-6, further comprising: The first source / drain metal layer is located on the substrate. A planarization layer is located on the side of the first source / drain metal layer away from the substrate. as well as The second source / drain metal layer is located on the side of the planarization layer away from the first source / drain metal layer. The second lead includes a first conductive portion located in the first source / drain metal layer and a second conductive portion located in the second source / drain metal layer. The first conductive portion and the second conductive portion are electrically connected through a planarization via in the planarization layer.

8. The display substrate according to any one of claims 1-7, wherein, The pixel driving circuit includes a storage capacitor, a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. The first plate of the storage capacitor and the gate of the driving transistor are connected to a first node. The second electrode of the first light-emitting control transistor and the first electrode of the driving transistor are connected to a second node. The second electrode of the driving transistor and the first electrode of the second light-emitting control transistor are connected to a third node. The second electrode of the second light-emitting control transistor and the light-emitting element are connected to a fourth node. The at least one constant voltage signal line includes a first constant voltage signal line, the first constant voltage signal line including a first lateral sub-constant voltage signal line extending along the first direction and a first longitudinal sub-constant voltage signal line extending along the second direction, the first lateral sub-constant voltage signal line being configured to provide a first initialization signal to the first node in a plurality of pixel units in a row of pixel units; The at least one constant voltage signal line further includes a second constant voltage signal line, the second constant voltage signal line including a second lateral sub-constant voltage signal line extending along the first direction and a second longitudinal sub-constant voltage signal line extending along the second direction, the second lateral sub-constant voltage signal line being configured to provide a second initialization signal to the fourth node among a plurality of pixel units in a pixel unit row.

9. The display substrate according to claim 8, wherein, The plurality of data line pairs include a first data line pair and a second data line pair, wherein the first longitudinal sub-constant voltage signal line is located between the first data line and the second data line in the first data line pair, and the second longitudinal sub-constant voltage signal line is located between the first data line and the second data line in the second data line pair.

10. The display substrate according to claim 8, wherein, The at least one constant voltage signal line includes a third constant voltage signal line, the third constant voltage signal line including a third lateral sub-constant voltage signal line extending along the first direction and a third longitudinal sub-constant voltage signal line extending along the second direction, the third lateral sub-constant voltage signal line being configured to provide a third initialization signal to the second node in a plurality of pixel units in a row of pixel units.

11. The display substrate according to claim 10, wherein, The plurality of data line pairs include a first data line pair, a second data line pair, and a third data line pair. The first longitudinal sub-constant voltage signal line is located between the first data line and the second data line in the first data line pair. The second longitudinal sub-constant voltage signal line is located between the first data line and the second data line in the second data line pair. The third longitudinal sub-constant voltage signal line is located between the first data line and the second data line in the third data line pair.

12. The display substrate according to claim 10, wherein, In the first direction, the first longitudinal sub-constant voltage signal line, the second longitudinal sub-constant voltage signal line, and the third longitudinal sub-constant voltage signal line are arranged sequentially.

13. The display substrate according to claim 10, wherein, In the entire display substrate, at least two of the following quantities are not equal: the number of the first vertical sub-constant voltage signal lines, the number of the second vertical sub-constant voltage signal lines, and the number of the third vertical sub-constant voltage signal lines.

14. The display substrate according to claim 13, wherein, In the entire display substrate, the number of the second vertical sub-constant voltage signal lines is greater than the number of the first vertical sub-constant voltage signal lines and the number of the third vertical sub-constant voltage signal lines.

15. The display substrate according to any one of claims 1-14, wherein, In the first display area, a second lead is provided between two adjacent data pairs in the first direction. Alternatively, in the first display area, two second lead-out lines are provided between two adjacent data pairs in the first direction.

16. The display substrate according to any one of claims 8-14, wherein, The first terminal of the compensation transistor is connected to the first node, and the second terminal of the compensation transistor is connected to the third node. The first terminal of the first initialization transistor is connected to the first constant voltage signal line, and the second terminal of the first initialization transistor is connected to the first node. The second lead is located between the two compensation transistors of two adjacent pixel driving circuits.

17. The display substrate according to claim 16, wherein, The pixel driving circuit also includes an isolation transistor, and the compensation transistor is connected to the first node via the isolation transistor.

18. The display substrate according to claim 2, wherein, The material of the first semiconductor layer includes silicon-based semiconductors, and the material of the second semiconductor includes metal oxide semiconductors.

19. A display device comprising a display substrate according to any one of claims 1-18, and a power supply assembly for providing electrical power to the display substrate.

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