Display substrate and manufacturing method therefor, and display apparatus

Abstract

Provided is a display substrate, comprising: a base substrate; a driving circuit layer, located on the base substrate; a bonding metal layer, located on the side of the driving circuit layer away from the base substrate and comprising a plurality of first bonding pads and a plurality of power wires respectively arranged at intervals, the plurality of first bonding pads being electrically connected to the driving circuit layer, separately; and a plurality of light-emitting devices, located on the side of the bonding metal layer away from the base substrate, and electrically connected to the plurality of first bonding pads, respectively. The base substrate has a first surface facing the driving circuit layer; and there is a first spacing between the surface of the first bonding pads away from the base substrate and the first surface, there is a second spacing between the surface of the power wires away from the base substrate and the first surface, and the first spacing is greater than the second spacing.

Description

Display substrate, its preparation method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for preparing the substrate, and a display device thereof. Background Technology

[0002] Micro light-emitting diodes (LEDs) are light-emitting diodes with dimensions on the micrometer scale. Due to their small size, Micro LEDs can be used as pixels on display panels, and display panels made using Micro LEDs are called Micro LED display panels. Micro LED technology involves miniaturizing existing LEDs to below 100µm, approximately 1% of the current LED size, and then using mass transfer technology to transfer these micrometer-sized Micro / mini-LEDs onto a driving substrate, thereby forming Micro LED displays of various sizes. Improving the yield rate of transferring LEDs to the driving substrate and bonding them to it is one of the important research topics for researchers.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising:

[0006] Substrate;

[0007] The driving circuit layer is located on the substrate.

[0008] A bonding metal layer is located on the side of the driving circuit layer away from the substrate. The bonding metal layer includes a plurality of first bonding pads and a plurality of power lines arranged at intervals. The plurality of first bonding pads are electrically connected to the driving circuit layer.

[0009] Multiple light-emitting devices are located on the side of the bonding metal layer away from the substrate, and the multiple light-emitting devices are electrically connected to the multiple first bonding pads respectively;

[0010] The substrate has a first plane facing the driving circuit layer, the first bonding pad has a first distance between the surface away from the substrate and the first surface, the power trace has a second distance between the surface away from the substrate and the first surface, and the first distance is greater than the second distance.

[0011] According to some exemplary embodiments, the difference between the first spacing and the second spacing is greater than or equal to 2 micrometers and less than or equal to 5 micrometers.

[0012] According to some exemplary embodiments, the substrate includes a pad layer located between the drive circuit layer and the bonding metal layer, wherein the orthographic projection of the first bonding pad on the substrate at least partially overlaps with the orthographic projection of the pad layer on the substrate, and the orthographic projection of the power trace on the substrate is spaced apart from the orthographic projection of the pad layer on the substrate.

[0013] According to some exemplary embodiments, the padding layer includes a plurality of spaced-apart pads, with the plurality of first bonding pads located on the side of the plurality of pads away from the substrate.

[0014] According to some exemplary embodiments, the orthographic projection of the first bonding pad on the substrate is located within the orthographic projection of the raised portion on the substrate.

[0015] According to some exemplary embodiments, the padding layer includes a plurality of trenches, and a plurality of power traces are respectively located in the plurality of trenches, and the orthographic projection of the trenches on the substrate is spaced apart from the orthographic projection of the first bonding pad on the substrate.

[0016] According to some exemplary embodiments, the power supply traces are spaced apart from the side of the pad layer located in the trench.

[0017] According to some exemplary embodiments, the display substrate further includes a first planarization layer located between the padding layer and the driving circuit layer, wherein the elastic modulus of the material of the padding layer is less than the elastic modulus of the material of the first planarization layer.

[0018] According to some exemplary embodiments, the material of the pad layer includes at least one of polyimide and polymethyl methacrylate.

[0019] According to some exemplary embodiments, the thickness of the first bonding pad perpendicular to the first surface is greater than the thickness of the power trace perpendicular to the first surface.

[0020] According to some exemplary embodiments, the first bonding pad includes a first pad portion and a second pad portion connected together, the second pad portion being located on the side of the first pad portion away from the substrate, and the thickness of the first pad portion perpendicular to the first surface being approximately the same as the thickness of the power trace perpendicular to the first surface.

[0021] According to some exemplary embodiments, the orthographic projection of the surface of the second pad portion near the substrate onto the substrate lies within the orthographic projection of the surface of the first pad portion away from the substrate onto the substrate.

[0022] According to some exemplary embodiments, the bonding metal layer further includes connection traces, which are integrally connected to the first bonding pad; and

[0023] The display substrate further includes a first planarization layer, which is located between the bonding metal layer and the driving circuit layer. The first planarization layer has a first via, and the connection trace is electrically connected to the driving circuit layer through the first via. The orthographic projection of the first via on the substrate is spaced apart from the orthographic projection of the first bonding pad on the substrate.

[0024] According to some exemplary embodiments, the display substrate further includes a second planarization layer, the second planarization layer being located on the side of the bonding metal layer away from the substrate, and the second planarization layer being located in the spacing region between adjacent light-emitting devices; and

[0025] The surface of the second planarization layer furthest from the substrate is further from the substrate than the surface of the first bonding pad furthest from the substrate; and / or,

[0026] The surface of the second planarization layer that is away from the substrate is closer to the substrate than the surface of the light-emitting device that is close to the substrate.

[0027] According to some exemplary embodiments, the display substrate further includes a third planarization layer located on the side of the second planarization layer away from the substrate. The third planarization layer has a plurality of spaced-apart planarization portions, each of which covers a plurality of side surfaces of the light-emitting devices. Each planarization portion has a first opening that exposes a portion of the surface of the light-emitting device away from the substrate.

[0028] The display substrate further includes a series electrode located on the side of the third planarization layer away from the substrate. In at least two adjacent light-emitting devices, one end of the series electrode is electrically connected to the side of one of the light-emitting devices away from the substrate through the first opening, and the other end extends along the side of the planarization portion to the surface of the second planarization layer away from the substrate and is electrically connected to a first bonding pad connected to another light-emitting device through a second via in the second planarization layer.

[0029] According to some exemplary embodiments, the planarization portion surrounds the side of the light-emitting device at an acute angle to the surface of the planarization portion adjacent to the substrate; and / or

[0030] The planarization portion is located at the side of the first opening, forming an obtuse angle with the surface of the light-emitting device away from the substrate.

[0031] According to some exemplary embodiments, the display substrate further includes a reflective layer located on the side of the second planarization layer away from the substrate, the reflective layer including at least one reflective portion located between adjacent light-emitting devices, the reflective portion having a reflective surface facing the adjacent light-emitting devices.

[0032] According to some exemplary embodiments, the display substrate further includes:

[0033] A black matrix layer, located on the side of the reflective layer away from the substrate, the reflective layer having a plurality of second openings, and the black matrix layer having a plurality of third openings, the plurality of second openings and the plurality of third openings being interconnected, the light-emitting device being located within the interconnected second and third openings; and

[0034] A color conversion layer is located on the side of the light-emitting device away from the substrate. The color conversion layer includes a plurality of color conversion sections, which are located within the second opening and the third opening. The surface of the color conversion section away from the substrate is further away from the substrate than the surface of the reflective section away from the substrate.

[0035] According to some exemplary embodiments, a plurality of the reflective portions are connected in a grid pattern, the reflective layer has a plurality of second openings, and a plurality of the planarization portions are located within the plurality of second openings.

[0036] According to some exemplary embodiments, the reflective portion is spaced apart from the adjacent planarization portion, and the display substrate further includes a color conversion layer located on the side of the light-emitting device away from the substrate, a portion of which is located between the reflective portion and the planarization portion.

[0037] According to some exemplary embodiments, the surface of the reflective portion away from the substrate is further away from the substrate than the surface of the planarized portion away from the substrate.

[0038] According to some exemplary embodiments, the reflective layer includes a fourth planarization layer located on the side of the second planarization layer away from the substrate and a reflective metal layer located on the side of the fourth planarization layer away from the substrate.

[0039] The fourth planarization layer has a plurality of sixth openings, and the light-emitting device is located within the sixth openings; and

[0040] The reflective metal layer includes a plurality of spaced-apart reflective metal portions that cover the side of the fourth planarization layer located at the sixth opening. Each reflective metal portion has at least a portion of a reflective surface facing an adjacent light-emitting device. Adjacent reflective metal portions are disconnected at a surface of the fourth planarization layer away from the substrate.

[0041] In another aspect, a method for preparing a display substrate is provided, comprising:

[0042] A driving circuit layer is formed on a substrate, the substrate having a first surface facing the driving circuit layer;

[0043] A bonding metal layer is formed on the side of the driving circuit layer away from the substrate. The bonding metal layer includes a plurality of first bonding pads and a plurality of power traces spaced apart. The plurality of first bonding pads are electrically connected to the driving circuit layer. A first spacing exists between the surface of the first bonding pads away from the substrate and the first surface. A second spacing exists between the surface of the power traces away from the substrate and the first surface. The first spacing is greater than the second spacing.

[0044] Multiple light-emitting devices are formed on the side of the bonding metal layer away from the substrate, and the multiple light-emitting devices are electrically connected to the multiple first bonding pads respectively.

[0045] In another aspect, a display device is provided, comprising a display substrate as described in any of the preceding claims. Attached Figure Description

[0046] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0047] Figures 1A-1D schematically illustrate a mass transfer process of a light-emitting device according to some embodiments of the present disclosure.

[0048] Figure 2 schematically illustrates the bonding process of a light-emitting device according to some embodiments of the present disclosure.

[0049] Figure 3 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0050] Figure 4A schematically shows a cross-sectional view taken along line AA' in Figure 3.

[0051] Figure 4B schematically shows a cross-sectional view of a light-emitting device of a display substrate according to some embodiments of the present disclosure.

[0052] Figure 4C schematically shows a plan view of the bonding metal layer of a display substrate located in the display area according to some embodiments of the present disclosure.

[0053] Figure 4D schematically shows a cross-sectional view taken along line BB' in Figure 3.

[0054] Figure 4E schematically shows a cross-sectional view taken along line CC' in Figure 3.

[0055] Figure 5 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0056] Figure 6 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0057] Figures 7A-7E schematically illustrate the formation process of the bonding metal layer of a display substrate according to some embodiments of the present disclosure.

[0058] Figure 8 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0059] Figures 9A-9E schematically illustrate the formation process of the bonding metal layer of a display substrate according to some embodiments of the present disclosure.

[0060] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0061] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0062] Figure 12 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0063] Figure 13 schematically shows a plan view of the reflective layer of a display substrate according to some embodiments of the present disclosure.

[0064] Figure 14 schematically illustrates an equivalent circuit diagram of a pixel circuit of a display substrate according to some embodiments of the present disclosure.

[0065] Figure 15 schematically illustrates a flowchart of a method for fabricating a display substrate according to some embodiments of the present disclosure.

[0066] Figures 16A-16J schematically illustrate process diagrams of methods for fabricating display substrates according to some embodiments of the present disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0068] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0069] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0070] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0071] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0072] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0073] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0074] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0075] Micro LED technology involves miniaturizing existing LEDs to below 100µm, approximately 1% the size of existing LEDs, and then using mass transfer technology to transfer these micron-sized Micro LEDs onto a driving substrate, thereby forming Micro LED displays of various sizes.

[0076] Figures 1A-1D schematically illustrate a mass transfer process of a light-emitting device according to some embodiments of the present disclosure.

[0077] In related technologies, the process of transferring a Micro LED to a driving substrate may include the following steps.

[0078] Referring to FIG1A, a light-emitting device carrier substrate 900 is provided. The light-emitting device carrier substrate 900 includes a plurality of light-emitting devices 310 spaced apart, and a second bonding pad PAD2 is disposed on the light-emitting device 310.

[0079] Referring to FIG1B, a driving substrate is provided, on which a plurality of first bonding pads PAD1 are disposed at intervals.

[0080] Referring to Figures 1A, 1B, and 1C, the carrier substrate 900 of the light-emitting device is assembled with the driving substrate, such that the second bonding pad PAD2 of the carrier substrate 900 contacts the first bonding pad PAD1 of the driving substrate, and the first bonding pad PAD1 and the second bonding pad PAD2 are bonded together in a high-temperature environment.

[0081] Referring to FIG1D, the light-emitting device 310 that needs to be transferred to the driving substrate is selectively detached from the light-emitting device carrier substrate 900.

[0082] It should be noted that the multiple light-emitting devices 310 are formed by epitaxial growth on a substrate 100 (such as sapphire or gallium nitride), and then the epitaxial layer is patterned to form multiple light-emitting devices 310 spaced apart. In order to improve the utilization rate of the epitaxial layer, the arrangement density of the light-emitting devices 310 in the carrier substrate 900 is greater than the arrangement density of the first bonding pad PAD1 in the driving substrate. Therefore, after bonding, it is necessary to selectively disassemble the light-emitting devices 310 in the carrier substrate 900.

[0083] Figure 2 schematically illustrates the bonding process of a light-emitting device according to some embodiments of the present disclosure.

[0084] The inventors discovered that the first bonding pad PAD1 and the power trace PL in the driving substrate can be placed on the same layer, thereby simplifying the fabrication process of the display substrate. When the first bonding pad PAD1 and the power trace PL are on the same layer, during the transfer bonding process, the power trace PL on the driving substrate will come into contact with and be bonded to the light-emitting device 310 in the carrier substrate 900 that does not require transfer bonding, thus causing defects.

[0085] Figure 3 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. Figure 4A schematically shows a cross-sectional view taken along line AA' in Figure 3. Figure 4B schematically shows a cross-sectional view of a light-emitting device of a display substrate according to some embodiments of the present disclosure.

[0086] Referring to Figures 3 and 4A, the display substrate includes a substrate 100, a driving circuit layer 200, a bonding metal layer ML, and multiple light-emitting devices 310. The driving circuit layer 200 is located on the substrate 100 and includes multiple pixel driving circuits. The bonding metal layer ML is located on the side of the driving circuit layer 200 away from the substrate 100. The bonding metal layer ML includes multiple first bonding pads PAD1 arranged at intervals and multiple power lines PL. The multiple first bonding pads PAD1 are electrically connected to the driving circuit layer 200. The multiple light-emitting devices 310 are located on the side of the bonding metal layer ML away from the substrate 100. The multiple light-emitting devices 310 are electrically connected to the multiple first bonding pads PAD1, that is, the multiple light-emitting devices 310 are electrically connected to the multiple pixel driving circuits through the multiple first bonding pads PAD1. The multiple light-emitting devices 310 are arranged in an array along a first direction X and a second direction Y. The driving circuit layer 200 is used to drive the multiple light-emitting devices 310 to emit light to achieve image display. The substrate 100 has a first surface 100a facing the driving circuit layer 200. The first bonding pad PAD1 has a first spacing D1 between the surface away from the substrate 100 and the first surface 100a. The power trace PL has a second spacing D2 between the surface away from the substrate 100 and the first surface 100a. The first spacing D1 is greater than the second spacing D2.

[0087] In the display substrate provided in this embodiment, the first bonding pad PAD1 and the power trace PL are located on the same layer, that is, the first bonding pad PAD1 and the power trace PL are formed through the same film deposition process and patterning process, which simplifies the fabrication process of the display substrate. In addition, the surface of the first bonding pad PAD1 away from the substrate 100 is set to be further away from the substrate 100 than the surface of the power trace PL away from the substrate 100. This ensures that when the light-emitting device 310 is bonded to the first bonding pad PAD1 during the fabrication of the display substrate, the power trace PL will not come into contact with other light-emitting devices 310 that do not need to be bonded, thereby avoiding defects caused by the bonding connection between the power trace PL and the light-emitting device 310 and improving the fabrication yield of the display substrate.

[0088] According to some exemplary embodiments, referring to FIG4A, the power trace PL may include a first power trace PL1 and a second power trace PL2. For example, the first power trace PL1 may be used to connect a first power signal to the first electrode of the light-emitting device 310, and the second power trace PL2 may be used to connect a second power signal to the second electrode of the light-emitting device 310.

[0089] Of course, depending on the specific configuration of the driver circuit layer 200, the power supply trace PL may also include traces for transmitting other related power signals.

[0090] According to some exemplary embodiments, referring to FIG4A and FIG4B, the light-emitting device 310 may include a first electrode 311 located on the driving circuit layer 200, a light-emitting functional part 312 located on the side of the first electrode 311 away from the substrate 100, and a second electrode 313 located on the side of the light-emitting functional part 312 away from the substrate 100.

[0091] The light-emitting device 310 is configured to emit light from the side of the second electrode 313, that is, the light-emitting device 310 is a top-emitting type light-emitting device 310. The light-emitting functional unit 312 includes a first light-emitting surface 312m close to the first surface 100a and a second light-emitting surface 312n away from the first surface 100a. The orthographic projection of the first light-emitting surface 312m on the substrate 100 is located at the orthographic projection of the second light-emitting surface 312n on the substrate 100, and the area of ​​the first light-emitting surface 312n is smaller than the area of ​​the second light-emitting surface 312m.

[0092] By designing the structure of the light-emitting functional part 312, the orthogonal projection of the first light-emitting surface 312m on the substrate 100 is located at the orthogonal projection of the second light-emitting surface 312n on the substrate 100, and the area of ​​the first light-emitting surface 312m is smaller than the area of ​​the second light-emitting surface 312n, which can further improve the light-emitting area and light-emitting efficiency of the light-emitting device 310.

[0093] According to some exemplary embodiments, referring to Figures 4A and 4B, the shape of the cross section of the light-emitting functional part 312 perpendicular to the first surface 100a is an inverted trapezoid. That is, along the light-emitting direction of the light-emitting device 310 (i.e., the direction in which the light-emitting device 310 is away from the first surface 100a), the area of ​​the light-emitting functional part 312 parallel to the first surface 100a increases sequentially, which is beneficial to achieving higher light-emitting efficiency.

[0094] According to some exemplary embodiments, referring to Figures 4A and 4B, the light-emitting functional part 312 has a first side surface 312a intersecting with the first surface 100a of the substrate 100. The acute angle β between the first side surface 312a of the light-emitting functional part 312 and the plane containing the surface of the light-emitting functional part 312 near the substrate 100 is 50°-70°. For example, the angle β is 50°, 55°, 60°, 65°, or 70°. The inventors have found that when this angle β is within the range of 50°-70°, the light-emitting device 310 can have a larger light extraction efficiency and light-emitting area.

[0095] For example, referring to FIG4B, the light-emitting device 310 can be a micro light-emitting diode (Micro LED), and the light-emitting functional part 312 includes a first semiconductor part 3121 located on the first electrode 311, a light-emitting part 3122 located on the side of the first semiconductor part 3121 away from the first electrode 311, and a second semiconductor part 3123 located on the side of the light-emitting part 3122 away from the substrate 100.

[0096] For example, referring to FIG4B, one of the first semiconductor portion 3121 and the second semiconductor portion 3123 is an N-type semiconductor portion, and the other is a P-type semiconductor portion. The material of the N-type semiconductor portion may include N-type gallium nitride, and the material of the P-type semiconductor portion may include P-type gallium nitride.

[0097] For example, referring to FIG4B, the first semiconductor section 3121 includes N-type gallium nitride, and the second semiconductor section 3123 includes P-type gallium nitride.

[0098] For example, referring to FIG4B, the light-emitting part 3123 may include a multiple quantum well (MQW) structure, which may be a periodic structure of alternating gallium nitride (GaN) and indium gallium nitride (InGaN), but is not limited thereto.

[0099] According to some exemplary embodiments, referring to Figures 4A and 4B, the display substrate further includes a second passivation layer PV2. The second passivation layer PV2 is located between the first electrode 311 and the light-emitting functional part 312. The second passivation layer PV2 extends from the first side surface 312a of the light-emitting functional part 312 to the surface of the light-emitting functional part 312 facing the substrate 100. The second passivation layer PV2 has a tenth via H10, which exposes a portion of the surface of the light-emitting functional part 312 facing the substrate 100. The first electrode 311 is connected to the light-emitting functional part 312 through the tenth via H10. For example, the material of the second passivation layer PV2 includes at least one of silicon oxide, silicon nitride, or titanium oxide, and the thickness of the second passivation layer PV2 can be 0.2 μm to 1.0 μm.

[0100] According to some exemplary embodiments, referring to Figures 4A and 4B, the first electrode 311 can be a reflective electrode, the second electrode 313 can be a transparent electrode, and the light-emitting device 310 emits light towards the second electrode 313. For example, the first electrode 311 can have a titanium / aluminum / titanium stacked structure with a thickness of 50 / 1000 / 100 angstroms or a titanium nitride / aluminum / titanium stacked structure with a thickness of 50 / 1000 / 100 angstroms, and the material of the second electrode 313 can include indium tin oxide.

[0101] According to some exemplary embodiments, referring to FIG4A, a second bonding pad PAD2 is also provided between the light-emitting device 310 and the first bonding pad PAD1. By bonding the first bonding pad PAD1 and the second bonding pad PAD2, the light-emitting device 310 is electrically connected to the driving circuit layer 200. The orthographic projection of the second bonding pad PAD2 on the substrate 100 covers the orthographic projection of the first bonding pad PAD1 on the substrate 100. Setting the area of ​​the second bonding pad PAD2 to be slightly larger is beneficial to improving the bonding yield between the second bonding pad PAD2 and the first bonding pad PAD1. At the same time, setting the area of ​​the first bonding pad PAD1 to be relatively small can increase the wiring space of other structures (such as power traces PL) located in the bonding metal layer ML.

[0102] For example, the distance between the edge of the orthographic projection of the second bonding pad PAD2 on the substrate 100 and the edge of the orthographic projection of the first bonding pad PAD1 on the substrate 100 is 1 micrometer to 5 micrometers.

[0103] According to some exemplary embodiments, the second bonding pad PAD2 may have a molybdenum alloy / copper stack structure with a thickness of 100 / 10000 angstroms, wherein the molybdenum alloy may be a molybdenum-niobium alloy or a molybdenum-niobium-titanium alloy.

[0104] According to some exemplary embodiments, referring to FIG4A, the difference between the first pitch D1 and the second pitch D2 is greater than or equal to 2 micrometers, and the surface of the first bonding pad PAD1 away from the substrate 100 is greater than or equal to 2 micrometers higher than the surface of the power line PL away from the substrate 100. Considering that during the process of transferring and bonding the light-emitting device 310 in the carrier substrate of the light-emitting device to the first bonding pad PAD1, the carrier substrate of the light-emitting device will be pressed towards the bonding metal layer ML side, and affected by factors such as the uniformity of the bonding metal layer ML, the surface of the first bonding pad PAD1 away from the substrate 100 needs to be a certain distance higher than the surface of the power line PL away from the substrate 100, so that the power line PL does not come into contact with the light-emitting device 310 in the carrier substrate 900 that does not need to be transferred during the transfer bonding process. The inventors discovered through research that setting the difference between the first pitch D1 and the second pitch D2 to be greater than or equal to 2 micrometers can effectively avoid the problem of the power trace PL coming into contact with the light-emitting device 310 in the carrier substrate 900 that does not need to be transferred during the transfer bonding process.

[0105] According to some exemplary embodiments, referring to FIG4A, the difference between the first pitch D1 and the second pitch D2 is less than or equal to 5 micrometers, and the height of the surface of the first bonding pad PAD1 away from the substrate 100 is less than or equal to 5 micrometers higher than the surface of the power trace PL away from the substrate 100. This ensures that the power trace PL does not come into contact with the light-emitting device 310 that does not need to be transferred in the carrier substrate 900 during the transfer bonding process, while avoiding other fabrication defects in the display substrate caused by the excessive height difference between the surface of the first bonding pad PAD1 away from the substrate 100 and the surface of the power trace PL away from the substrate 100.

[0106] According to some exemplary embodiments, referring to FIG4A, the substrate 100 includes a pad layer 600 located between the drive circuit layer 200 and the bonding metal layer ML. The orthographic projection of the first bonding pad PAD1 on the substrate 100 at least partially overlaps with the orthographic projection of the pad layer 600 on the substrate 100, and the orthographic projection of the power trace PL on the substrate 100 is spaced apart from the orthographic projection of the pad layer 600 on the substrate 100. By providing a pad height 600 with a specific pattern between the bonding metal layer ML and the driving circuit layer 200, at least a portion of the first bonding pad PAD1 is disposed on the side of the pad height 600 away from the substrate 100. At the same time, the pad height 600 avoids the area where the power trace PL is disposed. There is no pad height 600 between the power trace PL and the driving circuit layer 200. That is, the pad height 600 raises the first bonding pad PAD1 but does not raise the power trace PL, so that the surface of the first bonding pad PAD1 away from the substrate 100 is further away from the substrate 100 than the surface of the power trace PL away from the substrate 100.

[0107] It should be noted that the thickness of the padding layer 600 perpendicular to the first surface 100a is approximately equal to the difference between the first spacing D1 and the second spacing D2, and the thickness of the padding layer 600 can be 2 micrometers to 5 micrometers.

[0108] According to some exemplary embodiments, referring to FIG4A, the padding layer 600 includes a plurality of padding portions 610 spaced apart, and a plurality of first bonding pads PAD1 are respectively located on the side of the plurality of padding portions 610 away from the substrate 100. The padding layer 600 is only provided in the area where the first bonding pads PAD1 are provided, and the plurality of padding portions 610 are respectively used to pad the plurality of first bonding pads PAD1.

[0109] According to some exemplary embodiments, referring to FIG4A, the orthographic projection of the first bonding pad PAD1 on the substrate 100 is located within the orthographic projection of the padding portion 610 on the substrate 100. That is, the padding portion 610 raises the first bonding pad PAD1 as a whole, so that the surface of the first bonding pad PAD1 away from the substrate 100 has better flatness, which is beneficial to improving the bonding yield between the first bonding pad PAD1 and the light-emitting device 310.

[0110] Figure 4C schematically shows a plan view of the bonding metal layer of a display substrate located in the display area according to some embodiments of the present disclosure.

[0111] According to some exemplary embodiments, referring to FIG4A, the display substrate further includes a first planarization layer PLN1 and a first passivation layer PVX1. The first planarization layer PLN1 is located between the pad layer 600 and the driving circuit layer 200, and the first passivation layer PVX1 is located between the pad layer 600 and the bonding metal layer ML. The first planarization layer PLN1 has a first via H01, a third via H03 and a fourth via H04, and the first passivation layer PVX1 has a fifth via H05, a sixth via H06 and a seventh via H07. The first via H01 and the fifth via H05 are connected and expose a portion of the driving circuit layer 200, the second via H02 and the sixth via H06 are connected and expose a portion of the driving circuit layer 200, and the third via H03 and the seventh via H07 are connected and expose a portion of the driving circuit layer 200.

[0112] Referring to Figures 4A and 4C, the bonding metal layer ML also includes a connecting trace CL. The connecting trace CL is integrated with the first bonding pad PAD1. The connecting trace CL is electrically connected to the driving circuit layer 200 through the first via H01 and the fifth via H05. The orthographic projections of the first via H01 and the fifth via H05 on the substrate 100 are spaced apart from the orthographic projections of the first bonding pad PAD1 on the substrate 100. The first bonding pad PAD1 is indirectly electrically connected to the driving circuit layer 200 through the connecting trace CL. Setting the orthographic projections of the connecting vias (the first via H01 and the fifth via H05) on the substrate 100 to be spaced apart from the orthographic projections of the first bonding pad PAD1 on the substrate 100 can further improve the flatness of the surface of the first bonding pad PAD1 away from the substrate 100, which is beneficial to further improve the bonding yield between the first bonding pad PAD1 and the light-emitting device 310.

[0113] It should be noted that, referring to Figures 4A and 4C, the connecting trace CL and the first bonding pad PAD1 are formed by a single film deposition and patterning process. There is no boundary line between the connecting trace CL and the first bonding pad PAD1 due to factors such as material differences. The planar shapes of the first bonding pad PAD1 and the connecting trace CL are quite different. The width of the connecting trace CL is significantly smaller than the size of the first bonding pad PAD1 (for example, the width S1 of the first bonding pad PAD1 is greater than or equal to 1.5 times the width S2 of the connecting trace CL). In the integral structure of the connecting trace CL and the first bonding pad PAD1, the boundary line where the size changes significantly is the boundary line between the first bonding pad PAD1 and the connecting trace CL.

[0114] According to some exemplary embodiments, referring to FIG4A, the driving circuit layer 200 may include a light-shielding layer LS located on the substrate 100, a first buffer layer Buf1 located on the side of the light-shielding layer LS away from the substrate 100, a first active layer ACT1 located on the side of the first buffer layer Buf1 away from the substrate 100, a first gate insulating layer GI1 located on the side of the first active layer ACT1 away from the substrate 100, a first gate metal layer Gate1 located on the side of the first gate insulating layer GI1 away from the substrate 100, a second gate insulating layer GI2 located on the side of the first gate metal layer Gate1 away from the substrate 100, and a second gate metal layer Gate2 located on the side of the second gate insulating layer GI2 away from the substrate 100. 2. A first interlayer insulating layer ILD1 located on the side of the second gate metal layer Gate2 away from the substrate 100, a second buffer layer Bur2 located on the side of the first interlayer insulating layer ILD1 away from the substrate 100, a second active layer ACT2 located on the side of the second buffer layer Bur2 away from the substrate 100, a third gate insulating layer GI3 located on the side of the second active layer ACT2 away from the substrate 100, a third gate metal layer Gate3 located on the side of the third gate insulating layer GI3 away from the substrate 100, a second interlayer insulating layer ILD2 located on the side of the third gate metal layer Gate3 away from the substrate 100, and a source / drain metal layer SD located on the side of the second interlayer insulating layer ILD2 away from the substrate 100.

[0115] For example, referring to FIG4A, the material of the first active layer ACT1 may include low temperature polycrystalline silicon, and the material of the second active layer ACT2 may include metal oxide semiconductor material, such as indium gallium zinc oxide. That is, the driving circuit layer 200 adopts low temperature polycrystalline oxide (LTPO) technology, which enables the display substrate to have adaptive refresh rate adjustment capability, thereby achieving the effect of reducing power consumption.

[0116] Of course, the film structure of the driving circuit layer 200 can be adjusted according to actual process requirements. Some of the aforementioned film layers can be removed or other film layers can be added. This disclosure does not limit this.

[0117] Furthermore, it should be noted that Figure 4A only schematically shows the film layers included in the driving circuit layer 200. The specific structure of the pixel driving circuit in the driving circuit layer 200 can be set according to requirements, and this embodiment does not limit it.

[0118] Figure 5 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0119] According to some exemplary embodiments, referring to FIG5, the display substrate includes a pad layer 600, which is located between the driving circuit layer 200 and the bonding metal layer ML. The pad layer 600 includes a plurality of trenches 620, and a plurality of power traces PL are respectively located in the plurality of trenches 620. The orthographic projection of the trenches 620 on the substrate 100 is spaced apart from the orthographic projection of the first bonding pad PAD1 on the substrate 100. The pad layer 600 forms trenches 620 in the area where the power traces PL are provided, thereby lowering the power traces PL and raising the first bonding pad PAD1, so that the surface of the first bonding pad PAD1 away from the substrate 100 is further away from the substrate 100 than the surface of the power traces PL away from the substrate 100.

[0120] In the display substrate provided in this embodiment, the pad layer 600 only has trenches 620 and other vias for connection. The pad layer 600 is provided in all areas except for the trenches 620 and vias. The pad layer 600 can fill in the uneven topography caused by the height difference between the first bonding pad PAD1 and the power trace PL to a certain extent, so that other film layers located on the side of the bonding metal layer ML away from the substrate 100 can be formed better.

[0121] According to some exemplary embodiments, referring to FIG5, the power trace PL and the pad layer 600 are spaced apart on the side at the trench 620, that is, the orthographic projection of the power trace PL on the substrate 100 is located within the orthographic projection of the trench 620 on the substrate 100, so that even if the formation position of the power trace PL deviates from the design position due to process fluctuations during the formation of the bonding metal layer ML, the power trace PL can still fall completely into the trench 620 of the pad layer 600.

[0122] According to some exemplary embodiments, the distance between the power trace PL and the side of the pad 600 located in the trench 620 can be greater than or equal to 2 micrometers.

[0123] According to some exemplary embodiments, referring to FIG5, a groove 620 is disposed through the pad layer 600 in a direction perpendicular to the first surface 100a.

[0124] For example, referring to Figures 4C and 5, the power trace PL extends along the column direction (i.e., the second direction Y shown in Figure 3), and the corresponding trench 620 also extends along the column direction.

[0125] According to some exemplary embodiments, referring to Figures 4C and 5, the pad layer 600 further includes an eighth via H08, which is connected to the first via H01 and the fifth via H05. The connection trace CL is electrically connected to the drive circuit layer 200 through the eighth via H08, the first via H01 and the fifth via H05. The orthographic projection of the eighth via H08 on the substrate 100 is spaced apart from the orthographic projection of the first bonding pad PAD1 on the substrate 100.

[0126] It should be noted that Figure 5 only schematically shows the bonding metal layer ML in the display substrate and the film structure located on the side of the bonding metal layer ML close to the substrate 100. Other structures can be provided on the side of the bonding metal layer ML away from the substrate 100 as needed, such as the second bonding pad PAD2 and the light-emitting device 310 shown in Figure 4A.

[0127] According to some exemplary embodiments, referring to FIG4A, the elastic modulus of the padding layer 600 is less than that of the first planarization layer PLN1, that is, the padding layer 600 has a relatively low elastic modulus. The inventors have found that this is affected by factors such as the uniformity of the bonding metal layer ML's film thickness and the uniformity of the padding layer 600's film thickness. The first pitch D1 of different first bonding pads PAD1 will vary. To avoid this difference affecting the bonding yield, the material of the pad 600 can be set to a material with a relatively low elastic modulus. Thus, during the bonding process of the light-emitting device 310 to the first bonding pad PAD1, the pad 600 will undergo elastic deformation under the bonding pressure, that is, it will be compressed to a certain extent towards the side closer to the substrate 100. For the first bonding pad PAD1 with a larger first pitch D1, the compressed size of the part of the pad 600 located on the lower side of the first bonding pad PAD1 (the difference between the size of the pad 600 perpendicular to the first surface 100a before compression and the size of the pad 600 perpendicular to the first surface 100a after compression) is larger. After the pad 600 is compressed, the difference in the first pitch D1 between the surface of each first bonding pad PAD1 away from the substrate 100 and the first surface 100a is reduced, thereby improving the bonding yield between the light-emitting device 310 and the first bonding pad PAD1.

[0128] According to some exemplary embodiments, during the bonding process, the elastic deformation of the portion of the pad 600 located under different first bonding pads PAD1 is different, and the range of elastic deformation of the portion of the pad 600 located under different first bonding pads PAD1 can be 20%-80%.

[0129] According to some exemplary embodiments, the material of the padding layer 600 may include an organic resin material with a relatively low modulus of elasticity; for example, the material of the padding layer 600 may include polyimide.

[0130] Figure 6 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0131] According to some exemplary embodiments, referring to FIG6, the thickness of the first bonding pad PAD1 perpendicular to the first surface 100a is greater than the thickness of the power trace PL perpendicular to the first surface 100a. In the display substrate provided in this embodiment, it is not necessary to additionally set the pad layer 600, but to directly make the first bonding pad PAD1 thicker, so that the surface of the first bonding pad PAD1 away from the substrate 100 is further away from the substrate 100 than the surface of the power trace PL away from the substrate 100.

[0132] It should be noted that the thickness of the power trace PL perpendicular to the first surface 100a should be understood as the thickness of the portion of the power trace PL that does not overlap with the projection of the third via H03 or the fourth via H04 in the first planarization layer PLN1.

[0133] According to some exemplary embodiments, referring to FIG6, the difference between the thickness of the first bonding pad PAD1 perpendicular to the first surface 100a and the thickness of the power trace PL perpendicular to the first surface 100a is greater than or equal to 2 micrometers and less than or equal to 5 micrometers.

[0134] According to some exemplary embodiments, referring to FIG6, the first bonding pad PAD1 includes a first bonding pad portion PAD11 and a second bonding pad portion PAD12 connected to each other. The second bonding pad portion PAD12 is located on the side of the first bonding pad portion PAD11 away from the substrate 100. The thickness of the first bonding pad portion PAD11 perpendicular to the first surface 100a is approximately the same as the thickness of the power trace PL perpendicular to the first surface 100a. That is, the first bonding pad PAD1 can be formed by two film deposition processes. In the first film deposition process, the first bonding pad portion PAD11 and the power trace PL are formed together, and the thicknesses of the first bonding pad portion PAD11 and the power trace PL are approximately equal. In the second film deposition process, the second bonding pad portion PAD12 is formed only on the side of the first bonding pad portion PAD11 away from the substrate 100.

[0135] Furthermore, the connecting trace CL can be formed together with the first solder pad PAD11 in the first film deposition process, or the connecting trace CL can be formed together with the second solder pad PAD12 in the second film deposition process. Alternatively, a portion of the connecting trace CL can be formed together with the first solder pad PAD11 in the first film deposition process, and another portion can be formed together with the second solder pad PAD12 in the second film deposition process. Figure 6 schematically illustrates the case where the connecting trace CL is formed together with the first solder pad PAD11 in the first film deposition process.

[0136] According to some exemplary embodiments, referring to FIG6, the orthographic projection of the surface of the second bonding pad PAD12 near the substrate 100 on the substrate 100 is located within the orthographic projection of the surface of the first bonding pad PAD11 away from the substrate 100 on the substrate 100. The first bonding pad PAD11 and the second bonding pad PAD12 are formed sequentially through two film deposition processes. The first bonding pad PAD11 can be set to be slightly larger than the second bonding pad PAD12, so that the surface of the second bonding pad PAD12 near the substrate 100 can fall into the surface of the first bonding pad PAD11 away from the substrate 100, thereby enabling the surface of the first bonding pad PAD1 away from the substrate 100 to have better flatness.

[0137] Figures 7A-7E schematically illustrate the formation process of the bonding metal layer of a display substrate according to some embodiments of the present disclosure.

[0138] Referring to FIG7A, a seed layer SL is formed on the side of the first planarization layer PLN1 away from the substrate 100, and a first barrier layer Dam1 is formed on the side of the seed layer SL away from the substrate 100. The first barrier layer Dam1 has a first cutout portion LK1 and a second cutout portion LK2. The area where the first cutout portion LK1 is located is the area where the first bonding pad needs to be set, and the area where the second cutout portion LK2 is located is the area where power traces need to be set.

[0139] For example, the material of the seed layer SL can be copper, and the seed layer SL can be formed by a sputtering deposition process.

[0140] Referring to Figure 7B, a first solder pad PAD11 is formed in the first cutout LK1 through a first electroplating process, and a power trace PL is formed in the second cutout LK2.

[0141] Referring to FIG7C, a second barrier layer Dam2 is formed on the side of the first barrier layer Dam1 away from the substrate 100. The second barrier layer Dam2 completely covers the power trace PL, and the second barrier layer Dam2 has a third cutout LK3, which exposes a part of the first pad portion PAD11.

[0142] Referring to FIG7D, a second solder pad portion PAD12 is formed in the third cutout portion LK3 by a second electroplating process. The second solder pad portion PAD12 is located on the side of the first solder pad portion PAD11 away from the substrate 100.

[0143] Referring to Figures 7D and 7E, the second barrier layer Dam2 and the first barrier layer Dam1 are removed, and the resulting seed layer SL, as well as the first pad PAD11, the second pad PAD12, and the power trace PL located on the seed layer SL, are thinned across the entire surface until the seed layer SL located in the interval area between the first bonding pad PAD1 and the power trace PL is completely removed.

[0144] It should be noted that Figures 7A-7E are only intended to illustrate the formation process of the first bonding pad PAD1 and the power trace PL, and the via structure in the first planarization layer PLN1 and the specific film structure of the driving circuit layer 200 are omitted.

[0145] Figure 8 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0146] According to some exemplary embodiments, referring to FIG8, the first bonding pad PAD1 can be formed by a single film deposition process, and the side of the formed first bonding pad PAD1 does not have a stepped structure. That is, the first bonding pad PAD1 and the power trace PL are formed by two separate film deposition processes. By controlling the process parameters of the two film deposition processes, the thickness of the first bonding pad PAD1 can be made greater than the thickness of the power trace PL. In addition, the connecting trace CL can be formed with the first bonding pad PAD1 by a single film deposition process.

[0147] Figures 9A-9E schematically illustrate the formation process of the bonding metal layer of a display substrate according to some embodiments of the present disclosure.

[0148] Referring to FIG9A, a seed layer SL is formed on the side of the first planarization layer PLN1 away from the substrate 100, and a third barrier layer Dam3 is formed on the side of the seed layer SL away from the substrate 100. The third barrier layer Dam3 has a fourth cutout portion LK4, and the area where the fourth cutout portion LK4 is located is the area where power traces PL need to be set.

[0149] Referring to Figure 9B, the power trace PL is formed in the fourth cutout section LK4 through the first electroplating process.

[0150] Referring to Figures 9B and 9C, the third barrier layer Dam3 is removed, and a fourth barrier layer Dam4 is formed on the side of the power trace PL away from the substrate 100. The fourth barrier layer Dam4 completely covers the power trace PL. The fourth barrier layer Dam4 has a fifth cutout portion LK5. The area where the fifth cutout portion LK5 is located is the area where the first bonding pad needs to be set, and the height of the fifth cutout portion LK5 perpendicular to the first surface 100a of the substrate 100 is greater than the height of the fourth cutout portion LK4 perpendicular to the first surface 100a of the substrate 100.

[0151] Referring to Figures 9C and 9D, a first bonding pad PAD1 is formed in the fifth cutout LK5 through a second electroplating process. The thickness of the first bonding pad PAD1 is greater than the thickness of the power trace PL.

[0152] Referring to Figures 9D and 9E, the fourth barrier layer Dam4 is removed, and the resulting seed layer SL, as well as the first bonding pad PAD1 and power trace PL located on the seed layer SL, are thinned across the entire surface until the seed layer SL located in the interval area between the first bonding pad PAD1 and the power trace PL is completely removed.

[0153] It should be noted that the formation order of the first bonding pad PAD1 and the power trace PL can be reversed. That is, the first bonding pad PAD1 is formed first through the first electroplating process, and then the power trace PL is formed through the second electroplating process.

[0154] According to some exemplary embodiments, referring to FIG4A, the display substrate further includes a second planarization layer PLN2. The second planarization layer PLN2 is located on the side of the bonding metal layer ML away from the substrate 100, and the second planarization layer PLN2 is located in the spacing region of adjacent light-emitting devices 310. The surface of the second planarization layer PLN2 away from the substrate 100 is further away from the substrate 100 than the surface of the first bonding pad PAD1 away from the substrate 100. The second planarization layer PLN2 can fill in the uneven topography caused by the height difference between the first bonding pad PAD1 and the power trace PL, so that other film layers located on the side of the second planarization layer PLN2 away from the substrate 100 can be formed better.

[0155] According to some exemplary embodiments, referring to FIG4A, the surface of the second planarization layer PLN2 away from the substrate 100 is closer to the substrate 100 than the surface of the light-emitting device 310 near the substrate 100. That is, the second planarization layer PLN2 does not contact the light-emitting device 310, thus avoiding crosstalk problems caused by the light emitted laterally from the light-emitting device 310 entering the second planarization layer PLN2 and propagating laterally in the second planarization layer PLN2 through the optical waveguide effect.

[0156] For example, the thickness of the second planarization layer PLN2 is 4 micrometers to 8 micrometers.

[0157] According to some exemplary embodiments, referring to FIG4A, a light-blocking layer BANK is also provided on the side of the second planarization layer PLN2 away from the substrate 100. The light-blocking layer BANK has a plurality of fifth openings KK5, and a plurality of light-emitting devices 310 are respectively located in the plurality of fifth openings KK5. The surface of the light-blocking layer BANK away from the substrate 100 is further away from the substrate 100 than the surface of the light-emitting devices 310 away from the substrate 100. The light-blocking layer BANK can improve the light crosstalk problem between adjacent light-emitting devices 310.

[0158] According to some exemplary embodiments, referring to FIG4A, the distance between the surface of the light-blocking layer BANK away from the substrate 100 and the surface of the light-emitting device 310 away from the substrate 100 is 5 micrometers to 10 micrometers, and the thickness of the light-blocking layer BANK perpendicular to the first surface 100a is 8 micrometers to 16 micrometers.

[0159] According to some exemplary embodiments, referring to FIG4A, the light-blocking layer BANK may include a reflective material, such that the light-blocking layer BANK can reflect the light emitted by the adjacent light-emitting device 310 onto the surface of the light-blocking layer BANK, thereby improving the light emission efficiency.

[0160] According to some exemplary embodiments, referring to FIG4A, the angle α between the side of the light-blocking layer BANK at the fifth opening KK5 and the bottom surface of the light-blocking layer BANK near the substrate 100 is 40°-70°.

[0161] According to some exemplary embodiments, referring to FIG4A, a color conversion layer 700 is further provided on the side of the second planarization layer PLN2 away from the substrate 100. The color conversion layer 700 includes a plurality of color conversion portions 710. The color conversion portions 710 are located in the fifth opening KK5 of the light-blocking layer BANK. The surface of the second planarization layer PLN2 away from the substrate 100 is closer to the substrate 100 than the surface of the light-emitting device 310 near the substrate 100, so that the surface of the color conversion portions 710 near the substrate 100 is closer to the substrate 100 than the surface of the light-emitting device 310 near the substrate 100. This arrangement is beneficial to improving the light utilization rate of the light-emitting device 310.

[0162] According to some exemplary embodiments, referring to FIG4A, the surface of the color conversion section 710 away from the substrate 100 is substantially flush with the surface of the light-blocking layer BANK away from the substrate 100, such that the surface of the color conversion section 710 away from the substrate 100 is further away from the substrate 100 than the surface of the light-emitting device 310 away from the substrate 100, that is, the light-emitting device 310 is immersed in the color conversion section 710, which is beneficial to further improve the light utilization rate of the light-emitting device 310. For example, the distance between the surface of the color conversion section 710 away from the substrate 100 and the surface of the light-emitting device 310 away from the substrate 100 is 5 micrometers to 10 micrometers.

[0163] According to some exemplary embodiments, referring to FIG4A, the display substrate further includes an inorganic encapsulation layer TFE, which is located between the second planarization layer PLN2 and the first passivation layer PVX1. The inorganic encapsulation layer TFE covers the side of the first bonding pad PAD1, the side of the second bonding pad PAD2, and the side of the light-emitting device 310 (referring to FIG4B, the inorganic encapsulation layer TFE is located on the side of the second passivation layer PV2 away from the light-emitting device 310) and extends to the surface of the light-emitting device 310 away from the substrate 100. The inorganic encapsulation layer TFE has a seventh opening KK7, which exposes a portion of the surface of the light-emitting device 310 away from the substrate 100.

[0164] According to some exemplary embodiments, referring to Figures 3 and 4A, a plurality of light-emitting devices 310 include a plurality of light-emitting units 300G, each light-emitting unit 300G including at least two light-emitting devices 310, and each light-emitting device 310 in the light-emitting unit 300G is connected in series. The display substrate also includes a series electrode 810 located on the side of the inorganic encapsulation layer TFE away from the substrate 100. In two adjacent light-emitting devices 310 within the light-emitting unit 300G, one end of the series electrode 810 is electrically connected to the side of one light-emitting device 310 away from the substrate 100 through a seventh opening KK7, and the other end extends to the surface of the second planarization layer PLN2 away from the substrate 100 and is electrically connected to the first bonding pad PAD1 connected to the other light-emitting device 310 through a second via H02 in the second planarization layer PLN2 and a ninth via H09 in the inorganic encapsulation layer TFE. By connecting at least two light-emitting devices 310 in the light-emitting unit 300G in series via the series electrode 810, high-voltage driving of the light-emitting devices 310 can be achieved, which helps to reduce the power consumption of the display substrate.

[0165] According to some exemplary embodiments, referring to FIG4A, the second via H02 and the ninth via H09 expose a portion of the connection trace CL, and the series electrode 810 is directly connected to the connection trace CL through the second via H02 and the ninth via H09, thereby making the series electrode 810 and the first bonding pad PAD1 connected to the connection trace CL electrically connected.

[0166] Figure 4D schematically shows a cross-sectional view taken along line BB' in Figure 3. Figure 4E schematically shows a cross-sectional view taken along line CC' in Figure 3.

[0167] According to some exemplary embodiments, referring to Figures 3, 4A, and 4D, a plurality of light-emitting units 300G include a first light-emitting unit 301G, a second light-emitting unit 302G, and a third light-emitting unit 303G. The display substrate also includes a color conversion layer 700, which includes a color conversion portion 710 located within a fifth opening KK5 of a portion of an adjacent light-blocking layer BANK, and the color conversion portion 710 covers the light-emitting device 310. The color conversion unit 710 includes a first color conversion unit 711 and a second color conversion unit 712. The orthographic projection of the first color conversion unit 711 on the substrate 100 at least partially overlaps with the orthographic projection of the first light-emitting unit 301G on the substrate 100. The first color conversion unit 711 is used to convert the third color light emitted by the light-emitting device 310 into the first color light. The orthographic projection of the second color conversion unit 712 on the substrate 100 at least partially overlaps with the orthographic projection of the second light-emitting unit 302G on the substrate 100. The second color conversion unit 712 is used to convert the third color light into the second color light, thereby realizing the color display of the display substrate.

[0168] According to some exemplary embodiments, referring to FIG3 and FIG4E, the color conversion layer 700 further includes a light-transmitting portion 720, which is located within a fifth opening KK5 of a portion of the light-blocking layer BANK. The orthographic projection of the light-transmitting portion 720 on the substrate 100 at least partially overlaps with the orthographic projection of the third light-emitting unit 303G on the substrate 100. The light-transmitting portion 720 is used to transmit third color light.

[0169] According to some exemplary embodiments, referring to Figures 3 and 4E, the light-transmitting portion 720 may also be doped with scattering particles. The light-transmitting portion 720 can improve the light pattern of the light emitted by the light-emitting device 310 of the first light-emitting unit 301G, thereby improving the light emission efficiency.

[0170] According to some exemplary embodiments, the first color is red, the second color is green, and the third color is blue.

[0171] According to some exemplary embodiments, the material of the first color conversion unit 711 includes a quantum dot material or a fluorescent material that converts third-color light into first-color light. The material of the second color conversion unit 712 includes a quantum dot material or a fluorescent material that converts third-color light into second-color light.

[0172] According to some exemplary embodiments, referring to Figures 4A, 4B, and 4C, the display substrate further includes a color filter layer CF located on the side of the color conversion layer 700 away from the substrate 100. The color filter layer CF includes a first color filter portion CF1, a second color filter portion CF2, and a third color filter portion CF3. The first color filter portion CF1 is located on the side of the first color conversion portion 711 away from the substrate 100, the second color filter portion CF2 is located on the side of the second color conversion portion 712 away from the substrate 100, and the third color filter portion CF3 is located on the side of the light-transmitting portion 720 away from the substrate 100.

[0173] According to some exemplary embodiments, the color of the first color filter CF1 is red, the color of the second color filter CF2 is green, and the color of the third color filter CF3 is blue.

[0174] According to some exemplary embodiments, referring to Figures 4A, 4B and 4C, the display substrate further includes a black matrix layer BM, which fills the spacer regions in the color filter layer CF.

[0175] According to some exemplary embodiments, referring to FIG4A, the display substrate further includes an organic protective layer OC located on the side of the black matrix layer BM and the color filter layer CF away from the substrate 100.

[0176] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0177] According to some exemplary embodiments, referring to Figures 4B and 10, the display substrate further includes a reflective layer 400 located on the side of the second planarization layer PLN2 away from the substrate 100. The reflective layer 400 includes at least one reflective portion 410, which is located between adjacent light-emitting devices 310. The reflective portion 410 is disposed at least partially around the first side surface 312a of the light-emitting functional portion 312 and spaced apart from the light-emitting device 310. The reflective portion 410 has a reflective surface 410a facing the adjacent light-emitting device 310. The reflective surface 410a can reflect the light emitted by the light-emitting device 310, thereby improving the light emission efficiency of the light-emitting device 310.

[0178] According to some exemplary embodiments, referring to Figures 4B and 10, the tilt angle of at least one part of the reflective surface 410a relative to the first surface 100a is substantially equal to the tilt angle of the side surface of the light-emitting functional part 312 relative to the first surface 100a. By configuring the structure of the reflective part 410 such that the tilt angle of at least one part of the reflective surface 410a of the reflective part 410 facing the light-emitting functional part 312 is equal to the tilt angle of the side surface of the light-emitting functional part 312, the light emission efficiency of the light-emitting device 310 can be further improved.

[0179] It should be noted that "the tilt angle of at least one part of the reflective surface 410a relative to the first surface 100a is substantially equal to the tilt angle of the side surface of the light-emitting functional part 312 relative to the first surface 100a" can be understood as follows: when the reflective surface 410a includes a plane, at least a portion of the plane of the reflective surface 410a is substantially parallel to the side surface of the light-emitting functional part 312; when the reflective surface 410a includes a curved surface, at least one tangent plane of the reflective surface 410a is substantially parallel to the side surface of the light-emitting functional part 312.

[0180] According to some exemplary embodiments, referring to FIG10, the reflective layer 400 includes a fourth planarization layer 401 located on the side of the second planarization layer PLN2 away from the substrate 100 and a reflective metal layer 402 located on the side of the fourth planarization layer 401 away from the substrate 100. The fourth planarization layer 401 has a plurality of sixth openings KK6, and a plurality of light-emitting devices 310 are located within the plurality of sixth openings KK6, and the light-emitting devices 310 are spaced apart from the fourth planarization layer 401. At least a portion of the reflective metal layer 402 is located on the side of the fourth planarization layer 401 at the sixth openings KK6, and at least a portion of the reflective surface 410a is substantially parallel to the side of the fourth planarization layer 401 at the fourth openings KK4. That is, the shape of the reflective surface 410a of the reflective portion 410 depends on the shape of the sixth openings KK6 in the fourth planarization layer 401, and the shape of the sixth openings KK6 can be set accordingly according to the desired shape of the reflective surface 410a.

[0181] According to some exemplary embodiments, referring to FIG10, the material of the reflective metal layer 402 may include a metallic material with high reflectivity; for example, the material of the reflective metal layer 402 may include silver or aluminum. Exemplarily, the reflective metal layer 402 may include a stacked structure of indium tin oxide / silver / indium tin oxide.

[0182] According to some exemplary embodiments, referring to FIG10, the display substrate further includes a first black matrix layer BM1 located on the side of the reflective layer 400 away from the substrate 100. The reflective layer 400 has a plurality of second openings KK2, and the first black matrix layer BM1 has a plurality of third openings KK3. The plurality of second openings KK2 and the plurality of third openings KK3 are respectively connected. The light-emitting device 310 is located within the connected second openings KK2 and third openings KK3. The color conversion layer 700 is located within the connected second openings KK2 and third openings KK3 and covers the light-emitting device 310. The surface of the color conversion layer 700 away from the substrate 100 is further away from the substrate 100 than the surface of the reflective portion 410 away from the substrate 100. By providing the first black matrix layer BM1 on the side of the reflective layer 400 away from the substrate 100, the height of the color conversion layer 700 perpendicular to the first surface 100a can be increased, which is beneficial to improving the color conversion efficiency of the color conversion layer 700.

[0183] According to some exemplary embodiments, referring to FIG10, the display substrate further includes a color filter layer CF located on the side of the color conversion layer 700 away from the substrate 100 and a second black matrix layer BM2 located on the side of the first black matrix layer BM1 away from the substrate 100, wherein the second black matrix layer BM2 fills the spacing region of the color filter layer CF.

[0184] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0185] According to some exemplary embodiments, referring to FIG11, the display substrate further includes a third planarization layer PLN3, which is located on the side of the second planarization layer PLN2 away from the substrate 100. The third planarization layer PLN3 has a plurality of planarization portions 500 spaced apart, which surround the sides of the light-emitting device 310 and the second bonding pad PAD2. Each planarization portion 500 has a first opening KK1, which exposes a portion of the surface of the light-emitting device 310 away from the substrate 100.

[0186] In at least two adjacent light-emitting devices 310, one end of the series electrode 810 is electrically connected to the side of one light-emitting device 310 away from the substrate 100 through a first opening KK1, and the other end extends along the surface of the planarization portion 500 to the surface of the second planarization layer PLN2 away from the substrate 100, and is electrically connected to the first bonding pad PAD1 connected to the other light-emitting device 310 through a second via H02 in the second planarization layer PLN2 and a ninth via H09 in the inorganic encapsulation layer TFE. The orthographic projection of the second bonding pad PAD2 on the substrate 100 lies within the orthographic projection of the light-emitting device 310 on the substrate 100, that is, the second bonding pad PAD2 is concave relative to the edge of the light-emitting device 310. The planarization portion 500 can fill the step difference at the side of the light-emitting device 310 and the second bonding pad PAD2.

[0187] By providing a planarization portion 500 on the side of the second planarization layer PLN2 away from the substrate 100, the second planarization layer PLN2 can fill the uneven topography formed by the bonding metal layer ML. The planarization portion 500 then fills the step difference between the light-emitting device 310 and the side of the second bonding pad PAD2. Furthermore, a series electrode 810 is provided on the side of the planarization portion 500 away from the substrate 100. The series electrode 810 extends along the surface of the planarization portion 500 and the second planarization layer PLN2, thereby realizing the series connection of two adjacent light-emitting devices 310. This arrangement can greatly reduce the risk of the series electrode 810 breaking and causing display defects.

[0188] According to some exemplary embodiments, referring to FIG11, the outer edge of the planarization portion 500's orthogonal projection on the substrate 100 surrounds the edge of the orthogonal projection of the light-emitting device 310 on the substrate 100, and the outer edge of the planarization portion 500's orthogonal projection on the substrate 100 surrounds the edge of the orthogonal projection of the second bonding pad PAD2 on the substrate 100. That is, the planarization portion 500 completely covers the side surface of the light-emitting device 310 and the side surface of the second bonding pad PAD2.

[0189] According to some exemplary embodiments, the distance between the edge of the planarization portion 500's orthogonal projection on the substrate 100 and the edge of the light-emitting device 310's orthogonal projection on the substrate 100 is greater than or equal to 5 micrometers. This is to avoid the problem that the planarization portion 500 cannot completely cover the light-emitting device 310 and the second bonding pad PAD2 due to bonding process fluctuations between the first bonding pad PAD1 and the second bonding pad PAD2. The size of this distance is set according to the bonding process accuracy; for example, when the bonding accuracy is reduced to ±1 micrometer, the distance is greater than or equal to 3 micrometers.

[0190] According to some exemplary embodiments, the surface of the planarization portion 500 away from the substrate 100 is further away from the substrate 100 than the surface of the light-emitting device 310 away from the substrate 100. For example, the thickness of the planarization portion 500 is 6-8 micrometers. The distance between the surface of the planarization portion 500 away from the substrate 100 and the surface of the light-emitting device 310 away from the substrate 100 is 1-2 micrometers.

[0191] According to some exemplary embodiments, referring to FIG11, the angle γ1 formed between the side of the planarization portion 500 at the first opening KK1 and the surface of the light-emitting device 310 exposed by the first opening KK1 is an obtuse angle. This arrangement can effectively avoid the problem of the series electrode 810 breaking at the corner where the plane of the light-emitting device 310 extends from the plane away from the substrate 100 to the side of the planarization portion 500 at the first opening KK1.

[0192] According to some exemplary embodiments, referring to FIG11, the angle γ2 formed by the planarization portion 500 surrounding the side of the light-emitting device 310 and the plane of the planarization portion 500 near the substrate 100 is an acute angle. This arrangement can effectively avoid the problem of the series electrode 810 breaking at the corner where the second planarization layer PLN2 extends from the side of the planarization portion 500 surrounding the light-emitting device 310 to the plane away from the substrate 100.

[0193] Figure 12 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0194] According to some exemplary embodiments, referring to FIG12, in this display substrate, a reflective layer 400 and a third planarization layer PLN3 are disposed on the side of the second planarization layer PLN2 away from the substrate 100. Multiple reflective portions 410 are connected in a grid pattern. The reflective layer 400 has multiple second openings KK2, and multiple planarization portions 500 are located within the multiple second openings KK2. The reflective layer 400 forms a reflective surface 410a surrounding the light-emitting device 310 at the second openings KK2, thereby improving the light extraction efficiency of the light-emitting device 310. Furthermore, the planarization portions 500 cover the sides of the light-emitting device 310, effectively reducing the risk of breakage of the series electrodes 810.

[0195] Figure 13 schematically shows a plan view of the reflective layer of a display substrate according to some embodiments of the present disclosure.

[0196] According to some exemplary embodiments, referring to Figures 12 and 13, the reflective layer 400 includes a fourth planarization layer 401 located on the side of the second planarization layer PLN2 away from the substrate 100, and a reflective metal layer 402 located on the side of the fourth planarization layer 401 away from the substrate 100. The fourth planarization layer 401 has an integral mesh structure and has a plurality of sixth openings KK6, in which a plurality of light-emitting devices 310 are respectively located. The reflective metal layer 402 includes a plurality of spaced-apart reflective metal portions 4021, which have an annular structure and cover the side of the fourth planarization layer 401 located at the sixth openings KK6. Each reflective metal portion 4021 has a reflective surface 410a facing an adjacent light-emitting device 310, and adjacent reflective metal portions 4021 are disconnected at the surface of the fourth planarization layer 401 away from the substrate 100.

[0197] The series electrode 810 is located between the second planarization layer PLN2 and the reflective layer 400. A portion of the reflective metal portion 4021 will overlap with the series electrode 810 on the side closest to the substrate 100. Therefore, by spacing adjacent reflective metal portions 4021, the problem of the reflective metal portion 4021 short-circuiting adjacent series electrodes 810 can be avoided.

[0198] According to some exemplary embodiments, referring to FIG12, one end of the reflective metal portion 4021 away from the substrate 100 can extend to the surface of the fourth planarization layer 401 away from the substrate 100, so that the reflective portion 410 can completely cover the side of the fourth planarization layer 401 located at the sixth opening KK6 as much as possible, thereby increasing the area of ​​the reflective surface 410a, which is beneficial to further improve the light emission efficiency of the light-emitting device 310.

[0199] According to some exemplary embodiments, referring to FIG12, the reflective portion 410 and the adjacent planarization portion 500 are spaced apart. The display substrate also includes a color conversion layer 700 located on the side of the light-emitting device 310 away from the substrate 100. A portion of the color conversion layer 700 is located between the reflective portion 410 and the planarization portion 500, thereby enabling more light to excite the color conversion layer 700 to perform light color conversion, thereby improving the light utilization rate of the light-emitting device 310.

[0200] According to some exemplary embodiments, referring to FIG12, the surface of the reflective metal portion 4021 away from the substrate 100 is further away from the substrate 100 than the surface of the planarization portion 500 away from the substrate 100. On the one hand, by making the height of the reflective metal portion 4021 higher, the light extraction efficiency of the light-emitting device 310 can be improved by increasing the area of ​​the reflective surface 410a. On the other hand, by making the height of the planarization portion 500 lower, only slightly higher than the height of the light-emitting device 310, it is beneficial for the series electrode 810 to extend from the surface of the light-emitting device 310 across the planarization portion 500 to the second planarization layer PLN2.

[0201] Figure 14 schematically illustrates an equivalent circuit diagram of a pixel circuit of a display substrate according to some embodiments of the present disclosure.

[0202] According to some exemplary embodiments, referring to Figures 3 and 14, the driving circuit layer includes multiple pixel circuits, which are electrically connected to multiple light-emitting units. Each light-emitting unit includes N light-emitting devices, and each pixel circuit includes a pixel driving circuit and N-1 current control circuits, where N is an integer greater than 1.

[0203] The pixel driving circuit is used to generate driving current and output driving current through the driving current output terminal; the first electrode of the first light-emitting device is electrically connected to the driving current output terminal; the second electrode of the nth light-emitting device and the first electrode of the (n+1)th light-emitting device are both electrically connected to the nth display node, and the second electrode of the Nth light-emitting device is electrically connected to the first voltage terminal; n is a positive integer less than N; the nth current control circuit is electrically connected to the nth display node and is used to control the supply of the nth control current to the nth display node.

[0204] The pixel circuit of this embodiment drives N interconnected light-emitting devices through a pixel driving circuit, so that the driving transistor and the light-emitting control transistor in the pixel driving circuit are shared in the driving current path, and there is only one set of power consumption loss of the driving transistor, thereby achieving the purpose of reducing power consumption.

[0205] The following is an example of an exemplary embodiment, with N equal to 4, but not limited thereto; in practice, N can be an integer greater than 1.

[0206] According to some exemplary embodiments, the light-emitting device can be a Micro LED (micro light-emitting diode), a Mini LED (mini light-emitting diode), or an OLED (organic light-emitting diode). The first electrode of the light-emitting device can be an anode, and the second electrode of the light-emitting device can be a cathode, but this is not a limitation.

[0207] Optionally, the first voltage terminal may be a first low voltage terminal, but is not limited thereto.

[0208] According to some exemplary embodiments, the light-emitting device is a current-driven device. To achieve the required brightness, the current required for the brightness of the device is supplied. In at least one embodiment of the present disclosure, the pixel circuit drives N light-emitting devices through a driving transistor in a pixel driving circuit, so as to reduce power consumption.

[0209] For example, when the required brightness (L255) needs to be achieved, each light-emitting device requires a drive current Id to achieve the required brightness. Only one drive transistor is needed to provide the drive current Id. Compared with the power consumption of the related pixel drive circuit, the original power consumption can be reduced by 25%-50%, thereby reducing the power consumption of the backplane.

[0210] Referring to FIG14, in some embodiments, the pixel circuit and the light-emitting unit electrically connected to each other may include a pixel driving circuit 10, a first light-emitting device E1, a second light-emitting device E2, a third light-emitting device E3, a fourth light-emitting device E4, a first current control circuit 11, a second current control circuit 12, and a third current control circuit 13.

[0211] The pixel driving circuit 10 generates a driving current and outputs the driving current through the driving current output terminal OT. The first electrode of the first light-emitting device E1 is electrically connected to the driving current output terminal OT. The second electrodes of the first light-emitting device E1 and the first electrodes of the second light-emitting device E2 are both electrically connected to the first display node NX1. The second electrodes of the second light-emitting device E2 and the first electrodes of the third light-emitting device E3 are both electrically connected to the second display node NX2. The second electrodes of the third light-emitting device E3 and the first electrodes of the fourth light-emitting device E4 are both electrically connected to the third display node NX3. The second electrode of the fourth light-emitting device E4 is electrically connected to the first voltage terminal V1. The first current control circuit 11 is electrically connected to the first display node NX1 and is used to control the supply of a first control current to the first display node NX1. The second current control circuit 12 is electrically connected to the second display node NX2 and is used to control the supply of a second control current to the second display node NX2. The third current control circuit 13 is electrically connected to the third display node NX3 and is used to control the supply of a third control current to the third display node NX3.

[0212] According to some exemplary embodiments, the nth current control circuit includes an nth write control circuit, an nth energy storage circuit, an nth inverting energy storage circuit, an nth on / off control circuit, and an nth control circuit.

[0213] The nth write control circuit is electrically connected to the (n+1)th scan terminal, the (n+1)th inverted scan terminal, the nth control node, the nth inverted control node, the (n+1)th data line, and the (n+1)th inverted data line, respectively. Under the control of the (n+1)th scan signal provided by the (n+1)th scan terminal, it writes the data voltage provided by the (n+1)th data line to the nth control node, and under the control of the (n+1)th inverted scan signal provided by the (n+1)th inverted scan terminal, it writes the data voltage provided by the (n+1)th inverted data line to the nth inverted control node.

[0214] The nth energy storage circuit is electrically connected to the nth control node to maintain the potential of the nth control node;

[0215] The nth inverting energy storage circuit is electrically connected to the nth inverting control node and is used to maintain the potential of the nth inverting control node.

[0216] The nth on / off control circuit is electrically connected to the nth control node, the nth inverting control node, the (n+1)th power supply voltage terminal, the (n+1)th low voltage terminal, and the nth intermediate node, respectively. It is used to control the connection or disconnection between the (n+1)th power supply voltage terminal and the nth intermediate node under the control of the potential of the nth control node, and to control the connection or disconnection between the (n+1)th low voltage terminal and the nth intermediate node under the control of the potential of the nth inverting control node.

[0217] The nth control circuit is electrically connected to the (n+1)th light-emitting control terminal, the nth intermediate node, and the nth display node, respectively, and is used to control the connection or disconnection between the nth intermediate node and the nth display node under the control of the (n+1)th light-emitting control signal provided by the (n+1)th light-emitting control terminal.

[0218] Figure 15 schematically illustrates a flowchart of a method for fabricating a display substrate according to some embodiments of the present disclosure.

[0219] Some embodiments of this disclosure provide a method for fabricating a display substrate. Referring to FIG15, the fabrication method includes the following steps.

[0220] In step S10, a driving circuit layer is formed on a substrate, the substrate having a first surface facing the driving circuit layer.

[0221] In step S20, a bonding metal layer is formed on the side of the driving circuit layer away from the substrate. The bonding metal layer includes a plurality of first bonding pads and a plurality of power lines arranged at intervals. The plurality of first bonding pads are electrically connected to each other. There is a first gap between the surface of the first bonding pad away from the substrate and the first surface. There is a second gap between the surface of the power line away from the substrate and the first surface. The first gap is greater than the second gap.

[0222] In step S30, a plurality of light-emitting devices are formed on the side of the bonding metal layer away from the substrate, and the plurality of light-emitting devices are electrically connected to a plurality of first bonding pads respectively.

[0223] Figures 16A-16J schematically illustrate process diagrams of methods for fabricating display substrates according to some embodiments of the present disclosure.

[0224] According to some exemplary embodiments, referring to FIG16A, a light-emitting device intermediate substrate 900 is provided. The light-emitting device intermediate substrate 900 includes an intermediate substrate 910, a release adhesive layer 920 located on the intermediate substrate 910, a plurality of light-emitting devices 310 located on the side of the release adhesive layer 920 away from the intermediate substrate 910, and a plurality of second bonding pads PAD2 located on the side of the plurality of light-emitting devices 310 away from the intermediate substrate 910. The second bonding pads PAD2 are electrically connected to the light-emitting devices 310 and are adhered to the intermediate substrate 910 through the release adhesive layer 920.

[0225] Referring to FIG16B, a driving substrate is provided. The driving substrate includes a substrate 100 and a driving circuit layer 200 located on the substrate 100. The driving circuit layer 200 may include a light-shielding layer LS located on the substrate 100, a first buffer layer Buf1 located on the side of the light-shielding layer LS away from the substrate 100, a first active layer ACT1 located on the side of the first buffer layer Buf1 away from the substrate 100, a first gate insulating layer GI1 located on the side of the first active layer ACT1 away from the substrate 100, a first gate metal layer Gate1 located on the side of the first gate insulating layer GI1 away from the substrate 100, a second gate insulating layer GI2 located on the side of the first gate metal layer Gate1 away from the substrate 100, and a second gate insulating layer GI2 located on the side of the second gate insulating layer GI2 away from the substrate 100. The second gate metal layer Gate2 on one side of 100, the first interlayer insulating layer ILD1 on the side of the second gate metal layer Gate2 away from the substrate 100, the second buffer layer Buf2 on the side of the first interlayer insulating layer ILD1 away from the substrate 100, the second active layer ACT2 on the side of the second buffer layer Buf2 away from the substrate 100, the third gate insulating layer GI3 on ​​the side of the second active layer ACT2 away from the substrate 100, the third gate metal layer Gate3 on the side of the third gate insulating layer GI3 away from the substrate 100, the second interlayer insulating layer ILD2 on the side of the third gate metal layer Gate3 away from the substrate 100, and the source / drain metal layer SD on the side of the second interlayer insulating layer ILD2 away from the substrate 100.

[0226] A first planarization layer PLN1 is formed on the side of the source / drain metal layer SD away from the substrate 100. The first planarization layer PLN1 has a first via H01, a third via H03 and a fourth via H04, and the first via H01, the third via H03 and the fourth via H04 expose a portion of the drive circuit layer 200.

[0227] Referring to FIG16C, a pad layer 600 is formed on the side of the first planarization layer PLN1 away from the substrate 100. The pad layer 600 may include a plurality of spaced-apart pad portions 610. A first passivation layer PVX1 is then formed on the side of the pad layer 600 away from the substrate 100. The first passivation layer PVX1 includes a fifth via H05, a sixth via H06, and a seventh via H07. The fifth via H05 is connected to the first via H01 and exposes a portion of the drive circuit layer 200. The sixth via H06 is connected to the third via H03 and exposes a portion of the drive circuit layer 200. The seventh via H07 is connected to the fourth via H04 and exposes a portion of the drive circuit layer 200.

[0228] For example, the material of the first passivation layer PVX1 includes at least one of silicon nitride or silicon oxide, and the thickness of the first passivation layer PVX1 is 100 nanometers to 500 nanometers.

[0229] Referring to FIG16D, a fifth barrier layer Dam5 is formed on the side of the first passivation layer PVX1 away from the substrate 100. The fifth barrier layer Dam5 includes a sixth cutout portion LK6, a seventh cutout portion LK7, and an eighth cutout portion LK8. The sixth cutout portion LK6 exposes the fifth via H05 and the first via H01. The seventh cutout portion LK7 exposes the sixth via H06 and the third via H03. The eighth cutout portion LK8 exposes the seventh via H07 and the fourth via H04. Furthermore, the orthographic projection of the sixth cutout portion LK6 on the substrate 100 at least partially overlaps with the orthographic projection of the padding portion 610 on the substrate 100. The orthographic projections of the seventh cutout portion LK7 and the eighth cutout portion LK8 on the substrate 100 are spaced apart from the orthographic projection of the padding portion 610 on the substrate 100.

[0230] A bonding metal layer ML is then formed through an electroplating process. Forming the bonding metal layer ML includes forming a first bonding pad PAD1 and a connection trace CL within the sixth cutout portion LK6, and power traces PL within the seventh cutout portion LK7 and the eighth cutout portion LK8. The orthogonal projection of the first bonding pad PAD1 onto the substrate 100 lies within the orthogonal projection of the padding portion 610 onto the substrate 100. The first bonding pad PAD1 and the connection trace CL are integrated into a single structure. The connection trace CL is electrically connected to the driving circuit layer 200 through the fifth via H05 and the first via H01. A portion of the power trace PL is electrically connected to the driving circuit layer 200 through the sixth via H06 and the third via H03, and another portion of the power trace PL is electrically connected to the driving circuit layer 200 through the seventh via H07 and the fourth via H04.

[0231] For example, the bonding metal layer ML includes a copper film layer with a thickness of 2 micrometers to 8 micrometers and a tin film layer with a thickness of 0.8 micrometers to 1.2 micrometers located on the side of the copper film layer away from the substrate 100.

[0232] Referring to Figures 16D and 16E, the fifth barrier layer Dam5 is removed, and the bonding metal layer ML formed in the cutout of the fifth barrier layer Dam5 is retained.

[0233] Referring to Figure 16F, the carrier substrate 900 of the light-emitting device shown in Figure 16A and the driving substrate shown in Figure 16E are assembled into a vacuum assembly substrate, and a sealant sealant is applied around their perimeter for encapsulation, creating a high vacuum environment within the sealant sealant. The vacuum assembly substrate is placed in a furnace at a temperature above 250°C, and pressure is applied to the vacuum assembly substrate, causing a portion of the second bonding pad PAD2 on the light-emitting device 310 to bond with the first bonding pad PAD1 on the driving substrate. Furthermore, since the height of the power trace PL is lower than the height of the first bonding pad PAD1, the power trace PL will not contact the second bonding pad PAD2 on the carrier substrate 900 of the light-emitting device, thereby achieving selective bonding.

[0234] Referring to Figure 16G, a laser is used to selectively irradiate the area of ​​the light-emitting device 310 that is bonded to the first bonding pad PAD1 in the driving substrate in the disintegrating adhesive layer 920. The portion of the disintegrating adhesive layer 920 that is irradiated by the laser is disintegrated and loses its adhesiveness. Then, the carrier substrate 900 in the light-emitting device is removed, and the light-emitting device 310 that is bonded to the first bonding pad PAD1 in the driving substrate is separated from the carrier substrate 910.

[0235] Referring to FIG16H, an inorganic encapsulation layer TFE is formed on the side of the light-emitting device 310 away from the substrate 100. The inorganic encapsulation layer TFE has a ninth via H09, which exposes a portion of the connection trace CL. The inorganic encapsulation layer TFE also has a seventh opening KK7, which exposes a portion of the surface of the light-emitting device 310 away from the substrate 100. A second planarization layer PLN2 is then formed on the side of the inorganic encapsulation layer TFE away from the substrate 100. The surface of the second planarization layer PLN2 away from the substrate 100 is closer to the substrate 100 than the surface of the light-emitting device 310 near the substrate 100. The second planarization layer PLN2 has a second via H02, which is connected to the ninth via H09 and exposes a portion of the connection trace CL.

[0236] For example, the inorganic encapsulation layer TFE can have a stacked structure of silicon oxide / silicon nitride / silicon carbonitride, and the thickness of the inorganic encapsulation layer TFE can be 0.5 micrometers to 2 micrometers.

[0237] Referring to FIG16I, a series electrode 810 is formed on the side of the light-emitting device 310 and the second planarization layer PLN2 away from the substrate 100. In at least two adjacent light-emitting devices 310, one end of the series electrode 810 is electrically connected to the side of one light-emitting device 310 away from the substrate 100 through the seventh opening KK7, and the other end extends to the surface of the second planarization layer PLN2 away from the substrate 100 and is electrically connected to the connection trace CL connected to the other light-emitting device 310 through the second via H02 in the second planarization layer PLN2 and the ninth via H09 in the inorganic encapsulation layer TFE.

[0238] For example, the material of the series electrode 810 may include indium tin oxide or indium zinc oxide, and the thickness of the series electrode 810 may be 100 nanometers to 500 nanometers.

[0239] Referring to FIG16J, a light-blocking layer BANK is formed on the side of the second planarization layer PLN2 away from the substrate 100. The light-blocking layer BANK has a plurality of fifth openings KK5, and a plurality of light-emitting devices 310 are located in the plurality of fifth openings KK5. The surface of the light-blocking layer BANK away from the substrate 100 is further away from the substrate 100 than the surface of the light-emitting devices 310 away from the substrate 100.

[0240] A color conversion layer 700 is formed on the side of the second planarization layer PLN2 away from the substrate 100. The color conversion layer 700 includes a plurality of color conversion portions 710. The surface of the color conversion portion 710 away from the substrate 100 is further away from the substrate 100 than the surface of the light-emitting device 310 away from the substrate 100. The color conversion portion 710 is located in the fifth opening KK5 of the light-blocking layer BANK and covers the light-emitting device 310.

[0241] A color filter layer CF is formed on the side of the color conversion layer 700 away from the substrate 100. The color filter layer CF includes a plurality of color filter portions, which are respectively located on the side of the plurality of color conversion portions 710 away from the substrate 100.

[0242] A black matrix layer BM is formed on the side of the color conversion layer 700 away from the substrate 100, and the black matrix layer BM fills the spacer area in the color filter layer CF.

[0243] An organic protective layer OC is formed on the side of the black matrix layer and the color filter layer CF away from the substrate 100, thus preparing the display substrate.

[0244] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0245] It should be understood that the display panel and display device according to the embodiments of this disclosure have all the features and advantages of the display substrate described above, as detailed in the above description, which will not be repeated here. Although some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; The driving circuit layer is located on the substrate. A bonding metal layer is located on the side of the driving circuit layer away from the substrate. The bonding metal layer includes a plurality of first bonding pads and a plurality of power lines arranged at intervals. The plurality of first bonding pads are electrically connected to the driving circuit layer. Multiple light-emitting devices are located on the side of the bonding metal layer away from the substrate, and the multiple light-emitting devices are electrically connected to the multiple first bonding pads respectively; The substrate has a first surface facing the driving circuit layer, the first bonding pad has a first distance between the surface away from the substrate and the first surface, and the power trace has a second distance between the surface away from the substrate and the first surface, wherein the first distance is greater than the second distance.

2. The display substrate according to claim 1, wherein, The difference between the first spacing and the second spacing is greater than or equal to 2 micrometers and less than or equal to 5 micrometers.

3. The display substrate according to claim 1 or 2, wherein, The substrate includes a pad layer located between the driving circuit layer and the bonding metal layer. The orthographic projection of the first bonding pad on the substrate at least partially overlaps with the orthographic projection of the pad layer on the substrate. The orthographic projection of the power trace on the substrate is spaced apart from the orthographic projection of the pad layer on the substrate.

4. The display substrate according to claim 3, wherein, The padding layer includes a plurality of padding portions spaced apart, and the plurality of first bonding pads are respectively located on the side of the plurality of padding portions away from the substrate.

5. The display substrate according to claim 3, wherein, The orthographic projection of the first bonding pad on the substrate is located within the orthographic projection of the raised portion on the substrate.

6. The display substrate according to claim 3, wherein, The padding layer includes multiple trenches, and multiple power traces are located in the multiple trenches respectively. The orthographic projection of the trenches on the substrate is spaced apart from the orthographic projection of the first bonding pad on the substrate.

7. The display substrate according to claim 6, wherein, The power supply line is spaced apart from the side of the pad layer located in the trench.

8. The display substrate according to any one of claims 3-7, wherein, The display substrate further includes a first planarization layer, which is located between the padding layer and the driving circuit layer. The elastic modulus of the material of the padding layer is less than that of the material of the first planarization layer.

9. The display substrate according to claim 8, wherein, The material of the padding layer includes at least one of polyimide and polymethyl methacrylate.

10. The display substrate according to claim 1 or 2, wherein, The thickness of the first bonding pad perpendicular to the first surface is greater than the thickness of the power trace perpendicular to the first surface.

11. The display substrate according to claim 10, wherein, The first bonding pad includes a first pad portion and a second pad portion connected together. The second pad portion is located on the side of the first pad portion away from the substrate. The thickness of the first pad portion perpendicular to the first surface is approximately the same as the thickness of the power trace perpendicular to the first surface.

12. The display substrate according to claim 11, wherein, The orthographic projection of the surface of the second pad portion near the substrate onto the substrate lies within the orthographic projection of the surface of the first pad portion away from the substrate onto the substrate.

13. The display substrate according to any one of claims 1-12, wherein, The bonding metal layer further includes connection traces, which are integrally connected to the first bonding pad; and The display substrate further includes a first planarization layer, which is located between the bonding metal layer and the driving circuit layer. The first planarization layer has a first via, and the connection trace is electrically connected to the driving circuit layer through the first via. The orthographic projection of the first via on the substrate is perpendicular to the first bonding metal layer. The bonding pads are spaced apart by their orthogonal projections onto the substrate.

14. The display substrate according to any one of claims 1-12, wherein, The display substrate further includes a second planarization layer, which is located on the side of the bonding metal layer away from the substrate and in the spacing region between adjacent light-emitting devices. as well as The surface of the second planarization layer that is farther from the substrate is farther from the substrate than the surface of the first bonding pad that is farther from the substrate; And / or, the surface of the second planarization layer away from the substrate is closer to the substrate than the surface of the light-emitting device that is closer to the substrate.

15. The display substrate according to claim 14, wherein, The display substrate further includes a third planarization layer located on the side of the second planarization layer away from the substrate. The third planarization layer has a plurality of spaced-apart planarization portions, each covering a side surface of a plurality of light-emitting devices. Each planarization portion has a first opening that exposes a portion of the surface of the light-emitting device away from the substrate. The display substrate further includes a series electrode located on the side of the third planarization layer away from the substrate. In at least two adjacent light-emitting devices, one end of the series electrode is electrically connected to the side of one of the light-emitting devices away from the substrate through the first opening, and the other end extends along the side of the planarization portion to the surface of the second planarization layer away from the substrate and is electrically connected to a first bonding pad connected to another light-emitting device through a second via in the second planarization layer.

16. The display substrate according to claim 15, wherein, The planarization portion surrounds the side of the light-emitting device at an acute angle to the surface of the planarization portion near the substrate; and / or The planarization portion is located at the side of the first opening, forming an obtuse angle with the surface of the light-emitting device away from the substrate.

17. The display substrate according to claim 15 or 16, wherein, The display substrate further includes a reflective layer located on the side of the second planarization layer away from the substrate. The reflective layer includes at least one reflective portion located between adjacent light-emitting devices and has a reflective surface facing the adjacent light-emitting devices.

18. The display substrate according to claim 17, wherein, The display substrate further includes: A black matrix layer, located on the side of the reflective layer away from the substrate, the reflective layer having a plurality of second openings, and the black matrix layer having a plurality of third openings, the plurality of second openings and the plurality of third openings respectively communicating with each other, the light-emitting device being located within the communicating second and third openings; and A color conversion layer is located on the side of the light-emitting device away from the substrate. The color conversion layer includes a plurality of color conversion sections, which are located within the second opening and the third opening. The surface of the color conversion section away from the substrate is further away from the substrate than the surface of the reflective section away from the substrate.

19. The display substrate according to claim 17, wherein, The plurality of reflective portions are connected in a grid pattern, the reflective layer has a plurality of second openings, and the plurality of planarization portions are located within the plurality of second openings.

20. The display substrate according to claim 19, wherein, The reflective portion is spaced apart from the adjacent planarization portion, and the display substrate further includes a color conversion layer located on the side of the light-emitting device away from the substrate, a portion of which is located between the reflective portion and the planarization portion.

21. The display substrate according to any one of claims 17-20, wherein, The surface of the reflective portion that is farther from the substrate is farther from the substrate than the surface of the planarized portion that is farther from the substrate.

22. The display substrate according to any one of claims 17-21, wherein, The reflective layer includes a fourth planarization layer located on the side of the second planarization layer away from the substrate and a reflective metal layer located on the side of the fourth planarization layer away from the substrate. The fourth planarization layer has a plurality of sixth openings, and the light-emitting device is located within the sixth opening; as well as The reflective metal layer includes a plurality of spaced-apart reflective metal portions that cover at least a portion of the side of the fourth planarization layer located at the sixth opening. The reflective metal portions have reflective surfaces facing adjacent light-emitting devices, and adjacent reflective metal portions are disconnected at the surface of the fourth planarization layer away from the substrate.

23. A method for preparing a display substrate, wherein, The preparation method includes: A driving circuit layer is formed on a substrate, the substrate having a first surface facing the driving circuit layer. noodle; A bonding metal layer is formed on the side of the driving circuit layer away from the substrate. The bonding metal layer includes a plurality of first bonding pads and a plurality of power traces spaced apart. The plurality of first bonding pads are electrically connected to the driving circuit layer. A first spacing exists between the surface of the first bonding pads away from the substrate and the first surface. A second spacing exists between the surface of the power traces away from the substrate and the first surface. The first spacing is greater than the second spacing. Multiple light-emitting devices are formed on the side of the bonding metal layer away from the substrate, and the multiple light-emitting devices are electrically connected to the multiple first bonding pads respectively.

24. A display device, wherein, The display device includes a display substrate according to any one of claims 1-22.

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