Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of sub-pixels; at least one sub-pixel comprises a pixel driving circuit; the pixel driving circuit at least comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), and a shielding electrode (60); a first electrode of the second transistor (T2) is coupled to a first power line (81), and a second electrode of the second transistor (T2) is coupled to a first electrode of the third transistor (T3); a first electrode of the fourth transistor (T4) is coupled to a second power line (82), and a second electrode of the fourth transistor (T4) is coupled to a second electrode of the third transistor (T3); the shielding electrode (60) is connected to the first power line (81), and the orthographic projection of the shielding electrode (60) on a plane of the display substrate at least partially overlaps with the orthographic projection of a gate electrode of the third transistor (T3) on the plane of the display substrate.

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve weight reduction. Silicon-based OLEDs offer advantages such as small size, high resolution, and high refresh rate, and are widely used in near-eye displays for virtual reality and augmented reality.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate including a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel includes a pixel driving circuit, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor. The first electrode of the first transistor is coupled to a data signal line, the second electrode of the first transistor is coupled to the gate electrode of the third transistor, the first electrode of the second transistor is coupled to a first power line, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the first electrode of the fourth transistor is coupled to a second power line, and the second electrode of the fourth transistor is coupled to the second electrode of the third transistor. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the pixel driving circuit. At least one sub-pixel also includes a shielding electrode connected to the first power line. The orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0006] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the shielding electrode on the display substrate plane and the orthographic projection of the gate electrode of the third transistor on the display substrate plane has a first area, and the orthographic projection of the gate electrode of the third transistor on the display substrate plane has a second area, wherein the ratio of the first area to the second area is greater than or equal to 0.8.

[0007] In an exemplary embodiment, in the pixel row direction, there is a shielding gap between two adjacent shielding electrodes, the shielding gap being less than twice the width of the first power line, or the shielding gap being less than twice the width of the second power line.

[0008] In an exemplary embodiment, the first transistor includes at least a first source region and a first drain region, the second transistor includes at least a second source region and a second drain region, the third transistor includes at least a third source region and a third drain region, and the fourth transistor includes at least a fourth source region and a fourth drain region; the first drain region is connected to the gate electrode of the third transistor through a first node electrode, the second drain region is connected to the third source region and connected to the second node electrode through a via, and the third drain region is connected to the fourth drain region through a third node electrode; in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, and the first node electrode, the second node electrode, the third node electrode, and the shielding electrode are disposed in the same conductive layer.

[0009] In an exemplary embodiment, at least one sub-pixel further includes a first power connection electrode, and the shielding electrode is connected to the first power line through the first power connection electrode; in the pixel row direction, the first power connection electrode is disposed between the first node electrode and the second node electrode.

[0010] In an exemplary embodiment, the first power connection electrode includes at least a horizontal electrode extending along the pixel row direction and a first vertical electrode and a second vertical electrode extending along the pixel column direction. The first vertical electrode and the second vertical electrode are respectively disposed on both sides of the horizontal electrode in the pixel column direction. One end of the first vertical electrode is connected to the first power line and the other end is connected to the horizontal electrode. One end of the second vertical electrode is connected to the shielding electrode and the other end is connected to the horizontal electrode. In the pixel row direction, the second vertical electrode is disposed between the first node electrode and the second node electrode.

[0011] In an exemplary embodiment, at least one sub-pixel further includes a second power connection electrode disposed on the same layer as the data signal line. The first power line is connected to the second power connection electrode through a via, and the second power connection electrode is connected to the first power connection electrode through a via. In the pixel row direction, the spacing between the second power connection electrode in this sub-pixel and the data signal line in the adjacent sub-pixel is greater than or equal to the width of the data signal line.

[0012] In an exemplary embodiment, at least one sub-pixel further includes a data connection strip, a first end of which is connected to the data signal line, and a second end of which extends toward the second power connection electrode and is connected to the first electrode of the second transistor; in the pixel row direction, the distance between the second power connection electrode in the sub-pixel and the data connection strip in the sub-pixel is greater than or equal to the width of the data signal line.

[0013] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first metal layer disposed on a silicon substrate, a second metal layer disposed on the side of the first metal layer away from the silicon substrate, and a third metal layer disposed on the side of the second metal layer away from the silicon substrate; the first node electrode, the second node electrode, the third node electrode, and the shielding electrode are disposed in the first metal layer, the first power connection electrode is disposed in the second metal layer, and the data signal line and the second power connection electrode are disposed in the third metal layer.

[0014] In an exemplary embodiment, the second power line is disposed in the first metal layer, and the second metal layer further includes a second connecting line. The shape of the second power line is a straight line or a broken line extending along the pixel row direction and is continuously disposed in the pixel row direction. The shape of the second connecting line is a straight line or a broken line extending along the pixel column direction and is not continuously disposed in the pixel column direction. The second connecting line is connected to the second power line to form a mesh-like interconnected structure for transmitting the second power signal.

[0015] In an exemplary embodiment, the gate electrode of the fourth transistor is coupled to a third scan signal line, the shape of which is a straight line or a broken line extending along the pixel row direction; in the pixel column direction, the second connecting line is spaced apart by the third scan signal line.

[0016] In an exemplary embodiment, at least one sub-pixel further includes a power connection portion disposed on the same layer as the second power line. The power connection portion is a strip shape extending along the pixel row direction. A first end of the power connection portion is connected to the second power line, and a second end of the power connection portion extends away from the second power line and is connected to the second connection line through a via.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a first capacitor, which includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The first electrode plate is connected to the first node electrode, and the second electrode plate is connected to the second node electrode.

[0018] In an exemplary embodiment, at least one sub-pixel further includes a compensation electrode, the second electrode plate is connected to the second node electrode through the compensation electrode, the orthographic projection of the compensation electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane, the compensation electrode and the first electrode plate form a parasitic capacitance, and the parasitic capacitance is connected in parallel with the first capacitance.

[0019] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the compensation electrode on the display substrate plane and the orthographic projection of the first electrode plate on the display substrate plane has a third area, and the orthographic projection of the first electrode plate on the display substrate plane has a fourth area, wherein the ratio of the third area to the fourth area is greater than or equal to 0.5.

[0020] In an exemplary embodiment, at least one sub-pixel further includes a second connecting line and a thirteenth connecting electrode disposed on the same layer as the compensation electrode. The second connecting line is connected to the second power line and is disposed between two adjacent compensation electrodes in the pixel row direction. The thirteenth connecting electrode is connected to the first node electrode through a via. There is a first distance between the compensation electrode and the second connecting line, and a second distance between the compensation electrode and the thirteenth connecting electrode. The first distance is less than the second distance. The first distance is a dimension in the pixel row direction, and the second distance is a dimension in the pixel column direction.

[0021] In an exemplary embodiment, at least one sub-pixel further includes a sixteenth connecting electrode disposed on the same layer as the compensation electrode, the sixteenth connecting electrode being connected to the third node electrode through a via; there is a third distance between the compensation electrode and the sixteenth connecting electrode, the first distance being smaller than the third distance, the third distance being a dimension in the pixel column direction.

[0022] In an exemplary embodiment, at least one sub-pixel further includes a first power connection electrode and a thirteenth connection electrode disposed on the same layer as the compensation electrode. The shielding electrode is connected to the first power line through the first power connection electrode, and the thirteenth connection electrode is connected to the first node electrode through a via. There is a fourth distance between the first power connection electrode and the thirteenth connection electrode, and the second distance is greater than the fourth distance. The fourth distance is a dimension in the pixel row direction.

[0023] In an exemplary embodiment, at least one sub-pixel further includes a first power connection electrode and an eleventh connection electrode disposed on the same layer as the compensation electrode. The shielding electrode is connected to the first power line through the first power connection electrode, and the eleventh connection electrode is configured to be connected to the data signal line. There is a fifth distance between the first power connection electrode and the second connection line, and a sixth distance between the first power connection electrode and the eleventh connection electrode. The fifth distance is smaller than the sixth distance, and the fifth distance and the sixth distance are dimensions in the pixel row direction.

[0024] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first metal layer disposed on a silicon substrate, a second metal layer disposed on the side of the first metal layer away from the silicon substrate, and a third metal layer disposed on the side of the second metal layer away from the silicon substrate; the first node electrode and the second node electrode are disposed in the first metal layer, the compensation electrode is disposed in the second metal layer, and the first electrode plate is disposed in the third metal layer.

[0025] In an exemplary embodiment, the gate electrode of the first transistor is coupled to a first scan signal line, and the first scan signal line and the first power line are in the shape of a straight line or a broken line extending along the pixel row direction; in the pixel column direction, the first power line is disposed between two adjacent first scan signal lines.

[0026] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0027] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the fabrication method comprising:

[0028] A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor. The first electrode of the first transistor is coupled to a data signal line, the second electrode of the first transistor is coupled to the gate electrode of the third transistor, the first electrode of the second transistor is coupled to a first power line, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the first electrode of the fourth transistor is coupled to a second power line, and the second electrode of the fourth transistor is coupled to the second electrode of the third transistor. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the pixel driving circuit. The at least one sub-pixel also includes a shielding electrode connected to the first power line. The orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0031] Figure 1 is a schematic diagram of a silicon-based OLED display device;

[0032] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0033] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device;

[0034] Figure 4 is an equivalent circuit diagram of a pixel driving circuit;

[0035] Figure 5 is a driving timing diagram of the pixel driving circuit shown in Figure 4;

[0036] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 7 is a schematic diagram showing the N-well region, P-well region, and active region patterns formed according to the embodiments of this disclosure;

[0038] Figures 8A and 8B are schematic diagrams of the gate conductive layer pattern formed according to an embodiment of the present disclosure;

[0039] Figures 9A and 9B are schematic diagrams of the N-type doped region pattern formed according to the embodiments of this disclosure;

[0040] Figures 10A and 10B are schematic diagrams of the P-type doped region pattern formed according to the embodiments of this disclosure;

[0041] Figure 11 is a schematic diagram of the second insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0042] Figures 12A and 12B are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure;

[0043] Figure 13 is a schematic diagram of the third insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0044] Figures 14A and 14B are schematic diagrams of the second conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0045] Figure 15 is a schematic diagram of the fourth insulating layer pattern formed according to an embodiment of the present disclosure;

[0046] Figures 16A and 16B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0047] Figures 17A and 17B are schematic diagrams showing the formation of the fifth insulating layer and the fourth conductive layer in an embodiment of this disclosure.

[0048] Figure 18 is a schematic diagram of the formation of the sixth insulating layer pattern according to an embodiment of the present disclosure;

[0049] Figures 19A and 19B are schematic diagrams of the fifth conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0050] Figures 20A and 20B are schematic diagrams showing the formation of the seventh insulating layer and the sixth conductive layer according to an embodiment of the present disclosure.

[0051] Figure 21 is a schematic diagram of the formation of the eighth insulating layer pattern according to an embodiment of the present disclosure;

[0052] Figures 22A and 22B are schematic diagrams of the formation of the seventh conductive layer pattern according to an embodiment of the present disclosure;

[0053] Figure 23 is a schematic diagram of the structure of the first capacitor and the second capacitor in an embodiment of this disclosure.

[0054] Explanation of reference numerals in the attached figures:

[0055] 10A—N-well region; 10B—P-well region; 11—First active region;

[0056] 12—Second active region; 13—Third active region; 14—Fourth active region;

[0057] 15—First power supply region; 16—Second power supply region; 20A—N-type doped region;

[0058] 20B—P-type doped region; 21—First gate electrode; 22—Second gate electrode;

[0059] 23—Third gate electrode; 24—Fourth gate electrode; 31—First scan signal line;

[0060] 32—Second scan signal line; 33—Third scan signal line; 41—First connecting electrode;

[0061] 42—Second connecting electrode; 43—Third connecting electrode; 44—Fourth connecting electrode;

[0062] 45—Fifth connecting electrode; 46—Sixth connecting electrode; 47—Seventh connecting electrode;

[0063] 48—Eighth connecting electrode; 49—Ninth connecting electrode; 50—Shielding electrode;

[0064] 51—Eleventh connecting electrode; 52—Twelfth connecting electrode; 53—Thirteenth connecting electrode;

[0065] 54—Fourteenth connecting electrode; 55—Fifteenth connecting electrode; 56—Sixteenth connecting electrode;

[0066] 61—Twenty-first connecting electrode; 62—Twenty-second connecting electrode; 63—Twenty-third connecting electrode;

[0067] 64—Twenty-fourth connecting electrode; 65—Twenty-fifth connecting electrode; 70—Data signal line;

[0068] 71—Data connection bar; 81—First power cable; 82—Second power cable;

[0069] 83—Anode connection electrode; 92—Second connection line; 93—Third connection line;

[0070] 94—Fourth connecting line; 95—Fifth connecting line; 96—Sixth connecting line;

[0071] 97—Seventh connection line; 101—Silicon substrate; 102—Driver circuit layer;

[0072] 103—Light-emitting structure layer; 104—First encapsulation layer; 105—Color filter structure layer;

[0073] 106—Second encapsulation layer; 107—Cover layer; 110—First electrode plate;

[0074] 120—Second plate; 130—Third plate; 140—Fourth plate;

[0075] 201—First insulating layer; 202—Second insulating layer; 203—Third insulating layer;

[0076] 204—Fourth insulating layer; 205—Fifth insulating layer; 206—Sixth insulating layer;

[0077] 207—Seventh insulating layer; 208—Eighth insulating layer. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0079] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0080] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0081] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0082] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0083] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0084] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0085] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0086] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0087] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0088] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0089] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0090] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0091] Figure 1 is a schematic diagram of a silicon-based OLED display device. As shown in Figure 1, the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is connected to the i-th scan signal line and the j-th data signal line, respectively. i and j can be natural numbers. The non-display area may include at least a gate driver (GD) and a source driver (SD). The gate driver is connected to multiple scan signal lines in the display area and is configured to provide the necessary timing signals to the connected pixel driving circuits to achieve progressive scan functionality. The source driver is connected to multiple data signal lines in the display area and is configured to provide the necessary data signals to the connected pixel driving circuits to achieve switching and control of the display screen.

[0092] In one exemplary embodiment, the silicon-based OLED display device can be a one-chip display architecture, integrating gate driving devices, data driving devices, clock control circuits, image processing units, and memory units onto the same chip. The one-chip architecture chip includes both digital and analog parts, belonging to mixed-signal chips.

[0093] In another exemplary embodiment, the silicon-based OLED display device may be a two-chip display architecture, in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control circuit, the image processing unit, the mobile industry processor interface (MIPI), and the memory unit are integrated in one chip, which is bonded to the display substrate through a COC process.

[0094] Figure 2 is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device. As shown in Figure 2, on a plane parallel to the display device, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0095] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0096] In exemplary embodiments, the shape of a sub-pixel can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular pattern, etc., and this disclosure does not limit the arrangement. In other possible embodiments, a pixel unit may include four sub-pixels, and this disclosure does not limit the arrangement.

[0097] Figure 3 is a schematic cross-sectional view of the display area in a silicon-based OLED display device, illustrating a structure that achieves full color using a white light + color filter approach. As shown in Figure 3, in the direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited herein.

[0098] In an exemplary embodiment, the silicon substrate 101 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 can be fabricated on the silicon substrate 101 using silicon semiconductor processes. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit. The pixel driving circuit is connected to the scan signal line and data signal line, respectively. The pixel driving circuit can include multiple transistors and storage capacitors; only one transistor is shown as an example in Figure 3. The transistor can include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, source electrode S, and drain electrode D can be connected to corresponding connection electrodes via tungsten-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) via the connection electrodes.

[0099] In an exemplary embodiment, the light-emitting structure layer 103 may include multiple light-emitting devices. Each light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode D of a transistor via a connecting electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to a second power line. The organic light-emitting layer emits light under the drive of the anode and cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0100] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can employ thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is located in the red sub-pixel and filters the white light emitted by the light-emitting device into red light. The blue filter unit is located in the blue sub-pixel and filters the white light emitted by the light-emitting device into blue light. The green filter unit is located in the green sub-pixel and filters the white light emitted by the light-emitting device into green light. The cover plate layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0101] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit is a current-type 4T2C structure, which may include four transistors (first transistor T1, second transistor T2, third transistor T3 and fourth transistor T4) and two storage capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is coupled to six signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, data signal line DATA, first power supply line VDD and second power supply line VSS).

[0102] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is coupled to the second terminal of a first transistor T1, the gate electrode of a third transistor T3, and the first terminal of a first capacitor C1. The second node N2 is coupled to the second terminal of a second transistor T2, the first terminal of a third transistor T3, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is coupled to the second terminal of a third transistor T3 and the second terminal of a fourth transistor T4.

[0103] In an exemplary embodiment, the signal of the first scan signal line S1 can be a write switch (WS) signal, and the first scan signal line S1 can also be referred to as the write switch signal line WS. The signal of the second scan signal line S2 can be a display switch (DS) signal, and the second scan signal line S2 can also be referred to as the display switch signal line DS. The signal of the third scan signal line S3 can be a display reset (Auto Zero, AZ) signal, and the third scan signal line S3 can also be referred to as the display reset signal line AZ.

[0104] In an exemplary embodiment, the first transistor T1 may be referred to as a data write transistor or a source driver transistor. The gate electrode of the first transistor T1 is coupled to the first scan signal line S1, the first electrode of the first transistor T1 is coupled to the data signal line DATA, and the second electrode of the first transistor T1 is coupled to the first node N1.

[0105] In an exemplary embodiment, the second transistor T2 is a compensation transistor referred to as the threshold voltage (Vth). The gate electrode of the second transistor T2 is coupled to the second scan signal line S2. The first terminal of the second transistor T2 is coupled to the first power supply line VDD and the first terminal of the second capacitor C2, respectively. The second terminal of the second transistor T2 is coupled to the second node N2.

[0106] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor. The gate electrode of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the second node N2, and the second electrode of the third transistor T3 is coupled to the third node N3.

[0107] In an exemplary embodiment, the fourth transistor T4 may be referred to as an Auto Zero transistor. The gate electrode of the fourth transistor T4 is coupled to the third scan signal line S3, the first electrode of the fourth transistor T4 is coupled to the second power supply line VSS, and the second electrode of the fourth transistor T4 is coupled to the third node N3.

[0108] In an exemplary embodiment, the first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the first capacitor C1 is coupled to the second node N2. The first terminal of the second capacitor C2 is coupled to the first power line VDD, and the second terminal of the second capacitor C2 is coupled to the second node N2.

[0109] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. The first electrode of the light-emitting device EL is connected to a third node N3, and the second electrode of the light-emitting device EL is connected to a common voltage line VCOM.

[0110] In an exemplary embodiment, the signal of the first power line VDD can be a continuously supplied first power signal (high-level signal), the signal of the second power line VSS can be a continuously supplied second power signal (low-level signal), the voltage of the first power signal is greater than the voltage of the second power signal, and the signal of the common voltage line VCOM can be a continuously supplied low-level signal.

[0111] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be P-type transistors, and the fourth transistor T4 can be an N-type transistor.

[0112] Figure 5 is a timing diagram of one possible driving mechanism for the pixel driving circuit shown in Figure 4. In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0113] The first stage, A1, can be called the reset stage. The signals on the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal on the third scan signal line S3 is high-level, turning on the first transistor T1, the second transistor T2, and the fourth transistor T4. The first transistor T1 turns on, causing the bias voltage Vofs output from the data signal line DATA to be written into the first capacitor C1. The potential Vg of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vg = Vofs. The second transistor T2 turns on, causing the first power supply voltage ELVDD output from the first power supply line VDD to be written into the second node N2. The potential Vs of the second node N2 (i.e., the first electrode of the third transistor T3) is Vs = ELVDD, and the potential Vd of the third node N3 (i.e., the second electrode of the third transistor T3) is Vd = Vg + Vth. At this time, the gate-source voltage Vgs of the third transistor T3 is Vcs = ELVDD - Vofs, where Vcs is the storage voltage of the first capacitor C1. Let ELVDD - V... ofs >|Vth|, prepares for the next stage of discharge, where Vth is the threshold voltage of the third transistor T3.

[0114] The second stage, A2, can be called the self-discharge stage or the threshold reading stage. The signal on the third scan signal line S3 is high, and the fourth transistor T4 remains on. The signal on the first scan signal line S1 changes from low to high, causing the first transistor T1 to turn off first, and the first node N1 to float. Subsequently, the signal on the second scan signal line S2 changes from low to high, causing the second transistor T2 to turn off. The second node N2 forms a circuit through the on-state third transistor T3, the third node N3, and the on-state fourth transistor T4, and begins to discharge, causing the potential of the second node N2 to decrease. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged; therefore, the potential of the first node N1 decreases as the potential of the second node N2 decreases. Due to the back-gate effect of the third transistor T3, the equivalent threshold voltage |V| of the third transistor T3... th_EF |=α(ELVDD-Vs)+|Vth|. As the potential Vs of the second node N2 decreases, the equivalent threshold voltage |Vth| of the third transistor T3... th_EF |Gradually increase, as the equivalent threshold voltage of the third transistor T3|V th_EF When the gate-source voltage Vgs of the third transistor T3 is increased, the third transistor T3 is turned off, and the second node N2 stops discharging.

[0115] The third stage, A3, can be called the data writing stage or the threshold compensation stage. The signal on the third scan signal line S3 is high, and the fourth transistor T4 remains on. The signal on the second scan signal line S2 is high, and the second transistor T2 remains off. The signal on the first scan signal line S1 changes from high to low, turning on the first transistor T1. The turning on of the first transistor T1 causes the data voltage Vdata output from the data signal line DATA to be written to the first node N1, changing the potential of the first node N1 from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved.

[0116] The fourth stage, A4, can be called the light-emitting stage. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, while the signal on the first scan signal line S1 is high-level, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. The conduction of the second transistor T2 allows the power supply voltage output from the first power line VDD to provide a driving voltage to the first terminal of the light-emitting device EL through the conducting second transistor T2 and third transistor T3, driving the light-emitting device EL to emit light. During the light-emitting stage, the driving current of the third transistor T3 is not affected by its threshold voltage, eliminating the influence of the threshold voltage on the driving current, ensuring uniform brightness of the display product, and improving the overall display effect.

[0117] Currently, silicon-based OLED displays are increasingly being applied in near-eye display fields such as Virtual Reality (VR), Augmented Reality (AR), Extended Reality (XR), and Mixed Reality (MR), allowing users to experience realistic sensations in the virtual reality world. These displays offer powerful simulation systems and enable human-computer interaction. Research shows that when screen resolution is high enough, the human retina cannot distinguish individual pixels. Resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display substrate can display images at a higher density, resulting in richer image details. Therefore, significantly increasing PPI has become a key research focus for manufacturers to improve display quality. Silicon-based OLEDs are manufactured using semiconductor processes. As PPI increases, the spacing between signal lines becomes smaller. Process fluctuations or particle issues can cause short circuits between different signal lines, resulting in defects such as horizontal lines, vertical lines, or cross lines. In addition, with the increase of PPI, the spacing between the capacitor plates and the signal lines is smaller. When a short circuit occurs between the signal lines and the capacitor plates, defects such as vertical lines may also appear.

[0118] An exemplary embodiment of this disclosure provides a display substrate including a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel includes a pixel driving circuit, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor. A first electrode of the first transistor is coupled to a data signal line, a second electrode of the first transistor is coupled to the gate electrode of the third transistor, a first electrode of the second transistor is coupled to a first power line, a second electrode of the second transistor is coupled to the first electrode of the third transistor, a first electrode of the fourth transistor is coupled to a second power line, and a second electrode of the fourth transistor is coupled to the second electrode of the third transistor. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the pixel driving circuit. At least one sub-pixel also includes a shielding electrode connected to the first power line. The orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0119] In an exemplary embodiment, at least one sub-pixel further includes a first power connection electrode, and the shielding electrode is connected to the first power line through the first power connection electrode; in the pixel row direction, the first power connection electrode is disposed between the first node electrode and the second node electrode.

[0120] In an exemplary embodiment, the pixel driving circuit further includes a first capacitor, which includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The first electrode plate is connected to the first node electrode, and the second electrode plate is connected to the second node electrode.

[0121] In an exemplary embodiment, at least one sub-pixel further includes a compensation electrode, the second electrode plate is connected to the second node electrode through the compensation electrode, the orthographic projection of the compensation electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane, the compensation electrode and the first electrode plate form a parasitic capacitance, and the parasitic capacitance is connected in parallel with the first capacitance.

[0122] The technical solution of the display substrate of this disclosure is described below through exemplary embodiments.

[0123] Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a pixel driving circuit structure of 12 sub-pixels in 2 pixel rows (the Mth pixel row and the M+1th pixel row) and 6 pixel columns (the Nth pixel column to the N+5th pixel column). On a plane parallel to the display substrate, the display substrate may include multiple sub-pixels forming multiple pixel rows and multiple pixel columns. The sub-pixels in a pixel row can be sequentially arranged along a first direction X (i.e., the pixel row direction), and the sub-pixels in a pixel column can be sequentially arranged along a second direction Y (i.e., the pixel column direction). The multiple pixel rows and multiple pixel columns constitute an array-arranged pixel array, with the first direction X intersecting the second direction Y.

[0124] In an exemplary embodiment, at least one sub-pixel may include a pixel driving circuit, which may include at least a first transistor T1 as a data writing transistor, a second transistor T2 as a threshold voltage compensation transistor, a third transistor T3 as a driving transistor, and a fourth transistor T4 as a reset transistor. The gate electrode of the first transistor T1 is coupled to a first scan signal line, the first terminal of the first transistor T1 is coupled to a data signal line, and the second terminal of the first transistor T1 is coupled to the gate electrode of the third transistor T3. The gate electrode of the second transistor T2 is coupled to a second scan signal line, the first terminal of the second transistor T2 is coupled to a first power supply line, and the second terminal of the second transistor T2 is coupled to the first terminal of the third transistor T3. The gate electrode of the fourth transistor T4 is coupled to a third scan signal line, the first terminal of the fourth transistor T4 is coupled to a second power supply line, and the second terminal of the fourth transistor T4 is coupled to the second terminal of the third transistor T3. The first scan signal line, the second scan signal line, and the third scan signal line are configured to provide a first scan signal, a second scan signal, and a third scan signal to the respective pixel driving circuits. The data signal line is configured to provide a data signal to the pixel driving circuits. The first power line and the second power line are configured to provide a first power signal and a second power signal to the pixel driving circuits, respectively. The voltage of the first power signal may be greater than the voltage of the second power signal.

[0125] In an exemplary embodiment, the first scan signal line, the second scan signal line, the third scan signal line, the first power line, and the second power line may be in the shape of a straight line or a broken line extending along the first direction X, and the data signal line may be in the shape of a straight line or a broken line extending along the second direction Y.

[0126] In an exemplary embodiment, in at least one sub-pixel, the second transistor T2 can be disposed on one side of the first transistor T1 in the first direction X, the first transistor T1 and the second transistor T2 can be disposed on one side of the third transistor T3 in the second direction Y, and the fourth transistor T4 can be disposed on the other side of the third transistor T3 in the second direction Y. That is, the second transistor T2 and the fourth transistor T4 can be disposed on opposite sides of the third transistor T3 in the second direction Y. For example, in the Mth pixel row, the first transistor T1 and the second transistor T2 can be disposed on the opposite side of the third transistor T3 in the second direction Y, and the fourth transistor T4 can be disposed on one side of the third transistor T3 in the second direction Y. As another example, in the M+1th pixel row, the first transistor T1 and the second transistor T2 can be disposed on one side of the third transistor T3 in the second direction Y, and the fourth transistor T4 can be disposed on the opposite side of the third transistor T3 in the second direction Y.

[0127] In an exemplary embodiment, the first transistor T1 may include at least a first active region and a first gate electrode 21. The first active region may include at least a first source region 11-1 and a first drain region 11-2 located on both sides of the first gate electrode 21 in the second direction Y. The second transistor T2 may include at least a second active region and a second gate electrode 22. The second active region may include at least a second source region 12-1 and a second drain region 12-2 located on both sides of the second gate electrode 22 in the second direction Y. The third transistor T3 may include at least a third active region and a third gate electrode 23. The third active region may include at least a third source region 13-1 and a third drain region 13-2 located on both sides of the third gate electrode 23 in the second direction Y. The fourth transistor T4 may include at least a fourth active region and a fourth gate electrode 24. The fourth active region may include at least a fourth source region 14-1 and a fourth drain region 14-2 located on both sides of the fourth gate electrode 24 in the first direction X.

[0128] In an exemplary embodiment, at least one sub-pixel may further include a third connecting electrode 43 as a first node electrode, a fourth connecting electrode 44 as a second node electrode, and a fifth connecting electrode 45 as a third node electrode. The first drain region 11-2 can be connected to the third gate electrode 23 via the third connecting electrode 43. The second drain region 12-2 is interconnected with the third source region 13-1 and connected to the fourth connecting electrode 44. The third drain region 13-2 can be connected to the fourth drain region 14-2 via the fifth connecting electrode 45. Specifically, the first end of the third connecting electrode 43 is connected to the first drain region 11-2 via a via, and the first end of the third connecting electrode 43 is connected to the third gate electrode 23 via a via. The fourth connecting electrode 44 is connected to the second drain region 12-2 and the third source region 13-1 via a via. The first end of the fifth connecting electrode 45 is connected to the third drain region 13-2 via a via, and the second end of the fifth connecting electrode 45 is connected to the fourth drain region 14-2 via a via.

[0129] In an exemplary embodiment, at least one sub-pixel may further include a shielding electrode 50, which is connected to a first power line. The orthographic projection of the shielding electrode 50 on the display substrate plane at least partially overlaps with the orthographic projection of the third gate electrode (the gate electrode of the third transistor T3) 23 on the display substrate plane.

[0130] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the shielding electrode 50 on the display substrate plane and the orthographic projection of the third gate electrode 23 on the display substrate plane has a first area, and the orthographic projection of the third gate electrode 23 on the display substrate plane has a second area. The ratio of the first area to the second area can be greater than or equal to 0.8.

[0131] In an exemplary embodiment, the display substrate may include multiple conductive layers in a direction perpendicular to the display substrate. The third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45, and the shielding electrode 50 may be disposed in the same conductive layer and formed synchronously through the same patterning process.

[0132] In an exemplary embodiment, at least one sub-pixel may further include a twelfth connection electrode 52 serving as a first power connection electrode, and the shielding electrode 50 may be connected to the first power line via the twelfth connection electrode 52. In the first direction X, at least a portion of the twelfth connection electrode 52 may be disposed between the third connection electrode 43 and the fourth connection electrode 44.

[0133] In an exemplary embodiment, the twelfth connecting electrode 52 may include at least a first vertical electrode 52-1, a second vertical electrode 52-2, and a horizontal electrode 52-3. The first vertical electrode 52-1 and the second vertical electrode 52-2 may be strip-shaped extending along the second direction Y, and the horizontal electrode 52-3 may be strip-shaped extending along the first direction X. In at least one sub-pixel, the first vertical electrode 52-1 and the second vertical electrode 52-2 may be respectively disposed on both sides of the horizontal electrode 52-3 in the second direction Y. One end of the first vertical electrode 52-1 is connected to the first power line, and the other end is connected to the horizontal electrode 52-3. One end of the second vertical electrode 52-2 is connected to the shielding electrode 50, and the other end is connected to the horizontal electrode 52-3. In the first direction X, the second vertical electrode 52-2 may be disposed between the third connecting electrode 43 and the fourth connecting electrode 44.

[0134] In an exemplary embodiment, the fifth connection electrode 45 may include a first sub-electrode 45-1, a second sub-electrode 45-2, and a third sub-electrode 45-3 connected in sequence. The second sub-electrode 45-2 may be disposed on the side of the first sub-electrode 45-1 away from the third gate electrode 23, and the third sub-electrode 45-3 may be disposed on the side of the second sub-electrode 45-2 away from the third gate electrode 23. The first sub-electrode 45-1 and the third sub-electrode 45-3 may be strip-shaped extending along a first direction X, and the second sub-electrode 45-2 may be strip-shaped extending along a second direction Y. The two ends of the second sub-electrode 45-2 are respectively connected to the first sub-electrode 45-1 and the third sub-electrode 45-3. The first sub-electrode 45-1 is connected to the third drain region 13-2 through a via, and the third sub-electrode 45-3 is connected to the fourth drain region 14-2 through a via.

[0135] In an exemplary embodiment, the second power line 82 may be disposed on the side of the fourth transistor T4 away from the third transistor T3 and continuously disposed in the first direction X, and two adjacent pixel rows may share the same second power line 82.

[0136] In an exemplary embodiment, at least one sub-pixel may further include a second connecting line 92. The shape of the second connecting line 92 may be a straight line or a broken line extending along the second direction Y, and it is not continuously arranged in the second direction Y. The second power line 82 is connected to the second connecting line 92 to form a mesh-like interconnected structure for transmitting the second power signal.

[0137] In an exemplary embodiment, in the second direction Y, the second connection line 92 is spaced apart by the third scan signal line.

[0138] In an exemplary embodiment, at least one sub-pixel may further include a sixth connection electrode 46 or a ninth connection electrode 49 as a power connection portion. The shape of the sixth connection electrode 46 and the ninth connection electrode 49 may be a strip extending along the second direction Y. The first end of the sixth connection electrode 46 and the ninth connection electrode 49 is connected to the second power line 82. The second end of the sixth connection electrode 46 and the ninth connection electrode 49 extends in a direction away from the second power line 82 and is connected to the second connection line 92 through a via.

[0139] In an exemplary embodiment, the pixel driving circuit may further include a first capacitor, which includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The first electrode plate is connected to a third connecting electrode 43, and the second electrode plate is connected to a fourth connecting electrode 44.

[0140] In an exemplary embodiment, at least one sub-pixel further includes a fourteenth connecting electrode 54 as a compensation electrode, and the second electrode plate is connected to the fourth connecting electrode 44 through the fourteenth connecting electrode 54. The orthographic projection of the fourteenth connecting electrode 54 on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane, and the fourteenth connecting electrode 54 and the first electrode plate form a parasitic capacitance, which is connected in parallel with the first capacitor.

[0141] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the fourteenth connecting electrode 54 on the display substrate plane and the orthographic projection of the first electrode plate on the display substrate plane has a third area, and the orthographic projection of the first electrode plate on the display substrate plane has a fourth area. The ratio of the third area to the fourth area can be greater than or equal to 0.5.

[0142] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first metal layer (first conductive layer) disposed on a silicon substrate, a second metal layer (second conductive layer) disposed on the side of the first metal layer away from the silicon substrate, and a third metal layer (third conductive layer) disposed on the side of the second metal layer away from the silicon substrate. The third connecting electrode 43, the fourth connecting electrode 44, the fifth connecting electrode 45, and the shielding electrode 50 may be disposed in the first metal layer, the twelfth connecting electrode 52 and the fourteenth connecting electrode 54 may be disposed in the second metal layer, and the first electrode plate may be disposed in the third metal layer.

[0143] In an exemplary embodiment, the second power line 82 may be disposed in the first metal layer, the second connecting line 92 may be disposed in the second metal layer, and the data signal line may be disposed in the third metal layer.

[0144] In an exemplary embodiment, the display substrate may include at least a first center line O1 and a second center line O2. The first center line O1 may be a straight line located between adjacent pixel rows and extending along a first direction X, and the second center line O2 may be a straight line located between adjacent pixel columns and extending along a second direction Y.

[0145] In an exemplary embodiment, the pixel driving circuits of adjacent pixel rows can be substantially mirror-symmetrical with respect to the first center line O1.

[0146] In an exemplary embodiment, the positions and shapes of the first transistor T1, the second transistor T2, and the third transistor T3 in adjacent pixel columns may be substantially the same, and the fourth transistor T4 in adjacent pixel columns may be substantially mirror-symmetrical with respect to the second center line O2.

[0147] The following is an illustrative description of the fabrication process of a display device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes coating the organic material, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition (CVD); coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0148] In an exemplary embodiment, taking 12 sub-pixels in 2 pixel rows (the Mth pixel row and the M+1th pixel row) and 6 pixel columns (the Nth pixel column to the N+5th pixel column) as an example, the fabrication process of the display substrate may include the following steps.

[0149] (1) Form N-well region, P-well region and active region pattern on silicon substrate, as shown in Figure 7.

[0150] In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate, which can serve as the channel region of an N-type transistor. In some possible embodiments, the silicon substrate may be an N-type silicon material, which can serve as the channel region of a P-type transistor; this disclosure is not limited thereto.

[0151] In an exemplary embodiment, a photoresist pattern including an opening region can be formed by coating photoresist on a P-type silicon substrate, followed by exposure and development. The photoresist within the opening region is removed, exposing the surface of the P-type silicon substrate. N-type dopant ions are then implanted into the opening region via ion implantation. The remaining photoresist is stripped away, forming an N-well (N-type well, NW) region 10A on the P-type silicon substrate. A P-well (P-type well, PW) region 10B is formed outside the N-well region 10A. Subsequently, an active region pattern is formed on the silicon substrate with the aforementioned pattern.

[0152] In an exemplary embodiment, N-well region 10A is configured to form P-type transistors and P-type devices, and P-well region 10B (the region other than N-well region 10A) is configured to form N-type transistors and N-type devices.

[0153] In an exemplary embodiment, the n-type dopant ions can be phosphorus or arsenic plasma implanters, and the ion implantation depth and doping concentration can be achieved by controlling the implantation energy and dosage. The process for forming the N-well region may also include processes such as annealing, which allow the ion implanter to diffuse in the p-type silicon substrate, forming a stable N-well structure.

[0154] In an exemplary embodiment, in at least one sub-pixel, the N-well region 10A and the P-well region 10B can be rectangular in shape, and the N-well region 10A and the P-well region 10B can be sequentially arranged along the second direction Y. For example, in multiple sub-pixels in the Mth pixel row, the P-well region 10B can be located on one side of the N-well region 10A in the second direction Y. Similarly, in multiple sub-pixels in the M+1th pixel row, the N-well region 10A can be located on one side of the P-well region 10B in the second direction Y.

[0155] In an exemplary embodiment, in a pixel row, the N-well regions 10A of multiple sub-pixels can be an interconnected integral structure, and the P-well regions 10B of multiple sub-pixels can be an interconnected integral structure.

[0156] In an exemplary embodiment, the N-well regions 10A and P-well regions 10B of adjacent pixel rows can be mirror-symmetric with respect to the first center line O1. For example, the N-well regions 10A in the M-th pixel row and the (M+1)-th pixel row can be mirror-symmetric with respect to the first center line O1. Similarly, the P-well regions 10B in the M-th pixel row and the (M+1)-th pixel row can be mirror-symmetric with respect to the first center line O1.

[0157] In an exemplary embodiment, the two N-well regions 10A of partially adjacent pixel rows can be interconnected as a single structure, and the P-well regions 10B of partially adjacent pixel rows can be interconnected as a single structure. For example, the two N-well regions 10A in the (M-1)th pixel row and the Mth pixel row can be interconnected as a single structure, and the two N-well regions 10A in the (M+1)th pixel row and the (M+2)th pixel row can be interconnected as a single structure. Similarly, the two P-well regions 10B in the Mth pixel row and the (M+1)th pixel row can be interconnected as a single structure.

[0158] This disclosure enables the first transistor T1, the second transistor T2, and the third transistor T3 in adjacent pixel rows to share the same N-well region 10A, and the fourth transistor T4 in adjacent pixel rows to share the same P-well region 10B, by setting the N-well region 10A and the P-well region 10B of adjacent pixel rows to be mirror-symmetrical with respect to the first center line O1. This effectively reduces the layout space used by the N-well region and the P-well region, reduces the area occupied by the pixel driving circuit, and is beneficial for achieving high resolution.

[0159] In an exemplary embodiment, the active area (AA) pattern of each sub-pixel in the display substrate may include at least: a first active area 11, a second active area 12, a third active area 13, and a fourth active area 14.

[0160] In an exemplary embodiment, the shape of the first active region 11 can be a strip shape extending along the second direction Y, and it can be disposed within the region where the N-well region 10A is located. The first active region 11 can serve as the active region of the first transistor T1.

[0161] In an exemplary embodiment, the shape of the second active region 12 can be a strip shape extending along the second direction Y, and it can be disposed within the region where the N-well region 10A is located. The second active region 12 can serve as the active region of the second transistor T2.

[0162] In an exemplary embodiment, the third active region 13 can be a strip shape extending along the second direction Y, and can be located within the region where the N-well region 10A is located. The third active region 13 can serve as the active region of the third transistor T3.

[0163] In an exemplary embodiment, the shape of the fourth active region 14 can be a strip shape extending along the first direction X, and it can be disposed within the region where the P-well region 10B is located. The fourth active region 14 can serve as the active region of the fourth transistor T4.

[0164] In an exemplary embodiment, in at least one sub-pixel, the first active region 11 can be disposed on the side opposite to the first direction of the third active region 13, and the second active region 12 and the fourth active region 14 can be disposed on both sides of the third active region 13 in the second direction Y, respectively. For example, in the Mth pixel row, the first active region 11 and the second active region 12 can be disposed on the side opposite to the second direction Y of the third active region 13, and the fourth active region 14 can be disposed on the side of the third active region 13 in the second direction Y. As another example, in the (M+1)th pixel row, the first active region 11 and the second active region 12 can be disposed on the side of the third active region 13 in the second direction Y, and the fourth active region 14 can be disposed on the side opposite to the second direction Y of the third active region 13.

[0165] In an exemplary embodiment, the active region pattern may further include a first power region 15 and a second power region 16.

[0166] In an exemplary embodiment, the first power region 15 may be a strip extending along the second direction Y, and may be disposed within the region where the N-well region 10A is located. In the first direction X, the first power region 15 is disposed on the side opposite to the first direction of the third active region 13. In the second direction Y, the edge of the first power region 15 near the fourth active region 14 and the edge of the third active region 13 near the fourth active region 14 may be substantially flush. In an exemplary embodiment, the first power region 15 is configured to connect to a subsequently formed first power line.

[0167] In an exemplary embodiment, the second power region 16 may be a strip extending along the second direction Y, and may be disposed within the region of the P-well region 10B, and between partially adjacent pixel columns. For example, the second power region 16 may be disposed between the (N-1)th pixel column and the Nth pixel column, between the N+1th pixel column and the N+2th pixel column, between the N+3th pixel column and the N+4th pixel column, and between the N+5th pixel column and the N+6th pixel column. In an exemplary embodiment, the second power region 16 is configured to connect to a subsequently formed second power line.

[0168] In an exemplary embodiment, the active area patterns of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the (M-1)th pixel row and the Mth pixel row can be mirror-symmetrical with respect to the first center line O1. Similarly, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1. Furthermore, the first active area 11 to the fourth active area 14, the first power area 15, and the second power area 16 in the M+1th pixel row and the M+2th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0169] In an exemplary embodiment, the positions and shapes of the first active region 11 to the third active region 13 and the first power region 15 of adjacent pixel columns may be substantially the same.

[0170] In an exemplary embodiment, the fourth active region 14 and the second power region 16 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fourth active region 14 and the second power region 16 in the Nth pixel column and the N+1th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the fourth active region 14 and the second power region 16 in the N+1th pixel column and the N+2th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0171] In an exemplary embodiment, the active region of each transistor may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0172] In an exemplary embodiment, in at least one sub-pixel, the first source region 11-1 of the first active region may be located on the side of the first channel region of the first active region away from the third active region 13, and the first drain region 11-2 of the first active region may be located on the side of the first channel region of the first active region close to the third active region 13. The second source region 12-1 of the second active region may be located on the side of the second channel region of the second active region away from the third active region 13, and the second drain region 12-2 of the second active region may be located on the side of the second channel region of the second active region close to the third active region 13. The third source region 13-1 of the third active region may be located on the side of the third channel region of the third active region close to the second active region 12, and the third drain region 13-2 of the third active region may be located on the side of the third channel region of the third active region away from the second active region 12. The fourth source region 14-1 and the fourth drain region 14-2 of the fourth active region may be located on both sides of the fourth channel region of the fourth active region in the first direction X.

[0173] In an exemplary embodiment, in at least one sub-pixel, the second drain region 12-2 of the second active region and the third source region 13-1 of the third active region can be interconnected, and the second drain region 12-2 of the second active region can serve as the third source region 13-1 of the third active region.

[0174] In an exemplary embodiment, in at least one sub-pixel, the second active region 12 and the third active region 13 can be an interconnected integral structure.

[0175] In an exemplary embodiment, in at least one pixel column, the first active regions 11 in adjacent sub-pixels can be an integral structure interconnected, and the first active regions 11 of two sub-pixels can share the same first source region 11-1. For example, two sub-pixels in the (M-1)th pixel row and the Mth pixel row can share the same first source region 11-1. Similarly, two sub-pixels in the M+1th pixel row and the M+2th pixel row can share the same first source region 11-1. This disclosure, by setting the first transistors T1 of adjacent pixel rows to be mirrored and sharing the first electrode of the first transistor T1, can effectively reduce the vertical wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0176] In an exemplary embodiment, in at least one pixel row, the fourth active regions 14 in some adjacent sub-pixels can be an integral structure interconnected, and the fourth active regions 14 of two sub-pixels can share the same fourth source pole region 14-1. For example, two sub-pixels in the Nth pixel column and the N+1th pixel column can share the same fourth source pole region 14-1. Similarly, two sub-pixels in the N+2th pixel column and the N+3th pixel column can share the same fourth source pole region 14-1. Furthermore, two sub-pixels in the N+4th pixel column and the N+5th pixel column can share the same fourth source pole region 14-1. This disclosure, by setting the fourth transistors T4 of some adjacent pixel columns to be mirrored and sharing the first pole of the fourth transistor T4, can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0177] In an exemplary embodiment, in at least one pixel column, the second power supply regions 16 in adjacent sub-pixels can be an integral structure interconnected. By setting the second power supply regions 16 of adjacent pixel rows to be mirror images and interconnected as an integral structure, this disclosure can effectively reduce the vertical wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0178] In an exemplary embodiment, since the first active region 11, the second active region 12, the third active region 13, and the first power supply region 15 in adjacent pixel rows are mirrored, the first active region 11, the second active region 12, the third active region 13, and the first power supply region 15 in adjacent pixel rows can share the same N-well region 10A. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the N-well region and reduce the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution.

[0179] In an exemplary embodiment, since the fourth active region 14 and the second power supply region 16 in adjacent pixel rows are mirrored, the fourth transistors T4 in adjacent pixel rows can share the same P-well region 10B. That is, transistors of the same type share the same type of substrate region, which can effectively reduce the layout space used by the second substrate region and reduce the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution.

[0180] (2) Forming a gate conductive layer pattern. In an exemplary embodiment, forming a gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on a silicon substrate on which the aforementioned pattern is formed; firstly, patterning the polysilicon film using a patterning process to form a first insulating layer covering the active region pattern and a polysilicon layer pattern disposed on the first insulating layer; and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in Figures 8A and 8B, where Figure 8B is a schematic diagram of the gate conductive layer in Figure 8A.

[0181] In an exemplary embodiment, the gate conductive layer pattern of each sub-pixel in the display substrate may include at least: a first gate electrode 21, a second gate electrode 22, a third gate electrode 23, and a fourth gate electrode 24.

[0182] In an exemplary embodiment, the first gate electrode 21 can be block-shaped (such as rectangular), and the corners of the rectangular shape can be chamfered or grooved. The orthographic projection of the first gate electrode 21 on the silicon substrate at least partially overlaps with the orthographic projection of the first active region on the silicon substrate. The first gate electrode 21 can serve as the gate electrode of the first transistor T1.

[0183] In an exemplary embodiment, a first gate connecting block 21-1 may be disposed on the first gate electrode 21. The shape of the first gate connecting block 21-1 may be block-shaped (such as rectangular). In the first direction X, the first gate connecting block 21-1 may be disposed on one side of the first gate electrode 21 in the first direction X. In the second direction Y, the edges of the first gate electrode 21 and the first gate connecting block 21-1 on the side away from the third gate electrode 23 may be substantially flush.

[0184] In an exemplary embodiment, in at least one sub-pixel, the first gate electrode 21 and the first gate connection block 21-1 can be an integral structure that is interconnected.

[0185] In an exemplary embodiment, the second gate electrode 22 may be block-shaped (e.g., rectangular), and the orthographic projection of the second gate electrode 22 on the silicon substrate at least partially overlaps with the orthographic projection of the second active region on the silicon substrate. The second gate electrode 22 may serve as the gate electrode of the second transistor T2.

[0186] In an exemplary embodiment, a second gate connecting block 22-1 may be provided on the second gate electrode 22, and the shape of the second gate connecting block 22-1 may be block-shaped (such as rectangular). In the first direction X, the second gate connecting block 22-1 may be disposed on one side of the second gate electrode 22 in the first direction X. In the second direction Y, the edges of the second gate electrode 22 and the second gate connecting block 22-1 near the second gate electrode 22 may be substantially flush.

[0187] In an exemplary embodiment, in at least one sub-pixel, the second gate electrode 22 and the second gate connection block 22-1 can be an integral structure that is interconnected.

[0188] In an exemplary embodiment, the first gate electrode 21 is disposed on the upper first gate connection block 21-1, and the second gate electrode 22 is disposed on the lower second gate connection block 22-1. By staggering the arrangement of the gate connection blocks, the area occupied by the pixel driving circuit can be effectively reduced, which is beneficial to achieving high resolution.

[0189] In an exemplary embodiment, the third gate electrode 23 may be block-shaped (e.g., rectangular), and the orthographic projection of the third gate electrode 23 on the silicon substrate at least partially overlaps with the orthographic projection of the third active region on the silicon substrate. The third gate electrode 23 may serve as the gate electrode of the third transistor T3.

[0190] In an exemplary embodiment, a third gate connecting block 23-1 may be provided on the third gate electrode 23. The shape of the third gate connecting block 23-1 may be block-shaped (such as rectangular). In the first direction X, the third gate connecting block 23-1 may be located on the side of the third gate electrode 23 opposite to the first direction X. In the second direction Y, the edges of the third gate electrode 23 and the third gate connecting block 23-1 near the second gate electrode 22 may be substantially flush.

[0191] In an exemplary embodiment, in at least one sub-pixel, the third gate electrode 23 and the third gate connection block 23-1 can be an integral structure that is interconnected.

[0192] In an exemplary embodiment, the fourth gate electrode 24 may be block-shaped (e.g., rectangular), and the orthographic projection of the fourth gate electrode 24 on the silicon substrate at least partially overlaps with the orthographic projection of the fourth active region 14 on the silicon substrate. The fourth gate electrode 24 may serve as the gate electrode of the fourth transistor T4.

[0193] In an exemplary embodiment, a fourth gate connecting block 24-1 may be provided on the fourth gate electrode 24. The shape of the fourth gate connecting block 24-1 may be block-shaped (such as rectangular). In the first direction X, the edges of the fourth gate electrode 24 and the fourth gate connecting block 24-1 on the first direction X side may be substantially flush, or the edges of the fourth gate electrode 24 and the fourth gate connecting block 24-1 on the opposite side of the first direction X may be substantially flush.

[0194] In an exemplary embodiment, the gate conductive layer patterns of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first gate electrode 21, the second gate electrode 22, the third gate electrode 23, and the fourth gate electrode 24 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0195] In an exemplary embodiment, the positions and shapes of the first gate electrode 21, the second gate electrode 22, and the third gate electrode 23 of adjacent pixel columns can be substantially the same.

[0196] In an exemplary embodiment, the fourth gate electrode 24 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2. For example, the fourth gate electrode 24 in the Nth pixel column and the (N+1)th pixel column can be mirror-symmetrical with respect to the second center line O2. Similarly, the fourth gate electrode 24 in the (N+1)th pixel column and the (N+2)th pixel column can be mirror-symmetrical with respect to the second center line O2.

[0197] (3) Forming an N-type doped (SN) region pattern. In an exemplary embodiment, forming an N-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming an N-type doped pattern in the opening regions by a doping process, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the N-type doped pattern in Figure 9A.

[0198] In an exemplary embodiment, the N-type doping pattern of each sub-pixel in the display substrate may include an N-type doped region 20A and an N-type doped block 20A-1.

[0199] In an exemplary embodiment, the N-type doped region 20A can be rectangular in shape and can be located in the region where the P-well region 10B is located. The orthogonal projection of the N-type doped region 20A on the silicon substrate can include the orthogonal projection of the fourth active region on the silicon substrate, so that the fourth active region forms the fourth channel region, the fourth source region and the fourth drain region.

[0200] In an exemplary embodiment, the shape of the N-type doped block 20A-1 can be a strip shape extending along the second direction Y, and it can be located in the region where the N-well region 10A is located. The orthogonal projection of the N-type doped block 20A-1 on the silicon substrate can include the orthogonal projection of the first power supply region 15 on the silicon substrate, that is, the first power supply region 15 is N-type doped.

[0201] In an exemplary embodiment, within a pixel row, the N-type doped regions 20A of some adjacent sub-pixels can be interconnected as a single, integral structure. For example, the N-type doped regions 20A in the Nth pixel column and the (N+1)th pixel column can be interconnected as a single structure. Similarly, the N-type doped regions 20A in the (N+1)th pixel column and the (N+2)th pixel column can be interconnected as a single structure. Furthermore, the N-type doped regions 20A in the (N+2)th pixel column and the (N+3)th pixel column can be interconnected as a single structure.

[0202] In an exemplary embodiment, in a pixel column, the N-type doped regions 20A of adjacent sub-pixels can be an interconnected integral structure.

[0203] In an exemplary embodiment, the N-type doped regions 20A and N-type doped blocks 20A-1 of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1.

[0204] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming a P-type doped region pattern may include: coating a photoresist on a silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist in the plurality of opening regions, and forming a P-type doped pattern in the opening regions by a doping process, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the P-type doped pattern in Figure 10A.

[0205] In an exemplary embodiment, the P-type doping pattern of each sub-pixel in the display substrate may include a P-type doped region 20B and a P-type groove 20B-1.

[0206] In an exemplary embodiment, in at least one sub-pixel, the shape of the P-type doped region 20B can be rectangular, and it can be located in the region where the N-well region 10A is located. The orthogonal projection of the P-type doped region 20B on the silicon substrate can include the orthogonal projections of the first active region to the third active region on the silicon substrate, so that the first active region forms a first channel region, a first source region and a second drain region, the second active region forms a second channel region, a second source region and a second drain region, and the third active region forms a third channel region, a third source region and a third drain region.

[0207] In an exemplary embodiment, the shape of the P-type groove 20B-1 can be a strip shape extending along the second direction Y, and it can be disposed on the side of the P-type doped region 20B close to the N-type doped region 20A. The orthogonal projection of the P-type groove 20B-1 on the silicon substrate can include the orthogonal projection of the N-type doped block 20A-1 on the silicon substrate.

[0208] In an exemplary embodiment, the orthographic projection of the P-type groove 20B-1 onto the silicon substrate may include the orthographic projection of the first power region 15 onto the silicon substrate, i.e., the first power region 15 is not P-type doped.

[0209] In an exemplary embodiment, the P-type doped regions 20B of multiple sub-pixels in a pixel row can be an interconnected integral structure.

[0210] In an exemplary embodiment, the P-type doped regions 20B of adjacent pixel rows can be mirror-symmetric with respect to the first center line O1. For example, the P-type doped regions 20B in the Mth pixel row and the (M+1)th pixel row can be mirror-symmetric with respect to the first center line O1.

[0211] In an exemplary embodiment, the P-type doped pattern may further include P-type doped blocks 20B-2. The shape of the P-type doped blocks 20B-2 may be a strip extending along the second direction Y, and they may be disposed between partially adjacent pixel columns. For example, the P-type doped blocks 20B-2 may be disposed between the (N-1)th pixel column and the Nth pixel column, between the N+1th pixel column and the N+2th pixel column, between the N+3rd pixel column and the N+4th pixel column, and between the N+5th pixel column and the N+6th pixel column, respectively.

[0212] In an exemplary embodiment, the orthogonal projection of the P-type doped block 20B-2 onto the silicon substrate may include the orthogonal projection of the second power region 16 onto the silicon substrate, i.e., the second power region 16 is P-type doped.

[0213] In an exemplary embodiment, the P-type doped region 20B, P-type groove 20B-1 and P-type doped block 20B-2 of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1.

[0214] (5) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the second insulating film by a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG11.

[0215] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0216] In an exemplary embodiment, the orthogonal projection of the first via V1 onto the silicon substrate may be located within the range of the orthogonal projection of the first source region of the first active region onto the silicon substrate. The first insulating layer and the second insulating layer within the first via V1 are etched away, exposing the surface of the first source region. The first via V1 is configured to allow the subsequently formed first connection electrode to be connected to the first source region through the via.

[0217] In an exemplary embodiment, the orthographic projection of the first via V1 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0218] In an exemplary embodiment, since the first active regions of adjacent sub-pixels in a pixel column are interconnected as an integral structure, and the two sub-pixels share the first source region, adjacent sub-pixels in a pixel column can share the same first via V1, which can effectively reduce the number of vias. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution, but also reduces the process difficulty and improves the yield.

[0219] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the silicon substrate may be located within the range of the orthogonal projection of the second source region of the second active region onto the silicon substrate. The first and second insulating layers within the second via V2 are etched away, exposing the surface of the second source region. The second via V2 is configured to allow a subsequently formed second connection electrode to be connected to the second source region through the via.

[0220] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the silicon substrate may be located within the orthogonal projection range of the first drain region of the first active region onto the silicon substrate. The first and second insulating layers within the third via V3 are etched away, exposing the surface of the first drain region. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first drain region through the via.

[0221] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the silicon substrate may be located within the range of the orthogonal projection of the second drain region (which is also the third source region of the third active region) onto the silicon substrate. The first and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second drain region (which is also the third source region). The fourth via V4 is configured to allow the subsequently formed fourth connection electrode 44 to be connected to the second drain region (which is also the third source region) through the via.

[0222] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the silicon substrate may lie within the orthogonal projection of the third drain region of the third active region onto the silicon substrate. The first and second insulating layers within the fifth via V5 are etched away, exposing the surface of the third drain region. The fifth via V5 is configured to allow a subsequently formed fifth connection electrode to connect to the third drain region through this via. In an exemplary embodiment, multiple fifth vias V5 may be used to reduce contact resistance and improve connection reliability.

[0223] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the silicon substrate may be located within the range of the orthogonal projection of the fourth source region of the fourth active region onto the silicon substrate. The first and second insulating layers within the sixth via V6 are etched away, exposing the surface of the fourth source region. The sixth via V6 is configured to allow the subsequently formed sixth connection electrode to be connected to the fourth source region through the via.

[0224] In an exemplary embodiment, since the fourth active regions of some adjacent sub-pixels in a pixel row are interconnected as an integral structure, and the two sub-pixels share the fourth source region, some adjacent sub-pixels in a pixel column can share the same sixth via V6, which can effectively reduce the number of vias. This not only reduces the area occupied by the pixel driving circuit, which is beneficial to achieving high resolution, but also reduces the process difficulty and improves the yield.

[0225] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the silicon substrate may be located within the orthogonal projection of the fourth drain region of the fourth active region onto the silicon substrate. The first and second insulating layers within the seventh via V7 are etched away, exposing the surface of the fourth drain region. The seventh via V7 is configured to allow the subsequently formed fifth connection electrode to be connected to the fourth drain region through the via.

[0226] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the silicon substrate may be within the range of the orthographic projection of the first gate connection block 21-1 of the first gate electrode 21 onto the silicon substrate. The second insulating layer within the eighth via V8 is etched away, exposing the surface of the first gate connection block 21-1. The eighth via V8 is configured to allow the subsequently formed seventh connection electrode to be connected to the first gate connection block 21-1 through the via.

[0227] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the silicon substrate may be located within the range of the orthogonal projection of the second gate connection block 22-1 of the second gate electrode 22 onto the silicon substrate. The second insulating layer within the ninth via V9 is etched away, exposing the surface of the second gate connection block 22-1. The ninth via V9 is configured to allow the subsequently formed second scan signal line to be connected to the second gate connection block 22-1 through the via.

[0228] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the silicon substrate may be located within the range of the orthogonal projection of the third gate connection block 23-1 of the third gate electrode 23 onto the silicon substrate. The second insulating layer within the tenth via V10 is etched away, exposing the surface of the third gate connection block 23-1. The tenth via V10 is configured to allow the subsequently formed third connection electrode to be connected to the third gate connection block 23-1 through the via.

[0229] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the silicon substrate may be located within the range of the orthogonal projection of the fourth gate connection block 24-1 of the fourth gate electrode 24 onto the silicon substrate. The second insulating layer within the eleventh via V11 is etched away, exposing the surface of the fourth gate connection block 24-1. The eleventh via V11 is configured to allow the subsequently formed eighth connection electrode to be connected to the fourth gate connection block 24-1 through the via.

[0230] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the silicon substrate may lie within the range of the orthographic projection of the first power region 15 onto the silicon substrate. The first and second insulating layers within the twelfth via V12 are etched away, exposing the surface of the first power region 15. The twelfth via V12 is configured to allow a subsequently formed shielding electrode to connect to the first power region 15 through this via. In an exemplary embodiment, there may be multiple twelfth vias V12 to reduce contact resistance and improve connection reliability.

[0231] In an exemplary embodiment, the second insulating layer may further include a thirteenth via V13. The orthogonal projection of the thirteenth via V13 onto the silicon substrate may lie within the range of the orthogonal projection of the second power region 16 onto the silicon substrate. The first and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the second power region 16. The thirteenth via V13 is configured to allow a subsequently formed second power line to connect to the second power region 16 through the via. In an exemplary embodiment, there may be multiple thirteenth vias V13 to reduce contact resistance and improve connection reliability.

[0232] (6) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a second insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the first conductive layer in Figure 12A. In an exemplary embodiment, the first conductive layer may be referred to as a first metal layer.

[0233] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel of the display substrate may include at least: a second scan signal line 32, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a shielding electrode 50, and a second power line 82.

[0234] In an exemplary embodiment, the second scan signal line 32 can be a straight line with its main body extending along the first direction X, and can be located on the side of the third gate electrode 23 away from the fourth gate electrode 24. A second scan connection block 32-1 can be provided on the second scan signal line 32, and the second scan connection block 32-1 can be disposed in each sub-pixel. The shape of the second scan connection block 32-1 can be a strip extending along the second direction Y. The first end of the second scan connection block 32-1 is connected to the second scan signal line 32, and the second end of the second scan connection block 32-1 extends towards the third gate electrode 23 and is connected to the second gate connection block 22-1 through the ninth via V9. Since the second gate connection block 22-1 is connected to the second gate electrode 22, the second scan signal line 32 is connected to the gate electrode of the second transistor T2 in each sub-pixel, and the second scan signal line 32 can control the conduction or disconnection of the second transistor T2.

[0235] In an exemplary embodiment, in at least one pixel row, the second scan signal line 32 and the plurality of second scan connection blocks 32-1 can be an integral structure that is interconnected.

[0236] In an exemplary embodiment, the orthogonal projection of the second scan signal line 32 onto the silicon substrate at least partially overlaps with the orthogonal projections of the first gate electrode 21 and the second gate electrode 22 onto the silicon substrate.

[0237] In an exemplary embodiment, the second power line 82 can be a straight line extending along the first direction X, and can be located on the side of the fourth transistor T4 away from the third transistor T3. The second power line 82 can be connected to the second power region 16 through a portion of the thirteenth via V13, enabling the second power line 82 to write the second power signal into the second power region 16. Since the second power region 16 is located in the P-well region 10B, the second power line 82 writes the second power signal (negative voltage) into the P-well region 10B, which not only increases the anode dynamic range and improves the contrast of the display device, but also provides better signal isolation, reduces signal crosstalk and interference, and improves the stability and reliability of the circuit.

[0238] In an exemplary embodiment, the second power line 82 may be located between two fourth gate electrodes 24 of adjacent pixel rows. The orthographic projection of the second power line 82 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate. Two adjacent pixel rows may share the same second power line 82.

[0239] In an exemplary embodiment, the first connection electrode 41 may be a strip shape extending along the first direction X, and may be disposed on the side of the second scan signal line 32 away from the third gate electrode 23. The first connection electrode 41 may be connected to the first source region through the first via V1, and the first connection electrode 41 may be configured to be connected to the subsequently formed eleventh connection electrode.

[0240] In an exemplary embodiment, since adjacent sub-pixels in a pixel column share the first source region and the first via V1, adjacent sub-pixels in a pixel column can share the same first connection electrode 41, which effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, and is beneficial to achieving high resolution.

[0241] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first connecting electrode 41 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0242] In an exemplary embodiment, the second connection electrode 42 may be a strip shape extending along the first direction X, and may be disposed on the side of the second scan signal line 32 away from the third gate electrode 23. The second connection electrode 42 may be connected to the second source region through the second via V2, and the second connection electrode 42 may be configured to be connected to the subsequently formed twelfth connection electrode.

[0243] In an exemplary embodiment, the third connecting electrode 43 may include a first connecting strip 43-1, a second connecting strip 43-2, and a third connecting strip 43-3 connected sequentially. In the first direction X, the center lines of the first connecting strip 43-1 and the second connecting strip 43-2 may substantially overlap. The third connecting strip 43-3 may be disposed on one side of the second connecting strip 43-2 in the first direction X. The center line of the first connecting strip 43-1 may be a straight line that bisects the first connecting strip 43-1 in the first direction X and extends along the second direction Y. The center line of the second connecting strip 43-2 may be a straight line that bisects the second connecting strip 43-2 in the first direction X and extends along the second direction Y. In the second direction Y, the second connecting strip 43-2 may be disposed on the side of the third connecting strip 43-3 away from the third gate electrode 23, and the first connecting strip 43-1 may be disposed on the side of the second connecting strip 43-2 away from the third gate electrode 23. The first connecting strip 43-1 can be block-shaped (e.g., rectangular), the second connecting strip 43-2 can be a strip extending along the second direction Y, and the third connecting strip 43-3 can be a strip extending along the first direction X. The two ends of the second connecting strip 43-2 are connected to the first connecting strip 43-1 and the third connecting strip 43-3, respectively. The first connecting strip 43-1 is connected to the first drain region through the third via V3, and the third connecting strip 43-3 is connected to the third gate connecting block 23-1 through the tenth via V10. Since the third gate connecting block 23-1 is connected to the third gate electrode 23, the third connecting electrode 43 achieves the interconnection between the second electrode of the first transistor T1 and the gate electrode of the third transistor T3. In an exemplary embodiment, the third connecting electrode 43 can serve as the first node electrode of this disclosure.

[0244] In an exemplary embodiment, the fourth connection electrode 44 may be a strip extending along the second direction Y. The fourth connection electrode 44 is connected to the second drain region (which is also the third source region) through a fourth via V4. The fourth connection electrode 44 is configured to connect to the subsequently formed fourteenth connection electrode. In an exemplary embodiment, the fourth connection electrode 44 may serve as the second node electrode of this disclosure.

[0245] In an exemplary embodiment, the fifth connecting electrode 45 can be zigzag-shaped. The first end of the fifth connecting electrode 45 is connected to the third drain region via a fifth via V5, and the second end of the fifth connecting electrode 45 is connected to the fourth drain region via a seventh via V7. In an exemplary embodiment, the fifth connecting electrode 45 establishes a connection between the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, forming the third node N3 of the pixel driving circuit. In an exemplary embodiment, the fifth connecting electrode 45 can serve as the third node electrode of this disclosure.

[0246] In an exemplary embodiment, the fifth connection electrode 45 may include a first sub-electrode 45-1, a second sub-electrode 45-2, and a third sub-electrode 45-3 connected in sequence. The second sub-electrode 45-2 may be disposed on the side of the first sub-electrode 45-1 away from the third gate electrode 23, and the third sub-electrode 45-3 may be disposed on the side of the second sub-electrode 45-2 away from the third gate electrode 23. The first sub-electrode 45-1 and the third sub-electrode 45-3 may be strip-shaped extending along a first direction X, and the second sub-electrode 45-2 may be strip-shaped extending along a second direction Y. The two ends of the second sub-electrode 45-2 are respectively connected to the first sub-electrode 45-1 and the third sub-electrode 45-3. The first sub-electrode 45-1 is connected to the third drain region through a fifth via V5, and the third sub-electrode 45-3 is connected to the fourth drain region through a seventh via V7.

[0247] In an exemplary embodiment, a sub-electrode block 45-4 may be provided at the end of the third sub-electrode 45-3 away from the second sub-electrode 45-2, and the third sub-electrode 45-3 and the sub-electrode block 45-4 are connected to the fourth drain region through the seventh via V7.

[0248] In an exemplary embodiment, the orthogonal projections of the second sub-electrode 45-2 and the third sub-electrode 45-3 onto the silicon substrate may at least partially overlap with the orthogonal projection of the fourth gate electrode 24 onto the silicon substrate.

[0249] In an exemplary embodiment, the shapes of the fifth connecting electrodes 45 in adjacent sub-pixels in at least one pixel row may be different.

[0250] In an exemplary embodiment, the shape of the fifth connection electrode 45 in at least one pixel row may include a first shape and a second shape, and the fifth connection electrode 45 of the first shape and the fifth connection electrode 45 of the second shape may be alternately arranged along a first direction X. For example, the fifth connection electrode 45 of the first shape may be arranged in the Nth pixel column, the N+2nd pixel column, and the N+4th pixel column, respectively, and the fifth connection electrode 45 of the second shape may be arranged in the N+1th pixel column, the N+3rd pixel column, and the N+5th pixel column, respectively.

[0251] In an exemplary embodiment, in the fifth connecting electrode 45 of the first shape, the first sub-electrode 45-1 can be disposed on one side of the second sub-electrode 45-2 in the first direction X, while the third sub-electrode 45-3 can be disposed on the side opposite to the first direction X of the second sub-electrode 45-2, forming a shape similar to a "Z".

[0252] In an exemplary embodiment, in the fifth connecting electrode 45 of the second shape, the first sub-electrode 45-1 and the third sub-electrode 45-3 can both be disposed on one side of the second sub-electrode 45-2 in the first direction X, forming a shape similar to a "C".

[0253] In an exemplary embodiment, the sixth connecting electrode 46 can be a strip extending along the second direction Y, and can be disposed between the fourth gate electrodes 24 adjacent to each other in the first direction X. The first end of the sixth connecting electrode 46 is connected to the second power line 82, and the second end of the sixth connecting electrode 46 extends along the second direction Y towards the direction closer to the third transistor T3, and is connected to the fourth source region through the sixth via V6, thus enabling the second power line 82 to write the second power signal into the first electrode of the fourth transistor T4. In an exemplary embodiment, the sixth connecting electrode 46 can serve as a power connection part of this disclosure.

[0254] In an exemplary embodiment, since the fourth active regions of some adjacent sub-pixels in a pixel row are interconnected as a single structure, and the two sub-pixels share the fourth source region and the sixth via V6, some adjacent sub-pixels in a pixel row can share the same sixth connecting electrode 46. One sixth connecting electrode 46 can be provided for every two pixel columns, meaning that two adjacent sixth connecting electrodes 46 in the first direction X can be spaced two sub-pixels apart. For example, the sixth connecting electrode 46 can be located between the fourth gate electrode 24 of the Nth pixel column and the (N+1)th pixel column. Alternatively, the sixth connecting electrode 46 can be located between the fourth gate electrode 24 of the (N+2)th pixel column and the (N+3)th pixel column. Yet another example is that the sixth connecting electrode 46 can be located between the fourth gate electrode 24 of the (N+4)th pixel column and the (N+5)th pixel column.

[0255] In an exemplary embodiment, in at least one sub-pixel, the sixth connecting electrode 46 and the second power line 82 can be an integral structure that is interconnected.

[0256] In an exemplary embodiment, in at least one pixel row, a second power line 82 and a plurality of sixth connection electrodes 46 may be an integral structure interconnected with each other.

[0257] In an exemplary embodiment, in at least one pixel column, two sixth connection electrodes 46 and a second power line 82 in adjacent sub-pixels can be an integral structure that is interconnected.

[0258] In an exemplary embodiment, the seventh connecting electrode 47 may be block-shaped (e.g., rectangular), and the seventh connecting electrode 47 is connected to the first gate connecting block 21-1 through the eighth via V8. The seventh connecting electrode 47 is configured to be connected to the subsequently formed fifteenth connecting electrode.

[0259] In an exemplary embodiment, the eighth connection electrode 48 may be a strip shape extending along the second direction Y. The eighth connection electrode 48 is connected to the fourth gate connection block 24-1 through the eleventh via V11. The eighth connection electrode 48 is configured to be connected to the third scan signal line subsequently formed.

[0260] In an exemplary embodiment, the first conductive layer pattern may further include a ninth connecting electrode 49. The ninth connecting electrode 49 may be a strip shape in which the main body extends along the second direction Y. A first end of the ninth connecting electrode 49 is connected to the second power line 82, and a second end of the ninth connecting electrode 49 extends toward the third gate electrode 23. The ninth connecting electrode 49 is connected to the second power region 16 through a portion of the thirteenth via V13. In an exemplary embodiment, the ninth connecting electrode 49 may serve as another power connection portion of this disclosure.

[0261] In an exemplary embodiment, the ninth connection electrode 49 may be disposed between two fifth connection electrodes 45 in partially adjacent pixel columns. For example, the ninth connection electrode 49 may be disposed between the fifth connection electrodes 45 of the (N-1)th pixel column and the Nth pixel column, the (N+1)th pixel column and the (N+2)th pixel column, the (N+3)th pixel column and the (N+4)th pixel column, and the (N+5)th pixel column and the (N+6)th pixel column, respectively.

[0262] In an exemplary embodiment, in at least one sub-pixel, the ninth connecting electrode 49 and the second power line 82 can be an integral structure that is interconnected.

[0263] In an exemplary embodiment, in at least one pixel row, a second power line 82 and a plurality of ninth connection electrodes 49 may be an integral structure interconnected with each other.

[0264] In an exemplary embodiment, in at least one pixel column, two ninth connection electrodes 49 and a second power line 82 in adjacent sub-pixels can be an integral structure that is interconnected.

[0265] In an exemplary embodiment, in at least one pixel row, the sixth connecting electrode 46 and the ninth connecting electrode 49 may be alternately arranged along the first direction X.

[0266] In an exemplary embodiment, since the sixth connection electrode 46 is disposed between partially adjacent fourth gate electrodes 24 in a pixel row, and the ninth connection electrode 49 is disposed between partially adjacent fifth connection electrodes 45 in a pixel row, and both the sixth connection electrode 46 and the ninth connection electrode 49 are connected to the second power line 82, the sixth connection electrode 46, the ninth connection electrode 49 and the second power line in a sub-pixel can form a shielding structure surrounding the fourth transistor T4 in three directions, and the shielding structure has the potential of the second power line, which can effectively shield the fourth transistor T4 and the third node N3 in the sub-pixel, effectively reduce the mutual interference between adjacent fourth transistors T4 and the third node N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0267] In an exemplary embodiment, since the fifth connecting electrode is configured to be connected to the anode via multiple connecting electrodes, the ninth connecting electrode disposed between adjacent fifth connecting electrodes can also effectively shield crosstalk between adjacent anodes, improving output stability. The pixel driving circuit of this disclosure, by employing an N-type fourth transistor T4, and given that the fourth transistor T4 has a good isolation structure, can effectively improve the dynamic range of the anode and enhance the brightness of the OLED.

[0268] In an exemplary embodiment, the shielding electrode 50 can be block-shaped (e.g., rectangular), with chamfered or grooved corners or edges. The orthographic projection of the shielding electrode 50 onto the silicon substrate at least partially overlaps with the orthographic projection of the third gate electrode 23 onto the silicon substrate. The shielding electrode 50 is connected to the first power supply region 15 through the twelfth via V12. The shielding electrode 50 is configured to be connected to the first power line through a plurality of subsequently formed connection electrodes, thus the shielding electrode 50 has the potential of the first power line. Since the first power supply region 15 is located in the N-well region 10A, the first power line writes the first power signal into the N-well region 10A, which not only provides better current driving capability and response speed to meet the operational requirements of the pixel driving circuit, but also improves the overall efficiency of the pixel driving circuit.

[0269] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the shielding electrode 50 on the silicon substrate and the orthographic projection of the third gate electrode 23 on the silicon substrate has a first area, and the orthographic projection of the third gate electrode 23 on the silicon substrate has a second area. The ratio of the first area to the second area can be greater than or equal to 0.8, that is, the coverage area of ​​the shielding electrode 50 covering the third gate electrode 23 is greater than 80% of the area of ​​the third gate electrode.

[0270] In an exemplary embodiment, during the light-emitting stage, the gate electrode of the third transistor T3 (i.e., the third gate electrode 23) is in a floating state, making it susceptible to interference from signal traces and electrodes. Furthermore, the third gate electrode 23 has a relatively large area, making it prone to forming parasitic capacitances with other signal traces and electrodes, thus affecting the performance of the third transistor T3. For example, during the light-emitting stage, the anode potential (the potential of the third node N3) in different sub-pixels changes from the voltage of the second power supply signal to a corresponding voltage value (maximum increase to the voltage of the first power supply signal) according to the display requirements of different gray levels. This change in anode potential affects the gate voltage of the third transistor T3 through the parasitic capacitance between the anode and the gate electrode of the third transistor T3, leading to unstable output. This disclosure provides a shielding electrode 50 in the first conductive layer. The shielding electrode 50 essentially covers the gate electrode of the third transistor T3. The shielding electrode 50, which has a constant potential (the potential of the first power line), can effectively shield the gate electrode of the third transistor T3, effectively eliminate interference from signal traces and other electrodes to the third transistor T3, improve the working stability of the third transistor T3, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve the display quality.

[0271] In an exemplary embodiment, in the first direction X, the shielding electrodes 50 in adjacent sub-pixels may have a shielding spacing PL, and the second power line 82 may have a width BV. The shielding spacing PL may be greater than or equal to the width BV of the second power line, but less than 2 * the width BV of the second power line. The shielding spacing PL may be the average spacing between two shielding electrodes 50, which is the dimension in the first direction X. The width BV of the second power line may be the average width of the second power line 82, which is the dimension in the second direction Y.

[0272] In an exemplary embodiment, the shielding spacing PL can be equal to the width BV of the second power line.

[0273] In an exemplary embodiment, the first conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the second scan signal line 32, the first connection electrode 41 to the ninth connection electrode 49, the shielding electrode 50, and the second power line 82 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0274] In an exemplary embodiment, the positions and shapes of the second scan signal line 32, the first connection electrode 41 to the fourth connection electrode 44, the seventh connection electrode 47, and the shielding electrode 50 of adjacent pixel columns can be substantially the same.

[0275] In an exemplary embodiment, the sixth connection electrode 46, the eighth connection electrode 48, the ninth connection electrode 49, and the second power line 82 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0276] (7) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer covering the pattern of the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG13.

[0277] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, a twenty-eighth via V28, and a twenty-ninth via V29.

[0278] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the silicon substrate may be within the range of the orthographic projection of the first connection electrode 41 onto the silicon substrate. The third insulating layer within the 21st via V21 is etched away, exposing the surface of the first connection electrode 41. The 21st via V21 is configured to allow the subsequently formed 11th connection electrode to be connected to the first connection electrode 41 through the via.

[0279] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0280] In an exemplary embodiment, the orthogonal projection of the 22nd via V22 onto the silicon substrate may be within the range of the orthogonal projection of the second connection electrode 42 onto the silicon substrate. The third insulating layer within the 22nd via V22 is etched away, exposing the surface of the second connection electrode 42. The 22nd via V22 is configured to allow the subsequently formed 12th connection electrode to be connected to the second connection electrode 42 through the via.

[0281] In an exemplary embodiment, the orthogonal projection of the 23rd via V23 onto the silicon substrate may be located within the range of the orthogonal projection of the third connection electrode 43 onto the silicon substrate. The third insulating layer within the 23rd via V23 is etched away, exposing the surface of the third connection electrode 43. The 23rd via V23 is configured to allow the subsequently formed 13th connection electrode to be connected to the third connection electrode 43 through the via.

[0282] In an exemplary embodiment, the orthogonal projection of the 24th via V24 onto the silicon substrate may be within the range of the orthogonal projection of the fourth connection electrode 44 onto the silicon substrate. The third insulating layer within the 24th via V24 is etched away, exposing the surface of the fourth connection electrode 44. The 24th via V24 is configured to allow the subsequently formed 14th connection electrode to be connected to the fourth connection electrode 44 through the via.

[0283] In an exemplary embodiment, the orthogonal projection of the 25th via V25 onto the silicon substrate may be located within the range of the orthogonal projection of the third sub-electrode 45-3 in the fifth connecting electrode 45 onto the silicon substrate. The third insulating layer within the 25th via V25 is etched away, exposing the surface of the third sub-electrode 45-3. The 25th via V25 is configured to allow the subsequently formed 15th connecting electrode to be connected to the third sub-electrode 45-3 through the via.

[0284] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the silicon substrate may be within the range of the orthographic projection of the 6th connection electrode 46 onto the silicon substrate. The third insulating layer within the 26th via V26 is etched away, exposing the surface of the 6th connection electrode 46. The 26th via V26 is configured to allow a subsequently formed second connection line to be connected to the 6th connection electrode 46 through the via.

[0285] In an exemplary embodiment, since some adjacent sub-pixels in a pixel row share the same sixth connection electrode 46, some adjacent sub-pixels in a pixel column can share the same twenty-sixth via V26. In an exemplary embodiment, there can be multiple twenty-sixth vias V26 to reduce contact resistance and improve connection reliability.

[0286] In an exemplary embodiment, the orthogonal projection of the 27th via V27 onto the silicon substrate may be within the range of the orthogonal projection of the 7th connection electrode 47 onto the silicon substrate. The third insulating layer within the 27th via V27 is etched away, exposing the surface of the 7th connection electrode 47. The 27th via V27 is configured to allow the subsequently formed 16th connection electrode to be connected to the 7th connection electrode 47 through the via.

[0287] In an exemplary embodiment, the orthographic projection of the 28th via V28 onto the silicon substrate may be within the range of the orthographic projection of the 8th connection electrode 48 onto the silicon substrate. The third insulating layer within the 28th via V28 is etched away, exposing the surface of the 8th connection electrode 48. The 28th via V28 is configured to allow the subsequently formed third scan signal line to be connected to the 8th connection electrode 48 through the via.

[0288] In an exemplary embodiment, the orthogonal projection of the 29th via V29 onto the silicon substrate may be located within the range of the orthogonal projection of the shielding electrode 50 onto the silicon substrate. The third insulating layer within the 29th via V29 is etched away, exposing the surface of the shielding electrode 50. The 29th via V29 is configured to allow the subsequently formed 12th connection electrode to be connected to the shielding electrode 50 through the via.

[0289] In an exemplary embodiment, the plurality of vias on the third insulating layer may further include a thirtieth via V30. The orthogonal projection of the thirtieth via V30 onto the silicon substrate may lie within the range of the orthogonal projection of the ninth connection electrode 49 onto the silicon substrate. The third insulating layer within the thirtieth via V30 is etched away, exposing the surface of the ninth connection electrode 49. The thirtieth via V30 is configured to allow a subsequently formed second connection line to connect to the ninth connection electrode 49 through this via. In an exemplary embodiment, there may be multiple thirtieth vias V30 to reduce contact resistance and improve connection reliability.

[0290] (8) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming the second conductive layer pattern on a third insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the second conductive layer in Figure 14A. In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal2) layer.

[0291] In an exemplary embodiment, the second conductive layer pattern in each sub-pixel of the display substrate may include at least: a third scan signal line 33, an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, a fourteenth connecting electrode 54, a fifteenth connecting electrode 55, a sixteenth connecting electrode 56, and a second connecting line 92.

[0292] In an exemplary embodiment, the eleventh connection electrode 51 may be a strip shape extending along the first direction X, and may be disposed on the side of the second scan signal line 32 away from the third gate electrode 33. The eleventh connection electrode 51 may be connected to the first connection electrode 41 through the twenty-first via V21, and the eleventh connection electrode 51 may be configured to be connected to the subsequently formed data signal line.

[0293] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the eleventh connecting electrode 51 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same eleventh connecting electrode 51.

[0294] In an exemplary embodiment, the twelfth connecting electrode 52 includes a first vertical electrode 52-1, a second vertical electrode 52-2, and a horizontal electrode 52-3. In the first direction X, the first vertical electrode 52-1 can be disposed on one side of the horizontal electrode 52-3 in the first direction X, and the second vertical electrode 52-2 can be disposed on the opposite side of the horizontal electrode 52-3 in the first direction X. In the second direction Y, the horizontal electrode 52-3 can be disposed on the side of the first vertical electrode 52-1 near the shielding electrode 50, and the second vertical electrode 52-2 can be disposed on the side of the horizontal electrode 52-3 near the shielding electrode 50. The first vertical electrode 52-1 and the second vertical electrode 52-2 can be strip-shaped extending along the second direction Y, and the horizontal electrode 52-3 can be strip-shaped extending along the first direction X. The two ends of the horizontal electrode 52-3 are respectively connected to the first vertical electrode 52-1 and the second vertical electrode 52-2. The end of the first vertical electrode 52-1 furthest from the horizontal electrode 52-3 can be connected to the second connecting electrode 42 through the twenty-second via V22, and the end of the second vertical electrode 52-2 furthest from the horizontal electrode 52-3 can be connected to the shielding electrode 50 through the twenty-ninth via V29. In an exemplary embodiment, the twelfth connecting electrode 52 can serve as the first power supply connecting electrode of this disclosure.

[0295] In an exemplary embodiment, in the first direction X, the second vertical electrode 52-2 of the twelfth connecting electrode 52 can be disposed between the third connecting electrode 43, which serves as the first node electrode, and the fourth connecting electrode 44, which serves as the second node electrode. Since the third connecting electrode 43 is connected to the gate electrode of the third transistor T3, and the fourth connecting electrode 44 is connected to the first electrode of the third transistor T3, the twelfth connecting electrode 52, which has a constant potential (the potential of the first power line), can form a constant potential shield, effectively eliminating crosstalk between the gate electrode and the first electrode in the third transistor T3, improving the uniformity and stability of the output current or voltage of the pixel driving circuit, and improving display quality.

[0296] In an exemplary embodiment, the twelfth connecting electrodes 52 of adjacent sub-pixels in a pixel column can be interconnected by electrode connecting strips 52-4. The electrode connecting strips 52-4 can be strip-shaped extending along the second direction Y, disposed between the twelfth connecting electrodes 52 of partially adjacent pixel rows, and the two ends of the electrode connecting strips 52-4 are respectively connected to the twelfth connecting electrodes 52 of two sub-pixels.

[0297] In an exemplary embodiment, an electrode connecting block 52-5 may be provided on the electrode connecting strip 52-4. The electrode connecting block 52-5 may be provided on the side of the electrode connecting strip 52-4 near the eleventh connecting electrode 51 and connected to the electrode connecting strip 52-4. The electrode connecting block 52-5 is configured to connect to the subsequently formed twenty-first connecting electrode.

[0298] In an exemplary embodiment, the orthographic projection of the electrode connection block 52-5 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate.

[0299] In an exemplary embodiment, the two twelfth connecting electrodes 52, electrode connecting blocks 52-4 and electrode connecting blocks 52-5 of adjacent sub-pixels in a pixel column can be an integral structure that is interconnected.

[0300] In an exemplary embodiment, the thirteenth connecting electrode 53 may be block-shaped (e.g., rectangular), and the thirteenth connecting electrode 53 may be connected to the third connecting electrode 43 through the twenty-third through-hole V23. The thirteenth connecting electrode 53 is configured to be connected to the first electrode plate subsequently formed.

[0301] In an exemplary embodiment, the fourteenth connecting electrode 54 may include a block-shaped sub-electrode 54-1 and a strip-shaped sub-electrode 54-2 interconnected as a single unit. The strip-shaped sub-electrode 54-2 may be disposed on the side of the block-shaped sub-electrode 54-1 near the eleventh connecting electrode 51. The strip-shaped sub-electrode 54-2 may be connected to the fourth connecting electrode 44 via the twenty-fourth via V24. Since the fourth connecting electrode 44 is connected to the second drain region (which is also the third source region) via the via, the fourteenth connecting electrode 54 has the potential of the second node N2. In an exemplary embodiment, the fourteenth connecting electrode 54 may serve as a compensation electrode of this disclosure.

[0302] In an exemplary embodiment, the orthographic projection of the block sub-electrode 54-1 of the fourteenth connecting electrode 54 onto the silicon substrate at least partially overlaps with the orthographic projection of the shielding electrode 50 onto the silicon substrate, the orthographic projection of the block sub-electrode 54-1 onto the silicon substrate at least partially overlaps with the orthographic projection of the fifth connecting electrode 45 onto the silicon substrate, and the orthographic projection of the block sub-electrode 54-1 onto the silicon substrate at least partially overlaps with the orthographic projection of the eighth connecting electrode 48 onto the silicon substrate.

[0303] In an exemplary embodiment, the area of ​​the block-shaped sub-electrode 54-1 of the fourteenth connecting electrode 54 projected onto the silicon substrate can be larger than the area of ​​the shielding electrode 50 projected onto the silicon substrate.

[0304] In an exemplary embodiment, the fifteenth connecting electrode 55 may be a strip shape extending along the second direction Y. The fifteenth connecting electrode 55 may be connected to the seventh connecting electrode 47 through the twenty-seventh through-hole V27. The fifteenth connecting electrode 55 may be configured to be connected to the subsequently formed twenty-third connecting electrode.

[0305] In an exemplary embodiment, the sixteenth connecting electrode 56 may be a strip shape extending along the first direction X. The sixteenth connecting electrode 56 may be connected to the third sub-electrode 45-3 in the fifth connecting electrode 45 via the twenty-fifth via V25. The sixteenth connecting electrode 56 may be configured to be connected to the subsequently formed twenty-fourth connecting electrode.

[0306] In an exemplary embodiment, the third scan signal line 33 can be a straight line extending along the first direction X, and can be located on the side of the sixteenth connecting electrode 56 away from the fourteenth connecting electrode 54. A third scan connecting block 33-1 can be provided on the third scan signal line 33, and the third scan connecting block 33-1 can be located in each sub-pixel. The shape of the third scan connecting block 33-1 can be a strip extending along the second direction Y. The first end of the third scan connecting block 33-1 is connected to the third scan signal line 33, and the second end of the third scan connecting block 33-1 extends towards the third gate electrode 23 and is connected to the eighth connecting electrode 48 through the twenty-eighth via V28. Since the eighth connecting electrode 48 is connected to the fourth gate connecting block 24-1 through the via, and the fourth gate connecting block 24-1 is connected to the fourth gate electrode 24, the third scan signal line 33 is connected to the gate electrode of the fourth transistor T4 in each sub-pixel, and the third scan signal line 33 can control the conduction or disconnection of the fourth transistor T4.

[0307] In an exemplary embodiment, in at least one pixel row, the third scan signal line 33 and the plurality of third scan connection blocks 33-1 can be an integral structure that is interconnected.

[0308] In an exemplary embodiment, the orthographic projection of the third scan signal line 33 on the silicon substrate at least partially overlaps with the orthographic projection of the second power line 82 on the silicon substrate, and the second power line 82 with a constant potential can effectively shield the influence of the third scan signal on the pixel driving circuit.

[0309] In an exemplary embodiment, the shape of the second connection line 92 can be a straight line or a broken line extending along the second direction Y. In the first direction X, the second connection line 92 can be disposed between two fourth gate electrodes 24 of adjacent sub-pixels. In the second direction Y, the second connection line 92 can be disposed on the side of the third scan signal line 33 away from the second power supply line 82. Specifically, the second connection lines 92 between the Nth pixel column and the (N+1)th pixel column, between the (N+2)th pixel column and the (N+3)th pixel column, and between the (N+4)th pixel column and the (N+5)th pixel column can be connected to the sixth connection electrode 46 via the twenty-sixth via V26. The second connection lines 92 between the (N-1)th pixel column and the Nth pixel column, between the (N+1)th pixel column and the (N+2)th pixel column, between the (N+3)th pixel column and the (N+4)th pixel column, and between the (N+5)th pixel column and the (N+6)th pixel column can be connected to the ninth connection electrode 49 via the thirtieth via V30.

[0310] In an exemplary embodiment, in at least one pixel column, the second connecting lines 92 in some adjacent sub-pixels can be an integral structure that is interconnected, and the second connecting lines 92 in some adjacent sub-pixels can be separated by a third scan signal line 33. For example, the second connecting lines 92 in the Mth pixel row and the second connecting lines 92 in the M+1th pixel row can be separated by the third scan signal line 33. Alternatively, the second connecting lines 92 in the M-1th pixel row and the Mth pixel row can be an integral structure that is interconnected, and the second connecting lines 92 in the M+1th pixel row and the M+2th pixel row can be an integral structure that is interconnected.

[0311] In an exemplary embodiment, in at least one pixel column, two second connection lines 92 separated by the third scan signal line 33 can be connected by the sixth connection electrode 46 or the ninth connection electrode 49 to form a vertical trace that continuously transmits the second power signal in the second direction Y. The second power line 82 in the first conductive layer serves as a horizontal trace that continuously transmits the second power signal in the first direction X, thus realizing a mesh-like interconnection structure on the display substrate for transmitting the second power signal, where the horizontal trace extending along the first direction X and the vertical trace extending along the second direction Y are formed. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, ensuring that the potential (anode potential) of the third node N3 at each position in the reset phase, self-discharge phase, and data writing phase is reset to the voltage of the second power signal, effectively improving display uniformity and enhancing display quality.

[0312] In an exemplary embodiment, the orthographic projection of the second connecting line 92 on the silicon substrate at least partially overlaps with the orthographic projection of the second center line O2 on the silicon substrate. Since the second connecting line 92 is disposed between adjacent pixel columns, the second connecting line 92, having a constant potential, can not only effectively shield the pixel driving circuit in the sub-pixel, improving the output stability of the pixel driving circuit, but also effectively reduce mutual interference between pixel driving circuits in the sub-pixel, effectively improving the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0313] In an exemplary embodiment, the fourteenth connecting electrode 54 and the second connecting line 92 may have a first distance d1, and the fourteenth connecting electrode 54 and the thirteenth connecting electrode 53 may have a second distance d2. The first distance d1 may be less than the second distance d2. The first distance d1 may be the average distance between the edge of the fourteenth connecting electrode 54 near the second connecting line 92 and the edge of the second connecting line 92 near the fourteenth connecting electrode 54, and is a dimension in the first direction X. The second distance d2 may be the average distance between the edge of the block sub-electrode 54-1 in the fourteenth connecting electrode 54 near the thirteenth connecting electrode 53 and the edge of the thirteenth connecting electrode 53 near the block sub-electrode 54-1 in the fourteenth connecting electrode 54, and is a dimension in the second direction Y.

[0314] In an exemplary embodiment, a third distance d3 may exist between the fourteenth connecting electrode 54 and the sixteenth connecting electrode 56, and the first distance d1 may be less than the third distance d3. The third distance d3 may be the average distance between the edge of the block sub-electrode 54-1 in the fourteenth connecting electrode 54 near the sixteenth connecting electrode 56 and the edge of the sixteenth connecting electrode 56 near the block sub-electrode 54-1 in the fourteenth connecting electrode 54, and is a dimension in the second direction Y.

[0315] In an exemplary embodiment, a fourth distance d4 may exist between the twelfth connecting electrode 52 and the thirteenth connecting electrode 53, and the second distance d2 may be greater than the fourth distance d4. The fourth distance d4 may be the average distance between the edge of the second vertical electrode 52-2 in the twelfth connecting electrode 52 near the thirteenth connecting electrode 53 and the edge of the thirteenth connecting electrode 53 near the second vertical electrode 52-2 in the twelfth connecting electrode 52, and is a dimension in the first direction X.

[0316] In an exemplary embodiment, a fifth distance d5 may exist between the twelfth connecting electrode 52 and the second connecting line 92, and a sixth distance d6 may exist between the twelfth connecting electrode 52 and the eleventh connecting electrode 51. The fifth distance d5 may be less than the sixth distance d6. The fifth distance d5 may be the average distance between the edge of the first vertical electrode 52-1 in the twelfth connecting electrode 52 near the second connecting line 92 and the edge of the second connecting line 92 near the first vertical electrode 52-1 in the twelfth connecting electrode 52, which is a dimension in the first direction X. The sixth distance d6 may be the average distance between the edge of the electrode connecting block 52-5 in the twelfth connecting electrode 52 near the eleventh connecting electrode 51 and the edge of the eleventh connecting electrode 51 near the electrode connecting block 52-5 in the twelfth connecting electrode 52, which is a dimension in the first direction X.

[0317] In an exemplary embodiment, the second conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the third scan signal line 33, the eleventh to sixteenth connecting electrodes 51 and 56, and the second connecting line 92 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0318] In an exemplary embodiment, the positions and shapes of the eleventh to fifteenth connecting electrodes 55 of adjacent pixel columns can be substantially the same.

[0319] In an exemplary embodiment, the third scan signal line 33, the sixteenth connecting electrode 56, and the second connecting line 92 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0320] (9) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the pattern of the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG15.

[0321] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a 31st via V31, a 32nd via V32, a 33rd via V33, a 34th via V34, a 35th via V35, and a 36th via V36.

[0322] In an exemplary embodiment, the orthographic projection of the 31st via V31 onto the silicon substrate may be within the range of the orthographic projection of the 11th connection electrode 51 onto the silicon substrate. The fourth insulating layer within the 31st via V31 is etched away, exposing the surface of the 11th connection electrode 51. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the 11th connection electrode 51 through the via.

[0323] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 on the silicon substrate.

[0324] In an exemplary embodiment, the orthogonal projection of the 32nd via V32 onto the silicon substrate may be located within the range of the orthogonal projection of the electrode connection block 52-5 onto the silicon substrate. The fourth insulating layer within the 32nd via V32 is etched away, exposing the surface of the electrode connection block 52-5. The 32nd via V32 is configured to allow the subsequently formed 21st connection electrode to be connected to the electrode connection block 52-5 through the via.

[0325] In an exemplary embodiment, the orthographic projection of the 32nd via V32 onto the silicon substrate at least partially overlaps with the orthographic projection of the first centerline O1 onto the silicon substrate.

[0326] In an exemplary embodiment, the orthogonal projection of the 33rd via V33 onto the silicon substrate is within the range of the orthogonal projection of the 13th connecting electrode 53 onto the silicon substrate. The fourth insulating layer within the 33rd via V33 is etched away, exposing the surface of the 13th connecting electrode 53. The 33rd via V33 is configured to allow the subsequently formed first electrode plate to be connected to the 13th connecting electrode 53 through the via.

[0327] In an exemplary embodiment, the orthographic projection of the 34th via V34 onto the silicon substrate is within the range of the orthographic projection of the 14th connection electrode 54 onto the silicon substrate. The fourth insulating layer within the 34th via V34 is etched away, exposing the surface of the 14th connection electrode 54. The 34th via V34 is configured to allow the subsequently formed 22nd connection electrode to be connected to the 14th connection electrode 54 through the via.

[0328] In an exemplary embodiment, the orthographic projection of the 35th via V35 onto the silicon substrate is within the range of the orthographic projection of the 15th connection electrode 55 onto the silicon substrate. The fourth insulating layer within the 35th via V35 is etched away, exposing the surface of the 15th connection electrode 55. The 35th via V35 is configured to allow the subsequently formed 23rd connection electrode to be connected to the 15th connection electrode 55 through the via.

[0329] In an exemplary embodiment, the orthographic projection of the 36th via V36 onto the silicon substrate is within the range of the orthographic projection of the 16th connection electrode 56 onto the silicon substrate. The fourth insulating layer within the 36th via V36 is etched away, exposing the surface of the 16th connection electrode 56. The 36th via V36 is configured to allow the subsequently formed 24th connection electrode to be connected to the 16th connection electrode 56 through the via.

[0330] (10) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer pattern on a fourth insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a schematic diagram of the third conductive layer in Figure 16A. In an exemplary embodiment, the third conductive layer may be referred to as a third metal (Metal3) layer.

[0331] In an exemplary embodiment, the third conductive layer pattern in each sub-pixel of the display substrate may include at least: a twenty-first connecting electrode 61, a twenty-second connecting electrode 62, a twenty-third connecting electrode 63, a twenty-fourth connecting electrode 64, a data signal line 70, and a first electrode plate 110.

[0332] In an exemplary embodiment, the data signal line 70 can be a straight line or a broken line extending along the second direction Y. A data connection strip 71 can be provided on the data signal line 70. The data connection strip 71 can be a strip extending along the first direction X. The first end of the data connection strip 71 is connected to the data signal line 70, and the second end of the data connection strip 71 extends along the first direction X (near the twenty-first connecting electrode 61) and is connected to the eleventh connecting electrode 51 through the thirty-first via V31. Since the eleventh connecting electrode 51 is connected to the first connecting electrode 41 through a via, and the first connecting electrode 41 is connected to the first source region through a via, the data signal line 70 writes the data signal to the first electrode of the first transistor T1.

[0333] In an exemplary embodiment, the orthographic projection of the data connection strip 71 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate. Adjacent sub-pixels in a pixel column can share the same data connection strip 71, which effectively reduces the number of connection electrodes, reduces the area occupied by the pixel driving circuit, and is beneficial to achieving high resolution.

[0334] In an exemplary embodiment, in at least one pixel column, the data signal line 70 and the data connection bar 71 can be an integral structure that is interconnected.

[0335] In an exemplary embodiment, since adjacent sub-pixels in a pixel column share the first source region, the first connecting electrode 41, the eleventh connecting electrode 51, and the data connecting strip 71, the two first transistors T1 of adjacent sub-pixels in a pixel column are written with the same data signal.

[0336] In an exemplary embodiment, the orthographic projection of the data signal line 70 on the silicon substrate and the orthographic projection of the second connection line 92 on the silicon substrate at least partially overlap, and the second connection line 92 with a constant potential can effectively shield the impact of the voltage jump in the data signal line 70 on the critical nodes of the pixel driving circuit.

[0337] In an exemplary embodiment, the data signal lines are disposed in the third conductive layer. Even if a short circuit occurs between the data signal lines and the first electrode plate due to process variations and particle defects, it will only result in dark spots or bright spots, without causing vertical line defects. Compared to schemes where the data signal lines are disposed in other conductive layers, this embodiment neither affects the formation of the mesh-like interconnection structure for transmitting the second power signal nor causes vertical line defects due to short circuits between the data signal lines and the first power lines.

[0338] In an exemplary embodiment, the first electrode plate 110 can be rectangular in shape, with chamfered corners or grooves on the edges or corners. The first electrode plate 110 can be connected to the thirteenth connecting electrode 53 via the thirty-third via V33, and can serve as one electrode plate of the first capacitor. Since the thirteenth connecting electrode 53 is connected to the third connecting electrode 43 via the via, and the third connecting electrode 43 is connected to the first drain region and the third gate electrode via the via, the interconnection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first electrode plate 110 is achieved, forming the first node N1 of the pixel driving circuit, and the first electrode plate 110 has the potential of the first node N1.

[0339] In an exemplary embodiment, the orthographic projection of the first electrode 110 onto the silicon substrate at least partially overlaps with the orthographic projection of the fourteenth connection electrode 54, which serves as a compensation electrode, onto the silicon substrate. The overlapping area between the orthographic projection of the fourteenth connection electrode 54 onto the silicon substrate and the orthographic projection of the first electrode 110 onto the silicon substrate has a third area, and the orthographic projection of the first electrode 110 onto the silicon substrate has a fourth area. The ratio of the third area to the fourth area can be greater than or equal to 0.5.

[0340] In an exemplary embodiment, the twenty-first connecting electrode 61 may be a strip extending along the second direction Y. The twenty-first connecting electrode 61 can be connected to the electrode connecting block 52-5 via the thirty-second through-hole V32. The twenty-first connecting electrode 61 is configured to connect to the subsequently formed first power line. In an exemplary embodiment, the twenty-first connecting electrode 61 may serve as the second power connection electrode of this disclosure.

[0341] In an exemplary embodiment, the orthographic projection of the 21st connecting electrode 61 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and adjacent sub-pixels in a pixel column can share the same 21st connecting electrode 61.

[0342] In an exemplary embodiment, a first spacing L1 exists between the twenty-first connecting electrode 61 in this sub-pixel and the data connecting strip 71 in this sub-pixel. The data signal line 70 may have a width BD, and the first spacing L1 may be greater than or equal to the width BD of the data signal line. The first spacing L1 may be the minimum distance between the edge of the twenty-first connecting electrode 61 near the data connecting strip 71 and the edge of the data connecting strip 71 near the twenty-first connecting electrode 61, and is a dimension in the first direction X. The width BD of the data signal line may be the average width of the data signal line 70 (excluding the data connecting strip), and is a dimension in the first direction X.

[0343] In an exemplary embodiment, the first spacing L1 can be greater than or equal to 0.5 μm. By setting the spacing between the twenty-first connecting electrode 61 and the data connecting strip 71, this disclosure can avoid short circuits between the data signal line and the first power line, and can avoid vertical line defects caused by short circuits.

[0344] In an exemplary embodiment, the twenty-first connecting electrode 61 in this sub-pixel has a second spacing L2 between it and the data signal line 70 in the adjacent sub-pixel in the first direction X. The second spacing L2 can be greater than or equal to the width BD of the data signal line. The second spacing L2 can be the minimum distance between the edge of the twenty-first connecting electrode 61 near the data signal line 70 and the edge of the data signal line 70 near the twenty-first connecting electrode 61, and is a dimension in the first direction X.

[0345] In an exemplary embodiment, the second spacing L2 can be greater than or equal to 0.5 μm. By setting the spacing between the twenty-first connecting electrode 61 and the data signal line 70, this disclosure can avoid short circuits between the data signal line and the first power line, and can avoid vertical line defects caused by short circuits.

[0346] In an exemplary embodiment, the twenty-second connecting electrode 62 may be a strip extending along the first direction X, and may be disposed on the side of the first electrode plate 110 away from the twenty-first connecting electrode 61. The twenty-second connecting electrode 62 is connected to the fourteenth connecting electrode 54 through the thirty-fourth through-hole V34, and the twenty-second connecting electrode 62 is configured to connect to the subsequently formed third electrode plate. Since the fourteenth connecting electrode 54 has the potential of the second node N2, the twenty-second connecting electrode 62 also has the potential of the second node N2.

[0347] In an exemplary embodiment, the shape of the 23rd connecting electrode 63 may be a strip shape extending along the second direction Y. The 23rd connecting electrode 63 is connected to the 15th connecting electrode 55 through the 35th via V35. The 23rd connecting electrode 63 is configured to be connected to the subsequently formed first scan signal line.

[0348] In an exemplary embodiment, the twenty-fourth connecting electrode 64 may be a strip shape extending along the first direction X. The twenty-fourth connecting electrode 64 is connected to the sixteenth connecting electrode 56 through the thirty-sixth through-hole V36. The twenty-fourth connecting electrode 64 is configured to be connected to the subsequently formed twenty-fifth connecting electrode.

[0349] In an exemplary embodiment, the third conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the twenty-first connecting electrode 61 to the twenty-fourth connecting electrode 64, the data signal line 70, and the first electrode plate 110 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0350] In an exemplary embodiment, the positions and shapes of the 21st to 24th connecting electrodes 64, the data signal line 70, and the first electrode plate 110 of adjacent pixel columns can be substantially the same.

[0351] (11) Forming a fifth insulating layer and a fourth conductive layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the fourth conductive layer pattern may include: sequentially depositing a fifth insulating film and a fourth conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern, and a fourth conductive layer pattern disposed on the fifth insulating layer, as shown in Figures 17A and 17B, where Figure 17B is a schematic diagram of the fourth conductive layer in Figure 17A. In an exemplary embodiment, the fourth conductive layer may be referred to as a metal-insulator-metal (MIM) layer.

[0352] In an exemplary embodiment, the fourth conductive layer pattern in each sub-pixel may include at least a second electrode 120.

[0353] In an exemplary embodiment, the second electrode 120 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. The orthographic projection of the second electrode 120 on the silicon substrate at least partially overlaps with the orthographic projection of the first electrode 110 on the silicon substrate. The second electrode 120 may serve as another electrode of the first capacitor.

[0354] In an exemplary embodiment, the second plates 120 of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1, and the positions and shapes of the second plates 120 of adjacent pixel columns can be substantially the same.

[0355] (12) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film by a patterning process to form a sixth insulating layer covering the pattern of the third conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, as shown in FIG18.

[0356] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a forty-first via V41, a forty-second via V42, a forty-third via V43, a forty-fourth via V44, and a forty-fifth via V45.

[0357] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate is within the range of the orthographic projection of the twenty-first connecting electrode 61 on the silicon substrate. The fifth and sixth insulating layers within the forty-first via V41 are etched away, exposing the surface of the twenty-first connecting electrode 61. The forty-first via V41 is configured to allow a subsequently formed first power line to be connected to the twenty-first connecting electrode 61 through the via.

[0358] In an exemplary embodiment, the orthogonal projection of the forty-second via V42 onto the silicon substrate lies within the range of the orthogonal projection of the twenty-second connecting electrode 62 onto the silicon substrate. The fifth and sixth insulating layers within the forty-second via V42 are etched away, exposing the surface of the twenty-second connecting electrode 62. The forty-second via V42 is configured to allow a subsequently formed third electrode plate to connect to the twenty-second connecting electrode 62 through this via. In an exemplary embodiment, there can be multiple forty-second vias V42, which can be sequentially arranged along the first direction X to reduce contact resistance and improve connection reliability.

[0359] In an exemplary embodiment, the orthogonal projection of the forty-third via V43 on the silicon substrate is within the range of the orthogonal projection of the twenty-third connecting electrode 63 on the silicon substrate. The fifth and sixth insulating layers within the forty-third via V43 are etched away, exposing the surface of the twenty-third connecting electrode 63. The forty-third via V43 is configured to allow the subsequently formed first scan signal line to be connected to the twenty-third connecting electrode 63 through the via.

[0360] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 onto the silicon substrate is within the range of the orthographic projection of the twenty-fourth connection electrode 64 onto the silicon substrate. The fifth and sixth insulating layers within the forty-fourth via V44 are etched away, exposing the surface of the twenty-fourth connection electrode 64. The forty-fourth via V44 is configured to allow the subsequently formed twenty-fifth connection electrode to be connected to the twenty-fourth connection electrode 64 through the via.

[0361] In an exemplary embodiment, the orthogonal projection of the forty-fifth via V45 onto the silicon substrate lies within the range of the orthogonal projection of the second electrode 120 onto the silicon substrate. The sixth insulating layer within the forty-fifth via V45 is etched away, exposing the surface of the second electrode 120. The forty-fifth via V45 is configured to allow a subsequently formed third electrode to connect to the second electrode 120 through this via. In an exemplary embodiment, there can be multiple forty-fifth vias V45, which can be sequentially arranged along the second direction Y to reduce contact resistance and improve connection reliability.

[0362] (13) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the fifth conductive thin film using a patterning process, and forming a fifth conductive layer pattern on a sixth insulating layer, as shown in Figures 19A and 19B, where Figure 19B is a schematic diagram of the fifth conductive layer in Figure 19A. In an exemplary embodiment, the fifth conductive layer may be referred to as a fourth metal layer (Metal4).

[0363] In an exemplary embodiment, the fifth conductive layer pattern in each sub-pixel of the display substrate may include at least: a first scan signal line 31, a twenty-fifth connecting electrode 65, a first power line 81, and a third electrode plate 130.

[0364] In an exemplary embodiment, the third electrode plate 130 can be rectangular in shape, with chamfered or grooved corners. The third electrode plate 130 is connected to the twenty-second connecting electrode 62 via the forty-second via V42, and to the second electrode plate 120 via the forty-fifth via V45. The third electrode plate 130 can serve as one electrode of the second capacitor. Since the twenty-second connecting electrode 62 has the potential of the second node N2, the second electrode plate 120 and the third electrode plate 130 also have the potential of the second node N2.

[0365] In an exemplary embodiment, the orthographic projection of the second electrode 120 on the silicon substrate at least partially overlaps with the orthographic projection of the first electrode 110 on the silicon substrate, and the first electrode 110 having a potential of the first node N1 and the second electrode 120 having a potential of the second node N2 form the first capacitor C1 of the pixel driving circuit.

[0366] In an exemplary embodiment, since the fourteenth connecting electrode 54, which serves as a compensation electrode, has a potential of the second node N2, the first plate 110, which has a potential of the first node N1, and the fourteenth connecting electrode 54, which has a potential of the second node N2, form a parasitic capacitance. The parasitic capacitance is connected in parallel with the first capacitor C1, which effectively increases the capacitance of the first capacitor C1 and helps to reduce the flicker phenomenon.

[0367] In an exemplary embodiment, the first power line 81 can be a straight line or a broken line extending along the first direction X, and can be disposed on the side of the third electrode plate 130 away from the fourth transistor T4. The first power line 81 can be connected to the twenty-first connecting electrode 61 through the forty-first via V41. Since the twenty-first connecting electrode 61 is connected to the electrode connecting block 52-5 through the via, the electrode connecting block 52-5 is connected to the twelfth connecting electrode 52 through the electrode connecting strip 52-4, the twelfth connecting electrode 52 is connected to the second connecting electrode 42 through the via, and the second connecting electrode 42 is connected to the second source region through the via, the first power line 81 writes the first power line number into the first electrode of the second transistor T2.

[0368] In an exemplary embodiment, since the twelfth connecting electrode 52 is also connected to the shielding electrode 50 through a via, the shielding electrode 50 is connected to the first power line 81, and the shielding electrode 50 has the potential of the first power line.

[0369] In an exemplary embodiment, in the first direction X, the shielding distance PL between the shielding electrodes 50 in adjacent sub-pixels can be less than 2 * the width of the first power line. The width of the first power line can be the average width of the first power line 81, which is the dimension in the second direction Y.

[0370] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first power line 81 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and two adjacent pixel rows can share the same first power line 81.

[0371] In an exemplary embodiment, the first scan signal line 31 can be a straight line extending along the first direction X, and can be located between the first power line 81 and the third electrode plate 130. The first scan signal line 31 can be connected to the twenty-third connecting electrode 63 through the forty-third via V43. Since the twenty-third connecting electrode 63 is connected to the fifteenth connecting electrode 55 through a via, the fifteenth connecting electrode 55 is connected to the seventh connecting electrode 47 through a via, the seventh connecting electrode 47 is connected to the first gate connecting block 21-1 through a via, and the first gate connecting block 21-1 is connected to the first gate electrode 21, the first scan signal line 31 is connected to the gate electrode of the first transistor T1 in each sub-pixel, and the first scan signal line 31 can control the conduction or disconnection of the first transistor T1.

[0372] In an exemplary embodiment, the first power line 81 can be disposed between the two first scan signal lines 31 of two adjacent pixel rows. The first power line 81 with a constant potential can be shielded by a constant potential to prevent crosstalk between the first scan signal after shifting in one pixel row and the first scan signal without shifting in another pixel row, thereby improving the accuracy of data signal writing and enhancing display accuracy.

[0373] In an exemplary embodiment, the twenty-fifth connecting electrode 65 may be block-shaped (e.g., rectangular), and the twenty-fifth connecting electrode 65 is connected to the twenty-fourth connecting electrode 64 through the forty-fourth through-hole V44. The twenty-fifth connecting electrode 65 is configured to be connected to the subsequently formed anode connecting electrode.

[0374] In an exemplary embodiment, the fourth conductive layer pattern may further include a third connecting line 93 and a fourth connecting line 94.

[0375] In an exemplary embodiment, the shape of the third connecting line 93 can be a straight line or a broken line extending along the first direction X of the main body, and can be disposed between two fourth gate electrodes 24 of partially adjacent pixel rows. The orthographic projection of the third connecting line 93 on the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 on the silicon substrate, and is continuously disposed in the first direction X.

[0376] In an exemplary embodiment, the fourth connection line 94 can be a straight line or a broken line extending along the second direction Y. In the first direction X, the fourth connection line 94 can be disposed between two third plates 130 of adjacent sub-pixels. In the second direction Y, the fourth connection line 94 can be disposed on the side of the first scan signal line 31 near the third connection line 93, and the orthographic projection of the fourth connection line 94 on the silicon substrate at least partially overlaps with the orthographic projection of the second center line O2 on the silicon substrate.

[0377] In an exemplary embodiment, in at least one pixel column, the fourth connecting lines 94 in some adjacent sub-pixels can be an integral structure that is interconnected, and the fourth connecting lines 94 in some adjacent sub-pixels can be separated by the first scan signal line 31. For example, the fourth connecting lines 94 in the Mth pixel row and the fourth connecting lines 94 in the M+1th pixel row can be an integral structure that is interconnected. Alternatively, the fourth connecting lines 94 in the M-1th pixel row and the Mth pixel row can be separated by the first scan signal line 31, and the fourth connecting lines 94 in the M+1th pixel row and the M+2th pixel row can be separated by the first scan signal line 31.

[0378] In an exemplary embodiment, in at least one pixel row, multiple fourth connection lines 94 are connected to third connection lines 93. Since the third connection lines 93 and fourth connection lines 94 are configured to connect to subsequently formed first power lines, the third connection line 93 extending along the first direction X and the fourth connection line 94 extending along the second direction Y form a first layer of mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and decreases the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0379] In an exemplary embodiment, since the third connection line 93 is disposed between adjacent pixel rows and the fourth connection line 94 is disposed between adjacent pixel columns, the third connection line 93 and the fourth connection line 94, which have constant potentials, can not only effectively shield the pixel driving circuit in the sub-pixel and improve the output stability of the pixel driving circuit, but also effectively reduce the mutual interference between the pixel driving circuits in the sub-pixel and effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0380] In an exemplary embodiment, in at least one sub-pixel, the third connecting line 93 and the fourth connecting line 94 can be an integral structure that is interconnected.

[0381] In an exemplary embodiment, in at least one pixel row, a third connecting line 93 and multiple fourth connecting lines 94 can be an interconnected integral structure.

[0382] In an exemplary embodiment, the orthographic projection of the fourth connection line 94 on the silicon substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the silicon substrate. The fourth connection line 94, having a constant potential, can shield the impact of the voltage jumps in the data signal line 70 on critical nodes of the pixel driving circuit.

[0383] In an exemplary embodiment, the second connection line 92 and the fourth connection line 94 are respectively disposed below and above the data signal line 70 in a direction perpendicular to the silicon substrate, which can shield the impact of the switching voltage in the data signal line 70 on the critical nodes of the pixel driving circuit from both the top and bottom directions.

[0384] In an exemplary embodiment, the fourth conductive layer pattern of adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the first scan signal line 31, the twenty-fifth connecting electrode 65, the third connecting line 93, the fourth connecting line 94, and the third electrode plate 130 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0385] In an exemplary embodiment, the positions and shapes of the first scan signal line 31, the twenty-fifth connecting electrode 65, the first power line 81, the third connecting line 93, the fourth connecting line 94, and the third electrode plate 130 of adjacent pixel columns can be substantially the same.

[0386] (14) Forming a seventh insulating layer and a sixth conductive layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the sixth conductive layer pattern may include: sequentially depositing a seventh insulating film and a sixth conductive film on a silicon substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process to form a seventh insulating layer covering the fifth conductive layer pattern, and a sixth conductive layer pattern disposed on the seventh insulating layer, as shown in Figures 20A and 20B, where Figure 20B is a schematic diagram of the sixth conductive layer in Figure 20A. In an exemplary embodiment, the sixth conductive layer may be referred to as the top electrode (CTOP) layer.

[0387] In an exemplary embodiment, the sixth conductive layer pattern in each sub-pixel of the display substrate may include at least a fourth electrode plate 140.

[0388] In an exemplary embodiment, the fourth electrode plate 140 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. The orthographic projection of the fourth electrode plate 140 on the silicon substrate at least partially overlaps with the orthographic projection of the third electrode plate 130 on the silicon substrate. The fourth electrode plate 140 may serve as another electrode plate of the second capacitor.

[0389] In an exemplary embodiment, the orthographic projections of the first electrode plate 110, the second electrode plate 120, the third electrode plate 130, and the fourth electrode plate 140 on the silicon substrate do not overlap with the orthographic projection of the data signal line 70 on the silicon substrate. This can reduce the parasitic capacitance between the data signal line and each electrode plate, prevent the corresponding electrodes in the pixel driving circuit from affecting the data voltage of the data signal line, improve the anti-interference capability of the data signal line, and maximize the display quality.

[0390] In an exemplary embodiment, the fourth electrode plate 140 of adjacent pixel rows may be mirror-symmetrical with respect to the first center line O1, and the position and shape of the fourth electrode plate 140 of adjacent pixel columns may be substantially the same.

[0391] (15) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming an eighth insulating layer pattern may include: depositing an eighth insulating film on a silicon substrate on which the aforementioned pattern is formed, and patterning the eighth insulating film by a patterning process to form an eighth insulating layer covering the pattern of the sixth conductive layer, wherein a plurality of vias are provided on the eighth insulating layer, as shown in FIG21.

[0392] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include: a 51st via V51, a 52nd via V52, a 53rd via V53, and a 54th via V54.

[0393] In an exemplary embodiment, the orthogonal projection of the 51st via V51 onto the silicon substrate is within the range of the orthogonal projection of the 25th connecting electrode 65 onto the silicon substrate. The 7th and 8th insulating layers within the 51st via V51 are etched away, exposing the surface of the 25th connecting electrode 65. The 51st via V51 is configured to allow a subsequently formed anode connecting electrode to be connected to the 25th connecting electrode 65 through the via.

[0394] In an exemplary embodiment, the orthographic projection of the 52nd via V52 on the silicon substrate is within the range of the orthographic projection of the first power line 81 on the silicon substrate. The seventh and eighth insulating layers within the 52nd via V52 are etched away, exposing the surface of the first power line 81. The 52nd via V52 is configured to allow a subsequently formed fifth connection line to be connected to the first power line 81 through the via.

[0395] In an exemplary embodiment, the orthographic projection of the 53rd via V53 on the silicon substrate is within the range of the orthographic projection of the fourth electrode plate 140 on the silicon substrate. The eighth insulating layer within the 53rd via V53 is etched away, exposing the surface of the fourth electrode plate 140. The 53rd via V53 is configured to allow the subsequently formed seventh connection line to be connected to the fourth electrode plate 140 through the via.

[0396] In an exemplary embodiment, the orthographic projection of the 54th via V54 on the silicon substrate is within the range of the orthographic projection of the third connection line 93 on the silicon substrate. The seventh and eighth insulating layers within the 54th via V54 are etched away, exposing the surface of the third connection line 93. The 54th via V54 is configured to allow the subsequently formed sixth connection line to be connected to the third connection line 93 through the via.

[0397] (16) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming a seventh conductive layer pattern may include: depositing a seventh conductive thin film on a silicon substrate on which the aforementioned pattern is formed, patterning the seventh conductive thin film using a patterning process, and forming a seventh conductive layer pattern on an eighth insulating layer, as shown in Figures 22A and 22B, where Figure 22B is a schematic diagram of the seventh conductive layer in Figure 22A. In an exemplary embodiment, the seventh conductive layer may be referred to as a fifth metal layer (Metal5) or a second metal interconnect (TM2) layer.

[0398] In an exemplary embodiment, the seventh conductive layer pattern in each sub-pixel of the display substrate may include at least: an anode connecting electrode 83, a fifth connecting line 95, a sixth connecting line 96, and a seventh connecting line 97.

[0399] In an exemplary embodiment, the anode connection electrode 83 can be a strip extending along the second direction Y. The anode connection electrode 83 is connected to the twenty-fifth connection electrode 65 through the fifty-first via V51, and is configured to connect with the subsequently formed anode. Since the twenty-fifth connection electrode 65 is connected to the twenty-fourth connection electrode 64 through a via, the twenty-fourth connection electrode 64 is connected to the sixteenth connection electrode 56 through a via, the sixteenth connection electrode 56 is connected to the fifth connection electrode 45 through a via, and the fifth connection electrode 45 is connected to the third drain region and the fourth drain region through vias, the anode connection electrode 83 has the potential of the third node N3 of the pixel driving circuit, which enables the subsequent connection of the anode with the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, and allows the current output by the pixel driving circuit to be provided to the anode.

[0400] In an exemplary embodiment, the shape of the fifth connecting line 95 can be a straight line or a broken line extending along the first direction X of the main body, and it can be disposed between the two first scan signal lines 31 of two adjacent pixel rows. The fifth connecting line 95 is connected to the first power line 81 through the fifty-second via V52.

[0401] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the fifth connecting line 95 onto the silicon substrate at least partially overlaps with the orthographic projection of the first center line O1 onto the silicon substrate.

[0402] In an exemplary embodiment, the shape of the sixth connecting line 96 can be a straight line extending along the second direction Y of the main body, and it can be disposed between two third plates 130 of adjacent pixel columns. On the one hand, it is directly connected to the fifth connecting line 95, and on the other hand, it is connected to the third connecting line 93 through the fifty-fourth via V54.

[0403] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the sixth connecting line 96 onto the silicon substrate at least partially overlaps with the orthographic projection of the second center line O2 onto the silicon substrate.

[0404] In an exemplary embodiment, the shape of the seventh connecting line 97 can be a straight line or a broken line extending along the first direction X of the main body. It can be disposed between the fifth connecting line 95 and the anode connecting electrode 83, and is directly connected to the sixth connecting line 96 on the one hand, and connected to the fourth electrode plate 140 through the fifty-third through hole V53 on the other hand.

[0405] In an exemplary embodiment, in at least one pixel row, multiple sixth connection lines 96 are respectively connected to the fifth connection line 95 and the seventh connection line 97. Since the fifth connection line 95 is connected to the first power line 81 through a via, the fifth connection line 95 extending along the first direction X and the sixth connection line 96 extending along the second direction Y form a second-layer mesh-like interconnection structure on the display substrate for transmitting the first power signal. The seventh connection line 97 extending along the first direction X and the sixth connection line 96 extending along the second direction Y form another second-layer mesh-like interconnection structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0406] In an exemplary embodiment, the orthographic projection of the fifth connection line 95 on the silicon substrate and the orthographic projection of the first power line 81 on the silicon substrate at least partially overlap, forming two layers of lateral power lines for transmitting the first power signal. The two layers of lateral power lines can further reduce the resistance of the first power line, further reduce the voltage drop of the first power signal, further improve the uniformity of the first power signal in the display substrate, further improve the display uniformity, and further improve the display quality and display performance.

[0407] In an exemplary embodiment, the orthographic projection of the sixth connection line 96 on the silicon substrate and the orthographic projection of the fourth connection line 94 on the silicon substrate at least partially overlap, forming two layers of vertical power lines for transmitting the first power signal. This can further reduce the resistance of the first power line, further reduce the voltage drop of the first power signal, further improve the uniformity of the first power signal in the display substrate, further improve display uniformity, and further improve display quality and display performance.

[0408] In an exemplary embodiment, in at least one sub-pixel, the fifth connecting line 95, the sixth connecting line 96, and the seventh connecting line 97 can be an integral structure that is interconnected.

[0409] In an exemplary embodiment, in at least one pixel row, a fifth connecting line 95, a sixth connecting line 96, and multiple seventh connecting lines 97 can be an interconnected integral structure.

[0410] In an exemplary embodiment, the two fifth connecting lines 95, the two seventh connecting lines 97, and the multiple sixth connecting lines 96 of adjacent pixel rows can be an integral structure that is interconnected.

[0411] In an exemplary embodiment, since the seventh connection line 97 is connected to the first power line 81, the fourth electrode plate 140 has the potential of the first power line. Thus, the third electrode plate 130, which has the potential of the second node N2, and the fourth electrode plate 140, which has the potential of the first power line, form the second capacitor C2 in the pixel driving circuit.

[0412] In an exemplary embodiment, the pattern of the eighth conductive layer in adjacent pixel rows can be mirror-symmetrical with respect to the first center line O1. For example, the anode connection electrode 83, the fifth connection line 95 to the seventh connection line 97 in the Mth pixel row and the M+1th pixel row can be mirror-symmetrical with respect to the first center line O1.

[0413] In an exemplary embodiment, the positions and shapes of the anode connection electrodes 83 of adjacent pixel columns can be substantially the same.

[0414] In an exemplary embodiment, the fifth connecting line 95 to the seventh connecting line 97 of adjacent pixel columns can be mirror-symmetrical with respect to the second center line O2.

[0415] In an exemplary embodiment, subsequent fabrication processes may include forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first encapsulation layer, a color filter structure layer, and a second encapsulation layer, etc., which will not be described in detail here.

[0416] In an exemplary embodiment, the first to eighth insulating layers can be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), etc., and can be a single-layer structure or a multi-layer composite structure. The first to fifth metal layers can be metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), etc., or can be alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The alloy material can be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of Mo, Cu, and Mo layers, etc. In an exemplary embodiment, the planar shape of the via can be rectangular, circular, or elliptical, etc., and the dimensions of multiple vias can be the same or different; this disclosure does not limit this.

[0417] Figure 23 is a schematic diagram of the structure of the first capacitor and the second capacitor in an exemplary embodiment of the present disclosure. As shown in Figure 23, the first capacitor and the second capacitor are stacked, with the second capacitor disposed on the side of the first capacitor away from the silicon substrate. The first capacitor may include a stacked first electrode 110 and a second electrode 120, and the second capacitor may include a stacked third electrode 130 and a fourth electrode 140.

[0418] In an exemplary embodiment, the display substrate may include at least: a silicon substrate 101, a first insulating layer 201 disposed on the silicon substrate 101, a second insulating layer 202 disposed on the side of the first insulating layer 201 away from the silicon substrate 101, a third insulating layer 203 disposed on the side of the second insulating layer 202 away from the silicon substrate 101, a second conductive layer (Metal2) disposed on the side of the third insulating layer 203 away from the silicon substrate 101, a fourth insulating layer 204 disposed on the side of the second conductive layer away from the silicon substrate 101, a third conductive layer (Metal3) disposed on the side of the fourth insulating layer 204 away from the silicon substrate 101, and a third conductive layer (Metal3) disposed on the side of the third conductive layer away from the silicon substrate 101. The fifth insulating layer 205, the fourth conductive layer (MIM) disposed on the side of the fifth insulating layer 205 away from the silicon substrate 101, the sixth insulating layer 206 disposed on the side of the fourth conductive layer away from the silicon substrate 101, the fifth conductive layer (Metal4) disposed on the side of the sixth insulating layer 206 away from the silicon substrate 101, the seventh insulating layer 207 disposed on the side of the fifth conductive layer away from the silicon substrate 101, the sixth conductive layer (CTOP) disposed on the side of the seventh insulating layer 207 away from the silicon substrate 101, the eighth insulating layer 208 disposed on the side of the sixth conductive layer away from the silicon substrate 101, and the seventh conductive layer (TM2) disposed on the side of the eighth insulating layer 208 away from the silicon substrate 101.

[0419] In an exemplary embodiment, the second conductive layer may include at least a fourteenth connecting electrode 54 as a compensation electrode, the third conductive layer may include at least a first electrode plate 110, the fourth conductive layer may include at least a second electrode plate 120 (MIM), the fifth conductive layer may include at least a third electrode plate 130, the sixth conductive layer may include at least a fourth electrode plate 140 (CTOP), and the seventh conductive layer may include at least a seventh connecting line 97.

[0420] In an exemplary embodiment, the first electrode 110 has a potential of the first node N1. The third electrode 130 is connected to the second electrode 120 via a via and to the fourteenth connecting electrode 54 via the twenty-second connecting electrode 62. Therefore, the fourteenth connecting electrode 54, the second electrode 120, and the third electrode 130 have the same potential of the second node N2. The fourth electrode 140 is connected to the seventh connecting line 97 via a via, and therefore has the potential of the first power line. Thus, the first electrode 110 with the potential of the first node N1 and the second electrode 120 with the potential of the second node N2 form the first capacitor C1 of the pixel driving circuit, and the third electrode 130 with the potential of the second node N2 and the fourth electrode 140 with the potential of the first power line form the second capacitor C2 of the pixel driving circuit.

[0421] In an exemplary embodiment, the first electrode 110 having a potential of the first node N1 and the fourteenth connecting electrode 54 having a potential of the second node N2 also form a parasitic capacitance, and the parasitic capacitance is connected in parallel with the first capacitor C1, effectively increasing the capacity of the first capacitor C1.

[0422] In an exemplary embodiment, since both the first capacitor and the second capacitor are parallel plate capacitors, and only one insulating layer is provided between the first plate 110 and the second plate 120, and only one insulating layer is provided between the third plate 130 and the fourth plate 140, the capacitance of the first capacitor and the second capacitor can be effectively guaranteed. Under the premise of meeting the design requirements, the arrangement of the pixel driving circuit can be made more compact, which helps to improve the resolution of the display device.

[0423] In an exemplary embodiment, the capacitance of the first capacitor and the second capacitor can be further increased by increasing the number of conductive layers or decreasing the thickness of the insulating layer, and this disclosure does not limit the scope of the invention.

[0424] An exemplary embodiment of this disclosure provides a display substrate. By providing a shielding electrode connected to a first power line, the shielding electrode covers the gate electrode of a third transistor T3, which can effectively shield the gate electrode of the third transistor T3, effectively eliminate interference from signal traces and electrodes to the third transistor T3, improve the working stability of the third transistor T3, effectively improve the uniformity and stability of the output current or voltage of the pixel driving circuit, and improve display quality.

[0425] This disclosure, by setting a first capacitor and a second capacitor in a planar capacitor structure, and stacking the first capacitor and the second capacitor, not only solves the problem of capacitor area limitation, but also allows the parasitic capacitance generated by the stacked structure to be superimposed on the capacitor itself, reducing the influence of parasitic capacitance and increasing the capacitance value. This ensures the stability and uniformity of the output current of the pixel driving circuit, and allows for a more compact arrangement of the pixel driving circuit while meeting design requirements, which helps to improve the resolution of the display device.

[0426] This disclosure provides a compensation electrode, which forms a parasitic capacitance with the first plate. The parasitic capacitance is connected in parallel with the first capacitor, effectively increasing the capacitance of the first capacitor and helping to reduce flickering.

[0427] This disclosure provides a first power connection electrode between the first node electrode and the second node electrode. The first power connection electrode with a constant potential can form a constant potential shield, effectively eliminating crosstalk between the gate electrode and the first electrode in the third transistor T3, improving the uniformity and stability of the output current or voltage of the pixel driving circuit, and improving display quality.

[0428] This disclosure avoids short circuits between the data signal line and the first power line by setting the spacing between the second power connection electrode and the data signal line, thus preventing vertical line defects caused by short circuits.

[0429] This disclosure improves the accuracy of data signal writing and enhances display accuracy by placing a first power line between two first scan signal lines in two adjacent pixel rows. The first power line with a constant potential can be shielded by constant potential to prevent crosstalk between the shifted first scan signal in one pixel row and the unshifted first scan signal in another pixel row.

[0430] This disclosure effectively shields the fourth transistor T4 and the third node N3 in the sub-pixel by setting a shielding structure surrounding the fourth transistor T4 in three directions, and the shielding structure has the potential of the second power line. This can effectively reduce the mutual interference between adjacent fourth transistors T4 and third nodes N3, improve the reset performance and working stability of the fourth transistor T4, and improve the uniformity and stability of the output current or voltage of the pixel driving circuit.

[0431] This disclosure forms a mesh-like interconnected structure on the display substrate by setting a first connecting line and a second connecting line to transmit the second power signal. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0432] This disclosure forms a first-layer mesh-like interconnection structure for transmitting the first power signal by setting a third and a fourth connecting line, and a second-layer mesh-like interconnection structure for transmitting the first power signal by setting a fifth, a sixth, and a seventh connecting line, and the second-layer mesh-like interconnection structure is connected to the first-layer mesh-like interconnection structure. This minimizes the resistance of the first power line, minimizes the voltage drop of the first power signal, maximizes the uniformity of the first power signal in the display substrate, maximizes the display uniformity, and maximizes the display quality and display performance, which is beneficial for improving the low grayscale display effect.

[0433] This disclosure improves the uniformity and symmetry of the pixel driving circuit by setting the pixel driving circuit of adjacent pixel rows to be mirrored relative to the first center line. This not only enables the design of uniform process and coupling capacitors, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0434] This disclosure effectively reduces the horizontal and vertical wiring space, the number of vias, and the area occupied by the pixel driving circuit by setting the first transistor T1 of adjacent pixel rows to be mirrored and sharing the first electrode of the first transistor T1, and the fourth transistor T4 of adjacent pixel columns to be mirrored and sharing the first electrode of the fourth transistor T4, which is beneficial to achieving high resolution.

[0435] This disclosure effectively reduces the layout space used in the substrate area and the area occupied by the pixel driving circuit by setting transistors of the same type to share the same type of substrate area, which is beneficial to achieving high resolution.

[0436] This disclosure provides a second connecting line below and a fourth connecting line above the data signal line, respectively. These second and fourth connecting lines, each with a constant potential, can shield the data signal line from voltage fluctuations in both directions, preventing them from affecting critical nodes in the pixel driving circuit. Furthermore, by ensuring the data signal line does not overlap with any of the electrodes, this disclosure reduces parasitic capacitance between the data signal line and the electrodes, preventing the corresponding electrodes in the pixel driving circuit from affecting the data voltage of the data signal line. This improves the anti-interference capability of the data signal line and maximizes display quality.

[0437] This disclosure improves tolerance to process fluctuations and particle defects by adjusting the number of metal layers, trace positions, and trace spacing, reducing the proportion of line and point defects and improving product yield. Through the layout of the pixel driving circuit, the resistance and voltage drop of the power supply traces are significantly reduced, significantly improving circuit performance and enhancing display brightness uniformity. By adding shielded traces, crosstalk to key nodes of the pixel driving circuit is significantly reduced, lowering signal crosstalk and improving display stability. Optimized layout space effectively reduces the area occupied by the pixel driving circuit. The display substrate of this disclosure can achieve a resolution greater than or equal to 3800 PPI and a refresh rate of 60Hz to 120Hz, resulting in better display stability and smoothness. It can effectively reduce dizziness in VR applications and the screen-door effect in AR applications, effectively increasing immersion and improving the user experience.

[0438] The fabrication process disclosed herein is based on a 0.11μm integrated circuit process, which is highly compatible with existing fabrication processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0439] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as Micro OLED microdisplays, OLED displays, quantum dot displays (QLED), light-emitting diode microdisplays (Micro LED or Mini LED) or quantum dot light-emitting diode microdisplays (QDLED), etc., and this disclosure does not limit them.

[0440] In exemplary embodiments, the pixel driving circuit of the display substrate disclosed herein can be applied to product types including but not limited to integrated silicon-based, glass-based, printed circuit board (PCB)-based substrate materials, amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), low-temperature polycrystalline oxide (LTPO), oxide semiconductor materials represented by indium gallium zinc oxide (IGZO), and devices such as thin-film transistors (TFTs), metal-oxide semiconductors (MOS), and diodes with structures such as back channel etching structure (BCE), etch stop layer structure (ESL), top gate structure, and dual gate structure.

[0441] The structure of the display device and its fabrication process in the exemplary embodiments disclosed herein are merely illustrative examples. The corresponding structure and the patterning process may be modified or increased or decreased according to actual circumstances. This disclosure does not limit the scope of the invention.

[0442] This exemplary embodiment also provides a method for fabricating a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the fabrication method may include:

[0443] A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor, and a fourth transistor. The first electrode of the first transistor is coupled to a data signal line, the second electrode of the first transistor is coupled to the gate electrode of the third transistor, the first electrode of the second transistor is coupled to a first power line, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the first electrode of the fourth transistor is coupled to a second power line, and the second electrode of the fourth transistor is coupled to the second electrode of the third transistor. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the pixel driving circuit. The at least one sub-pixel also includes a shielding electrode connected to the first power line. The orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0444] This exemplary embodiment also provides a display device, including the aforementioned display substrate. The display device of this disclosure can be used in virtual reality devices, augmented reality devices, extended reality devices, mixed reality devices, sights, and rangefinders, and can also be used in, but is not limited to, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or any product or component with display functionality.

[0445] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor and a fourth transistor, a first electrode of the first transistor being coupled to a data signal line, a second electrode of the first transistor being coupled to the gate electrode of the third transistor, a first electrode of the second transistor being coupled to a first power line, a second electrode of the second transistor being coupled to the first electrode of the third transistor, a first electrode of the fourth transistor being coupled to a second power line, and a second electrode of the fourth transistor being coupled to the second electrode of the third transistor, the first power line being configured to provide a first power signal to the pixel driving circuit, and the second power line being configured to provide a second power signal to the pixel driving circuit; the at least one sub-pixel further comprising a shielding electrode connected to the first power line, the orthographic projection of the shielding electrode on a plane of the display substrate at least partially overlapping the orthographic projection of the gate electrode of the third transistor on a plane of the display substrate.

2. The display substrate according to claim 1, wherein, The overlapping area of ​​the orthographic projection of the shielding electrode on the display substrate plane and the orthographic projection of the gate electrode of the third transistor on the display substrate plane has a first area, and the orthographic projection of the gate electrode of the third transistor on the display substrate plane has a second area, wherein the ratio of the first area to the second area is greater than or equal to 0.

8.

3. The display substrate according to claim 1, wherein, In the pixel row direction, there is a shielding gap between two adjacent shielding electrodes, the shielding gap being less than twice the width of the first power line, or the shielding gap being less than twice the width of the second power line.

4. The display substrate according to claim 1, wherein, The first transistor includes at least a first source region and a first drain region, the second transistor includes at least a second source region and a second drain region, the third transistor includes at least a third source region and a third drain region, and the fourth transistor includes at least a fourth source region and a fourth drain region; the first drain region is connected to the gate electrode of the third transistor through a first node electrode, the second drain region is connected to the third source region and connected to the second node electrode through a via, and the third drain region is connected to the fourth drain region through a third node electrode; in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, and the first node electrode, the second node electrode, the third node electrode, and the shielding electrode are disposed in the same conductive layer.

5. The display substrate according to claim 1, wherein, At least one sub-pixel also includes a first power connection electrode, and the shielding electrode is connected to the first power line through the first power connection electrode; in the pixel row direction, the first power connection electrode is disposed between the first node electrode and the second node electrode.

6. The display substrate according to claim 5, wherein, The first power connection electrode includes at least a horizontal electrode extending along the pixel row direction and a first vertical electrode and a second vertical electrode extending along the pixel column direction. The first vertical electrode and the second vertical electrode are respectively disposed on both sides of the horizontal electrode in the pixel column direction. One end of the first vertical electrode is connected to the first power line and the other end is connected to the horizontal electrode. One end of the second vertical electrode is connected to the shielding electrode and the other end is connected to the horizontal electrode. In the pixel row direction, the second vertical electrode is disposed between the first node electrode and the second node electrode.

7. The display substrate according to claim 6, wherein, At least one sub-pixel further includes a second power connection electrode disposed on the same layer as the data signal line, the first power line being connected to the second power connection electrode through a via, and the second power connection electrode being connected to the first power connection electrode through a via; in the pixel row direction, the spacing between the second power connection electrode in this sub-pixel and the data signal line in the adjacent sub-pixel is greater than or equal to the width of the data signal line.

8. The display substrate according to claim 7, wherein, At least one sub-pixel also includes a data connection strip, the first end of which is connected to the data signal line, and the second end of which extends toward the second power connection electrode and is connected to the first electrode of the second transistor; in the pixel row direction, the distance between the second power connection electrode in the sub-pixel and the data connection strip in the sub-pixel is greater than or equal to the width of the data signal line.

9. The display substrate according to claim 7, wherein, In a direction perpendicular to the display substrate, the display substrate includes at least a first metal layer disposed on a silicon substrate, a second metal layer disposed on the side of the first metal layer away from the silicon substrate, and a third metal layer disposed on the side of the second metal layer away from the silicon substrate; the first node electrode, the second node electrode, the third node electrode and the shielding electrode are disposed in the first metal layer, the first power connection electrode is disposed in the second metal layer, and the data signal line and the second power connection electrode are disposed in the third metal layer.

10. The display substrate according to claim 9, wherein, The second power line is disposed in the first metal layer. The second metal layer further includes a second connecting line. The shape of the second power line is a straight line or a broken line extending along the pixel row direction and is continuously disposed in the pixel row direction. The shape of the second connecting line is a straight line or a broken line extending along the pixel column direction and is not continuously disposed in the pixel column direction. The second connecting line is connected to the second power line to form a mesh-like interconnected structure for transmitting the second power signal.

11. The display substrate according to claim 10, wherein, The gate electrode of the fourth transistor is coupled to the third scan signal line, which is a straight line or a broken line extending along the pixel row direction; in the pixel column direction, the second connecting line is spaced apart by the third scan signal line.

12. The display substrate according to claim 10, wherein, At least one sub-pixel also includes a power connection portion disposed on the same layer as the second power line. The power connection portion is a strip shape extending along the pixel row direction. A first end of the power connection portion is connected to the second power line, and a second end of the power connection portion extends away from the second power line and is connected to the second connection line through a via.

13. The display substrate according to any one of claims 1 to 12, wherein, The pixel driving circuit further includes a first capacitor, which includes at least a first electrode plate and a second electrode plate. The orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane. The first electrode plate is connected to the first node electrode, and the second electrode plate is connected to the second node electrode.

14. The display substrate according to claim 13, wherein, At least one sub-pixel also includes a compensation electrode, the second electrode plate is connected to the second node electrode through the compensation electrode, the orthographic projection of the compensation electrode on the display substrate plane overlaps at least partially with the orthographic projection of the first electrode plate on the display substrate plane, the compensation electrode and the first electrode plate form a parasitic capacitance, and the parasitic capacitance is connected in parallel with the first capacitance.

15. The display substrate according to claim 14, wherein, The overlapping area of ​​the orthographic projection of the compensation electrode on the display substrate plane and the orthographic projection of the first electrode plate on the display substrate plane has a third area, and the orthographic projection of the first electrode plate on the display substrate plane has a fourth area, wherein the ratio of the third area to the fourth area is greater than or equal to 0.

5.

16. The display substrate according to claim 14, wherein, At least one sub-pixel also includes a second connecting line and a thirteenth connecting electrode disposed on the same layer as the compensation electrode. The second connecting line is connected to the second power line and is disposed between two adjacent compensation electrodes in the pixel row direction. The thirteenth connecting electrode is connected to the first node electrode through a via. The compensation electrode has a first distance from the second connecting line, and the compensation electrode has a second distance from the thirteenth connecting electrode. The first distance is less than the second distance. The first distance is a dimension in the pixel row direction, and the second distance is a dimension in the pixel column direction.

17. The display substrate according to claim 16, wherein, At least one sub-pixel also includes a sixteenth connecting electrode disposed on the same layer as the compensation electrode, the sixteenth connecting electrode being connected to the third node electrode through a via; there is a third distance between the compensation electrode and the sixteenth connecting electrode, the first distance being smaller than the third distance, the third distance being a dimension in the pixel column direction.

18. The display substrate according to claim 16, wherein, At least one sub-pixel also includes a first power connection electrode and a thirteenth connection electrode disposed on the same layer as the compensation electrode. The shielding electrode is connected to the first power line through the first power connection electrode, and the thirteenth connection electrode is connected to the first node electrode through a via. There is a fourth distance between the first power connection electrode and the thirteenth connection electrode, and the second distance is greater than the fourth distance. The fourth distance is a dimension in the pixel row direction.

19. The display substrate according to claim 16, wherein, At least one sub-pixel further includes a first power connection electrode and an eleventh connection electrode disposed on the same layer as the compensation electrode. The shielding electrode is connected to the first power line through the first power connection electrode, and the eleventh connection electrode is configured to be connected to the data signal line. There is a fifth distance between the first power connection electrode and the second connection line, and a sixth distance between the first power connection electrode and the eleventh connection electrode. The fifth distance is smaller than the sixth distance, and the fifth distance and the sixth distance are dimensions in the pixel row direction.

20. The display substrate according to claim 14, wherein, In a direction perpendicular to the display substrate, the display substrate includes at least a first metal layer disposed on a silicon substrate, a second metal layer disposed on the side of the first metal layer away from the silicon substrate, and a third metal layer disposed on the side of the second metal layer away from the silicon substrate; the first node electrode and the second node electrode are disposed in the first metal layer, the compensation electrode is disposed in the second metal layer, and the first electrode plate is disposed in the third metal layer.

21. The display substrate according to any one of claims 1 to 12, wherein, The gate electrode of the first transistor is coupled to the first scan signal line. The first scan signal line and the first power line are straight lines or broken lines extending along the pixel row direction. In the pixel column direction, the first power line is disposed between two adjacent first scan signal lines.

22. A display device comprising a display substrate as described in any one of claims 1 to 21.

23. A method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns; the fabrication method comprising: A pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit including at least a first transistor, a second transistor, a third transistor and a fourth transistor, the first terminal of the first transistor being coupled to a data signal line, the second terminal of the first transistor being coupled to the gate electrode of the third transistor, the first terminal of the second transistor being coupled to a first power line, the second terminal of the second transistor being coupled to the first terminal of the third transistor, the first terminal of the fourth transistor being coupled to a second power line, and the second terminal of the fourth transistor being coupled to the second terminal of the third transistor, the first power line being configured to provide a first power signal to the pixel driving circuit, and the second power line being configured to provide a second power signal to the pixel driving circuit; At least one sub-pixel also includes a shielding electrode connected to the first power line, wherein the orthographic projection of the shielding electrode on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

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