Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises: a base substrate (1); a driving circuit layer group (2), which comprises gate lines (212) and data lines (241), wherein every two adjacent gate lines (212) form a gate line group (212Z), the plurality of data lines (241) and the plurality of gate line groups (212Z) are arranged to intersect with each other so as to define a plurality of pixel areas within a display area, and the driving circuit layer group (2) comprises first transistors (T1) and second transistors (T2); a conductive auxiliary layer (4), which comprises first auxiliary traces (41) electrically connected to first electrodes (3); and second electrodes (6), wherein every two adjacent second electrodes (6) comprise a first pixel electrode (6a) and a second pixel electrode (6b), the first pixel electrode (6a) comprises a first electrode portion (6a1) and a first lead portion (6a2) connected to each other, the second pixel electrode (6b) comprises a second electrode portion (6b1) and a second lead portion (6b2) connected to each other, the first lead portion (6a2) is connected to a first transistor (T1), the first transistor (T1) and the first electrode portion (6a1) are located in the same pixel column, the second lead portion (6b2) is connected to a second transistor (T2), and the second electrode portion (6b1) and the second transistor (T2) are respectively located in adjacent pixel columns, and orthographic projections of the first auxiliary traces (41) on the base substrate (1) do not overlap with orthographic projections of the first lead portions (6a2) and the second lead portions (6b2) on the base substrate (1).

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in various display fields, such as homes, public places, offices, and personal electronic products.

[0003] However, with the development of technology, current display products cannot meet the increasingly higher requirements of customers.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0007] According to one aspect of this disclosure, an array substrate is provided having a display area and a non-display area, the non-display area including a fan-out region and a bonding region, the array substrate comprising:

[0008] Substrate;

[0009] A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes a data line, and the data line extends along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor.

[0010] A first electrode, a conductive auxiliary layer, and a second electrode are disposed on the side of the driving circuit layer group facing away from the substrate; the conductive auxiliary layer includes a first auxiliary trace, which is electrically connected to the first electrode.

[0011] A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns. The orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate.

[0012] In one exemplary embodiment of this disclosure, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the first auxiliary trace near the corner of the first auxiliary trace on the substrate, while the other portions of the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the first auxiliary trace on the substrate.

[0013] In one exemplary embodiment of this disclosure, the first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0014] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0015] A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.

[0016] In one exemplary embodiment of this disclosure, the first electrode portion and the second electrode portion are located within the same pixel region.

[0017] In one exemplary embodiment of this disclosure, three pixel regions arranged along the first direction form a group, and a first auxiliary trace is provided in a group of pixel regions, or a first auxiliary trace is provided between two adjacent groups of pixel regions.

[0018] In one exemplary embodiment of this disclosure, the conductive auxiliary layer further includes a third auxiliary trace, the orthographic projection of the third auxiliary trace on the substrate is located between the orthographic projections of two adjacent second electrodes on the substrate, the third auxiliary trace is disconnected, and the virtual extension line of the third auxiliary trace intersects with the second lead portion.

[0019] In one exemplary embodiment of this disclosure, in the second direction, the first transistor and the second transistor are each located on opposite sides of the pixel region.

[0020] In one exemplary embodiment of this disclosure, the plurality of transistors include multiple groups of transistors, each group of transistors includes two transistors, the two transistors in the same group are located between two adjacent gate lines in the same group, the two transistors in the same group are connected to opposite sides of the same data line in the first direction, and are staggered in the second direction.

[0021] In one exemplary embodiment of this disclosure, the two gates of two transistors in the same group are connected one-to-one to two adjacent gate lines in the same group.

[0022] In one exemplary embodiment of this disclosure, the gate line is configured as a straight line extending along the first direction.

[0023] In one exemplary embodiment of this disclosure, the conductor layer further includes signal traces, the data lines and the signal traces are configured as strips extending along the second direction, the signal traces and the data lines are arranged alternately at intervals, the first electrode is multiplexed as a touch electrode, the driving circuit layer group includes a first insulating layer, the first insulating layer is located between the conductor layer and the first electrode, the first electrode is connected to the signal traces through a third via on the first insulating layer, and the orthographic projection of the third via on the substrate is located between the orthographic projections of two adjacent transistors on the substrate.

[0024] In one exemplary embodiment of this disclosure, the orthographic projection of the second lead portion on the substrate overlaps with the orthographic projection of the signal trace on the substrate, while the orthographic projection of the first lead portion on the substrate does not overlap with the orthographic projection of the signal trace on the substrate.

[0025] In an exemplary embodiment of this disclosure, the display area and the bonding area are connected to opposite sides of the fan-out area in the second direction. The fan-out area includes a first fan-out area, and the bonding area includes a first sub-bonding area. The first sub-bonding area includes an invalid pin area for setting invalid pins of the driver chip. The first fan-out area and the first sub-bonding area are disposed opposite to each other in the second direction. The array substrate further includes:

[0026] The first trace group is located in the first fan-out area and is connected between the display area and the first sub-binding area. The first trace group includes multiple parallel first traces. Each first trace includes a trace section and a compensation section. The compensation section includes at least two trace segments arranged at a set angle. The compensation section is arranged opposite to the invalid pin area.

[0027] In one exemplary embodiment of this disclosure, the wiring portion extends along the second direction and is connected to the first sub-binding area, and the compensation portion includes:

[0028] A first compensation trace is connected to the display area, and the first compensation trace extends along the second direction;

[0029] The second compensation trace is connected between the first compensation trace and the trace portion, and the second compensation trace extends along the first direction.

[0030] In one exemplary embodiment of this disclosure, the line width of the compensation section is greater than the line width of the routing section.

[0031] In an exemplary embodiment of this disclosure, the fan-out region further includes a second fan-out region and a third fan-out region, the second fan-out region and the third fan-out region being disposed on opposite sides of the first fan-out region in the first direction; the bonding region further includes a second sub-bonding region and a third sub-bonding region, the second sub-bonding region and the third sub-bonding region being disposed on opposite sides of the first sub-bonding region in the first direction; the array substrate further includes:

[0032] The second wiring group is located in the second fan-out area, and the second wiring group is connected between the display area and the second sub-binding area;

[0033] The third wiring group is located in the third fan-out area, and the third wiring group is connected between the display area and the third sub-binding area;

[0034] The second wiring group and the third wiring group are located on opposite sides of the first wiring group in the first direction.

[0035] In an exemplary embodiment of this disclosure, the second trace group includes a plurality of second traces arranged in parallel along the first direction, and the third trace group includes a plurality of third traces arranged in parallel along the first direction. The resistance difference between the first trace and the adjacent second trace is less than or equal to 2Ω, and the resistance difference between the first trace and the adjacent third trace is less than or equal to 2Ω.

[0036] In an exemplary embodiment of this disclosure, at least a portion of the second trace includes a first trace segment, a second trace segment, a third trace segment, and a fourth trace segment connected in sequence. The first trace segment extends along the second direction, and the extension direction of the second trace segment has a predetermined angle with the second direction. The third trace segment extends along the first direction, and the extension direction of the fourth trace segment has a predetermined angle with the first direction. The end of the first trace segment away from the second trace segment is connected to the second sub-binding area, and the end of the fourth trace segment away from the third trace segment is connected to the display area.

[0037] At least a portion of the third trace includes a seventh trace segment, an eighth trace segment, a ninth trace segment, and a tenth trace segment connected in sequence. The seventh trace segment extends along the second direction, the extension direction of the eighth trace segment has a set angle with the second direction, the ninth trace segment extends along the first direction, and the extension direction of the tenth trace segment has a set angle with the first direction. The end of the seventh trace segment away from the eighth trace segment is connected to the third sub-binding area, and the end of the tenth trace segment away from the ninth trace segment is connected to the display area.

[0038] In an exemplary embodiment of this disclosure, at least a portion of the second trace includes a first trace segment, a second trace segment, a third trace segment, a fourth trace segment, a fifth trace segment, and a sixth trace segment connected sequentially. The first trace segment extends along the second direction, and the extension direction of the second trace segment has a predetermined angle with the second direction. The third trace segment and the fifth trace segment extend along the first direction, and the extension directions of the fourth trace segment and the sixth trace segment have a predetermined angle with the first direction. The end of the first trace segment away from the second trace segment is connected to the second sub-binding area, and the end of the sixth trace segment away from the fifth trace segment is connected to the display area.

[0039] At least a portion of the third trace includes a seventh trace segment, an eighth trace segment, a ninth trace segment, a tenth trace segment, an eleventh trace segment, and a twelfth trace segment connected in sequence. The seventh trace segment extends along the second direction. The extension direction of the eighth trace segment forms a predetermined angle with the second direction. The ninth and eleventh trace segments extend along the first direction. The extension directions of the tenth and twelfth trace segments form a predetermined angle with the first direction. The end of the seventh trace segment away from the eighth trace segment is connected to the third sub-binding area. The end of the twelfth trace segment away from the eleventh trace segment is connected to the display area.

[0040] In an exemplary embodiment of this disclosure, the second fan-out region includes a first sub-region, a second sub-region, and a third sub-region connected sequentially along the first direction, the third sub-region being connected to the first fan-out region; the third fan-out region includes a fourth sub-region, a fifth sub-region, and a sixth sub-region connected sequentially along the first direction, the fourth sub-region being connected to the first fan-out region; the fifth and sixth routing segments are located in the first sub-region, the third and fourth routing segments are located in the second sub-region, and the first and second routing segments are located in the third sub-region; the seventh and eighth routing segments are located in the fourth sub-region, the ninth and tenth routing segments are located in the fifth sub-region, and the eleventh and twelfth routing segments are located in the sixth sub-region.

[0041] In an exemplary embodiment of this disclosure, the ratio of line width to line spacing in the first sub-region is a first ratio, the ratio of line width to line spacing in the second sub-region is a second ratio, and the ratio of line width to line spacing in the third sub-region is a third ratio. The ratio of the first ratio to the third ratio is greater than or equal to 2.0 and less than or equal to 2.5, and the ratio of the second ratio to the third ratio is greater than or equal to 1.2 and less than or equal to 1.5. The ratio of line width to line spacing in the fourth sub-region is a fourth ratio, the ratio of line width to line spacing in the fifth sub-region is a fifth ratio, and the ratio of line width to line spacing in the sixth sub-region is a sixth ratio. The ratio of the sixth ratio to the fourth ratio is greater than or equal to 2.0 and less than or equal to 2.5, and the ratio of the fifth ratio to the fourth ratio is greater than or equal to 1.2 and less than or equal to 1.5.

[0042] In one exemplary embodiment of this disclosure, the gate layer is disposed on one side of the substrate, and the driving circuit layer group further includes:

[0043] A gate insulating layer is disposed on the side of the gate layer opposite to the substrate.

[0044] An active layer is disposed on the side of the gate insulating layer away from the substrate. The active layer includes a first conductive connection portion, a channel portion, and a second conductive connection portion connected in sequence. A conductor layer is disposed on the side of the active layer away from the substrate. The conductor layer also includes a source and a drain. The source is connected to the first conductive connection portion. The data line is connected to the source. The drain is connected to the second conductive connection portion. Two pixel columns are disposed between two adjacent data lines.

[0045] A first insulating layer is disposed on the side of the conductor layer opposite to the substrate. A first via is disposed on the first insulating layer. A second via is disposed on the second insulating layer and communicates with the first via. The second electrode is connected to the drain electrode through the second via and the first via.

[0046] In an exemplary embodiment of this disclosure, the drain includes an electrode block, a connecting block, and a compensation block connected sequentially in a first direction. The electrode block is connected to the second conductive connection portion, and the second electrode is connected to the connecting block through the second via and the first via. In the second direction, the distance between the electrode block and the gate line is less than the distance between the compensation block and the gate line, and the width of the connecting block is greater than the width of the electrode block and the compensation block.

[0047] In one exemplary embodiment of this disclosure, in the second direction, the size of the source electrode is larger than the size of the electrode block, and the orthographic projection of the portion of the source electrode extending beyond the active layer onto the substrate overlaps with the orthographic projection of the gate line onto the substrate.

[0048] In one exemplary embodiment of this disclosure, the multiple data lines have different lengths, and the length of the data lines increases with the increase of the distance from the first center line in the first direction. The first center line is the center line of the bonding area that extends along the second direction for bonding a portion of the driver chip.

[0049] In an exemplary embodiment of this disclosure, at least a portion of the data line includes a first portion and a second portion that are interconnected, wherein the orthographic projection of the second portion onto the substrate lies within a region between mutually distant edges of the orthographic projections of the two gate lines of the same group onto the substrate.

[0050] The width of the second portion is greater than the width of the first portion, and the number of the second portions increases with the increase of the distance from the first center line in the first direction; or, the width of the second portion is less than the width of the first portion, and the number of the second portions decreases with the increase of the distance from the first center line in the first direction.

[0051] In one exemplary embodiment of this disclosure, the connection between the second part and the first part is arc-shaped.

[0052] In one exemplary embodiment of this disclosure, the conductive auxiliary layer further includes a second auxiliary trace extending along the second direction. The orthographic projection of the second auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate. The driving circuit layer group includes a first insulating layer located between the conductor layer and the first electrode. A fourth via is provided on the first insulating layer, the fourth via communicating with the data line. The second auxiliary trace is connected to the data line through the fourth via. The number of the second auxiliary traces increases with the increase of the distance from the first center line in the first direction.

[0053] In one exemplary embodiment of this disclosure, the orthographic projection of the fourth via on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

[0054] In one exemplary embodiment of this disclosure, there is a non-zero gap between the first center line and the second center line. The first center line is a center line extending along a second direction for a portion of the bonding area used to bond a driver chip. The second center line is a center line extending along a second direction for a portion of the display area corresponding to one of the driver chips.

[0055] According to another aspect of this disclosure, a display device is provided, comprising: an array substrate, which is any of the array substrates described above.

[0056] In one exemplary embodiment of this disclosure, the display device includes alternating rows of red sub-pixels, green sub-pixels, and blue sub-pixels, and the orthographic projection of the first auxiliary trace on the substrate is located between the orthographic projections of the red sub-pixel rows and the green sub-pixel rows on the substrate.

[0057] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0058] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0059] Figure 1 is a schematic diagram of an example embodiment of the array substrate disclosed herein.

[0060] Figure 2 is a schematic diagram of the cross-sectional structure of a portion of the area shown in Figure 1.

[0061] Figure 3 is an equivalent circuit diagram of the array substrate of this disclosure.

[0062] Figure 4 is a partial top view of the gate layer in Figure 2.

[0063] Figure 5 is a schematic diagram of the structure after the active layer is formed based on Figure 4.

[0064] Figure 6 is a schematic diagram of the structure after the conductor layer is formed based on Figure 5.

[0065] Figure 7 is a partial top view of the conductor layer in Figure 6.

[0066] Figure 8 is a schematic diagram of the structure after the first insulating layer and the first via are formed based on Figure 6.

[0067] Figure 9 is a schematic diagram of the structure after forming a conductive auxiliary layer based on Figure 8.

[0068] Figure 10 is a schematic diagram of the structure of the first auxiliary wiring in Figure 9.

[0069] Figure 11 is a schematic diagram of the structure after the second electrode is formed based on Figure 9.

[0070] Figure 12 is a partial top view of the structure of the second electrode in Figure 11.

[0071] Figure 13 is a schematic diagram of the structure after the septum portion is formed based on Figure 11.

[0072] Figure 14 is a schematic diagram showing a poor display of alternating bright and dark areas in the sky blue image.

[0073] Figure 15 is a schematic cross-sectional view of the section cut according to NN in Figure 11.

[0074] Figure 16 is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0075] Figure 17 is a schematic diagram of an example embodiment of the data lines in the display area of ​​the array substrate of this disclosure.

[0076] Figure 18 is a schematic diagram of another example embodiment of the data lines in the display area of ​​the array substrate of this disclosure.

[0077] Figure 19 is a schematic cross-sectional view of the section cut according to MM in Figure 16.

[0078] Figure 20 is a schematic diagram of the fan-out region corresponding to one of the driver chips in Figure 1.

[0079] Figure 21 is a schematic diagram of the structure of the first fan-out region and the first sub-binding region in Figure 20.

[0080] Figure 22 is a partially enlarged schematic diagram of the part indicated by H in Figure 21.

[0081] Figure 23 is a partially enlarged schematic diagram of the part indicated by I in Figure 21.

[0082] Figure 24 is a structural schematic diagram of another example implementation of the first wiring group.

[0083] Figure 25 is a schematic diagram of the structure of the second fan-out region and the second sub-binding region in Figure 20.

[0084] Figure 26 is a schematic diagram of the structure of the third fan-out region and the third sub-binding region in Figure 20.

[0085] Figure 27 is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0086] Figure 28 is a schematic diagram of another example embodiment after forming a conductive auxiliary layer based on Figure 8.

[0087] Figure 29 is a schematic diagram of the structure after the second electrode is formed based on Figure 28.

[0088] Explanation of reference numerals in the attached figures:

[0089] 1. Substrate;

[0090] 2. Driving circuit layer group; TFTZ, thin film transistor group; TFT, thin film transistor; T1, first transistor; T2, second transistor; 21, gate layer; 211, gate; 212Z, gate line group; 212, gate line; 213, capacitor compensation section; 22, gate insulating layer; 23, active layer; 231, first conductive connection section; 232, channel section; 233, second conductive connection section; 24, conductor layer; 241, data line; 2411, first part; 2412, second part; 242, source; 243, drain; 2431, electrode block; 2432, connection block; 2433, compensation block; 244, signal trace; 25, first insulating layer; 25a, inorganic layer; 25b, organic layer; 251, first via; 252, third via; 253, fourth via;

[0091] 3. First electrode;

[0092] 4. Conductive auxiliary layer; 41. First auxiliary trace; 42. Second auxiliary trace; 43. Third auxiliary trace; 431. Virtual extension line;

[0093] 5. Second insulating layer; 51. Second via;

[0094] 6. Second electrode; 6a. First pixel electrode; 6a1. First electrode portion; 6a2. First lead portion; 6b. Second pixel electrode; 6b1. Second electrode portion; 6b2. Second lead portion;

[0095] 7. First wiring group; 71. First wiring; 711. Wiring section; 712. Compensation section; 712a. Wiring segment; 7121. First compensation wiring; 7122. Second compensation wiring; 7123. Third compensation wiring;

[0096] 8. Second wiring group; 81. Second wiring; 811. First wiring segment; 812. Second wiring segment; 813. Third wiring segment; 814. Fourth wiring segment; 815. Fifth wiring segment; 816. Sixth wiring segment;

[0097] 9. Third wiring group; 91. Third wiring; 911. Seventh wiring segment; 912. Eighth wiring segment; 913. Ninth wiring segment; 914. Tenth wiring segment; 915. Eleventh wiring segment; 916. Twelfth wiring segment;

[0098] AA, Display Area; NAA, Non-Display Area; Fanout, Fanout Region; Fanout1, First Fanout Region; Fanout2, Second Fanout Region; Fanout21, First Sub-region; Fanout22, Second Sub-region; Fanout23, Third Sub-region; Fanout3, Third Fanout Region; Fanout31, Fourth Sub-region; Fanout32, Fifth Sub-region; Fanout33, Sixth Sub-region; BOD, Bonding Region; BOD1, First Sub-Bonding Region; WX, Invalid Pin Region; BOD2, Second Sub-Bonding Region; BOD3, Third Sub-Bonding Region; IC, Driver Chip;

[0099] PXQ, pixel region; PXH, pixel row; PXL, pixel column; PX, pixel; PX1, first pixel; PX2, second pixel; R, first sub-pixel; G, second sub-pixel; B, third sub-pixel;

[0100] PS (partition gasket); FPC (flexible printed circuit board); PCB (printed circuit board);

[0101] ZX1, First Centerline; ZX2, Second Centerline;

[0102] X, the first direction; Y, the second direction. Detailed Implementation

[0103] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0104] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0105] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0106] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0107] This disclosure provides an array substrate, as shown in Figures 1-27. The array substrate has a display area AA and a non-display area NAA. The array substrate may include a substrate 1, a driving circuit layer group 2, a first electrode 3, a conductive auxiliary layer 4, a second insulating layer 5, and a second electrode 6. The driving circuit layer group 2 is disposed on one side of the substrate 1. The driving circuit layer group 2 may include a gate layer 21 and a conductor layer 24. The gate layer 21 may include a gate 211 and a gate line 212. The gate line 212 extends along a first direction X. The conductor layer 24 may include data lines 241. The data lines 241 extend along a second direction Y. Two adjacent gate lines 212 form a gate line group 212Z. Multiple data lines 241 and multiple gate line groups 212Z are intersected to define the display area AA as multiple pixel areas PXQ. The second direction Y intersects with the first direction X. The driving circuit layer group 2 may include multiple transistors, including a first transistor T1 and a second transistor T2. The first electrode 3, conductive auxiliary layer 4, second insulating layer 5, and second electrode 6 are also present. The auxiliary layer 4 and the second electrode 6 are disposed on the side of the driving circuit layer group 2 away from the substrate 1; the conductive auxiliary layer 4 may include a first auxiliary trace 41, which is electrically connected to the first electrode 3; a second insulating layer 5 is disposed between the second electrode 6 and the first electrode 3, and two adjacent second electrodes 6 are a first pixel electrode 6a and a second pixel electrode 6b. The first pixel electrode 6a may include a first electrode portion 6a1 and a first lead portion 6a2 connected to each other, and the second pixel electrode 6b may include a second electrode portion 6b1 and a second lead portion 6b2 connected to each other. The first lead portion 6a2 is connected to the first transistor T1, and the first transistor T1 and the first electrode portion 6a1 are located in the same pixel column PXL. The second lead portion 6b2 is connected to the second transistor T2, and the second electrode portion 6b1 and the second transistor T2 are located in adjacent pixel columns PXL respectively. The orthographic projection of the first auxiliary trace 41 on the substrate 1 does not overlap with the orthographic projections of the first lead portion 6a2 and the second lead portion 6b2 on the substrate 1.

[0108] The array substrate disclosed herein has, on the one hand, a first auxiliary trace 41 connected to a first electrode 3. The resistance of the first electrode 3 can be reduced by the first auxiliary trace 41, thereby improving the recovery capability and uniformity of the first electrode 3 and improving high-frequency Excel Crosstalk and low-frequency Flicker defects. On the other hand, it can avoid the defect of sub-pixel PX not being displayed due to the first lead portion 6a2 and the second lead portion 6b2 being broken due to the protrusion formed by crossing the first auxiliary trace 41, or it can avoid the first auxiliary trace 41 being broken due to the protrusion formed by crossing the first lead portion 6a2 and the second lead portion 6b2, thus affecting the resistance of the first electrode 3.

[0109] Referring to FIG1, the array substrate may include a display area AA (Active Area) and a non-display area NAA. Specifically, the non-display area NAA may surround the outer periphery of the display area AA. The array substrate may be rectangular, and the display area AA may be rectangular, such that the non-display area NAA is a rectangular frame.

[0110] Referring to FIG2, the array substrate may include a substrate 1, a driving circuit layer group 2, a first electrode 3, a conductive auxiliary layer 4, a second insulating layer 5, and a second electrode 6. The material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layer material may be any of the aforementioned materials. Of course, the substrate 1 may also be a single layer, and may be any of the aforementioned materials.

[0111] The driving circuit layer group 2 may include multiple transistors arranged in an array. Specifically, referring to Figures 2 and 4, the driving circuit layer group 2 may include a gate layer 21, a gate insulating layer 22, an active layer 23, a conductor layer 24, and a first insulating layer 25. The gate layer 21 is disposed on one side of the substrate 1. The gate layer 21 may include a gate 211, a gate line 212, and a capacitance compensation part 213. The capacitance compensation part 213 is connected to the gate line 212, and the gate line 212 is connected to the gate 211. Alternatively, a portion of the gate line 212 may be reused as the gate 211. The gate line 212 may extend along a first direction X. The gate layer 21 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate layer 21 may be a single-layer film or a multilayer film.

[0112] A gate insulating layer 22 is disposed on the side of the gate layer 21 facing away from the substrate 1. The gate insulating layer 22 may include silicon compounds, metal oxides, or the like. For example, the gate insulating layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used individually or in combination. The gate insulating layer 22 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stacked structure of different materials. The gate insulating layer 22 may be disposed only on the side of the gate layer 21 facing away from the substrate 1; of course, the gate insulating layer 22 may also be disposed over the entire surface of the substrate 1.

[0113] Referring to Figures 2 and 5, the active layer 23 is disposed on the side of the gate insulating layer 22 facing away from the substrate 1. The active layer 23 may include polycrystalline silicon. However, this disclosure is not limited thereto, and the active layer 23 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor, etc. The active layer 23 may include a first conductive connection portion 231, a channel portion 232, and a second conductive connection portion 233 connected in sequence. For example, the first conductive connection portion 231 and the second conductive connection portion 233 are connected to opposite ends of the channel portion 232.

[0114] Referring to Figures 2, 6, and 7, the conductor layer 24 is disposed on the side of the active layer 23 facing away from the substrate 1. The conductor layer 24 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The conductor layer 24 may be a single-layer film or a multilayer film. For example, the conductor layer 24 may be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu. The conductor layer 24 may include a data line 241, a source 242, and a drain 243. The source 242 may be part of the data line 241, or the source 242 may be connected to the data line 241. The source electrode 242 is connected to the first conductive connection portion 231, and the drain electrode 243 is connected to the second conductive connection portion 233. The data line 241 extends along the second direction Y. The orthographic projection of the drain electrode 243 on the substrate 1 overlaps with the orthographic projection of the capacitor compensation portion 213 on the substrate 1. A capacitor can be formed through the drain electrode 243 and the capacitor compensation portion 213 to compensate for the storage capacitor and avoid capacitance inconsistency caused by process fluctuations.

[0115] Referring to Figures 2 and 8, a first insulating layer 25 is provided on the side of the conductor layer 24 facing away from the substrate 1. The first insulating layer 25 may include an inorganic layer 25a. The material of the inorganic layer 25a may be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0116] The first insulating layer 25 may also include an organic layer 25b, which may be made of organic materials, such as polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. Of course, the first insulating layer 25 may consist only of the organic layer 25b, or it may include two inorganic layers.

[0117] The channel 232, gate 211, source 242 and drain 243 constitute a thin-film transistor (TFT), that is, the transistor is a thin-film transistor (TFT).

[0118] It should be noted that the thin-film transistor TFT described in this specification is a top-gate type thin-film transistor TFT. In other exemplary embodiments of this disclosure, the thin-film transistor TFT can also be a bottom-gate type or a dual-gate type (two gates 211), and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistor TFTs with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 242" and the "drain 243" are sometimes interchanged. Therefore, in this specification, the "source 242" and the "drain 243" can be interchanged.

[0119] Furthermore, the transistor described in this specification is a thin-film transistor (TFT). The following description uses a thin-film transistor (TFT) as an example of a transistor. In other exemplary embodiments of this disclosure, the transistor may also be other conventional transistors.

[0120] A first electrode 3 is disposed on the side of the driving circuit layer group 2 facing away from the substrate 1. Specifically, the first electrode 3 is disposed on the side of the first insulating layer 25 facing away from the substrate 1. The material of the first electrode 3 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first electrode 3 may be a common electrode.

[0121] Referring to Figures 2, 9, and 10, a conductive auxiliary layer 4 is provided on the side of the first electrode 3 facing away from the substrate 1. The conductive auxiliary layer 4 can be made of metal. The conductive auxiliary layer 4 may include a first auxiliary trace 41 and a second auxiliary trace 42.

[0122] A second insulating layer 5 is provided on the side of the conductive auxiliary layer 4 facing away from the substrate 1. The material of the second insulating layer 5 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0123] Referring to Figures 2, 11, and 12, a second electrode 6 is disposed on the side of the second insulating layer 5 facing away from the substrate 1. The material of the second electrode 6 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. A first via 251 is disposed on the first insulating layer 25, and a second via 51 communicating with the first via 251 is disposed on the second insulating layer 5. The second electrode 6 may be a pixel electrode. The second electrode 6 can be connected to the drain 243 through the second via 51 on the second insulating layer 5 and the first via 251 on the first insulating layer 25. A display driving signal can be input to the second electrode 6 through the drain 243.

[0124] Of course, in some other exemplary embodiments of this disclosure, the second electrode 6 may be disposed on the side of the first insulating layer 25 away from the substrate 1. The second electrode 6 may be connected to the drain 243 through the first via 251 on the first insulating layer 25, and a display driving signal may be input to the second electrode 6 through the drain 243. A second insulating layer 5 is disposed on the side of the second electrode 6 away from the substrate 1, a first electrode 3 is disposed on the side of the second insulating layer 5 away from the substrate 1, and a conductive auxiliary layer 4 is disposed on the side of the first electrode 3 away from the substrate 1; alternatively, the conductive auxiliary layer 4 may be disposed on the side of the first electrode 3 close to the substrate 1.

[0125] Referring to Figure 3, the array substrate may include multiple pixels PX arranged in an array. Each pixel PX may include three sub-pixels of different colors: a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. Specifically, each pixel PX may include the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B arranged sequentially along a first direction X. More specifically, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged periodically along the first direction X to form a pixel row PXH. In other words, multiple pixels PX are arranged along the first direction X to form a pixel row PXH, or, within each pixel row PXH, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged periodically along the first direction X. Multiple sub-pixels PX are arranged sequentially along a second direction Y to form a pixel column PXL. For example, multiple first sub-pixels R, multiple second sub-pixels G, and multiple third sub-pixels B are arranged sequentially along the second direction Y to form a pixel column PXL.

[0126] The first sub-pixel R can be defined by the first pixel electrode, the second sub-pixel G can be defined by the second pixel electrode, and the third sub-pixel B can be defined by the third pixel electrode.

[0127] Referring to Figures 3 and 11, multiple gate lines 212 are used to transmit scan signals. The scanning direction of the gate lines 212 is from the nth row pixel PX to the (n+1)th row pixel PX, where n is an integer greater than or equal to 1. The gate lines 212 can extend along a first direction X, and multiple gate lines 212 can be arranged along a second direction Y to transmit scan signals to different sub-pixels. Two adjacent gate lines 212 form a gate line group 212Z.

[0128] Data lines 241 can extend along the second direction Y, and multiple data lines 241 can be arranged along the first direction X. Multiple data lines 241 intersect with multiple gate line groups 212Z to define the display area AA as multiple pixel regions PXQ. Every two sub-pixels PX are confined within one pixel region PXQ, meaning every two second electrodes 6 are located within the same pixel region PXQ. This results in two columns of sub-pixels PX of different colors being provided between every two adjacent data lines 241, i.e., two columns of pixels PXL being provided between every two adjacent data lines 241. Two gate lines 212 are provided between two adjacent rows of pixels PXH.

[0129] Two sub-pixels PX located within the same pixel region PXQ are connected to the same data line 241 and driven through the same data line 241. Two sub-pixels PX located within the same pixel region PXQ are connected to different gate lines 212 and driven through two different gate lines 212. The two gate lines 212 connected to the same pixel region PXQ are parallel to each other and located on opposite sides of the pixel region PXQ. This structure is a dual-gate structure. Using a dual-gate liquid crystal display panel increases the number of gate lines 212 on the array substrate, thereby reducing the number of data lines 241, and thus reducing the number of source driver ICs, thereby lowering costs.

[0130] The resolution of the array substrate using a dual-gate structure can be improved from FHD (1920×1080) to QD (3840x2160), and the refresh rate can be increased from 60Hz to 120Hz and above. This significantly reduces the pixel PX charging time from 7.7μs (Dual Gate FHD 60Hz) to 2.6μs~1.8μs (Dual Gate QD 120Hz~165Hz). The significant reduction in pixel PX charging time makes pixel PX charging very challenging. The common electrode (first electrode 3) is pulled by the coupling of the gate line 212 and the data line 241 signal line. If the voltage of the common electrode does not recover to the set value at the end of charging, the pixel PX voltage will change, and the grayscale display will be abnormal. Therefore, improving the recovery capability and uniformity of the common electrode is the key to ensuring the product quality of the dual-gate structure.

[0131] The first auxiliary trace 41 is directly connected to the first electrode 3 (common electrode). The resistance of the first electrode 3 can be reduced through the first auxiliary trace 41, thereby improving the recovery capability and uniformity of the first electrode 3, and improving high-frequency Excel Crosstalk and low-frequency Flicker.

[0132] Referring to Figures 11 and 12, two adjacent second electrodes 6 are first pixel electrodes 6a and second pixel electrodes 6b. Specifically, two second electrodes 6 located within the same pixel region PXQ are first pixel electrodes 6a and second pixel electrodes 6b. The first pixel electrode 6a may include a first electrode portion 6a1 and a first lead portion 6a2 connected to each other. The second pixel electrode 6b may include a second electrode portion 6b1 and a second lead portion 6b2 connected to each other. The first lead portion 6a2 is connected to a first transistor T1. The first transistor T1 and the first electrode portion 6a1 are located in the same pixel column PXL. The second lead portion 6b2 is connected to a second transistor T2. The second electrode portion 6b1 and the second transistor T2 are located in adjacent pixel columns PXL, respectively.

[0133] The second insulating layer 5 is an inorganic material, and its planarization effect is weak, as is its buffering effect on the ramping of the second electrode 6. The widths of the first lead portion 6a2 and the second lead portion 6b2 are small, making them prone to breakage during ramping. This would prevent the first pixel electrode 6a and the second pixel electrode 6b from conducting and thus prevent display driving. The orthographic projection of the first auxiliary trace 41 on the substrate 1 does not overlap with the orthographic projections of the first lead portion 6a2 and the second lead portion 6b2 on the substrate 1, thus avoiding the defect of the sub-pixel PX not being displayed due to the first lead portion 6a2 and the second lead portion 6b2 breaking because they cross the protrusion formed by the first auxiliary trace 41.

[0134] In some exemplary embodiments of this disclosure, the first pixel electrode 6a and the second pixel electrode 6b are connected to the same data line 241, such that the length of the second lead portion 6b2 of the second pixel electrode 6b, which is away from the data line 241, is greater than the length of the first lead portion 6a2, so that the first lead portion 6a2 and the second lead portion 6b2 can be connected to the same data line 241.

[0135] Alternatively, the orthographic projection of the second electrode 6 on the substrate 1 may overlap with the orthographic projection of the first auxiliary trace 41 near the corner of the first auxiliary trace 41 on the substrate 1, while the other parts of the orthographic projection of the second electrode 6 on the substrate 1 may not overlap with the orthographic projection of the first auxiliary trace 41 on the substrate 1. This can mitigate or even avoid the defect of the sub-pixel PX being unable to be displayed due to the second electrode 6 breaking due to the second electrode 6 crossing the first auxiliary trace 41 and forming a ramp.

[0136] Referring to Figures 9-11, the first auxiliary trace 41 extends along the second direction Y, which can avoid the first auxiliary trace 41 from overlapping with the second electrode 6, thereby avoiding the second electrode 6 from breaking due to the second electrode 6 crossing the first auxiliary trace 41 and causing the sub-pixel PX to be unable to be displayed.

[0137] The orthographic projection of the first auxiliary trace 41 on the substrate 1 at least partially overlaps with the orthographic projection of the data line 241 on the substrate 1. For example, the edge of the orthographic projection of the first auxiliary trace 41 on the substrate 1 may coincide with the edge of the orthographic projection of the data line 241 on the substrate 1. Alternatively, the orthographic projection of the first auxiliary trace 41 on the substrate 1 may cover and be larger than the orthographic projection of the data line 241 on the substrate 1. Or, the orthographic projection of the data line 241 on the substrate 1 may cover and be larger than the orthographic projection of the first auxiliary trace 41 on the substrate 1.

[0138] Of course, in some other example embodiments of this disclosure, a portion of the orthographic projection of the first auxiliary trace 41 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the data line 241 on the substrate 1, that is, the first auxiliary trace 41 may be slightly offset to both sides relative to the data line 241 in the first direction X.

[0139] Specifically, the shape of the first auxiliary trace 41 can be basically the same as the shape of the data line 241. The line width of the first auxiliary trace 41 can be slightly wider than the line width of the data line 241, or the line width of the data line 241 can be slightly wider than the line width of the first auxiliary trace 41. Specifically, the ratio of the line width of the first auxiliary trace 41 to the line width of the data line 241 can be greater than or equal to 0.9 and less than or equal to 3. For example, the ratio of the line width of the first auxiliary trace 41 to the line width of the data line 241 can be 0.92, 0.95, 0.97, 1, 1.03, 1.05, 1.08, 1.3, 1.5, 1.8, 2, 2.2, 2.5, 2.7, etc.

[0140] This configuration ensures that the second electrode 6 (pixel PX electrode) formed subsequently does not need to cross the first auxiliary trace 41 when connected to the corresponding data line 241.

[0141] Alternatively, referring to Figures 2 and 13, the array substrate may further include a spacer portion PS. The spacer portion PS is disposed on the side of the second insulating layer 5 away from the substrate 1. The orthographic projection of the spacer portion PS on the substrate 1 does not overlap with the orthographic projection of the first auxiliary trace 41 on the substrate 1. Since the first auxiliary trace 41 causes unevenness on the side of the second insulating layer 5 away from the substrate 1, the height of the second insulating layer 5 will be higher at the location where the first auxiliary trace 41 is set. The spacer portion PS is not disposed directly above the first auxiliary trace 41, so as to avoid the abnormal shape and inconsistent height of the spacer portion PS caused by the spacer portion PS being formed on the uneven substrate layer, thereby avoiding uneven display caused by uneven gap between the array substrate and the color filter substrate.

[0142] In this example embodiment, three pixel regions PXQ arranged along the first direction X are grouped together, and a first auxiliary trace 41 is provided between two adjacent groups of pixel regions PXQ.

[0143] Of course, in some other example embodiments of this disclosure, a first auxiliary trace 41 may be provided in a set of pixel regions PXQ.

[0144] For example, as shown in FIG3, six second electrodes 6 are provided in the three pixel regions PXQ. The six second electrodes 6 form two pixels PX. Therefore, the two pixels PX are a pixel group, and the two pixels PX are the first pixel PX1 and the second pixel PX2. That is, a pixel group includes a first sub-pixel R, a second sub-pixel G, a third sub-pixel B, and a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B arranged sequentially along the first direction X.

[0145] A data line 241 can be provided on the side of the first pixel PX1 away from the second pixel PX2, a data line 241 can be provided between the second sub-pixel G and the third sub-pixel B of the first pixel PX1, and a data line 241 can be provided between the first sub-pixel R and the second sub-pixel G of the second pixel PX2.

[0146] The first auxiliary trace 41 can be located between the adjacent second sub-pixel G and the third sub-pixel B in the first pixel PX1, or between the adjacent first sub-pixel R and the second sub-pixel G in the second pixel PX2, or between two adjacent pixel groups.

[0147] Since it is necessary to ensure the setting density of the spacer PS to ensure the support effect of the spacer PS, one of the above three positions can generally be selected; of course, any two of the above three positions can also be selected. In addition, in general, multiple first auxiliary lines 41 can be evenly arranged. Of course, in some other example embodiments of this disclosure, multiple first auxiliary lines 41 can be unevenly arranged. For example, the positions of the first auxiliary lines 41 can be different in different pixel groups.

[0148] The first auxiliary trace 41 can essentially run through the entire array substrate. The first auxiliary trace 41 can be directly connected to the common signal line, transmitting the common signal to the first electrode 3, thus allowing the first electrode 3 and the first auxiliary trace 41 to jointly transmit the common signal. Alternatively, the first electrode 3 can be directly connected to the common signal line, transmitting the common signal to the first auxiliary trace 41, similarly allowing the first electrode 3 and the first auxiliary trace 41 to jointly transmit the common signal. The number of first auxiliary traces 41 is limited.

[0149] Referring to Figures 28 and 29, in Figure 29, the virtual extension line 431 is represented by a bold black dashed line. The conductive auxiliary layer 4 may also include a third auxiliary trace 43. The orthographic projection of the third auxiliary trace 43 on the substrate 1 is located between the orthographic projections of two adjacent second electrodes 6 on the substrate 1. The third auxiliary trace 43 is disconnected, and the virtual extension line 431 of the third auxiliary trace 43 intersects with the second lead portion 6b2. Specifically, the orthographic projection of each segment of the third auxiliary trace 43 on the substrate 1 is located between the orthographic projections of two adjacent second electrode portions 6b1 on the substrate 1. In the second direction Y, each segment of the third auxiliary trace 43 does not protrude from the second electrode portion 6b1. This arrangement increases the number of auxiliary traces, further reducing the resistance of the first electrode 3 and reducing power consumption.

[0150] Furthermore, if the array substrate using a dual-gate structure is not charged sufficiently, it is prone to defects such as mixed colors and vertical stripes. Referring to the sky blue image shown in Figure 14, the dashed circle represents sufficient pre-charge and the pixel PX is brighter; the solid circle represents insufficient pre-charge and the pixel PX is darker. This alternation of bright and dark displays macroscopically manifests as vertical stripes.

[0151] In some exemplary embodiments of this disclosure, referring to Figures 3 and 11, in the second direction Y, the first transistor T1 and the second transistor T2 are each located on opposite sides of the pixel region PXQ, that is, the first transistor T1 is located on one side of the pixel region PXQ in the second direction Y, and the second transistor T2 is located on the opposite side of the pixel region PXQ in the second direction Y; the first transistor T1 and the second transistor T2 are not located within the pixel region PXQ.

[0152] Referring to Figures 3 and 6, the orthographic projection of the thin-film transistor (TFT) on the substrate 1 is located between the orthographic projections of each pair of adjacent gate lines 212 on the substrate 1. In other words, the orthographic projection of the TFT on the substrate 1 is located inside the orthographic projection of each pair of adjacent gate lines 212 on the substrate 1. This eliminates the need for a winding structure for the gate lines 212, allowing them to be set as straight lines extending along the first direction X. As a result, the impedance of the straight gate lines 212 can be reduced by 10% to 20% compared to the winding structure gate lines 212. This reduces the gate delay synchronically, effectively increasing the current of the thin-film transistor TFT and improving the charging rate, thereby avoiding vertical stripe problems caused by charging differences in special images such as color mixing.

[0153] Specifically, the orthographic projection of the active layer 23 on the substrate 1 lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the active layer 23 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1; the orthographic projection of the drain 243 on the substrate 1 lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the drain 243 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1; the orthographic projection of the source 242 on the substrate 1 also lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the source 242 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1. Multiple gates 211 are connected to one gate line 212, and the multiple gates 211 are located between two adjacent gate lines 212, meaning the gates 211 are located inside the two adjacent gate lines 212.

[0154] With this configuration, as shown in Figures 11 and 12, the second electrode 6 (pixel PX electrode) of each sub-pixel PX does not need to be designed to avoid the thin-film transistor TFT, making the edges of the second electrode 6 of each sub-pixel PX relatively flat, avoiding electric field disturbance at the junction, and thus avoiding trace mura defects; moreover, the aperture ratio is larger, for example, the aperture ratio can be improved by 2% to 5% compared with the prior art.

[0155] Alternatively, as shown in FIG6, the multiple thin-film transistors (TFTs) may include multiple groups of thin-film transistor groups (TFTZ). Each group of thin-film transistors (TFTZ) may include two thin-film transistors (TFTs). The two thin-film transistors (TFTs) in the same group are located between two adjacent gate lines 212 in the same group. For example, the two thin-film transistors (TFTs) in the same group may be a first thin-film transistor (TFT1) and a second thin-film transistor (TFT2). The two adjacent gate lines 212 in the same group may be a first gate line 212a and a second gate line 212b. The first thin-film transistor (TFT1) is located between the first gate line 212a and the second gate line 212b, and the second thin-film transistor (TFT2) is also located between the first gate line 212a and the second gate line 212b. Two thin-film transistors (TFTs) of the same group are connected to opposite sides of the same data line 241 in the first direction X, that is, two thin-film transistors (TFTs) of the same group are connected to the same data line 241 but are not located on the same side of the data line 241; two thin-film transistors (TFTs) of the same group are staggered in the second direction Y. For example, the first thin-film transistor TFT1 can be set closer to the first gate line 212a, and the second thin-film transistor TFT2 can be set closer to the second gate line 212b; of course, it is also possible that the first thin-film transistor TFT1 is set closer to the second gate line 212b, and the second thin-film transistor TFT2 is set closer to the first gate line 212a.

[0156] Specifically, the two gates 211 of the two thin-film transistors (TFTs) in the same group are connected one-to-one to two adjacent gate lines 212 in the same group. For example, the gate 211 of the first thin-film transistor TFT1 can be connected to the first gate line 212a; the gate 211 of the second thin-film transistor TFT2 can be connected to the second gate line 212b.

[0157] In addition, the two sources 242 of the two thin-film transistor TFTs in the same group are connected to opposite sides of the same data line 241 in the first direction X, and are staggered in the second direction Y. For example, the source 242 of the first thin-film transistor TFT1 can be set closer to the first gate line 212a, and the source 242 of the second thin-film transistor TFT2 can be set closer to the second gate line 212b; of course, it is also possible that the source 242 of the first thin-film transistor TFT1 is set closer to the second gate line 212b, and the source 242 of the second thin-film transistor TFT is set closer to the first gate line 212a.

[0158] In some exemplary embodiments of this disclosure, referring to Figures 6-8, the drain 243 may include an electrode block 2431, a connecting block 2432, and a compensation block 2433 connected sequentially in the first direction X. The electrode block 2431, connecting block 2432, and compensation block 2433 are all solid structures without any intermediate hollow structures. The electrode block 2431 is connected to the second conductive connection portion 233. The second electrode 6 is connected to the connecting block 2432 through the second via 51 and the first via 251. The electrode block 2431 and the compensation block 2433 are offset in the second direction Y, meaning they are not on the same straight line in the second direction Y. Specifically, in the second direction Y, the distance between the electrode block 2431 and the gate line 212 is less than the distance between the compensation block 2433 and the gate line 212, i.e., the distance between the compensation block 2433 and the gate line 212 is less than the distance between the compensation block 2433 and the gate line 212. The larger distance between 212 is to meet the requirements of process margin (i.e., the range of process parameter fluctuations); the smaller distance between electrode block 2431 and gate line 212 is to ensure the connection between electrode block 2431 and second conductive connection part 233. In addition, electrode block 2431 needs to be positioned opposite to source 242, so that the center line of electrode block 2431 extending along the first direction X coincides with the center line of source 242 extending along the first direction X, so as to ensure the functional effect of thin film transistor.

[0159] To ensure that the source 242 and the electrode block 2431 are positioned opposite each other, the size of the source 242 in the second direction Y can be set to be larger than the size of the electrode block 2431 in the second direction Y, resulting in a larger size of the source 242 in the second direction Y. In the second direction Y, the orthographic projection of the portion of the source 242 extending beyond the active layer 23 on the substrate 1 overlaps with the orthographic projection of the gate line 212 on the substrate 1, which can reduce the occupied area of ​​the source 242, thereby compressing the occupied area of ​​the thin film transistor and improving the aperture ratio.

[0160] The width of the connecting block 2432 is greater than the width of the electrode block 2431 and the compensation block 2433, that is, the width of the connecting block 2432 is greater than the width of the electrode block 2431 and also greater than the width of the compensation block 2433, so as to ensure the area of ​​the second via 51 and the first via 251, thereby ensuring the connection strength and connection area between the second electrode 6 and the connecting block 2432.

[0161] The orthographic projection of the compensation block 2433 on the substrate 1 overlaps with the orthographic projection of the capacitor compensation part 213 on the substrate 1, forming a capacitor and performing capacitor compensation.

[0162] In some exemplary embodiments of this disclosure, referring to Figures 6 and 7, the data line 241 is configured as a strip extending along the second direction Y. Specifically, the data line 241 is configured as a zigzag line extending along the second direction Y, with the bend position designed to match the structure of the second electrode 6. This means that the data line 241 is generally configured as a straight line extending along the second direction Y, rather than the "bow"-shaped structure in the related art, thereby reducing the length of the data line 241 and significantly reducing its impedance. For example, the impedance of the data line 241 can be reduced by 50%, thereby effectively improving the charging rate and avoiding vertical stripe problems caused by charging differences in special images such as color mixing.

[0163] Referring to Figures 3, 6, and 7, the conductor layer 24 may further include a signal trace 244, which can be used as a touch trace. The signal trace 244 is configured as a strip extending along the second direction Y. Specifically, the signal trace 244 is configured as a zigzag line extending along the second direction Y, with the bend position to match the structure of the second electrode 6. This means that the signal trace 244 is generally configured as a straight line extending along the second direction Y, rather than the "bow"-shaped structure in related technologies, thereby reducing the length of the signal trace 244 and significantly reducing its impedance. For example, the impedance of the signal trace 244 can be reduced by 50%, thereby effectively improving touch performance.

[0164] A portion of the signal trace 244 is located within the pixel region PXQ. For example, the signal trace 244 and the data line 241 can be arranged in a basically parallel manner. The signal trace 244 and the data line 241 are arranged alternately, that is, there is a signal trace 244 between two adjacent data lines 241 and a data line 241 between two adjacent signal traces 244, so that there are also two pixel columns PXL between two adjacent signal traces 244.

[0165] Specifically, as shown in FIG3, a signal trace 244 is provided between the first sub-pixel R and the second sub-pixel G of the first pixel PX1, a signal trace 244 is provided between the third sub-pixel B of the first pixel PX1 and the first sub-pixel R of the second pixel PX2, and a signal trace 244 is provided between the second sub-pixel G of the second pixel PX2 and the third sub-pixel B of the second pixel PX2.

[0166] In this case, the first electrode 3 can be reused as a touch electrode; that is, when implementing the display function, the first electrode 3 is used as a common electrode; when implementing the touch function, the first electrode 3 is used as a touch electrode. Of course, the signal trace 244 can also be used as a common electrode line.

[0167] Referring to Figures 11 and 15, the first electrode 3 can be connected to the signal trace 244 through the third via 252 on the first insulating layer 25, so that when the first electrode 3 is used as a touch electrode, touch signals can be transmitted through the signal trace 244. The orthogonal projection of the third via 252 on the substrate 1 is located between the orthogonal projections of two adjacent transistors on the substrate 1. Specifically, the orthogonal projection of the third via 252 on the substrate 1 is located between two adjacent data lines 241, and between the orthogonal projections of two adjacent transistors connected to different data lines 241 on the substrate 1. That is, the arrangement of the gate line 212 and the thin-film transistor TFT can accommodate the third via 252 connecting the signal trace 244 to the first electrode 3, so that the data line 241 and the signal trace 244 do not need to be bent into an "arch" shape, thereby reducing the impedance of the signal trace 244 by 50%, which can effectively improve the touch performance, and the impedance of the data line 241 can be reduced by 50%, which can effectively improve the charging rate.

[0168] Of course, in some other exemplary embodiments of this disclosure, the signal trace 244 may also be a dummy trace. A dummy trace may not be powered. The dummy trace is only set up to ensure the consistency of the process. In this case, the signal trace 244 does not need to be connected to the first electrode 3.

[0169] Referring to FIG11, the orthographic projection of the second lead portion 6b2 on the substrate 1 overlaps with the orthographic projection of the signal trace 244 on the substrate 1, that is, the second lead portion 6b2 needs to cross the signal trace 244; the orthographic projection of the first lead portion 6a2 on the substrate 1 does not overlap with the orthographic projection of the signal trace 244 on the substrate 1, and the first lead portion 6a2 does not need to cross the signal trace 244.

[0170] Referring to FIG16, the data line 241 is not only set in the display area AA, but also extends from the display area AA to the fanout area Fanout, passes through the fanout area Fanout to the bonding area BOD, and connects to the bonding pin of the bonding area BOD, so as to achieve bonding connection with the driver chip IC in the bonding area BOD.

[0171] One, two, or more driver chip ICs can be set in the bonding area BOD. One driver chip IC is connected to a portion of the data lines 241 in the display area AA. Since the length of the driver chip IC in the first direction X is less than the length of the display area AA connected to it in the first direction X, some data lines 241 need to be bent to extend to the bonding pin, which makes the length of these data lines 241 longer. Moreover, the length of the data lines 241 increases with the increase of the distance from the first center line ZX1 in the first direction X, so that the lengths of multiple data lines 241 can be different. The first center line ZX1 is the center line of a portion of the bonding area BOD used to bond the driver chip IC, extending along the second direction Y. It can also be said that the first center line ZX1 is the center line of the driver chip IC extending in the second direction Y.

[0172] The resistance of data line 241 increases with the increase of the distance from the first center line ZX1 in the first direction X, resulting in poor uniformity of the resistance of data line 241. This leads to a large difference in the charging rate of sub-pixels PX in different columns, resulting in uneven display color of sub-pixels PX in different columns.

[0173] In some exemplary embodiments of this disclosure, referring to FIG17, at least a portion of the data line 241 may include a first portion 2411 and a second portion 2412, the first portion 2411 being connected to the second portion 2412, the width of the second portion 2412 being greater than the width of the first portion 2411, such that the resistance of the second portion 2412 is less than the resistance of the first portion 2411.

[0174] The orthographic projection of the second portion 2412 on the substrate 1 lies within the region between the mutually distant edges of the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. For example, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the orthographic projection of the gate line 212 on the substrate 1. Specifically, a portion of the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may lie within the orthographic projection of the gate line 212 on the substrate 1. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the region between the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the orthographic projection of the gate line 212 on the substrate 1, and at least partially overlap with the region between the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. With this configuration, even if the width of the data cable 241 is increased, the opening ratio will not be affected; moreover, increasing the width of the data cable 241 at the ramp point prevents the data cable 241 from breaking.

[0175] Because the longer the data line 241 is farther from the first center line ZX1, the greater its resistance, and the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance; the number of second parts 2412 increases with the distance from the first center line ZX1 in the first direction X, that is, the data line 241 farther from the first center line ZX1 includes more second parts 2412, and the data line 241 closer to the first center line ZX1 includes fewer second parts 2412; the more second parts 2412 there are, the more the resistance of the data line 241 decreases, which makes the resistance of the data line 241 farther from the first center line ZX1 decrease more; the more second parts 2412 there are, the less the resistance of the data line 241 decreases, which makes the resistance of the data line 241 closer to the first center line ZX1 decrease less; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and thus the display color of sub-pixels PX in different columns is more uniform, achieving the purpose of uniform image quality.

[0176] It should be noted that "the number of second parts 2412 increases with the increase of distance from the first center line ZX1 in the first direction X" means that the number of second parts 2412 generally increases with the distance from the first center line ZX1 in the first direction X. Specifically, the second part 2412 may not be set on some data lines 241. For example, since the length of one, two, or more data lines 241 closest to the first center line ZX1 is the shortest and the resistance is the smallest, the second part 2412 may not be set on one, two, or more data lines 241 closest to the first center line ZX1, so that part of the data lines 241 only includes the first part 2411. In addition, since the lengths of two, three, or more adjacent data lines 241 are not much different, the resistances are also not much different. Therefore, the number of second parts 2412 included in two, three, or more adjacent data lines 241 can be the same.

[0177] In some other exemplary embodiments of this disclosure, referring to FIG18, at least a portion of the data line 241 may include a first portion 2411 and a second portion 2412, the first portion 2411 being connected to the second portion 2412, the width of the second portion 2412 being smaller than the width of the first portion 2411, such that the resistance of the second portion 2412 is greater than the resistance of the first portion 2411. The orthographic projection of the second portion 2412 on the substrate 1 at least partially overlaps with the orthographic projection of the gate line 212 on the substrate 1. For example, a portion of the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1, or the orthographic projection of the second portion 2412 on the substrate 1 may be located within the orthographic projection of the gate line 212 on the substrate 1. This configuration can reduce the parasitic capacitance between the data line 241 and the gate line 212, reduce the mutual interference between the data line 241 and the gate line 212, and has no impact on the aperture ratio.

[0178] Because the longer the data line 241 is farther from the first center line ZX1, the greater its resistance, and the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance; the number of second parts 2412 decreases as the distance from the first center line ZX1 in the first direction X increases, that is, the number of second parts 2412 included in the data line 241 farther from the first center line ZX1 is smaller, and the number of second parts 2412 included in the data line 241 closer to the first center line ZX1 is larger; the fewer the number of second parts 2412, the less the resistance of the data line 241 increases, so the resistance of the data line 241 further away from the first center line ZX1 increases less; the more the number of second parts 2412, the more the resistance of the data line 241 increases, so the resistance of the data line 241 closer to the first center line ZX1 increases more; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and the display color of sub-pixels PX in different columns is more uniform, thus achieving the purpose of uniform image quality.

[0179] It should be noted that "the number of second parts 2412 decreases as the distance from the first center line ZX1 in the first direction X increases" means that the number of second parts 2412 generally decreases with increasing distance from the first center line ZX1 in the first direction X. Specifically, second parts 2412 may not be provided on some data lines 241. For example, since the longest and highest resistance of one, two, or more data lines 241 furthest from the first center line ZX1, second parts 2412 may not be provided on these data lines, so that these data lines 241 only include the first part 2411. Furthermore, since the lengths of two, three, or more adjacent data lines 241 are not significantly different, their resistances are also not significantly different. Therefore, the number of second parts 2412 included in two, three, or more adjacent data lines 241 can be the same.

[0180] Alternatively, the connection between the second part 2412 and the first part 2411 can be arc-shaped, so that the second part 2412 and the first part 2411 can be smoothly connected. For example, the connection between the second part 2412 and the first part 2411 can be set as an arc-shaped structure to avoid sharp corners, thereby avoiding sharp corner breakdown defects caused by static electricity (ESD) in the manufacturing process.

[0181] In some other exemplary embodiments of this disclosure, referring to Figures 16 and 19, in Figure 16, the thick solid lines represent the first auxiliary trace 41 and the second auxiliary trace 42, and the thin solid lines represent the data line 241; the conductive auxiliary layer 4 may further include the second auxiliary trace 42, which extends along the second direction Y. Specifically, the second auxiliary trace 42 may be configured as a straight line extending along the second direction Y. The orthographic projection of the second auxiliary trace 42 on the substrate 1 at least partially overlaps with the orthographic projection of the data line 241 on the substrate 1. For example, the orthographic projection of the second auxiliary trace 42 on the substrate 1 may be located within the orthographic projection of the data line 241 on the substrate 1, or a portion of the orthographic projection of the second auxiliary trace 42 on the substrate 1 may overlap with a portion of the orthographic projection of the data line 241 on the substrate 1.

[0182] A fourth via 253 is provided on the first insulating layer 25, which is connected to the data line 241. The second auxiliary trace 42 is connected to the data line 241 through the fourth via 253, so that the second auxiliary trace 42 and the data line 241 are connected in parallel, thereby reducing the resistance of the data line 241 through the second auxiliary trace 42.

[0183] The longer the data line 241 is farther from the first center line ZX1, the greater its resistance; conversely, the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance. The number of second auxiliary traces 42 increases with the distance from the first center line ZX1 in the first direction X. That is, the farther the data line 241 is from the first center line ZX1, the more second auxiliary traces 42 are provided; the closer the data line 241 is to the first center line ZX1, the fewer second auxiliary traces 42 are provided. The more data lines there are, the greater the reduction in resistance after being connected in parallel with data line 241, resulting in a greater reduction in resistance for data line 241 that is further away from the first center line ZX1; the fewer the second auxiliary traces 42 there are, the less the reduction in resistance after being connected in parallel with data line 241, resulting in a less reduction in resistance for data line 241 that is closer to the first center line ZX1; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and the display color of sub-pixels PX in different columns is more uniform, achieving the purpose of uniform image quality.

[0184] It should be noted that "the number of second auxiliary traces 42 increases with the increase of the distance from the first center line ZX1 in the first direction X" means that the number of second auxiliary traces 42 generally increases with the distance from the first center line ZX1 in the first direction X. Specifically, second auxiliary traces 42 can be not set in parallel on some data lines 241. For example, since the length of one, two, or more data lines 241 closest to the first center line ZX1 is the shortest and the resistance is the smallest, second auxiliary traces 42 can be not set in parallel on one, two, or more data lines 241 closest to the first center line ZX1. In addition, since the lengths of some adjacent two, three, or more data lines 241 are not much different, their resistances are also not much different. Therefore, the number of second auxiliary traces 42 connected in parallel on adjacent two, three, or more data lines 241 can be the same.

[0185] Alternatively, referring to FIG19, the orthographic projection of the fourth via 253 on the substrate 1 at least partially overlaps with the orthographic projection of the gate line 212 on the substrate 1. For example, the orthographic projection of the fourth via 253 on the substrate 1 may be located within the orthographic projection of the gate line 212 on the substrate 1, or a portion of the orthographic projection of the fourth via 253 on the substrate 1 may overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1. Therefore, the fourth via 253 is disposed at the intersection of the data line 241 and the gate line 212.

[0186] The first electrode 3, as a common electrode, is essentially a single piece. Since the second auxiliary trace 42 overlaps with the data line 241, it cannot overlap with the first electrode 3. Therefore, an opening needs to be provided on the first electrode 3 to accommodate the second auxiliary trace 42 and prevent it from overlapping with the first electrode 3. Because the fourth via 253 connects to the data line 241, and the fourth via 253 is located at the intersection of the data line 241 and the gate line 212, most of the second auxiliary trace 42 is located between two adjacent gate lines 212. This reduces the extension of the second auxiliary trace 42 to the display area of ​​each sub-pixel, avoiding the need for openings on the first electrode 3 in the display area of ​​each sub-pixel, thus ensuring the overlap area between the first electrode 3 and the second electrode 6; and also facilitating process operations.

[0187] The above mainly describes the specific structure of the display area AA of the array substrate. The following describes the specific structure of the non-display area NAA of the array substrate.

[0188] Referring to Figure 1, the non-display area (NAA) may include a data pad (DP), a data pad opposite (DPO), a gate pad left (GPL), and a gate pad left (GPR). Gate driver on array (GOA) circuits are provided on the gate pad left (GPL) and gate pad right (GPR). The gate pad left (GPL) and gate pad right (GPR) are positioned opposite each other in the first direction X. The gate pad left (GPL) generally corresponds to the coverage area of ​​the left bezel, and the gate pad right (GPR) generally corresponds to the coverage area of ​​the right bezel. The data pad side (DP) generally corresponds to the coverage area of ​​the bottom bezel. The data pad side (DP) and the data pad opposite (DPO) are positioned opposite each other in the second direction Y. The data pad opposite (DPO) generally corresponds to the coverage area of ​​the top bezel.

[0189] The data bonding side DP can include a fanout area and a bonding area BOD. The display area AA and the bonding area BOD are connected on opposite sides of the fanout area in the second direction Y. That is, the fanout area is connected between the display area AA and the bonding area BOD. Specifically, the fanout area is connected to the display area AA, and the bonding area BOD is connected to the side of the fanout area away from the display area AA. The bonding area BOD is provided with multiple bonding pins. Some bonding pins are used to bond the driver chip IC, and other bonding pins are used to bond the flexible circuit board FPC. Various traces are provided in the fanout area.

[0190] A printed circuit board (PCB) is bonded to the end of the flexible circuit board (FPC) away from the array substrate. The flexible circuit board (FPC) can be bent so that the PCB is located on the side of the array substrate away from the color filter substrate.

[0191] In this example embodiment, referring to Figures 20 and 21, the fanout area may include a first fanout area Fanout1, the binding area BOD may include a first sub-binding area BOD1, and the first sub-binding area BOD1 may include an invalid pin area WX. The invalid pin area WX is used to set invalid pins of the driver chip IC. Invalid pins are pins that do not need to be connected to the traces. Since the invalid pin area WX is set with invalid pins of the driver chip IC, the number of traces led out from the first sub-binding area BOD1 is small. However, the traces led out from the first sub-binding area BOD1 need to be connected to the display area AA through the first fanout area Fanout1. This results in the first fanout area Fanout1, which is set opposite to the first sub-binding area BOD1 in the second direction Y, forming a large area of ​​blank space, especially the area opposite to the invalid pin area WX.

[0192] Referring to Figures 21, 22, and 23, the array substrate may further include a first trace group 7, which is located in the first fanout area Fanout1. The first trace group 7 is connected between the display area AA and the first sub-binding area BOD1. That is, the trace introduced into the first sub-binding area BOD1 is the first trace group 7, and the first trace group 7 is connected to the display area AA.

[0193] The first trace group 7 may include multiple first traces 71 arranged in parallel, that is, the first trace group 7 may include multiple first traces 71 arranged in basically parallel; the first trace 71 may include a trace portion 711 and a compensation portion 712. The compensation portion 712 may include at least two trace segments 712a arranged at a set angle. The compensation portion 712 is arranged opposite to the invalid pin area WX, that is, the compensation portion 712 is arranged in the blank area opposite to the invalid pin area WX, so that the first trace group 7 occupies an area of ​​the first fanout area Fanout1 greater than or equal to 90%. For example, the area occupied by the first trace group 7 in the first fanout area Fanout1 may be 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, or 100%.

[0194] Because the length of the driver chip IC in the first direction X is less than the length of the display area AA in the first direction X, the part of the trace directly opposite the driver chip IC is shorter and has lower resistance, while the part of the trace not directly opposite the driver chip IC is longer and has higher resistance. This results in a large difference in the impedance of the traces, which can easily lead to problems such as displaying grayscale blocks or solid color vertical stripes.

[0195] In this disclosure, the first trace 71 of the first trace group 7 in the first fanout area Fanout1 may include a trace portion 711 and a compensation portion 712. The compensation portion 712 can increase the length of the first trace 71, thereby increasing the resistance of the first trace 71, thereby reducing the impedance difference and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0196] Furthermore, the compensation unit 712 may include at least two trace segments 712a arranged at a set angle. The compensation unit 712 is arranged opposite to the invalid pin area WX, so that the first trace group 7 occupies an area of ​​the first fanout area Fanout1 greater than or equal to 90%. This allows the compensation unit 712 to make full use of most of the space in the first fanout area Fanout1, reduce the area of ​​the blank area, fully increase the length of the first trace 71, further increase the resistance of the first trace 71, thereby reducing the impedance difference and further mitigating or even avoiding problems such as grayscale blocks or solid color vertical lines.

[0197] Specifically, referring to Figures 21, 22, and 23, the trace portion 711 extends along the second direction Y and is connected to the first sub-binding area BOD1. The compensation portion 712 may include a first compensation trace 7121 and a second compensation trace 7122. The first compensation trace 7121 may be connected to the display area AA. For example, the first compensation trace 7121 can be connected to the display area AA via a connecting trace. The first compensation trace 7121 extends along the second direction Y. The second compensation trace 7122 is connected to the first sub-binding area BOD1. Between the compensation trace 7121 and the trace portion 711, one end of the second compensation trace 7122 is connected to the first compensation trace 7121, and the other end of the second compensation trace 7122 is connected to the trace portion 711; the second compensation trace 7122 extends along the first direction X, and the second direction Y intersects the first direction X. For example, the second direction Y is perpendicular to the first direction X. Of course, the angle between the second direction Y and the first direction X can be greater than 90 degrees, and the angle between the second direction Y and the first direction X can also be less than 90 degrees.

[0198] Of course, in some other exemplary embodiments of this disclosure, referring to FIG24, a portion of the compensation unit 712 may also be a three-segment structure including a first compensation trace 7121, a second compensation trace 7122, and a third compensation trace 7123; the first compensation trace 7121 is connected to the display area AA and extends along the second direction Y; one end of the second compensation trace 7122 is connected to the first compensation trace 7121, and the other end of the second compensation trace 7122 is connected to the third compensation trace 7123; the other end of the third compensation trace 7123 is connected to the trace portion 711 and extends along the first direction X; the extension direction of the second compensation trace 7122 has a set angle with both the first direction X and the second direction Y. Additionally, the compensation unit 712 may also be configured as a four-segment structure or a five-segment structure, which will not be described in detail here.

[0199] Alternatively, referring to Figures 21, 22, and 23, the line width of the compensation section 712 can be greater than the line width of the trace section 711, increasing the strength of the compensation section 712 and preventing breakage. Furthermore, it can reduce the resistance of the compensation section 712, allowing for a wider range of adjustable impedance differences to meet various user needs. Of course, the line width of the compensation section 712 can also be equal to the line width of the trace section 711.

[0200] Of course, in some other exemplary embodiments of this disclosure, the linewidth of the compensation portion 712 can be set as a gradient structure. For example, the linewidth of the end where the compensation portion 712 is connected to the trace portion 711 is the narrowest, and the linewidth of the compensation portion 712 increases as the distance between the compensation portion 712 and the trace portion 711 increases. This setting makes the linewidth transition uniform, avoids inconsistent etching speed, that is, the linewidth changes uniformly, the etching solution concentration changes uniformly, which is beneficial to etching.

[0201] In this example embodiment, referring to FIG20, the fanout area may further include a second fanout area Fanout2 and a third fanout area Fanout3, which are located on opposite sides of the first fanout area Fanout1 in the first direction X; that is, the fanout area Fanout may include the second fanout area Fanout2, the first fanout area Fanout1 and the third fanout area Fanout3 connected sequentially along the first direction X.

[0202] The binding area BOD may also include a second sub-binding area BOD2 and a third sub-binding area BOD3, which are located on opposite sides of the first sub-binding area BOD1 in the first direction X; that is, the binding area BOD may include the second sub-binding area BOD2, the first sub-binding area BOD1 and the third sub-binding area BOD3 connected sequentially along the first direction X.

[0203] Referring to Figures 25 and 26, the array substrate may further include a second trace group 8 and a third trace group 9. The second trace group 8 is located in the second fanout region Fanout2 and is connected between the display region AA and the second sub-bonding region BOD2. The second trace group 8 extends from the second sub-bonding region BOD2 along the first direction X, substantially away from the third fanout region Fanout3. The third trace group 9 is located in the third fanout region Fanout3 and is connected between the display region AA and the third sub-bonding region BOD3. The third trace group 9 extends from the third sub-bonding region BOD3 along the first direction X, substantially away from the second fanout region Fanout2. The second trace group 8 and the third trace group 9 are located on opposite sides of the first trace group 7 in the first direction X, such that one first trace 71 in the first trace group 7 is adjacent to the second trace group 8, and another first trace 71 in the first trace group 7 is adjacent to the third trace group 9.

[0204] Specifically, the second trace group 8 may include multiple second traces 81 arranged in parallel along the first direction X, that is, the second trace group 8 may include multiple second traces 81 arranged substantially parallel along the first direction X; the third trace group 9 may include multiple third traces 91 arranged in parallel along the first direction X, that is, the third trace group 9 may include multiple third traces 91 arranged substantially parallel along the first direction X; the resistance difference between the first trace 71 and the adjacent second trace 81 is less than or equal to 2Ω, and the resistance difference between the first trace 71 and the adjacent third trace 91 is less than or equal to 2Ω. This configuration effectively avoids problems such as displaying grayscale blocks or solid color vertical stripes.

[0205] In some exemplary embodiments of this disclosure, referring to FIG25, at least a portion of the second trace 81 may include a first trace segment 811, a second trace segment 812, a third trace segment 813, and a fourth trace segment 814 connected in sequence. The first trace segment 811 extends along a second direction Y, and the extension direction of the second trace segment 812 has a predetermined angle with the second direction Y, that is, there is a predetermined angle between the second trace segment 812 and the first trace segment 811, which is greater than 90 degrees. For example, the angle may be 91°, 92°, 93°, 94°, 95°, 96°, etc. The third trace segment 813 extends along the first direction X, and the extension direction of the fourth trace segment 814 has a set angle with the first direction X, that is, there is a set angle between the fourth trace segment 814 and the third trace segment 813. This angle is greater than 90 degrees. For example, this angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The end of the first trace segment 811 away from the second trace segment 812 can be connected to the second sub-binding area BOD2, and the end of the fourth trace segment 814 away from the third trace segment 813 can be connected to the display area AA.

[0206] Referring to FIG26, at least a portion of the third trace 91 may include a seventh trace segment 911, an eighth trace segment 912, a ninth trace segment 913, and a tenth trace segment 914 connected in sequence. The seventh trace segment 911 extends along the second direction Y, and the extension direction of the eighth trace segment 912 has a set angle with the second direction Y, that is, there is a set angle between the eighth trace segment 912 and the seventh trace segment 911. The angle is greater than 90 degrees. For example, the angle can be 91°, 92°, 93°, 94°, 95°, 96°, etc. The ninth routing segment 913 extends along the first direction X, and the extension direction of the tenth routing segment 914 forms a set angle with the first direction X. That is, there is a set angle between the tenth routing segment 914 and the ninth routing segment 913. This angle is greater than 90 degrees. For example, the angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The end of the seventh routing segment 911 furthest from the eighth routing segment 912 can be connected to the third sub-binding area BOD3, and the end of the tenth routing segment 914 furthest from the ninth routing segment 913 can be connected to the display area AA.

[0207] It should be noted that the second trace 81 and the third trace 91 can be set entirely to the above structure, or only partially to the above structure.

[0208] This configuration, compared to a structure with only the first trace segment 811 and the second trace segment 812, increases the area occupied by the second trace group 8 and increases the length of the second trace 81, thereby reducing the resistance of the second trace 81, thus reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0209] Similarly, this configuration, compared to a structure with only the seventh trace segment 911 and the eighth trace segment 912, increases the area occupied by the third trace group 9 and increases the length of the third trace 91, thereby reducing the resistance of the third trace 91, thus reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0210] In some exemplary embodiments of this disclosure, referring to FIG25, at least a portion of the second trace 81 includes a first trace segment 811, a second trace segment 812, a third trace segment 813, a fourth trace segment 814, a fifth trace segment 815, and a sixth trace segment 816 connected in sequence. The first trace segment 811 extends along the second direction Y, and the extension direction of the second trace segment 812 has a set angle with the second direction Y, that is, there is a set angle between the second trace segment 812 and the first trace segment 811. The angle is greater than 90 degrees. For example, the angle can be 91°, 92°, 93°, 94°, 95°, 96°, etc. The third routing segment 813 and the fifth routing segment 815 extend along the first direction X. The extension directions of the fourth routing segment 814 and the sixth routing segment 816 have a set angle with the first direction X. That is, there is a set angle between the fourth routing segment 814 and the third routing segment 813. This angle is greater than 90 degrees. For example, this angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The sixth routing segment 816 and the fifth routing segment 815 have a set angle. This angle is greater than 90 degrees. For example, this angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The end of the first routing segment 811 furthest from the second routing segment 812 can be connected to the second sub-binding area BOD2, and the end of the sixth routing segment 816 furthest from the fifth routing segment 815 can be connected to the display area AA.

[0211] Referring to FIG26, at least a portion of the third trace 91 includes a seventh trace segment 911, an eighth trace segment 912, a ninth trace segment 913, a tenth trace segment 914, an eleventh trace segment 915, and a twelfth trace segment 916 connected in sequence. The seventh trace segment 911 extends along the second direction Y. The extension direction of the eighth trace segment 912 has a set angle with the second direction Y, that is, there is a set angle between the eighth trace segment 912 and the seventh trace segment 911. The angle is greater than 90 degrees. For example, the angle can be 91°, 92°, 93°, 94°, 95°, 96°, etc. The ninth routing segment 913 and the eleventh routing segment 915 extend along the first direction X. The extension directions of the tenth routing segment 914 and the twelfth routing segment 916 have a set angle with the first direction X, that is, there is a set angle between the tenth routing segment 914 and the ninth routing segment 913. This angle is greater than 90 degrees. For example, this angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The twelfth routing segment 916 and the eleventh routing segment 915 have a set angle. This angle is greater than 90 degrees. For example, this angle can be 170°, 171°, 172°, 173°, 174°, 175°, 176°, 177°, 178°, 179°, 180°, etc. The end of the seventh routing segment 911 that is furthest from the eighth routing segment 912 can be connected to the third sub-binding area BOD3, and the end of the twelfth routing segment 916 that is furthest from the eleventh routing segment 915 can be connected to the display area AA.

[0212] It should be noted that the second trace 81 and the third trace 91 can be set entirely to the above structure, or only partially to the above structure.

[0213] This configuration, compared to a structure with only the first trace segment 811 and the second trace segment 812, increases the area occupied by the second trace group 8 and increases the length of the second trace 81, thereby reducing the resistance of the second trace 81, thus reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0214] Similarly, this configuration, compared to a structure with only the seventh trace segment 911 and the eighth trace segment 912, increases the area occupied by the third trace group 9 and increases the length of the third trace 91, thereby reducing the resistance of the third trace 91, thus reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0215] Alternatively, referring to Figures 20, 25, and 26, the second fanout region Fanout2 may include a first sub-region Fanout21, a second sub-region Fanout22, and a third sub-region Fanout23 connected sequentially along the first direction X; the third sub-region Fanout23 is connected to the first fanout region Fanout1. The third fanout region Fanout3 may include a fourth sub-region Fanout31, a fifth sub-region Fanout32, and a sixth sub-region Fanout33 connected sequentially along the first direction X; the fourth sub-region Fanout31 is connected to the first fanout region Fanout1. The fifth line segment 815 and the sixth line segment 816 can be located in the first sub-region Fanout21; the third line segment 813 and the fourth line segment 814 can be located in the second sub-region Fanout22; the first line segment 811 and the second line segment 812 can be located in the third sub-region Fanout23; the seventh line segment 911 and the eighth line segment 912 can be located in the fourth sub-region Fanout31; the ninth line segment 913 and the tenth line segment 914 are located in the fifth sub-region Fanout32; and the eleventh line segment 915 and the twelfth line segment 916 are located in the sixth sub-region Fanout33.

[0216] The ratio of line width to line spacing in the first sub-region Fanout21 is the first ratio, the ratio in the second sub-region Fanout22 is the second ratio, and the ratio in the third sub-region Fanout23 is the third ratio. The ratio of the first ratio to the third ratio is greater than or equal to 2.0 and less than or equal to 2.5. For example, the ratio of the first ratio to the third ratio can be 2.05, 2.1, 2.15, 2.2, 2.25, 2.3, 2.35, 2.4, 2.45, etc., meaning that the ratio of line width to line spacing in the first sub-region Fanout21 is 2.0 to 2.5 times that of the ratio in the third sub-region Fanout23. The ratio of the second ratio to the third ratio is greater than or equal to 1.2 and less than or equal to 1.5. For example, the ratio of the second ratio to the third ratio can be 1.25, 1.3, 1.35, 1.4, 1.45, etc. That is, the ratio of the line width to the line spacing of the second sub-region Fanout22 is 1.2 to 1.5 times the ratio of the line width to the line spacing of the third sub-region Fanout23.

[0217] Since the first sub-region Fanout21 has the fewest traces, the trace width of the first sub-region Fanout21 can be increased to further reduce the resistance of the traces extending to the first sub-region Fanout21; the second sub-region Fanout22 has the second fewest traces, so the trace width of the second sub-region Fanout22 can also be appropriately increased to further reduce the resistance of the traces extending to the second sub-region Fanout22; this makes the increase in resistance of longer traces less, thereby reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0218] The line width to line spacing ratio of the fourth sub-region Fanout31 is the fourth ratio, the ratio of the fifth sub-region Fanout32 is the fifth ratio, and the ratio of the sixth sub-region Fanout33 is the sixth ratio. The ratio of the sixth ratio to the fourth ratio is greater than or equal to 2.0 and less than or equal to 2.5. For example, the ratio of the sixth ratio to the fourth ratio can be 2.05, 2.1, 2.15, 2.2, 2.25, 2.3, 2.35, 2.4, 2.45, etc., meaning that the line width to line spacing ratio of the sixth sub-region Fanout33 is 2.0 to 2.5 times that of the fourth sub-region Fanout31. The ratio of the fifth ratio to the fourth ratio is greater than or equal to 1.2 and less than or equal to 1.5. For example, the ratio of the fifth ratio to the fourth ratio can be 1.25, 1.3, 1.35, 1.4, 1.45, etc. That is, the ratio of the line width to the line spacing of the fifth sub-region Fanout32 is 1.2 to 1.5 times the ratio of the line width to the line spacing of the fourth sub-region Fanout31.

[0219] Since the sixth sub-region Fanout33 has the fewest traces, the trace width of the sixth sub-region Fanout33 can be increased to further reduce the resistance of the traces extending to the sixth sub-region Fanout33; the fifth sub-region Fanout32 has the second fewest traces, so the trace width of the fifth sub-region Fanout32 can also be appropriately increased to further reduce the resistance of the traces extending to the fifth sub-region Fanout32; this makes the increase in resistance of longer traces less, thereby reducing impedance differences and mitigating or even avoiding problems such as grayscale blocks or solid color vertical stripes.

[0220] It should be noted that, for ease of viewing, Figures 16 and 21-26 only schematically show a portion of the wiring; the actual wiring density in the product is much higher than shown in the figures. Furthermore, the wiring of the second fanout area (Fanout2) can be the same as or different from that of the third fanout area (Fanout3).

[0221] The array substrate using a dual-gate structure requires fewer driver ICs, which helps to reduce the length of the printed circuit board (PCB) and facilitates the design of a small P-board.

[0222] Referring to FIG1, in some exemplary embodiments of this disclosure, since the position of the connector CNT is required to be relatively close to the center line of the array substrate, the driver chip ICs on both sides can also be moved towards the center line, so that the printed circuit board PCB can be made smaller.

[0223] Referring to FIG27, in some other exemplary embodiments of this disclosure, since the position of the connector CNT is required to be relatively close to the edge of the array substrate, in order to avoid interference between the flexible circuit board FPC and the connector, the driver chip IC can be moved to both sides of the edge, so that the length of the printed circuit board PCB is slightly increased, but the length of the printed circuit board PCB is still relatively small.

[0224] However, both of the above situations result in a non-zero gap between the first center line ZX1 and the second center line ZX2. The first center line ZX1 is the center line extending along the second direction Y of a portion of the bonding area BOD used to bond the driver chip IC; the second center line ZX2 is the center line extending along the second direction Y of a portion of the display area AA connected to a corresponding driver chip IC. That is, the center line extending along the second direction Y of the driver chip IC and the center line extending along the second direction Y of the portion of the display area AA connected to the driver chip IC are not on the same straight line. In other words, there is a non-zero gap between the center line extending along the second direction Y of the bonding area BOD of the driver chip IC and the center line extending along the second direction Y of the display area AA connected to the driver chip IC. This leads to non-standard fan-shaped wiring in the fanout area, resulting in increased wiring distance, reduced line width, increased impedance, and a greater likelihood of displaying grayscale blocks or solid color vertical stripes. Therefore, the wiring structure of the display area AA and the wiring structure of the fanout area are more suitable for the scaled-down printed circuit board (PCB) structures shown in Figures 1 and 27.

[0225] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0226] The display device can be a liquid crystal display panel, an OLED (Organic Electroluminescence Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0227] When the display device can be a liquid crystal display panel, the display device may also include a color filter substrate, and the color filter substrate and the array substrate are bonded together by a frame.

[0228] The display device may include alternating rows of red, green, and blue subpixels, i.e., a row of red, green, and blue subpixels forms a subpixel column group, and multiple subpixel column groups are arranged sequentially. The orthographic projection of the first auxiliary trace on the substrate is located between the orthographic projections of the red and green subpixel columns on the substrate. For example, the first auxiliary trace may be provided between each red and green subpixel column, or the first auxiliary trace may be provided between a portion of the red and green subpixel columns, while no first auxiliary trace is provided between another portion of the red and green subpixel columns.

[0229] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0230] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0231] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0232] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate having a display area and a non-display area, wherein the non-display area includes a fan-out area and a bonding area, wherein, The array substrate includes: Substrate; A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes a data line, and the data line extends along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor. A first electrode, a conductive auxiliary layer, and a second electrode are disposed on the side of the driving circuit layer group facing away from the substrate; the conductive auxiliary layer includes a first auxiliary trace, which is electrically connected to the first electrode. A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns. The orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate.

2. The array substrate according to claim 1, wherein, The orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the first auxiliary trace near the corner of the first auxiliary trace on the substrate. Other parts of the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the first auxiliary trace on the substrate.

3. The array substrate according to claim 1, wherein, The first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

4. The array substrate according to claim 1, wherein, The array substrate further includes: A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.

5. The array substrate according to claim 1, wherein, The first electrode portion and the second electrode portion are located within the same pixel region.

6. The array substrate according to claim 5, wherein, The three pixel regions arranged along the first direction form a group, and a first auxiliary trace is provided in a group of pixel regions, or a first auxiliary trace is provided between two adjacent groups of pixel regions.

7. The array substrate according to claim 6, wherein, The conductive auxiliary layer further includes a third auxiliary trace, the orthographic projection of which is located between the orthographic projections of two adjacent second electrodes on the substrate, the third auxiliary trace being disconnected, and the virtual extension of which intersects with the second lead portion.

8. The array substrate according to claim 1, wherein, In the second direction, the first transistor and the second transistor are each located on opposite sides of the pixel region.

9. The array substrate according to claim 8, wherein, The plurality of transistors include multiple groups of transistors, each group of transistors includes two transistors, the two transistors in the same group are located between two adjacent gate lines in the same group, the two transistors in the same group are connected to opposite sides of the same data line in the first direction and are staggered in the second direction; the two gates of the two transistors in the same group are connected one-to-one to two adjacent gate lines in the same group.

10. The array substrate according to claim 8, wherein, The grid lines are configured as straight lines extending along the first direction.

11. The array substrate according to claim 6, wherein, The conductor layer further includes signal traces, the data lines and the signal traces are configured as strips extending along the second direction, a portion of the signal traces is located within the pixel region, the driving circuit layer group includes a first insulating layer, the first insulating layer is located between the conductor layer and the first electrode, the first electrode is connected to the signal traces through a third via on the first insulating layer, the orthographic projection of the third via on the substrate is located between the orthographic projections of two adjacent transistors on the substrate.

12. The array substrate according to claim 11, wherein, The orthographic projection of the second lead portion on the substrate overlaps with the orthographic projection of the signal trace on the substrate, while the orthographic projection of the first lead portion on the substrate does not overlap with the orthographic projection of the signal trace on the substrate.

13. The array substrate according to any one of claims 1 to 12, wherein, The display area and the bonding area are connected to opposite sides of the fan-out area in the second direction. The fan-out area includes a first fan-out area, and the bonding area includes a first sub-bonding area. The first sub-bonding area includes an invalid pin area, which is used to set invalid pins of the driver chip. The first fan-out area and the first sub-bonding area are disposed opposite to each other in the second direction. The array substrate further includes: The first trace group is located in the first fan-out area and is connected between the display area and the first sub-binding area. The first trace group includes multiple parallel first traces. Each first trace includes a trace section and a compensation section. The compensation section includes at least two trace segments arranged at a set angle. The compensation section is arranged opposite to the invalid pin area.

14. The array substrate according to claim 13, wherein, The wiring portion extends along the second direction and is connected to the first sub-binding area, and the compensation portion includes: A first compensation trace is connected to the display area, and the first compensation trace extends along the second direction; The second compensation trace is connected between the first compensation trace and the trace portion, and the second compensation trace extends along the first direction.

15. The array substrate according to claim 13, wherein, The line width of the compensation section is greater than the line width of the routing section.

16. The array substrate according to claim 13, wherein, The fan-out region further includes a second fan-out region and a third fan-out region, the second fan-out region and the third fan-out region being located on opposite sides of the first fan-out region in the first direction; the bonding region further includes a second sub-bonding region and a third sub-bonding region, the second sub-bonding region and the third sub-bonding region being located on opposite sides of the first sub-bonding region in the first direction; the array substrate further includes: The second wiring group is located in the second fan-out area, and the second wiring group is connected between the display area and the second sub-binding area; The third wiring group is located in the third fan-out area, and the third wiring group is connected between the display area and the third sub-binding area; The second wiring group and the third wiring group are located on opposite sides of the first wiring group in the first direction.

17. The array substrate according to claim 16, wherein, The second routing group includes multiple second routing lines arranged in parallel along the first direction, and the third routing group includes multiple third routing lines arranged in parallel along the first direction. The resistance difference between the first routing line and the adjacent second routing line is less than or equal to 2Ω, and the resistance difference between the first routing line and the adjacent third routing line is less than or equal to 2Ω.

18. The array substrate according to claim 16, wherein, At least a portion of the second trace includes a first trace segment, a second trace segment, a third trace segment, and a fourth trace segment connected in sequence. The first trace segment extends along the second direction, and the extension direction of the second trace segment has a set angle with the second direction. The third trace segment extends along the first direction, and the extension direction of the fourth trace segment has a set angle with the first direction. The end of the first trace segment away from the second trace segment is connected to the second sub-binding area, and the end of the fourth trace segment away from the third trace segment is connected to the display area. At least a portion of the third trace includes a seventh trace segment, an eighth trace segment, a ninth trace segment, and a tenth trace segment connected in sequence. The seventh trace segment extends along the second direction, the extension direction of the eighth trace segment has a set angle with the second direction, the ninth trace segment extends along the first direction, and the extension direction of the tenth trace segment has a set angle with the first direction. The end of the seventh trace segment away from the eighth trace segment is connected to the third sub-binding area, and the end of the tenth trace segment away from the ninth trace segment is connected to the display area.

19. The array substrate according to claim 16, wherein, At least a portion of the second trace includes a first trace segment, a second trace segment, a third trace segment, a fourth trace segment, a fifth trace segment, and a sixth trace segment connected in sequence. The first trace segment extends along the second direction, and the extension direction of the second trace segment has a set angle with the second direction. The third trace segment and the fifth trace segment extend along the first direction, and the extension directions of the fourth trace segment and the sixth trace segment have a set angle with the first direction. The end of the first trace segment away from the second trace segment is connected to the second sub-binding area, and the end of the sixth trace segment away from the fifth trace segment is connected to the display area. At least a portion of the third trace includes a seventh trace segment, an eighth trace segment, a ninth trace segment, a tenth trace segment, an eleventh trace segment, and a twelfth trace segment connected in sequence. The seventh trace segment extends along the second direction. The extension direction of the eighth trace segment forms a predetermined angle with the second direction. The ninth and eleventh trace segments extend along the first direction. The extension directions of the tenth and twelfth trace segments form a predetermined angle with the first direction. The end of the seventh trace segment away from the eighth trace segment is connected to the third sub-binding area. The end of the twelfth trace segment away from the eleventh trace segment is connected to the display area.

20. The array substrate according to claim 19, wherein, The second fan-out region includes a first sub-region, a second sub-region, and a third sub-region connected sequentially along the first direction, with the third sub-region connected to the first fan-out region; the third fan-out region includes a fourth sub-region, a fifth sub-region, and a sixth sub-region connected sequentially along the first direction, with the fourth sub-region connected to the first fan-out region; the fifth and sixth routing segments are located in the first sub-region, the third and fourth routing segments are located in the second sub-region, and the first and second routing segments are located in the third sub-region; the seventh and eighth routing segments are located in the fourth sub-region, the ninth and tenth routing segments are located in the fifth sub-region, and the eleventh and twelfth routing segments are located in the sixth sub-region.

21. The array substrate according to claim 20, wherein, The ratio of line width to line spacing in the first sub-region is a first ratio; the ratio of line width to line spacing in the second sub-region is a second ratio; the ratio of line width to line spacing in the third sub-region is a third ratio; the ratio of the first ratio to the third ratio is greater than or equal to 2.0 and less than or equal to 2.5; the ratio of the second ratio to the third ratio is greater than or equal to 1.2 and less than or equal to 1.5; the ratio of line width to line spacing in the fourth sub-region is a fourth ratio; the ratio of line width to line spacing in the fifth sub-region is a fifth ratio; the ratio of line width to line spacing in the sixth sub-region is a sixth ratio; the ratio of the sixth ratio to the fourth ratio is greater than or equal to 2.0 and less than or equal to 2.5; the ratio of the fifth ratio to the fourth ratio is greater than or equal to 1.2 and less than or equal to 1.

5.

22. The array substrate according to any one of claims 1 to 12, wherein, The gate layer is disposed on one side of the substrate, and the driving circuit layer group further includes: A gate insulating layer is disposed on the side of the gate layer opposite to the substrate. An active layer is disposed on the side of the gate insulating layer away from the substrate. The active layer includes a first conductive connection portion, a channel portion, and a second conductive connection portion connected in sequence. A conductor layer is disposed on the side of the active layer away from the substrate. The conductor layer also includes a source and a drain. The source is connected to the first conductive connection portion. The data line is connected to the source. The drain is connected to the second conductive connection portion. Two pixel columns are disposed between two adjacent data lines. A first insulating layer is disposed on the side of the conductor layer opposite to the substrate. A first via is disposed on the first insulating layer. A second via is disposed on the second insulating layer and communicates with the first via. The second electrode is connected to the drain electrode through the second via and the first via.

23. The array substrate according to claim 22, wherein, The drain includes an electrode block, a connecting block, and a compensation block connected sequentially in a first direction. The electrode block is connected to the second conductive connection portion. The second electrode is connected to the connecting block through the second via and the first via. In the second direction, the distance between the electrode block and the gate line is less than the distance between the compensation block and the gate line. The width of the connecting block is greater than the width of the electrode block and the compensation block.

24. The array substrate according to claim 23, wherein, In the second direction, the size of the source electrode is larger than the size of the electrode block, and the orthographic projection of the portion of the source electrode extending beyond the active layer onto the substrate overlaps with the orthographic projection of the gate line onto the substrate.

25. The array substrate according to any one of claims 1 to 12, wherein, The multiple data lines have different lengths, and the length of the data lines increases with the increase of the distance from the first center line in the first direction. The first center line is the center line of the bonding area that extends along the second direction for bonding a portion of the driver chip.

26. The array substrate according to claim 25, wherein, At least a portion of the data line includes a first portion and a second portion that are interconnected, wherein the orthographic projection of the second portion on the substrate lies within the region between the mutually distant edges of the orthographic projections of the two gate lines of the same group on the substrate. The width of the second portion is greater than the width of the first portion, and the number of the second portions increases with the increase of the distance from the first center line in the first direction; or, the width of the second portion is less than the width of the first portion, and the number of the second portions decreases with the increase of the distance from the first center line in the first direction.

27. The array substrate according to claim 26, wherein, The connection between the second part and the first part is arc-shaped.

28. The array substrate according to claim 25, wherein, The conductive auxiliary layer further includes a second auxiliary trace extending along the second direction. The orthographic projection of the second auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate. The driving circuit layer group includes a first insulating layer located between the conductor layer and the first electrode. A fourth via is provided on the first insulating layer, which is connected to the data line. The second auxiliary trace is connected to the data line through the fourth via. The number of the second auxiliary traces increases with the increase of the distance from the first center line in the first direction.

29. The array substrate according to claim 28, wherein, The orthographic projection of the fourth via on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

30. The array substrate according to any one of claims 1 to 12, wherein, There is a non-zero gap between the first center line and the second center line. The first center line is a center line extending along the second direction for a portion of the bonding area used to bond the driver chip. The second center line is a center line extending along the second direction for a portion of the display area corresponding to one of the driver chips.

31. A display device, wherein, include: The array substrate is the array substrate as described in any one of claims 1 to 30.

32. The display device according to claim 31, wherein, The display device includes alternating rows of red, green, and blue subpixels, with the first auxiliary trace's orthographic projection on the substrate located between the orthographic projections of the red and green subpixels on the substrate.

Images