Array substrate and method for preparing same, display panel, and display device

Abstract

The present application provides an array substrate and a method for preparing same, a display panel, and a display device. The array substrate comprises a substrate, an active layer, a first driving transistor and a first switching transistor, wherein the active layer is disposed on one side of the substrate; a control terminal of the first driving transistor is electrically connected to a first node; a first electrode of the first switching transistor is electrically connected to a second electrode of the first driving transistor, and a second electrode of the first switching transistor is electrically connected to the first node; and the first switching transistor comprises a first sub-switching transistor and a second sub-switching transistor. The first sub-switching transistor comprises a first channel portion located in the active layer, and the second sub-switching transistor comprises a second channel portion located in the active layer, wherein a gap is present between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate, and the electrical resistivity of the first channel portion is less than the electrical resistivity of the second channel portion.

Description

Array substrate and its fabrication method, display panel, display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411541523.7, filed on October 31, 2024, entitled “Array substrate and method of preparation thereof, display panel, display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display device technology, and in particular to an array substrate and its preparation method, a display panel, and a display device. Background Technology

[0004] With the continuous development of display technologies such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), display panels are widely used in various industries. However, screen flickering may still occur during the use of current display panels, affecting the user's viewing experience. Summary of the Invention

[0005] This application provides an array substrate and its fabrication method, a display panel, and a display device, which can improve screen flickering issues.

[0006] In a first aspect, embodiments of this application provide an array substrate, which includes a substrate, an active layer, a first driving transistor, and a first switching transistor. The active layer is disposed on one side of the substrate. The control terminal of the first driving transistor is electrically connected to a first node. The first electrode of the first switching transistor is electrically connected to the second electrode of the first driving transistor. The second electrode of the first switching transistor is electrically connected to the first node. The first switching transistor includes a first sub-switching transistor and a second sub-switching transistor.

[0007] The first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer. The first channel portion is electrically connected to the second terminal of the first switch transistor, and the second communication portion is electrically connected to the first terminal of the first switch transistor. There is a gap between the orthographic projection of the first channel portion onto the substrate and the orthographic projection of the second channel portion onto the substrate. The resistivity of the first channel portion is less than the resistivity of the second channel portion.

[0008] Secondly, embodiments of this application provide a display panel, which includes an array substrate as described in any of the foregoing embodiments and a plurality of sub-pixels. The array substrate includes a plurality of pixel circuits, and the pixel circuits include a first driving transistor and a first switching transistor. The pixel circuits are used to control the light emission of the sub-pixels.

[0009] Thirdly, embodiments of this application provide a display device, which includes the display panel in any of the foregoing embodiments.

[0010] Fourthly, embodiments of this application provide a method for fabricating an array substrate. The array substrate includes a first switching transistor and a first driving transistor. The control terminal of the first driving transistor is electrically connected to a first node. The first electrode of the first switching transistor is electrically connected to the second electrode of the first driving transistor. The second electrode of the first switching transistor is electrically connected to the first node. The first switching transistor includes a first sub-switching transistor and a second sub-switching transistor. The fabrication method includes:

[0011] An active layer is formed on one side of the substrate;

[0012] The first channel section is subjected to plasma treatment.

[0013] This application provides an array substrate and its fabrication method, a display panel, and a display device. Since the first channel portion is located between the first node and the fifth node and the first channel portion has strong conductivity, when there is a certain voltage difference between the fifth node and the first node, the current can flow from the fifth node to the first node quickly through the first channel portion. This allows the potential at the first node to be consistent with the potential at the fifth node in a short time, thereby reducing the leakage between the first node and the fifth node during the light-emitting stage, reducing the flicker of the displayed image, and improving the display effect. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is a top view of a partial film layer in an array substrate provided in an embodiment of this application;

[0016] Figure 2 is an enlarged structural diagram of the first switching transistor in Figure 1;

[0017] Figure 3 is a schematic diagram of the cross-sectional structure at point AA in Figure 2;

[0018] Figure 4 is a simplified circuit diagram of a pixel circuit in an array substrate provided in an embodiment of this application;

[0019] Figure 5 is the timing diagram corresponding to the circuit structure shown in Figure 4;

[0020] Figure 6 is an enlarged schematic diagram of the structure at the second switching transistor in Figure 1;

[0021] Figure 7 is a cross-sectional structural diagram of another array substrate provided in an embodiment of this application;

[0022] Figure 8 is a top view of a partial film layer in an array substrate provided in an embodiment of this application.

[0023] Figure 9 is an enlarged structural schematic diagram of an array substrate at the first switching transistor according to an embodiment of this application;

[0024] Figure 10 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0025] Figure 11 is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0026] Figure 12 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application.

[0027] Labeling Explanation: 100, Array substrate; 200, Display panel; 300, Display device; 10, Pixel circuit; 20, Substrate; 30, Active layer; 31, First channel portion; 32, Second channel portion; 33, Third channel portion; 34, Fourth channel portion; 35, Fifth channel portion; 36, First active structure; 40, First conductive layer; 41, First sub-control terminal; 42, Second sub-control terminal; 43, Third sub-control terminal; 44, Fourth sub-control terminal; 50, Storage capacitor; 51, First electrode plate; 52, Second electrode plate; 60, Sub-pixel; 70, Second conductive layer; T3, First driving transistor; T4, First switching transistor; T41, First sub-switching transistor; T42, Second sub-switching transistor; T5, Second switching transistor; T51, Third sub-switching transistor; T52, Fourth sub-switching transistor; N1, the first node; N3, the third node; N4, the fourth node; N5, the fifth node. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] In the first aspect, please refer to Figures 1 to 5. An embodiment of this application provides an array substrate 100. The array substrate 100 includes a substrate 20, an active layer 30, a first driving transistor T3, and a first switching transistor T4. The active layer 30 is disposed on one side of the substrate 20. The control terminal of the first driving transistor T3 is electrically connected to a first node N1. The first electrode of the first switching transistor T4 is electrically connected to the second electrode of the first driving transistor T3. The second electrode of the first switching transistor T4 is electrically connected to the first node N1. The first switching transistor T4 includes a first sub-switching transistor T41 and a second sub-switching transistor T42.

[0031] The first sub-switching transistor T41 includes a first channel portion 31 located within the active layer 30, and the second sub-switching transistor T42 includes a second channel portion 32 located within the active layer 30. The first channel portion 31 is electrically connected to the second terminal of the first switching transistor T4, and the second channel portion 32 is electrically connected to the first terminal of the first switching transistor T4. There is a gap between the orthographic projection of the first channel portion 31 onto the substrate 20 and the orthographic projection of the second channel portion 32 onto the substrate 20. The resistivity of the first channel portion 31 is less than the resistivity of the second channel portion 32.

[0032] The array substrate 100 is used for subsequent fabrication to form a display panel, which includes, but is not limited to, a liquid crystal display panel and an organic light-emitting display panel. For ease of description, this application embodiment uses the array substrate 100 as an example to illustrate the formation of an organic light-emitting display panel.

[0033] The array substrate 100 includes a pixel circuit 10, which, in the subsequently formed display panel 200, is a circuit structure used to control whether the sub-pixels 60 emit light. Figure 4 shows a simplified circuit diagram of the pixel circuit 10 in a 7T1C configuration, i.e., when the pixel circuit 10 includes seven thin-film transistors and a storage capacitor. Each thin-film transistor includes a control terminal, a first electrode, and a second electrode. The control terminal is used to control whether the first electrode and the second electrode are turned on or off.

[0034] The pixel circuit 10 includes a first driving transistor T3, a first switching transistor T4, and five other switching transistors. Referring to Figures 1 and 4, the control terminal of the first driving transistor T3 is electrically connected to the first node N1, and the control terminal of the first driving transistor T3 can be reused as the first plate 51 of the storage capacitor 50. The first electrode of the first driving transistor T3 is electrically connected to the first power supply signal VDD, and the second electrode of the first driving transistor T3 is electrically connected to the first electrode of the first switching transistor T4. The control terminal of the first switching transistor T4 is electrically connected to the second scan signal Scan2, and the second electrode of the first switching transistor T4 is electrically connected to the first node N1.

[0035] Figure 5 is a circuit timing diagram corresponding to Figure 4. Specifically, as shown in Figures 1, 4 and 5, within a frame time I, the pixel circuit 10 may include a reset stage, a charging stage and a light-emitting stage. The reset stage corresponds to the time period t1. In the reset stage, the second switching transistor T5 is turned on by the low level of the first scan signal ScanN1, and the first reset signal Vref1 is applied to the first node N1, resetting the control terminal of the first driving transistor T3 and the first plate 51 of the storage capacitor 50.

[0036] The charging phase corresponds to time period t2. At this time, the first switching transistor T4 is turned on by the low level of the second scan signal ScanN2, and transistors T2 and T7 are turned on by the low level of the third scan signal ScanP. After passing through transistor T2, the first driving transistor T3 and the first switching transistor T4, the data signal charges the first node N1 (that is, charges the first plate 51 of the storage capacitor 50). The potential at the first node N1 rises, and the second reset signal Vref2 is applied to the anode 61 of the sub-pixel 60 and resets the anode 61 of the sub-pixel 60.

[0037] Based on the inherent characteristics of the first driving transistor T3, the potentials of the first node N1 and the third node N3 can increase to Vdata + Vth during the charging process. Here, Vdata represents the voltage value of the data signal Data, and Vth represents the threshold voltage of the first driving transistor T3. Since the first driving transistor T3 is illustrated using a PMOS transistor as an example, the threshold voltage Vth is a negative value here.

[0038] The light-emitting phase is time period t3. At this time, transistors T1 and T6 are turned on by the low level of the light-emitting signal Emit, while the potential maintained at the first node N1 causes the first driving transistor T3 to also be turned on. The first power supply signal VDD is applied to the anode of the sub-pixel after passing through transistors T1, T3, and T6. The second power supply signal VEE is applied to the cathode of the sub-pixel. Under the joint drive of the anode and cathode of the sub-pixel, the sub-pixel 60 realizes the light-emitting function.

[0039] It should be noted that, in Figure 3, the example given is that all thin-film transistors are PMOS transistors (conducting at low level and cutting off at high level). In the actual pixel circuit 10, some or all of the transistors can be changed to NMOS transistors (conducting at high level and cutting off at low level). Furthermore, depending on the actual needs, the pixel circuit 10 can adopt the 7T1C circuit structure shown in Figure 1, or it can adopt other circuit structures such as 8T1C. This embodiment of the application does not limit this.

[0040] Furthermore, Figure 4 shows the case where transistor T7 and the second switching transistor T5 are controlled by different scan signals. Of course, in other embodiments, the same scan signal can be applied to the control terminals of both the second switching transistor T5 and transistor T7. Based on this, during the reset phase, the conduction of both the second switching transistor T5 and transistor T7 can be controlled simultaneously to reset the anode of the sub-pixel while resetting the first node N1. In other words, the anode of the sub-pixel can be reset during the reset phase or during the charging phase. Similarly, in other embodiments, the control terminals of the first switching transistor T4 and transistor T2 can also be electrically connected to the same scan signal. This application does not limit this; for ease of description, the following embodiments of this application will be described using the pixel circuit shown in Figure 4.

[0041] Furthermore, the first switching transistor T4 includes a first sub-switching transistor T41 and a second sub-switching transistor T42, meaning the first switching transistor T4 is a dual-gate transistor. Specifically, the control terminals of the first switching transistor T4 include a first sub-control terminal 41 located in the first sub-switching transistor T41 and a second sub-control terminal 42 located in the second sub-switching transistor T42. The first sub-control terminal 41 and the second sub-control terminal 42 are electrically connected to the second scan signal ScanN2.

[0042] Compared to a single-gate transistor, setting the first switching transistor T4 as a dual-gate transistor helps reduce the leakage characteristics of the first switching transistor T4 itself. However, there is a fifth node N5 between the first sub-switching transistor T41 and the second sub-switching transistor T42. During the charging phase, the voltage at the fifth node N5 and the first node N1 often remain the same or similar. At the end of the charging phase, the level at the second scan signal ScanN2 will suddenly rise from a low level to a high level.

[0043] In related technologies, the fifth node N5 is inherently an unstable node. Therefore, the abrupt change in the second scan signal ScanN2 causes the voltage at the fifth node N5 to be coupled to a larger potential, resulting in a significant potential difference between the first node N1 and the fifth node N5. This potential difference leads to leakage between the first node N1 and the fifth node N5. Furthermore, since the structure between the first node N1 and the fifth node N5 is a semiconductor structure with high resistivity, the leakage process between them is relatively slow. During the light-emitting stage, a continuous and slow leakage occurs between the first node N1 and the fifth node N5, causing flickering in the display and affecting the actual display experience.

[0044] Therefore, this embodiment of the application adjusts the resistivity of the first channel portion 31 in the first sub-switch transistor T41 to reduce screen flicker. Specifically, the array substrate 100 includes a substrate 20 and an active layer 30 located on one side of the substrate 20. The substrate 20 is a film structure in the array substrate 100 that serves as a support, and the active layer 30 is a film structure in the array substrate 100 that includes semiconductor material. The active layer 30 includes a first channel portion 31 and a second channel portion 32. The first channel portion 31 is a portion of the active layer 30 that overlaps with the orthographic projection of the first sub-control terminal 41 onto the substrate 20, and the second channel portion 32 is a portion of the active layer 30 that overlaps with the orthographic projection of the second sub-control terminal 42 onto the substrate 20. The first channel portion 31 and the second channel portion 32 together form the channel structure of the first switch transistor T4.

[0045] It should be noted that the active layer 30 can have various material compositions, and this application embodiment does not limit this. For example, the first switching transistor T4 can be an IGZO (Indium Gallium Zinc Oxide)-TFT, in which case the material of the active layer 30 includes metal oxides; or the first switching transistor T4 can be an LTPS (Low Temperature Poly-Silicon)-TFT, in which case the material of the active layer 30 includes low temperature polysilicon.

[0046] In addition to the substrate 20 and the active layer 30, the array substrate 100 may also include other film layer structures. The embodiments of this application do not limit the specific film layer composition within the array substrate 100.

[0047] In some optional embodiments, the array substrate 100 further includes a first conductive layer 40 located on the side of the active layer 30 facing away from the substrate 20, and an insulating layer located between the first conductive layer 40 and the active layer 30. The first sub-control terminal 41 and the second sub-control terminal 42 in the first switching transistor T4 are both located within the first conductive layer 40. Figure 1 only shows the arrangement of the active layer 30, the first conductive layer 40, and a few other cross-line structures in a local area of ​​the array substrate.

[0048] The first channel portion 31 is electrically connected to the second terminal of the first switching transistor T4, meaning one end of the first channel portion 31 is electrically connected to the second terminal of the first driving transistor T3. The second communication portion is electrically connected to the first terminal of the first switching transistor T4, meaning one end of the second channel portion 32 is electrically connected to the first node N1. The first channel portion 31 and the second channel portion 32 are two separate structures, and there is a gap between the orthographic projection of the first channel portion 31 onto the substrate 20 and the orthographic projection of the second channel portion 32 onto the substrate 20.

[0049] Based on this, the embodiments of this application have adjusted the first channel portion 31 to reduce its resistivity. The embodiments of this application do not limit how the resistivity of the first channel portion 31 is reduced. For example, the resistivity of the first channel portion 31 can be reduced by adjusting the material composition within it, or by increasing the doping concentration of the original material within the first channel portion 31, or by using other processing methods.

[0050] Furthermore, the resistivity of the adjusted first channel portion 31 is lower than that of the second channel portion 32. Resistivity is a parameter characterizing the conductivity of a structure; a lower resistivity indicates that the first channel portion 31 has stronger conductivity. In this design, since the first channel portion 31 is located between the first node N1 and the fifth node N5 and has strong conductivity, when there is a voltage difference between the fifth node N5 and the first node N1, current can quickly flow from the fifth node N5 through the first channel portion 31 to the first node N1. This allows the potential at the first node N1 to be consistent with the potential at the fifth node N5 for a short time, thereby reducing leakage between the first node N1 and the fifth node N5 during the light-emitting stage, reducing screen flicker, and improving display performance.

[0051] In some embodiments, the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32.

[0052] Doping concentration refers to the chemical concentration of impurities incorporated into a material. These impurities can be atoms, ions, molecules, or small particles. By incorporating impurities of different elements into a material, its properties in photoelectricity, heat, conductivity, and magnetism can be altered.

[0053] The resistivity of the first channel portion 31 and the second channel portion 32 is generally closely related to the doping concentration. Specifically, a higher doping concentration in the first channel portion 31 indicates a higher concentration of impurities incorporated into it. These impurities can donate or accept electrons, thereby increasing the number of charge carriers, reducing resistivity, and giving the first channel portion 31 better conductivity. Conversely, a lower doping concentration in the first channel portion 31 results in a higher resistivity and relatively poorer conductivity.

[0054] In this embodiment, by setting the doping concentration of the first channel portion 31 to be greater than that of the second channel portion 32, the first channel portion 31 can have more impurities for providing or receiving electrons compared to the second channel portion 32, thereby increasing the number of charge carriers in the first channel portion 31 and giving it stronger conductivity. As a result, when there is a certain voltage difference between the fifth node N5 and the first node N1, the current can flow quickly from the fifth node N5 through the first channel portion 31 to the first node N1, thereby improving the flickering problem of the display screen and enhancing the display effect.

[0055] It should be noted that the types of materials used for the dopants in the first channel portion 31 and the second channel portion 32 are not limited in the embodiments of this application. Optionally, the first channel portion 31 and the second channel portion 32 may contain the same dopant, such as boron ions.

[0056] Furthermore, in some optional embodiments, during the fabrication of the active layer 30, doping can be performed simultaneously at corresponding positions of the first channel portion 31 and the second channel portion 32, followed by an additional secondary doping of the first channel portion 31 to ensure that the doping concentration of the first channel portion 31 is greater than that of the second channel portion 32. Compared to the original fabrication process, this design only requires an additional doping process to improve the flickering problem of the display image, with minimal impact on the fabrication cost and efficiency of the array substrate 100, making it highly practical.

[0057] Alternatively, when performing additional secondary doping on the first channel portion 31, a sacrificial layer can be formed on the active layer 30 first. The sacrificial layer is used to cover other structures in the active layer 30 except for the first channel portion 31, and an opening structure for exposing the first channel portion 31 is provided on the sacrificial layer. Then, a doping process is performed so that the doping concentration at the first channel portion 31 can be greater than the doping concentration at other locations in the active layer 30.

[0058] Of course, in other embodiments, the first channel portion 31 and the second channel portion 32 can also be formed by completely separate doping processes, that is, the first channel portion 31 is doped only once, and the doping process corresponding to the first channel portion 31 is relatively independent from the doping process corresponding to the second channel portion 32. This application does not limit this.

[0059] In some embodiments, the doping concentration of the first channel portion 31 is E, where E satisfies: 10 12 pcs / cm - 3 ≤E≤10 15 pcs / cm -3 Optionally, E is 10. 12 pcs / cm -3 10 13 pcs / cm -3 5*10 13 pcs / cm - 3 15 14 pcs / cm -3 and 10 15 pcs / cm -3 one of them.

[0060] During the fabrication of the active layer 30, doping of the first channel portion 31 and the second channel portion 32 can be achieved through ion implantation. Specifically, dopant ions can be implanted into a portion of the active layer 30 in the form of an ion beam to form the first channel portion 31 and the second channel portion 32. The doping concentration of the first channel portion 31 and the second channel portion 32 is often related to the implantation energy and the number of implantation cycles during the ion implantation process.

[0061] Based on the foregoing, it can be understood that the first channel portion 31 can undergo a second ion implantation process, while the second channel portion 32 can undergo a single ion implantation process, thereby increasing the doping concentration of the first channel portion 31 to be greater than that of the second channel portion 32. Alternatively, only the first channel portion 31 and the second channel portion 32 can undergo a single ion implantation process. In this case, the ion implantation energy for the first channel portion 31 needs to be greater than that for the second channel portion 32, so that the doping concentration of the first channel portion 31 is greater than that of the second channel portion 32.

[0062] Furthermore, when the first channel portion 31 is doped using only a single ion implantation process, the corresponding ion beam energy is W, where W satisfies: 8 KeV ≤ W ≤ 25 KeV. This design allows the doping concentration of the first channel portion 31 to be greater than that of the second channel portion 32, and makes E satisfy: 10 12 pcs / cm -3 ≤E≤10 15 pcs / cm -3 .

[0063] In this embodiment, the doping concentration E of the first channel portion 31 is limited to not less than 10. 12 cm -3 This results in the first channel portion 31 having a lower resistivity, thereby improving its conductivity. Consequently, when a voltage difference exists between the fifth node N5 and the first node N1, current can quickly flow from the fifth node N5 through the first channel portion 31 to the first node N1, improving the flickering problem of the displayed image. Simultaneously, the doping concentration E of the first channel portion 31 is limited to no more than 10. 15 cm -3 This ensures that the first channel portion 31 remains in a semiconductor state, satisfying the cutoff and conduction control requirements of the first sub-switch transistor T41.

[0064] In some embodiments, the ratio between the doping concentration in the first channel portion 31 and the doping concentration in the second channel portion 32 is denoted as a, where a satisfies: 3 ≤ a ≤ 200. Optionally, a is one of 3, 10, 20, 50, 100, 150, and 200.

[0065] All other factors remaining constant, the resistivity of the first channel portion 31 and the second channel portion 32 is negatively correlated with their corresponding doping concentrations. When the doping concentrations of the first channel portion 31 and the second channel portion 32 are the same or similar, they will have the same or similar resistivity. Based on this, in related technologies, when the fifth node N5 is coupled to a larger potential due to the abrupt change of the second scan signal ScanN2, the voltage difference between the fifth node N5 and the first node N1 can cause slow leakage at the first channel portion 31, easily leading to flickering problems. The voltage difference between the fifth node N5 and the third node N3 can also cause slow leakage at the second channel portion 32, affecting display accuracy.

[0066] In this embodiment, by setting the doping concentration in the first channel portion 31 to be greater than the doping concentration in the second channel portion 32, and setting the ratio α between the doping concentrations in the first channel portion 31 and the second channel portion 32 to be not less than 3, the first channel portion 31 has a lower resistivity relative to the second channel portion 32. This not only allows current to flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31, improving the flicker problem, but also utilizes the resistivity difference between the first channel portion 31 and the second channel portion 32 to allow more current to flow from the fifth node N5 to the first node N1, rather than from the fifth node N5 to the third node N3, thereby reducing the leakage between the fifth node N5 and the third node N3 and improving display accuracy. Simultaneously, setting α to be not greater than 200 ensures that the first channel portion 31 remains in a semiconductor state, meeting the cutoff and conduction control requirements of the first sub-switch transistor T41.

[0067] In some embodiments, the first channel portion 31 is plasma treated.

[0068] Plasma treatment is a method of processing semiconductor materials by placing them in a plasma environment. It uses ions from a plasma beam to sinter the material surface, remove impurities, reduce resistivity, and increase conductivity. Unlike ion implantation, which involves injecting dopant ions into the semiconductor material, plasma treatment is a process that treats the semiconductor material itself.

[0069] In this embodiment, plasma treatment of the first channel portion 31 can also help reduce the resistivity of the first channel portion 31, thereby improving its conductivity and reducing flicker. Furthermore, compared to existing fabrication processes, this design only requires an additional process to improve the flicker problem, with minimal impact on the fabrication cost and efficiency of the array substrate 100, making it highly practical.

[0070] In some embodiments, as shown in FIG1 and FIG2, the first driving transistor T3 includes a third channel portion 33 located within the active layer 30, wherein the resistivity of the first channel portion 31 is less than the resistivity of the third channel portion 33.

[0071] The third channel portion 33 is the part of the active layer 30 that overlaps with the control terminal of the first driving transistor T3 in the orthographic projection onto the substrate 20. As can be seen from Figure 1, the control terminal of the first driving transistor T3 can be reused as the first electrode 51 of the storage capacitor 50 and electrically connected to the first node N1. Based on this, the third channel portion 33 is the part of the active layer 30 that overlaps with the first electrode 51 in the orthographic projection onto the substrate 20.

[0072] Similar to the first channel portion 31, reducing the resistivity of the third channel portion 33 also helps to improve the current transfer rate, thereby reducing flicker. However, increasing the resistivity of the third channel portion 33 will increase its conductivity, which may cause the first driving transistor T3 to fail to turn off properly, resulting in screen splitting on the display.

[0073] Therefore, in this embodiment, only the first channel portion 31 is adjusted so that the resistivity of the first channel portion 31 is simultaneously less than the resistivity of both the first channel portion 31 and the second channel portion 32. This allows current to flow quickly from the fifth node N5 through the first channel portion 31 to the first node N1, improving the flickering problem of the displayed image. Furthermore, since the second channel portion 32 and the third channel portion 33 are not adjusted, the turn-off reliability of the first switching transistor T4 can be improved by means of the second channel portion 32, and the turn-off reliability of the first driving transistor T3 can be improved by means of the third channel portion 33, thereby meeting the normal operation requirements of the pixel circuit 10.

[0074] In some embodiments, referring to Figures 1, 4, and 6, the array substrate 100 further includes a second switching transistor T5. The first terminal of the second switching transistor T5 is electrically connected to the first node N1. The second switching transistor T5 includes a third sub-switching transistor T51 and a fourth sub-switching transistor T52. The third sub-switching transistor T51 includes a fourth channel portion 34 located within the active layer 30. The fourth sub-switching transistor T52 includes a fifth channel portion 35 located within the active layer 30. The fourth channel portion 34 is electrically connected to the first terminal of the second switching transistor T5, and the fifth channel portion 35 is electrically connected to the second terminal of the second switching transistor T5. There is a gap between the orthographic projection of the fourth channel portion 34 onto the substrate 20 and the orthographic projection of the fifth channel portion 35 onto the substrate 20. The resistivity of the fourth channel portion 34 is less than the resistivity of the fifth channel portion 35.

[0075] Referring to the accompanying drawings, the control terminal of the second switching transistor T5 is electrically connected to the first scan signal line ScanN1, the first electrode of the second switching transistor T5 is electrically connected to the first node N1, and the second electrode of the second switching transistor T5 is electrically connected to the first reset signal Vref1. Further, during the reset phase, the second switching transistor T5 is turned on by the low level of the first scan signal ScanN1, and the first reset signal Vref1 is applied to the first node N1, resetting the control terminal of the first driving transistor T3 and the first plate 51 of the storage capacitor 50.

[0076] Furthermore, the second switching transistor T5 includes a third sub-switching transistor T51 and a fourth sub-switching transistor T52, meaning the second switching transistor T5 is a dual-gate transistor. Specifically, the control terminals of the second switching transistor T5 include a third sub-control terminal 43 located in the third sub-switching transistor T51 and a fourth sub-control terminal 44 located in the fourth sub-switching transistor T52. The third sub-control terminal 43 and the fourth sub-control terminal 44 are electrically connected to the first scan signal ScanN1.

[0077] Compared to a single-gate transistor, setting the second switching transistor T5 as a dual-gate transistor helps reduce the leakage characteristics of the second switching transistor T5 itself. However, there is a fourth node N4 between the third sub-switching transistor T51 and the fourth sub-switching transistor T52. During the reset phase, the voltage at the fourth node N4 and the first node N1 often remain the same or similar. At the end of the reset phase, the level at the first scan signal ScanN1 will suddenly rise from a low level to a high level.

[0078] In related technologies, similar to the fifth node N5, the fourth node N4 is inherently an unstable node. Therefore, a sudden change in the first scan signal ScanN1 causes the voltage at the fourth node N4 to be coupled to a larger potential, resulting in a significant potential difference between the first node N1 and the fourth node N4. This potential difference leads to leakage between the first node N1 and the fourth node N4. Furthermore, because the structure between the first node N1 and the fourth node N4 is a semiconductor structure with high resistivity, the leakage process between them is relatively slow. During the light-emitting phase, continuous and slow leakage occurs between the first node N1 and the fourth node N4, causing flickering in the display and affecting the actual viewing experience.

[0079] In view of this, the present application embodiment adjusts the resistivity of the fourth channel portion 34 in the second sub-switch transistor T42 to reduce screen flicker. Specifically, the active layer 30 includes a fourth channel portion 34 and a fifth channel portion 35. The fourth channel portion 34 is a portion of the active layer 30 that overlaps with the orthographic projection of the third sub-control terminal onto the substrate 20. The fifth channel portion 35 is a portion of the active layer 30 that overlaps with the orthographic projection of the fourth sub-control terminal onto the substrate 20. The fourth channel portion 34 and the fifth channel portion 35 together form the channel structure of the second switch transistor T5.

[0080] The fourth channel portion 34 is electrically connected to the first terminal of the second switching transistor T5, that is, one end of the fourth channel portion 34 is electrically connected to the first node N1. The fifth communication portion is electrically connected to the second terminal of the second switching transistor T5, that is, one end of the fifth channel portion 35 is electrically connected to the first reset signal Vref1. The fourth channel portion 34 and the fifth channel portion 35 are two separate structures, and there is a gap between the orthographic projection of the fourth channel portion 34 onto the substrate 20 and the orthographic projection of the fifth channel portion 35 onto the substrate 20.

[0081] Based on this, the embodiments of this application adjust the fourth channel portion 34 to reduce its resistivity. The embodiments of this application do not limit how the resistivity of the fourth channel portion 34 is reduced. For example, the resistivity of the fourth channel portion 34 can be reduced by adjusting the number of ion implantations and the energy level. Alternatively, the resistivity of the fourth channel portion 34 can be reduced by performing plasma treatment on it. Optionally, the fourth channel portion 34 has the same or similar doping concentration as the first channel portion 31.

[0082] Furthermore, the resistivity of the adjusted fourth channel portion 34 is lower than that of the fifth channel portion 35, giving the fifth channel portion 35 stronger conductivity. In this design, since the fifth channel portion 35 is located between the first node N1 and the fourth node N4 and has strong conductivity, when there is a voltage difference between the fourth node N4 and the first node N1, current can quickly flow from the fourth node N4 through the fourth channel portion 34 to the first node N1. This allows the potential at the first node N1 to be consistent with the potential at the fourth node N4 for a short time, thereby reducing leakage between the first node N1 and the fourth node N4 during the light-emitting stage, reducing screen flicker, and improving display performance.

[0083] In some embodiments, referring to Figures 1, 2, 4, and 7, the active layer 30 further includes a first active structure 36, the two ends of which are respectively connected to a first channel portion 31 and a second channel portion 32. The array substrate 100 includes a shielding structure P, which is located on one side of the active layer 30 in the thickness direction of the substrate 20. The orthographic projection of the shielding structure P onto the substrate 20 overlaps with the orthographic projection of the first active structure 36 onto the substrate 20, and the shielding structure P is used to transmit a constant voltage potential.

[0084] The first active structure 36 is a semiconductor structure located between the first channel portion 31 and the second channel portion 32 in the active layer 30. Optionally, the first active structure 36, the first channel portion 31, and the second channel portion 32 are integrated into one structure. During the fabrication process, different degrees of doping are performed on the regions on both sides of the first active structure 36 to form the first channel portion 31 and the second channel portion 32 on both sides of the first active structure 36, respectively.

[0085] The first active structure 36 corresponds to the location of the fifth node N5. At the end of the charging phase, the level of the second scan signal ScanN2 will suddenly change from low to high. As can be seen from the attached figure, the first sub-control terminal 41 and the second sub-control terminal 42, which are used to receive the second scan signal ScanN2, are relatively close to the first active structure 36. Therefore, in related technologies, when the second scan signal ScanN2 changes abruptly, at least one of the first sub-control terminal 41 and the second sub-control terminal 42 will couple with the first active structure 36 and form a parasitic capacitance. This causes the potential at the first active structure 36 to rise along with the second scan signal ScanN2, resulting in a large difference between the potential of the active layer 30 at the first node N1 and the potential at the first active structure 36. Therefore, during the light emission phase, the first active structure 36 will continuously leak current to the structure of the active layer 30 at the first node N1 through the first channel portion 31, causing screen flickering.

[0086] In this embodiment, besides improving the flicker problem by reducing the resistivity of the first channel portion 31, a shielding structure P can also be used to improve the flicker problem. Specifically, a shielding structure P can be present at the corresponding position of the first active structure 36 in the array substrate 100 by adding a conductor structure or changing the original conductor structure layout. The shielding structure P is a conductor structure used to provide shielding. The shielding structure P and the first active structure 36 can have various positional relationships. For example, the shielding structure P can be located on the side of the first active structure 36 facing the substrate 20, or the shielding structure P can be located on the side of the first active structure 36 away from the substrate 20. The shielding structure P is used to transmit a constant voltage potential. This embodiment does not limit the specific type of signal for the constant voltage potential. Optionally, the shielding structure P can be used to transmit the first power signal VDD.

[0087] In this embodiment, by transmitting a constant voltage potential through the shielding structure P and having its orthographic projection on the substrate 20 overlap with the orthographic projection of the first active structure 36 on the substrate 20, the parasitic capacitance generated between at least one of the first sub-control terminal 41 and the second sub-control terminal 42 and the first active structure 36 is reduced by means of the shielding structure P. As a result, when the level at the second scan signal ScanN2 changes abruptly from low to high, the potential change at the first active structure 36, i.e., the fifth node N5, is reduced, thereby reducing the potential difference between the first node N1 and the fifth node N5. This design can reduce the leakage between the first node N1 and the fifth node N5, thereby improving the flickering problem of the display screen.

[0088] In some embodiments, referring to Figures 2, 4, and 8, the array substrate 100 further includes a storage capacitor 50. The storage capacitor 50 includes a first electrode 51 located within a first conductive layer and a second electrode 52 located on the side of the first electrode 51 facing away from the substrate. The control terminals of the first sub-switching transistor T41 and the second switching transistor T5 are located within the first conductive layer. The second electrode 52 includes a shielding structure P.

[0089] The storage capacitor 50 includes a first electrode 51 and a second electrode 52, with the orthographic projections of the first electrode 51 and the second electrode 52 on the substrate overlapping. The first electrode 51 is located on the side of the second electrode 52 facing the substrate, and the first electrode 51, the first sub-control terminal 41, and the second sub-control terminal 42 are all located within the first conductive layer. The first electrode 51 is electrically connected to the fifth node N5 and can be reused as the control terminal of the first driving transistor T3. The channel portion of the first driving transistor T3 is a partial structure in the active layer 30 that overlaps with the orthographic projection of the first electrode 51 on the substrate. Figure 8 only shows the arrangement of the active layer 30, the first conductive layer 40, the second electrode 52, and a few other cross-line structures in a local area of ​​the array substrate.

[0090] The second electrode 52 is the electrode in the storage capacitor 50 used for electrical connection to the first power signal VDD, and the first power signal VDD is a constant voltage potential. Based on this, this embodiment adjusts the size and layout of the second electrode 52 so that a portion of the structure in the second electrode 52 can be reused as a shielding structure P. The shielding structure P is the portion of the second electrode 52 whose orthographic projection is located outside the orthographic projection of the first electrode 51 on the substrate, and the orthographic projection of the shielding structure P on the substrate can overlap with the orthographic projection of the first active structure 36 on the substrate. Under this design, the shielding structure P can be formed without adding a new conductive layer in the array substrate 100, and the constant voltage potential required by the first power signal VDD can be met. This improves the screen flicker problem and simplifies the fabrication process of the array substrate 100, making it highly practical.

[0091] It should be noted that the specific positional relationship between the second electrode plate 52 and the first active structure 36 is not limited in this embodiment. The orthographic projection of the second electrode plate 52 on the substrate 20 may overlap with the orthographic projection of some or all of the structures in the first active structure 36 on the substrate 20, as long as the second electrode plate 52 can overlap with the orthographic projection of the first active structure 36 on the substrate 20 to form a shielding structure P.

[0092] In some embodiments, the orthographic projection of the second electrode 52 onto the substrate covers the orthographic projection of the first active structure 36 onto the substrate.

[0093] In this embodiment, the orthographic projection of the first active structure 36 onto the substrate is completely within the orthographic projection of the second electrode plate 52 onto the substrate. This improves the shielding effect of the second electrode plate 52 on the first active structure 36, thereby further reducing the parasitic capacitance generated between at least one of the first sub-control terminal 41 and the second sub-control terminal 42 and the first active structure 36, reducing the potential difference between the first node N1 and the fifth node N5, and improving the screen flicker problem.

[0094] In some embodiments, as shown in FIG1, FIG2, FIG4 and FIG7, the array substrate 100 further includes a second conductive layer 70 located on the side of the active layer 30 facing the substrate 20, and the shielding structure P is located within the second conductive layer 70.

[0095] The second conductive layer 70 is a conductive film layer located on the side of the active layer 30 near the substrate 20. The shielding structure P is disposed within the second conductive layer 70 and overlaps with the first active structure 36 as projected onto the substrate 20. The second conductive layer 70 may include only the shielding structure P, or it may include other structures; this embodiment does not limit this.

[0096] In related technologies, during the use of a display panel, light emitted by the display panel or ambient light may enter the interior of the display panel and be reflected at or below the substrate 20 to the active layer 30, thereby adversely affecting the performance of the thin-film transistors and causing problems such as display abnormalities.

[0097] In this embodiment, by setting the shielding structure P on the side of the active layer 30 close to the substrate 20, it can shield the first active structure 36 to improve the flicker problem. At the same time, the shielding structure P blocks some of the reflected light that propagates to the active layer 30, thereby improving the performance of the thin film transistors in the array substrate 100 and improving the display reliability of the subsequently formed display panel.

[0098] In some embodiments, please refer to Figures 4, 7 and 9, the aspect ratio of the first active structure 36 is greater than the aspect ratio of at least one of the first channel portion 31 and the second channel portion 32.

[0099] The aspect ratio of the first active structure 36 refers to the ratio of its width to its length. Depending on the actual layout of the active layer 30, the first active structure 36 can be linear, in which case its length is the dimension of the first active structure 36 along the direction of the corresponding line. Alternatively, the first active structure 36 can be curved or linear, in which case its extension direction changes at different positions, and its length is the sum of its extension lengths at each different position. The lengths of the first channel portion 31 and the second channel portion 32 are similarly determined, and this embodiment does not impose any limitations on them.

[0100] Furthermore, in this embodiment, the aspect ratio of the first active structure 36 is set to be greater than that of at least one of the first channel portion 31 and the second channel portion 32. Thus, the first active structure 36 has a larger width relative to at least one of the first channel portion 31 and the second channel portion 32. This design helps to increase the capacitance formed between the first active structure 36 and the shielding structure P, thereby further enhancing the shielding effect of the shielding structure P on the first active structure 36, reducing the risk of potential changes in the first active structure 36 due to the sudden change of the second scan signal ScanN2, thereby reducing the leakage between the first node N1 and the fifth node N5 and improving the flickering problem of the display screen.

[0101] In some embodiments, the active layer 30 is made of low-temperature polycrystalline silicon.

[0102] The active layer 30 is made of low-temperature polycrystalline silicon, indicating that the first switching transistor T4 is an LTPS-TFT. Compared to an IGZO-TFT, LTPS-TFT has higher mobility and lower resistance, resulting in less impact on signal transmission. However, LTPS-TFT is more prone to leakage, especially at low frequencies. Therefore, this embodiment further reduces the resistivity of the first channel portion 31 to facilitate rapid leakage between the first node N1 and the fifth node N5. This reduces screen flicker caused by slow leakage during the light-emitting stage, improving the display experience.

[0103] Secondly, please refer to Figures 1, 2, 4 and 10. This application provides a display panel 200, which includes an array substrate 100 as described in any of the preceding embodiments and a plurality of sub-pixels 60. The array substrate 100 includes a plurality of pixel circuits 10, and each pixel circuit 10 includes a first driving transistor T3 and a first switching transistor T4. The pixel circuits 10 are used to control the sub-pixels 60 to emit light.

[0104] It should be noted that the display panel 200 provided in this application embodiment can be an organic light-emitting display panel 200, a liquid crystal display panel 200, or a micro light-emitting diode display panel 200. This application embodiment does not limit the specific type of display panel 200. For ease of description, this application embodiment uses an organic light-emitting display panel 200 as an example for explanation.

[0105] In this embodiment, by adjusting the resistivity of the first channel portion 31 to be less than that of the second channel portion 32, when there is a certain voltage difference between the fifth node N5 and the first node N1, the current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31. In this way, the potential at the first node N1 can be kept consistent with the potential at the fifth node N5 in a short time, thereby reducing the leakage between the first node N1 and the fifth node N5 during the light-emitting stage, reducing the flicker of the display screen, and improving the display effect.

[0106] Furthermore, the display panel 200 in this application embodiment can possess the beneficial effects of the array substrate 100 in any of the aforementioned embodiments. For details, please refer to the foregoing description of the beneficial effects of the array substrate 100. This application embodiment will not repeat the details.

[0107] In some embodiments, the plurality of sub-pixels 60 includes first sub-pixels 60 and second sub-pixels 60 with different colors, and the plurality of pixel circuits 10 includes a first pixel circuit 10 for driving the first sub-pixels 60 and a second pixel circuit 10 for driving the second sub-pixels 60. The resistivity of the first switching transistor T4 in the first pixel circuit 10 corresponding to the first channel portion 31 is less than the resistivity of the first channel portion 31 corresponding to the first switching transistor T4 in the second pixel circuit 10.

[0108] In order to achieve the color emission function, the display panel 200 may include multiple types of sub-pixels 60 with different colors. The first sub-pixel 60 and the second sub-pixel 60 are sub-pixels 60 with different emission colors. The specific emission colors of the first sub-pixel 60 and the second sub-pixel 60 are not limited in this embodiment.

[0109] The first pixel circuit 10 is a circuit structure used to control whether the first sub-pixel 60 emits light or not, and the second pixel circuit 10 is a circuit structure used to control whether the second sub-pixel 60 emits light or not. In order to reduce the fabrication and design difficulty of the array substrate 100, the number and connection method of the thin film transistors and storage capacitors 50 in the first pixel circuit 10 and the second pixel circuit 10 can be kept the same. Furthermore, both the first pixel circuit 10 and the second pixel circuit 10 include a first driving transistor T3 and a first switching transistor T4.

[0110] Considering the different sensitivities of the human eye to different colors of light and some other factors, the contribution of the first sub-pixel 60 and the second sub-pixel 60 of different colors to the display effect will also be different. Based on this, the embodiments of this application carry out differentiated designs for the first pixel circuit 10 used to control the first sub-pixel 60 and the second pixel circuit 10 used to control the second sub-pixel 60.

[0111] Specifically, in this embodiment, for cases where the first sub-pixel 60 has a greater impact on the display effect than the second sub-pixel 60, the resistivity of the first channel portion 31 corresponding to the first switching transistor T4 in the first pixel circuit 10 is set to be less than the resistivity of the first channel portion 31 corresponding to the first switching transistor T4 in the second pixel circuit 10. This makes the first channel portion 31 in the first pixel circuit 10 have stronger conductivity than the first channel portion 31 in the second pixel circuit 10, thereby further reducing the flickering problem caused by the first sub-pixel 60 emitting light and improving the display effect.

[0112] It should be noted that in the first pixel circuit 10, the resistivity of the first channel portion 31 is less than the resistivity of the second channel portion 32. However, depending on the degree of influence of the second sub-pixel 60 on the display effect, in the second pixel circuit 10, the resistivity of the first channel portion 31 may be less than the resistivity of the second channel portion 32, or the resistivity of the first channel portion 31 may be equal to the resistivity of the second channel portion 32. This embodiment does not impose any limitations on this.

[0113] In some embodiments, the first sub-pixel 60 is used to emit green light.

[0114] Compared to other colors, the human eye is more sensitive to green light. If the green light flickers, the user can perceive the change in the display effect. In view of this, the embodiments of this application have adjusted the first pixel circuit 10 used to control the first sub-pixel 60, and reduced the resistivity of the first channel portion 31 in the first pixel circuit 10, thereby helping to reduce the flickering problem corresponding to green light and improve the user's viewing experience.

[0115] Thirdly, referring to FIG11, this application embodiment provides a display device 300, which includes the display panel in any of the foregoing embodiments.

[0116] It should be noted that the display device 300 in this application embodiment can have the beneficial effects of the array substrate and display panel in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the array substrate and display panel. This application embodiment will not repeat the details.

[0117] Fourthly, referring to Figures 1 to 4 and Figure 12, this application provides a method for fabricating an array substrate 100. The array substrate 100 includes a first switching transistor T4 and a first driving transistor T3. The control terminal of the first driving transistor T3 is electrically connected to a first node N1. The first electrode of the first switching transistor T4 is electrically connected to the second electrode of the first driving transistor T3, and the second electrode of the first switching transistor T4 is electrically connected to the first node N1. The first switching transistor T4 includes a first sub-switching transistor T41 and a second sub-switching transistor T42. The fabrication method includes:

[0118] S100: An active layer is formed on one side of the substrate.

[0119] In step S100, the first sub-switch transistor T41 includes a first channel portion 31 located within the active layer 30, and the second sub-switch transistor T42 includes a second channel portion 32 located within the active layer 30.

[0120] S110: Plasma treatment is performed on the first channel section.

[0121] In step S110, the resistivity of the first channel portion 31 after plasma treatment is less than that of the second channel portion 32. Thus, when the potential at the fifth node N5 located between the first channel portion 31 and the second channel portion 32 is increased, current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31. This allows the potential at the first node N1 to be consistent with the potential at the fifth node N5 in a short time, thereby reducing the leakage between the first node N1 and the fifth node N5 during the light-emitting stage, reducing the flicker of the displayed image, and improving the display effect.

[0122] It should be noted that in some other embodiments, in step S110, the first channel portion 31 may not be subjected to plasma treatment, but instead, the first channel portion 31 may be subjected to secondary doping treatment by ion implantation, so that the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32. In this way, the resistivity of the first channel portion 31 can also be less than the resistivity of the second channel portion 32, thereby improving the screen flicker problem.

[0123] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0124] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, comprising: Substrate; An active layer is disposed on one side of the substrate; A first driving transistor, the control terminal of the first driving transistor is electrically connected to a first node; A first switching transistor, wherein a first terminal of the first switching transistor is electrically connected to a second terminal of the first driving transistor, and the second terminal of the first switching transistor is electrically connected to the first node, and the first switching transistor includes a first sub-switching transistor and a second sub-switching transistor. The first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer. The first channel portion is electrically connected to the second terminal of the first switch transistor, and the second channel portion is electrically connected to the first terminal of the first switch transistor. There is a gap between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate. The resistivity of the first channel is less than that of the second channel.

2. The array substrate according to claim 1, wherein, The doping concentration in the first channel is greater than the doping concentration in the second channel.

3. The array substrate according to claim 2, characterized in that, The doping concentration of the first channel is E, which satisfies: 10¹² particles / cm⁻³ ≤ E ≤ 10¹⁵ particles / cm⁻³.

4. The array substrate according to claim 2, wherein, The ratio of the doping concentration in the first channel to the doping concentration in the second channel is a, where a satisfies: 3≤a≤200.

5. The array substrate according to claim 1, characterized in that, The first channel section is subjected to plasma treatment.

6. The array substrate according to claim 1, wherein, The control terminal of the first driving transistor includes a third channel portion located within the active layer, wherein the resistivity of the first channel portion is less than the resistivity of the third channel portion.

7. The array substrate according to claim 1 further includes a second switching transistor, the first electrode of the second switching transistor being electrically connected to the first node, and the control terminal of the second switching transistor including a third sub-switching transistor and a fourth sub-switching transistor; The third sub-switch transistor includes a fourth channel portion located within the active layer, the fourth sub-switch transistor includes a fifth channel portion located within the active layer, the fourth channel portion is electrically connected to a first terminal of the second switch transistor, the fifth channel portion is electrically connected to a second terminal of the second switch transistor, and there is a gap between the orthographic projection of the fourth channel portion on the substrate and the orthographic projection of the fifth channel portion on the substrate. in, The resistivity of the fourth channel is less than that of the fifth channel.

8. The array substrate according to claim 1, wherein, The active layer further includes a first active structure, the two ends of which are respectively connected to the first channel portion and the second channel portion; The array substrate further includes a shielding structure located on one side of the active layer in the thickness direction of the substrate. The orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the first active structure on the substrate, and the shielding structure is used to transmit a constant voltage potential.

9. The array substrate according to claim 8 further includes a storage capacitor, the storage capacitor including a first electrode plate located within the first conductive layer and a second electrode plate located on the side of the first electrode plate opposite to the substrate, and the control terminal of the first switching transistor is located within the first conductive layer. in, The second electrode plate includes the shielding structure.

10. The array substrate according to claim 9, wherein, The orthographic projection of the second electrode on the substrate covers the orthographic projection of the first active structure on the substrate.

11. The array substrate according to claim 8, further comprising a second conductive layer located on the side of the active layer facing the substrate, wherein the shielding structure is located within the second conductive layer.

12. The array substrate according to claim 8, wherein, The aspect ratio of the first active structure is greater than the aspect ratio of at least one of the first channel portion and the second channel portion.

13. The array substrate according to claim 1, wherein, The active layer is made of low-temperature polycrystalline silicon.

14. A display panel comprising an array substrate as described in any one of claims 1 to 13 and a plurality of sub-pixels, the array substrate comprising a plurality of pixel circuits, the pixel circuits comprising a first driving transistor and a first switching transistor, the pixel circuits being configured to control the sub-pixels to emit light.

15. The display panel according to claim 14, wherein, The plurality of sub-pixels include a first sub-pixel and a second sub-pixel with different colors, and the plurality of pixel circuits include a first pixel circuit for driving the first sub-pixel and a second pixel circuit for driving the second sub-pixel. Wherein, the resistivity of the first switching transistor in the first pixel circuit corresponding to the first channel portion is less than the resistivity of the first switching transistor in the second pixel circuit corresponding to the first channel portion.

16. The display panel according to claim 15, wherein, The first sub-pixel is used to emit green light.

17. A display device comprising a display panel as described in any one of claims 14 to 16.

18. A method for fabricating an array substrate, the array substrate comprising a first switching transistor and a first driving transistor, wherein the control terminal of the first driving transistor is electrically connected to a first node, a first electrode of the first switching transistor is electrically connected to a second electrode of the first driving transistor, the second electrode of the first switching transistor is electrically connected to the first node, and the first switching transistor comprises a first sub-switching transistor and a second sub-switching transistor; the fabrication method comprising: An active layer is formed on one side of the substrate, the first sub-switch transistor includes a first channel portion located within the active layer, and the second sub-switch transistor includes a second channel portion located within the active layer; The first channel portion is subjected to plasma treatment to make the resistivity of the first channel portion less than that of the second channel portion.

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