Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (10) and at least one test unit (20). The base substrate (10) has a display area (11) and a non-display area (12). The test unit (20) is located in the non-display area (12), and the test unit (20) comprises a test element (21), test pads (22) and traces (23), wherein each port of the test element (21) corresponds to a test pad (22) and a trace (23), and is connected to the corresponding test pad (22) by means of the corresponding trace (23); and the orthographic projections of the test pads (22) on the base substrate are circular.

Description

Array substrate and display device Cross-reference to related applications

[0001] This disclosure claims priority to Chinese patent application No. 2024115354708, filed on October 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0003] The array substrate is the main structure of a display and requires relevant testing to ensure product yield. Current testing of array substrates includes Electronic Performance Measurement (EPM) of the Thin Film Transistor (TFT). EPM involves setting up TFT test element groups (TEGs) on the array substrate, and using customized probes from the EPM equipment to penetrate the square pads of the TEGs for testing. If even one probe deviates from the square pad, the entire substrate risks being scrapped. Summary of the Invention

[0004] This disclosure provides an array substrate and a display device, which aims to at least partially solve the problem of probes easily deviating from the pads.

[0005] In a first aspect of this disclosure, an array substrate is provided, the array substrate comprising: a substrate having a display area and a non-display area located on one side of the display area; and at least one test unit located within the non-display area; the test unit comprising a test element, a test pad, and a trace; each port of the test element corresponding to the test pad and the trace, and connected to the corresponding test pad through the corresponding trace; the orthographic projection of the test pad on the substrate is circular.

[0006] In some embodiments, the test element is a transistor with three ports, and the test unit includes three test pads and three traces, each of which corresponds to one of the three ports of the test element.

[0007] In some embodiments, the centers of the orthographic projections of the three test pads onto the substrate are not collinear.

[0008] In some embodiments, the orthographic projections of two of the test pads on the substrate are located on a first side of the orthographic projection of the test element on the substrate; the orthographic projection of the other test pad on the substrate is located on a second side of the orthographic projection of the test element on the substrate, the second side being opposite to the first side.

[0009] In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is a triangle.

[0010] In some embodiments, the line connecting the centers of the two test pads located on the same side of the test element is parallel to one side of the triangle.

[0011] In some embodiments, the array substrate includes a plurality of test units, and the plurality of test areas are arranged in at least one row and multiple columns; the orthographic projection of two adjacent test areas in the same row onto the substrate is a point-symmetric pattern.

[0012] In some embodiments, the plurality of test areas are arranged in at least two rows; the orthographic projection of two adjacent test areas in the same column onto the substrate is an axisymmetric figure, and the axis of symmetry is parallel to the row direction.

[0013] In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the distance between the centers of the orthographic projections of the three test pads onto the substrate is equal.

[0014] In some embodiments, the orthographic projections of the three test pads on the substrate are spaced apart along a first direction.

[0015] In some embodiments, the orthographic projections of the three test pads on the substrate are located on the same side of the orthographic projections of the test element on the substrate; the orthographic projections of the test pads and the test element on the substrate are spaced apart along a second direction, which intersects the first direction.

[0016] In some embodiments, the non-display area includes test areas corresponding one-to-one with the test units, and the test units are located within the corresponding test areas; the orthographic projection of the test area on the substrate is rectangular.

[0017] In some embodiments, the array substrate includes a plurality of the test units, and the plurality of test areas are arranged in an array.

[0018] In some embodiments, the orthographic projections of the three test pads onto the substrate are circles of equal size, and the centers of the orthographic projections of the three test pads onto the substrate are collinear.

[0019] In some embodiments, one side of the orthographic projection of two adjacent test areas onto the substrate coincides.

[0020] In some embodiments, the array substrate further includes: a pixel circuit located in the display area; the pixel circuit includes a plurality of thin-film transistors, and the test element has the same material, thickness and aspect ratio as the thin-film transistors.

[0021] In a second aspect of this disclosure, a display device is provided, the display device comprising an array substrate as provided in the first aspect. Attached Figure Description

[0022] The above and various other advantages and benefits of this disclosure will become clear to those skilled in the art upon reading the following detailed description of preferred embodiments.

[0023] Figure 1 shows a top view of the test component group in the related technology.

[0024] Figure 2 shows a schematic diagram of the test unit in Figure 1.

[0025] Figure 3 shows a schematic diagram of the offset of the probe inserted into the pad in Figure 2.

[0026] Figure 4 shows a top view of an array substrate in one or more embodiments of the present disclosure.

[0027] Figure 5 shows a top view of a test unit in one embodiment of this disclosure.

[0028] Figure 6 shows a schematic diagram of the offset of the probe inserted into the pad in Figure 5.

[0029] Figure 7 shows a schematic diagram of the distribution of the test units in Figure 5.

[0030] Figure 8 shows a schematic diagram of the process of the solder pad penetrating the probe as shown in Figure 7.

[0031] Figure 9 shows a top view of the test unit in another embodiment of this disclosure.

[0032] Figure 10 shows a schematic diagram of the offset of the pad insertion probe in Figure 9.

[0033] Figure 11 shows a schematic diagram of the distribution of the test units in Figure 9.

[0034] Figure 12 illustrates a schematic diagram of the electrical characteristic testing process in one or more embodiments of this disclosure.

[0035] Explanation of reference numerals in the attached figures: 10': Pad; 11': Source pad; 12': Drain pad; 13': Gate pad; 20': TFT under test; 30': Connection trace; 40': Test equipment; 41': Probe; 10: Substrate; 11: Display area; 12: Non-display area; 120: Test area; 20: Test unit; 21: Test element; 22: Test pad; 23: Trace. Detailed Implementation

[0036] The present disclosure will now be further described with reference to the accompanying drawings and specific embodiments. The following description is merely illustrative of the basic principles of the present disclosure and is not intended to limit it.

[0037] To enable those skilled in the art to more clearly understand this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0038] Figure 1 is a top view of a TEG in the related technology. Referring to Figure 1, the TEG includes multiple test units, which are arranged in an array on the substrate. Each test unit includes a source pad 11', a drain pad 12', a gate pad 13', a TFT under test 20', and a connection trace 30'. The source pad 11', drain pad 12', gate pad 13', and TFT under test 20' are arranged sequentially at intervals along the row direction of the test unit array. The source pad 11', drain pad 12', and gate pad 13' are connected to the TFT under test 20' through the connection trace 30'. The connection trace 30' connected to the source pad 11' is located on the first side of the TFT under test 20', the connection trace 30' connected to the drain pad 12' is located on the second side of the TFT under test 20', and the connection trace 30' connected to the gate pad 13' is located on the side of the TFT under test 20' closest to the gate pad 13'. The first side and the second side of the TFT 20' to be tested are opposite each other and are adjacent to the side of the TFT 20' to be tested that is close to the gate pad 13'.

[0039] Figure 2 is a schematic diagram of the test unit in Figure 1. Referring to Figure 2, the orthographic projection of the test unit on the substrate is a rectangle with a length X0 = 450 μm and a width Y0 = 200 μm. The orthographic projections of the source pad 11', drain pad 12', and gate pad 13' on the substrate are squares with a side length X1 = 100 μm. The pad spacing X2 = 50 μm. The width W of the placement space for the TFT 20' to be tested is 50 μm, and the critical dimension CD of the connection trace 30' is 16 μm. At this time, the area of ​​the orthographic projection of the test unit on the substrate is X0 × Y0 = 90000 μm2, and the area of ​​the orthographic projection of the pads on the substrate is X1 × X1 = 10000 μm2. The area ratio of the pads to the orthographic projection area of ​​the test unit on the substrate is 3 × X1 × X1 / (X0 × Y0) = 33.33%. Figure 3 is a schematic diagram of the offset of the probe inserted into the pad in Figure 2. Please refer to Figure 3. The maximum offset of the probe in the pad is X3 = X1 / 2 = 50μm, that is, the tolerance offset of the probe is 50μm.

[0040] Figure 4 is a top view of an array substrate according to one or more embodiments of the present disclosure. Referring to Figure 4, a first aspect embodiment of the present disclosure provides an array substrate including a substrate 10 and at least one test unit 20. The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The test unit 20 is located within the non-display area 12.

[0041] Figure 5 is a top view of a test unit in one embodiment of this disclosure. Referring to Figure 5, the test unit 20 includes a test element 21, a test pad 22, and a trace 23. Each port of the test element 21 corresponds to a test pad 22 and a trace 23, and is connected to the corresponding test pad 22 through the corresponding trace 23. The orthographic projection of the test pad 22 on the substrate 10 is circular.

[0042] Figure 6 is a schematic diagram of the offset of the probe inserted into the pad in Figure 5. Referring to Figure 6, taking the orthogonal projection of the test pad 22 on the substrate 10 as a circle with radius R = 60 μm as an example, the area of ​​the orthogonal projection of the test pad 22 on the substrate 10 is π × R × R = 11309.73 μm2. The maximum offset of the probe in the pad is X3 = 60 μm, that is, the probe's tolerance offset is 60 μm. Compared with Figure 3, the probe's tolerance offset increases from 50 μm to 60 μm. The probe's tolerance offset increases by (60 μm - 50 μm) / 50 μm = 20%, while the area of ​​the pad only increases by (11309.73 μm2 - 10000 μm2) / 10000 μm2 = 13.09%. Therefore, the test pads projected onto the substrate in this disclosure are circular. Compared with square pads of the same area, this can increase the probe's tolerance for offset, increase the difficulty of the probe offsetting off the pad, and reduce the risk of the probe being scrapped due to offsetting off the square pad.

[0043] In summary, the array substrate described above includes a substrate 10 and at least one test unit 20. The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The test unit 20 is located within the non-display area 12 and will not affect normal display. The test unit 20 includes a test element 21, test pads 22, and traces 23. Each port of the test element 21 corresponds to a test pad 22 and a trace 23, and is connected to the corresponding test pad 22 through the corresponding trace 23. Probes are inserted into each test pad 22 of the test unit 20 to test the test element 21. The orthographic projection of the test pad 22 on the substrate 10 is circular. Compared with a square pad of the same area, the probe's tolerance for offset is improved, thereby increasing the difficulty of the probe offsetting off the pad, reducing the risk of the probe being scrapped due to offset off the square pad, improving the probe's lifespan, and ensuring the test effect.

[0044] In some embodiments, referring to FIG5, the test element 21 can be a transistor with three ports, and the test unit 20 includes three test pads 22 and three traces 23, which correspond one-to-one with the three ports of the test element 21.

[0045] For example, the three ports of a transistor may include a source, a drain, and a gate, or they may include a collector, an emitter, and a base.

[0046] In one possible embodiment, referring to Figure 5, the centers of the orthographic projections of the three test pads 22 onto the substrate 10 may not be collinear. In this case, the line connecting the centers of the orthographic projections of the three test pads 22 onto the substrate 10 can form a triangle.

[0047] For example, referring to Figure 5, the orthographic projections of two test pads 22 on the substrate 10 can be located on the first side of the orthographic projection of the test element 21 on the substrate 10. The orthographic projection of the other test pad 22 on the substrate 10 can be located on the second side of the orthographic projection of the test element 21 on the substrate 10. The second side of the orthographic projection of the test element 21 on the substrate 10 is opposite to the first side of the orthographic projection of the test element 21 on the substrate 10. By placing the test element 21 in the middle of the three test pads 22, the blank area in the middle of the three test pads 22 can be fully utilized, saving the space occupied by the test unit 20.

[0048] For example, the three test pads 22 can be designated as a first test pad, a second test pad, and a third test pad, with the second test pad located between the first and third test pads. The orthographic projections of the first and third test pads onto the substrate 10 are located on the first side of the orthographic projection of the test element 21 onto the substrate 10. The orthographic projection of the second test pad onto the substrate 10 is located on the second side of the orthographic projection of the test element 21 onto the substrate 10.

[0049] For example, the triangle formed by the center line connecting the orthographic projections of the three test pads 22 onto the substrate 10 can be an acute triangle.

[0050] For example, referring to Figure 5, the orthographic projections of the three test pads 22 onto the substrate 10 can be circles of equal size. The distance between the centers of the orthographic projections of the three test pads 22 onto the substrate 10 is equal. In this case, the line connecting the centers of the orthographic projections of the three test pads 22 onto the substrate 10 can form an equilateral triangle. This provides a larger space in the blank area between the three test pads 22, facilitating the placement of test components.

[0051] In some embodiments, referring to FIG5, the non-display area 12 includes test areas 120 corresponding one-to-one with the test units 20, and the test units 20 are located within the corresponding test areas 120. The orthographic projection of the test area 120 on the substrate 10 can be triangular to match the setting of the test pads 22.

[0052] For example, the center line connecting two test pads 22 located on the same side of the test element 21 can be parallel to one side of the orthogonal projection of the test area 120 onto the substrate 10. Again, taking three test pads 22 as an example, namely the first test pad, the second test pad, and the third test pad, the second test pad is located between the first and third test pads, the first and third test pads are located on the same side of the test element 21, and the center line connecting the orthogonal projections of the first and third test pads onto the substrate 10 is parallel to one side of the orthogonal projection of the test area 120 onto the substrate 10.

[0053] For example, the orthographic projection of the test area 120 onto the substrate 10 can be an equilateral triangle.

[0054] Please refer to Figure 5. Taking the orthographic projection of the test pad 22 on the substrate 10 as a circle with radius R = 60 μm as an example, the orthographic projection of the test unit on the substrate (i.e., the test area 120) is an equilateral triangle with side length L = 380 μm. The spacing of the test pads 22 is D = 35 μm. The shortest distance S1 between the orthographic projection of the test pad 22 on the substrate 10 and the edge of the test area 120 is 5 μm. The distance S2 between the center of the orthographic projection of the test pad 22 on the substrate 10 and the vertex of the test area 120 is S2 = (R / 2 + S1) / sin(30° / 2) = 130 μm. The width W of the placement space for the test component 21 is W = (L / 2) × tan60° - (S2 + 2 × 2 × R + S1) = 14 μm. The critical dimension CD of the trace 30 is 10 μm. At this point, the area of ​​the test unit's orthographic projection on the substrate is L×(L / 2)×tan60° / 2=62527.03μm2, and the area ratio of the test pad 22 relative to the orthographic projection of the test unit on the substrate is 3×π×R×R / (L×(L / 2)×tan60° / 2)=54.26%. Compared with Figure 3, the area of ​​the test unit's orthographic projection on the substrate decreases from 90000μm2 to 62527.03μm2, and the area ratio of the test pad relative to the test unit increases from 33.33% to 54.26%. Therefore, the arrangement of the test units in this disclosure can improve the space utilization within the test units and reduce the area occupied by the test units, which is beneficial for setting up a larger number of test units and saving the effective area of ​​the array substrate. In some embodiments, the radius R of the orthographic projection of the test pad 22 on the substrate 10, the critical dimension CD of the trace 30, etc., can be adjusted according to actual conditions.

[0055] Figure 7 is a schematic diagram of the distribution of the test units in Figure 5. Referring to Figure 7, exemplarily, the array substrate may include multiple test units 20, and multiple test areas 120 arranged in at least one row and multiple columns. The orthographic projection of two adjacent test areas 120 in the same row onto the substrate 10 is a point-symmetric pattern. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0056] For example, referring to Figure 7, multiple test areas 120 are arranged in at least two rows. The orthographic projection of two adjacent test areas 120 in the same column onto the substrate 10 is an axisymmetric figure, and the axis of symmetry is parallel to the row direction. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0057] For example, referring to Figure 7, the orthographic projections of two adjacent test areas 120 on the substrate 10 can overlap along one edge. This facilitates the neat arrangement of the test areas 120 and saves space occupied by the non-display area 12.

[0058] Figure 8 is a schematic diagram of the process of inserting the probe into the pad in Figure 7. Please refer to Figure 8. The twelve probes are double-sided crimped. First, the test element 21 in the test area 120 with one arrangement is tested. Then, the array substrate 10 is rotated 180° to test the test element 21 in the test area 120 with another arrangement.

[0059] Figure 9 is a top view of the test unit in another embodiment of this disclosure. Referring to Figure 9, in another possible embodiment, the orthographic projections of the three test pads 22 on the substrate 10 can be arranged at intervals along a first direction. In this case, the orthographic projections of the three test pads 22 on the substrate 10 are located in the same row.

[0060] Taking the three test pads 22 as an example, which can be designated as the first test pad, the second test pad, and the third test pad, with the second test pad located between the first and third test pads, the orthographic projections of the first, second, and third test pads on the substrate 10 are arranged in a row.

[0061] For example, referring to Figure 9, the orthographic projections of the three test pads 22 on the substrate 10 can be located on the same side as the orthographic projection of the test element 21 on the substrate 10. The orthographic projections of the test pads 22 and the test element 21 on the substrate 10 are arranged at intervals along a second direction, which intersects with the first direction. In this way, the test element 21 and the traces 30 are all located on the same side of the three test pads 22, which facilitates the connection of the test element 21 to the three test pads 22 through the traces 30, and reduces the space occupied by the traces 30, thereby saving space occupied by the test unit 20.

[0062] For example, the second direction may be perpendicular to the first direction, and the orthographic projections of one of the three test pads 22 and the test element 21 on the substrate 10 are spaced apart along the second direction.

[0063] For example, referring to Figure 9, the orthographic projections of the three test pads 22 onto the substrate 10 can be circles of equal size. The centers of the orthographic projections of the three test pads 22 onto the substrate 10 are collinear. In this case, the centers of the orthographic projections of the three test pads 22 onto the substrate 10 are collinear and their areas are the same, so that the area occupied by each test pad 22 can be maximized, and the space occupied by the test unit is not wasted.

[0064] In some embodiments, referring to FIG9, the non-display area 12 includes test areas 120 corresponding one-to-one with the test units 20, and the test units 20 are located within the corresponding test areas 120. The orthographic projection of the test area 120 on the substrate 10 can be rectangular to match the setting of the test pads 22.

[0065] For example, the orthographic projection of the test area 120 onto the substrate 10 can be rectangular.

[0066] Referring to Figure 9, taking the orthographic projection of the test pad 22 onto the substrate 10 as a circle with radius R = 60 μm as an example, the orthographic projection of the test unit onto the substrate (i.e., the test area 120) is a rectangle with length X0 = 450 μm and width Y0 = 200 μm. The spacing between the test pads 22 is D = (X0 / 3 - R) = 30 μm, the width of the space for placing the test component 21 is W = 50 μm, and the critical dimension CD of the trace 30 is 10 μm. In this case, the area of ​​the orthographic projection of the test unit onto the substrate is X0 × Y0 = 90000 μm², and the area ratio of the test pad 22 relative to the area of ​​the orthographic projection of the test unit onto the substrate is 3 × π × R × R / (X0 × Y0) = 37.70%. Compared to Figure 3, the area of ​​the orthographic projection of the test unit onto the substrate remains unchanged, but the area ratio of the test pad relative to the test unit increases from 33.33% to 37.70%.

[0067] The radius R of the orthographic projection of the test pad 22 onto the substrate 10 and the critical dimension CD of the trace 30 can be adjusted according to the actual situation. For example, the orthographic projection of the test pad 22 onto the substrate 10 may be a circle with radius R = 70 μm, and the orthographic projection of the test unit onto the substrate (i.e., the test area 120) may still be a rectangle with length X0 = 450 μm and width Y0 = 200 μm. The spacing between the test pads 22 may be D = (X0 / 3 - R) = 10 μm, the width W of the space for placing the test component 21 may be 50 μm, and the critical dimension CD of the trace 30 may be 3 μm. In this case, the area of ​​the orthographic projection of the test unit onto the substrate is X0 × Y0 = 90000 μm², and the area ratio of the test pad 22 to the area of ​​the orthographic projection of the test unit onto the substrate is 3 × π × R × R / (X0 × Y0) = 51.31%. Compared to Figure 3, the area of ​​the test unit's orthographic projection on the substrate remains unchanged, while the area ratio of the test pad to the test unit increases from 33.33% to 51.31%. Therefore, the arrangement of the test units in this disclosure can improve the space utilization within the test units without changing the area occupied by the test units.

[0068] In some embodiments, the probe's tolerance offset is further increased. Figure 10 is a schematic diagram of the probe offset in Figure 9. Referring to Figure 9, when the orthographic projection of the test pad 22 on the substrate 10 is a circle with radius R = 70 μm, the maximum offset of the probe in the pad is X3 = 70 μm, that is, the probe's tolerance offset is 70 μm. Compared with Figure 6, the probe's tolerance offset increases from 60 μm to 70 μm. Compared with Figure 3, the probe's tolerance offset increases from 50 μm to 70 μm.

[0069] Figure 11 is a schematic diagram of the distribution of the test units in Figure 9. Referring to Figure 11, by way of example, the array substrate may include multiple test units 20 and multiple test areas 120 arranged in an array. This facilitates the neat arrangement of the test areas 120 and saves the space occupied by the non-display area 12.

[0070] For example, referring to Figure 11, the orthographic projections of two adjacent test areas 120 on the substrate 10 can overlap along one edge. This facilitates the neat arrangement of the test areas 120 and saves space occupied by the non-display area 12.

[0071] In some embodiments, the array substrate may further include pixel circuitry located in the display area 11. The pixel circuitry includes multiple thin-film transistors, and the test element 21 is identical to the thin-film transistors in material, thickness, and aspect ratio.

[0072] Semiconductor photolithography follows a sequence of cleaning, deposition, exposure, development, etching, and lift-off to form film layers with a pattern identical to the photomask, such as source / drain (SD) layers, gate (Gate) layers, semiconductor layers, and gate insulator (GI) layers. The source / drain, gate, semiconductor, and gate insulator layers work together to form a TFT. However, the characteristics of the TFTs in the active area (AA) cannot be directly obtained from the above process; currently, EPM (Engineering Processing) is performed by placing TFT TEGs in the non-display area.

[0073] The test unit 20 disclosed herein serves as a TFT TEG. The transistor serving as test element 21 is fabricated at the same time and using the same process as the TFT within the AA, and its materials, film thickness, aspect ratio, etc., are all consistent with the TFT within the AA. Therefore, the test results of the transistor serving as test element 21 can reflect the characteristics of the TFT within the AA. Each of the three ports of the transistor serving as test element 21 is connected to a test pad 22 via a trace 23. By simultaneously inserting the probes of the test equipment into the three test pads 22 connected to one transistor, the electrical characteristics of the transistor serving as test element 21 can be tested. Thus, the electrical characteristics of the TFT within the AA can be determined from the test results of the transistor serving as test element 21.

[0074] Figure 12 is a schematic diagram of the EPM process in one or more embodiments of this disclosure. Referring to Figure 1, the probes 41' of the test device 40' are inserted into the three test pads 22 of the transistor, which serves as the test element 21, and connected by the traces 23. The pre-set test signal is input to the test element 21, and the feedback signal from the test element 21 is received and processed to perform various tests, such as threshold voltage Vth, mobility, dynamic range DR Range, subthreshold swing SS, on-current Ion, off-current Ioff, hysteresis Hys, contact resistance Rc, load resistance Rs, capacitance Cap, etc.

[0075] For example, the test apparatus may include twelve probes. Each probe inserts into one test pad 22, and the twelve probes can insert into twelve test pads 22 simultaneously (using single-sided or double-sided crimping). Since each test element 21 is connected to three test pads 22, the twelve probes can simultaneously insert into four pads connected to the test elements 21. The goal of each probe is to insert into the center point of the corresponding test pad 22.

[0076] However, probes undergo plastic deformation during long-term use, causing some probes to shift. Some probes may not be centered on their corresponding pads. Because probes are precision components and cannot be repaired, and given their high cost and long lead times, if even one probe shifts off-center from a pad, it risks being rendered unusable.

[0077] A second aspect of this disclosure provides a display device including an array substrate as provided in the first aspect embodiment.

[0078] An array substrate and display device according to one or more embodiments of this application include a substrate and at least one test unit. The substrate has a display area and a non-display area located on one side of the display area. The test unit is located in the non-display area and does not affect normal display. The test unit includes test elements, test pads, and traces. Each port of the test element corresponds to a test pad and a trace, and is connected to the corresponding test pad through the corresponding trace. Customized probes of the EPM device are inserted into each test pad of the test unit to test the test element. The orthographic projection of the test pad on the substrate is circular. Compared with a square pad of the same area, the probe's tolerance for offset is improved, thereby increasing the difficulty of the probe offsetting off the pad and reducing the risk of the probe being scrapped due to offset off the square pad.

[0079] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0080] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0081] In this disclosure, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0082] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0083] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

[0084] The foregoing description has described specific embodiments, which, along with other embodiments, are covered within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than those shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily follow the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also feasible or advantageous.

[0085] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0086] It should be understood that the above-described embodiments are merely illustrative of the purpose of this disclosure and are not intended to limit the scope of this disclosure. Those skilled in the art can implement this disclosure in other ways without departing from its basic spirit and characteristics. The scope of this disclosure is determined by the appended claims, and any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be covered herein.

Claims

1. An array substrate, comprising: a substrate (10) having a display area (11) and a non-display area (12) located at one side of the display area (11) ; and at least one test unit (20) located in the non-display area (12) ; the test unit (20) comprises a test element (21), a test pad (22) and a trace (23) ; each port of the test element (21) corresponds to the test pad (22) and the trace (23), and is connected to the corresponding test pad (22) through the corresponding trace (23) ; the orthogonal projection of the test pad (22) on the substrate (10) is circular. The test element (21) is a transistor with three ports, the test unit (20) comprises three test pads (22) and three traces (23), and the three test pads (22) and the three traces (23) correspond to the three ports of the test element (21) one by one.

2. The array substrate according to claim 1, wherein, The centers of the orthogonal projections of the three test pads (22) on the substrate (10) are not collinear.

3. The array substrate according to claim 2, wherein, The orthogonal projections of two test pads (22) on the substrate (10) are located on a first side of the orthogonal projection of the test element (21) on the substrate (10), and the orthogonal projection of the other test pad (22) on the substrate (10) is located on a second side of the orthogonal projection of the test element (21) on the substrate (10), and the second side is opposite to the first side.

4. The array substrate according to claim 3, wherein, The non-display area (12) comprises a test area (120) corresponding to the test unit (20), and the test unit (20) is located in the corresponding test area (120) ; the orthogonal projection of the test area (120) on the substrate (10) is a triangle.

5. The array substrate according to claim 4, wherein, The center line of two test pads (22) located on the same side of the test element (21) is parallel to one side of the triangle.

6. The array substrate according to claim 5, wherein, The array substrate comprises a plurality of test units (20), and a plurality of test areas (120) are arranged in at least one row and multiple columns; the orthogonal projections of two adjacent test areas (120) in the same row on the substrate (10) are point-symmetric patterns.

7. The array substrate according to claim 5, wherein, A plurality of test areas (120) are arranged in at least two rows; the orthogonal projections of two adjacent test areas (120) in the same column on the substrate (10) are axis-symmetric patterns, and the axis of symmetry is parallel to the row direction.

8. The array substrate of claim 6, wherein, The orthogonal projections of the three test pads (22) on the substrate (10) are circular with equal sizes, and the distances between the centers of the orthogonal projections of the three test pads (22) on the substrate (10) is equal.

9. The array substrate according to any one of claims 3 to 8, wherein, The orthogonal projections of the three test pads (22) on the substrate (10) are arranged in a first direction.

10. The array substrate of claim 2, wherein, ​ 11. The array substrate of claim 10, wherein, Projections of the three test pads (22) on the substrate (10) are on the same side of the projection of the test element (21) on the substrate (10); the projections of the test pads (22) and the test element (21) on the substrate (10) are arranged along a second direction, which intersects the first direction.

12. The array substrate of claim 11, wherein, The non-display area (12) includes a test area (120) corresponding to each test unit (20), and the test unit (20) is located in the corresponding test area (120); the projection of the test area (120) on the substrate (10) is rectangular.

13. The array substrate of claim 12, wherein, The array substrate includes a plurality of test units (20), and the plurality of test areas (120) are arranged in an array.

14. The array substrate according to any one of claims 10 to 13, wherein, The projections of the three test pads (22) on the substrate (10) are equal in size and circular, and the centers of the projections of the three test pads (22) on the substrate (10) are collinear.

15. The array substrate according to any one of claims 7, 8, 13, wherein, The projections of two adjacent test areas (120) on the substrate (10) coincide on one side.

16. The array substrate of any one of claims 2-8, 10-13, further comprising: A pixel circuit is located in the display area (11); the pixel circuit includes a plurality of thin film transistors, and the test element (21) is consistent with the material, thickness, and aspect ratio of the thin film transistors.

17. A display device comprising the array substrate of any one of claims 1-16.

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