Display module, display driving method, and display device

Abstract

The present disclosure provides a display module, a display driving method, and a display device. The display module comprises a display panel comprising a plurality of pixel rows, each of the pixel rows being provided with at least one gate line; a gate driving circuit, comprising a plurality of gate driving ends that are respectively connected to the plurality of gate lines; and a timing controller, connected to the gate driving circuit, and configured to receive, in the display of at least one picture frame, update data corresponding to the picture frame, and on the basis of a target pixel row where the update data is located, control, within a scanning period of the picture frame, the gate driving ends connected to gate lines of some of the pixel rows to output a gate start signal, so that some of the pixel rows are refreshed, wherein the refreshed pixel rows include the target pixel row.

Description

Display module, display driving method and display device

[0001] This disclosure claims priority to Chinese Patent Application No. 202411529121.5, filed on October 29, 2024, entitled “Display Module, Display Driving Method and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display module, a display driving method, and a display device. Background Technology

[0003] With the development of display technology, display panels are increasingly moving towards higher integration and lower cost, and the types of display panels are becoming more and more diverse. For example, current display devices can include liquid crystal display devices (LCD), plasma display devices (PDD), organic light-emitting display devices (OLED), etc.

[0004] Generally, a display device includes data lines and gate lines that define multiple sub-pixels of the display device, as well as a data driving unit that provides data signals to the data lines and a gate driving circuit that provides scan signals to the gate lines. The gate driving circuit can scan the sub-pixels and charge them according to the image data of the image to be displayed in order to achieve image display.

[0005] Overview

[0006] Based on the background art, this disclosure proposes a display module, a display driving method, and a display device.

[0007] In a first aspect, this disclosure provides a display module, comprising:

[0008] The display panel includes multiple pixel rows, and each pixel row is provided with at least one grid line;

[0009] A gate driving circuit includes multiple gate driving terminals, each of which is connected to multiple gate lines.

[0010] A timing controller, connected to the gate driving circuit, is configured to receive update data corresponding to the frame during the display of at least one frame, and based on the target pixel row where the update data is located, control the gate driving terminal connected to the gate line of a portion of the pixel row to output a gate start signal during the scanning cycle of the frame, so that a portion of the pixel row is refreshed.

[0011] The refreshed pixel row includes the target pixel row.

[0012] In some possible examples disclosed herein, the timing controller is at least configured to, in a first driving mode, control the gate driving terminals of the plurality of gate driving terminals corresponding to the pixel rows in the same row interval to output gate signals of the same type in each frame, so that the plurality of pixel rows located in the same row interval have the same refresh rate in each frame.

[0013] The gate signal includes the gate start signal and the gate stop signal.

[0014] In some possible examples of this disclosure, the plurality of pixel rows are divided into a plurality of first pixel row groups, the first pixel row group comprising a plurality of adjacent pixel rows;

[0015] Specifically, the timing controller is configured to respond to the first driving mode by controlling the gate driving terminal corresponding to the first pixel row group where the target pixel row is located to output the gate start signal and the gate driving terminal corresponding to the first pixel row group excluding the target pixel row to output the gate stop signal during the scanning period of the frame.

[0016] In some possible examples disclosed herein, the timing controller is configured, at least in a second driving mode, to control the first pixel row to form a pixel row group with a different number and / or position of the second pixel row in at least two different frame scan cycles, and to control the gate driving terminal corresponding to the pixel row group to output the same type of gate signal;

[0017] The gate signal includes the gate start signal and the gate stop signal.

[0018] In some possible examples disclosed herein, the timing controller is specifically configured to, in response to the second driving mode, divide a plurality of pixel rows into a plurality of second pixel row groups based on the target pixel row, and, within the scanning period of the frame, control the gate driving terminal corresponding to the second pixel row group where the target pixel row is located to output the gate start signal, and the gate driving terminal corresponding to the second pixel row group excluding the target pixel row to output the gate stop signal.

[0019] In this context, different frames correspond to the same number of second pixel row groups.

[0020] In some possible examples disclosed herein, the timing controller is specifically configured to, in response to the second driving mode, control the gate driving terminal corresponding to the target pixel row to output the gate start signal during the scanning period of the frame; and control the gate driving terminal corresponding to the pixel row other than the target pixel row to output the gate stop signal.

[0021] In some possible examples disclosed herein, the timing controller is further configured to determine the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row and each pixel row at the current refresh rate, and to control the gate driver terminal corresponding to the third pixel row to output the gate start signal and the gate driver terminal corresponding to the fourth pixel row to output the gate cut-off signal during the scanning cycle of the frame.

[0022] The third pixel row includes the target pixel row.

[0023] In some possible examples disclosed herein, the timing controller is specifically configured to acquire multiple third pixel row groups obtained by grouping multiple pixel rows based on the target pixel row, and control the gate driver terminal corresponding to a portion of the pixel rows within the target range to output a gate start signal and the gate driver terminal corresponding to the remaining portion of the pixel rows to output a gate cut-off signal according to the current refresh rate of each pixel row.

[0024] The target range is the adjacent area between two adjacent third pixel row groups whose refresh rate difference is greater than a preset difference. The third pixel row also includes the pixel row within the target range where the gate start signal is output. The fourth pixel row includes the pixel row within the target range where the gate cut-off signal is output.

[0025] In some possible examples of this disclosure, at least one fourth pixel row is spaced between two adjacent third pixel rows within the target range; and / or, at least one third pixel row is spaced between two adjacent fourth pixel rows within the target range.

[0026] In some possible examples disclosed herein, in two adjacent third pixel row groups where the difference between refresh rates is greater than a preset difference, each of the third pixel row groups includes the third pixel row and the fourth pixel row.

[0027] In some possible examples disclosed herein, in two adjacent third pixel row groups where the difference between refresh rates is greater than a preset difference, the density of the third pixel row within the target range in the third pixel row group with the smaller refresh rate is less than the density of the third pixel row within the target range in the third pixel row group with the larger refresh rate; and the density of the fourth pixel row within the target range in the third pixel row group with the smaller refresh rate is less than the density of the fourth pixel row within the target range in the third pixel row group with the larger refresh rate.

[0028] In some possible examples disclosed herein, the display panel includes a liquid crystal display panel, and the display module further includes:

[0029] The source drive circuit, connected to the timing controller, is configured to output source voltages of opposite polarity within the scan cycles of two adjacent frames.

[0030] The timing controller is also configured to record the cumulative holding time of the line interval in each polarity, and based on the time difference between the cumulative holding times of the different polarities of the line interval, control the source drive circuit to output the source voltage of the same target polarity in the N adjacent frames after the current frame;

[0031] Where N is greater than or equal to 1, the target polarity is the same as the polarity with the shorter retention time.

[0032] In some possible examples disclosed herein, in the current frame, the number of first row intervals is greater than the number of second row intervals; wherein the cumulative holding time of the target polarity in the first row interval is less than the cumulative holding time of the polarity opposite to the target polarity, and the cumulative holding time of the target polarity in the second row interval is not less than the cumulative holding time of the polarity opposite to the target polarity.

[0033] In some possible examples disclosed herein, the gate drive circuit includes a plurality of cascaded shift register units, the input side of which includes a first cascaded clock signal terminal and J first drive clock signal terminals; the timing controller includes K second cascaded clock signal terminals and M second drive clock signal terminals.

[0034] Wherein, J of the first drive clock signal terminals are respectively connected to J of the M second drive clock signal terminals, and one of the first drive clock signal terminals is connected to one of the gate drive terminals located on the output side; wherein, K = M / J;

[0035] The timing controller is configured to load different first clock signals to K first cascaded clock signal terminals and load a second clock signal to the m-th second drive clock signal terminal during the scanning period of the frame.

[0036] Wherein, the first clock signal is a signal that alternates between valid and invalid levels, the second clock signal and the first clock signal are valid levels in the refresh timing of the refreshed pixel row, and the second clock signal is invalid level in the refresh timing of the non-refreshed pixel row.

[0037] In some possible examples disclosed herein, the display module further includes:

[0038] The processor, connected to the timing controller, is configured to send update data to the timing controller, which shows that each frame is newer than the previous frame.

[0039] The timing controller is further configured to, when the update data indicates that some pixel rows in the current frame have been updated compared to the previous frame, obtain the currently triggered driving mode, divide the multiple pixel rows based on the currently triggered driving mode and the target pixel row where the update data is located, and control the gate driver terminal corresponding to the pixel row group where the target pixel row is located to output a gate start signal within the scanning cycle of the frame.

[0040] The driving mode includes a first driving mode and a second driving mode. The first driving mode is used to indicate that the multiple pixel rows are divided according to fixed boundaries, and the second driving mode is used to indicate that the multiple pixel rows are divided according to non-fixed boundaries.

[0041] The boundary is used to distinguish different pixel row groups.

[0042] In some possible examples disclosed herein, the timing controller is specifically configured to acquire the power information of the display module, and when the power information meets the switching conditions, switch the currently triggered first driving mode to the second driving mode; or, switch the currently triggered second driving mode to the first driving mode.

[0043] The power information includes power consumption rate and / or remaining power.

[0044] A second aspect of this disclosure provides a display driving method applied to a display module comprising a plurality of pixel rows, the method comprising:

[0045] Acquire image data for each frame, the image data including update data corresponding to the target pixel row, the target pixel row being the pixel row whose image data has changed compared to the previous frame;

[0046] Based on the target pixel row, within the scanning cycle of each frame, a pixel row to be refreshed is determined, wherein the pixel row to be refreshed includes the target pixel row; wherein, in at least one frame, the pixel row to be refreshed is a portion of a plurality of pixel rows.

[0047] A gate enable signal is output to the pixel row to be refreshed so that the pixel row to be refreshed is refreshed.

[0048] In some possible examples disclosed herein, determining the pixel row to be refreshed within the scan cycle of each frame, based on the target pixel row, includes at least one of the following:

[0049] Among multiple first pixel row groups, determine the target pixel row group in which the target pixel row is located, and determine the target pixel row group as the pixel row to be refreshed;

[0050] Based on the position of the target pixel row, the multiple pixel rows are divided into multiple second pixel row groups according to a preset number of pixel row groups, and the pixel rows included in the second pixel row where the target pixel row is located are determined as the pixel row to be refreshed;

[0051] The target pixel row is determined as the pixel row to be refreshed.

[0052] In some possible examples disclosed herein, determining the pixel row to be refreshed within the scan cycle of each frame, based on the target pixel row, includes:

[0053] Get the current refresh rate for each pixel row;

[0054] Based on the target pixel row and the current refresh rate of each pixel row, determine the third pixel row to be refreshed and the fourth pixel row not to be refreshed; wherein, the third pixel row includes the target pixel row;

[0055] The method further includes:

[0056] During the scanning cycle of at least one frame, the gate drive terminal corresponding to the fourth pixel row is controlled to output a gate cut-off signal so that the fourth pixel row is not refreshed in the current frame.

[0057] In some possible examples disclosed herein, determining the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row and each pixel row at the current refresh rate includes:

[0058] Based on the target pixel rows, the plurality of pixel rows are divided into a plurality of third pixel row groups;

[0059] For two adjacent third pixel row groups whose refresh rates differ by a preset difference, determine the target range located in the boundary interval of the two adjacent third pixel row groups.

[0060] The target pixel row and a portion of the pixel rows within the target range are defined as the third pixel row, and the remaining pixel rows within the target range are defined as the fourth pixel row.

[0061] In some possible examples disclosed herein, when the target pixel row in a plurality of first pixel row groups is determined as the pixel row to be refreshed, the method further includes:

[0062] In two adjacent frames, source voltages of opposite polarity are output to multiple rows of pixels;

[0063] Record the cumulative duration of the row interval in each polarity;

[0064] Based on the time difference between the cumulative holding times of different polarities in the line interval, the source drive circuit is controlled to output the source voltage of the same target polarity in the N adjacent frames after the current frame.

[0065] Where N is greater than or equal to 1, the target polarity is the same as the polarity with the shorter retention time.

[0066] A third aspect of this disclosure provides a display device including the display module described in any possible example of the first aspect.

[0067] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0068] Brief description of the attached diagram

[0069] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0070] Figure 1 illustrates a flowchart of the screen display process in related technologies;

[0071] Figure 2 shows a schematic diagram of the layout structure of a display module;

[0072] Figure 3 shows a schematic diagram of the system framework of a display module;

[0073] Figure 4 shows a schematic diagram of the array substrate in the display module;

[0074] Figure 5 shows a schematic diagram of the pixel architecture of a sub-pixel;

[0075] Figures 6 and 7 show two schematic diagrams of the screen display process, respectively;

[0076] Figure 8 shows a schematic diagram of the second clock signal during the screen display shown in Figure 6;

[0077] Figure 9 shows a schematic diagram of the second clock signal during the screen display shown in Figure 7;

[0078] Figures 10a and 10b show two schematic diagrams of dividing multiple pixel rows in the first driving mode, respectively;

[0079] Figures 11a and 11b respectively show two schematic diagrams of dividing multiple pixel rows in the second driving mode;

[0080] Figure 12 shows a schematic diagram of dividing multiple pixel rows by a fixed number of pixel groups;

[0081] Figures 13a-13c show schematic diagrams of the boundary blurring process, respectively;

[0082] Figure 14 shows a schematic diagram of the timing signals of the source voltages with and without polarity compensation;

[0083] Figure 15a shows a schematic diagram of the connection architecture between a gate drive circuit and a timing controller;

[0084] Figure 15b shows a schematic diagram of a shift register unit;

[0085] Figure 16 shows a schematic diagram of another connection architecture between the gate drive circuit and the timing controller;

[0086] Figure 17, using the connection architecture of Figure 16 as an example, shows the timing diagram of the first clock signal and the second clock signal when performing global display in the display area;

[0087] Figure 18, using the connection architecture of Figure 16 as an example, shows the timing diagram of the first clock signal and the second clock signal when performing partial refresh in the display area;

[0088] Figure 19 shows a schematic diagram of the structure of the image data received by the timing controller.

[0089] Detailed description

[0090] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0091] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0092] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0093] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0094] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0095] In the embodiments of this application, since the source and drain of the transistor are symmetrical, their source and drain can be interchanged. In the embodiments of this application, one of the source and drain of the transistor can also be called the first electrode, and the other of the source and drain can be called the second electrode.

[0096] Display devices typically include a timing controller (TCON), which is connected to the gate drive circuit and the data drive unit. The TCON sends drive signals to the gate drive circuit and data signals to the data drive unit. The drive signals are converted into gate drive signals for the gate lines in the gate drive circuit. Currently, low power consumption in display devices remains a continuous requirement for customers. For example, in laptops, the display is always on during use, so the display's power consumption significantly impacts the laptop's standby time.

[0097] In related technologies, to reduce the power consumption of display devices, improvements are generally made from the system side of the display device. For example, the system chip on the display device system side, such as the CPU (Central Processing Unit), can reduce the size of the data packets sent to the timing controller, thereby reducing bandwidth and saving power. Referring to Figure 1, a flowchart illustrating the display process in related technologies is shown. As shown in Figure 1, the processor on the system side sends the PSR2 data of the current i-th frame to the timing controller. Then, the timing controller determines which areas in the image are updated based on the cached image data of the i-th frame, i.e., locates the update areas. Next, the data corresponding to the update areas in the PSR2 data of the i-th frame is replaced in the image data of the i-th frame, thus obtaining the image data of the i-th frame. Afterward, the image data of the i-th frame is displayed line by line. In this technology, since the processor only sends the updated data of the i-th frame compared to the (i-1)-th frame to the timing controller, bandwidth is reduced, thereby saving power.

[0098] Of course, there are other ways to reduce power consumption in related technologies, such as installing a camera on the display device to detect the user's head position. When the user is facing the screen and looking at it, the display powers on and shows the image; when the user is not in front of the screen, the display powers off. However, this method requires additional camera placement, increasing hardware costs, and also requires hardware and software resources to support the detection of the user's head position. In reality, its contribution to reducing power consumption is limited, and it is also prone to false detections that prevent the user from using the display device.

[0099] In view of this, the present disclosure provides a display module, a display driving method, and a display device, which aim to achieve the ultimate power saving effect while ensuring the normal display of the screen. The main technical idea is: based on the image data of each frame to be displayed, the high refresh rate of the image update area is retained to ensure the normal display of the image, while the refresh rate of the image non-updated area or the image with less update is reduced to save power.

[0100] An embodiment of the first aspect of this disclosure provides a display module, which may include a display panel, a gate driving circuit 20, and a timing controller 30. The display panel includes a plurality of pixel rows 11, each pixel row 11 having at least one gate line GL. The gate driving circuit 20 includes a plurality of gate driving terminals, each of which is connected to a plurality of gate lines GL. The timing controller 30 is connected to the gate driving circuit 20 and is configured to receive update data corresponding to a frame during the display of at least one frame, and based on the target pixel row 11n where the update data is located, control the gate driving terminals connected to the gate lines GL of a portion of the pixel rows 11 to output gate start signals during the scanning period of the frame, so that a portion of the pixel rows 11 are refreshed. The refreshed pixel rows 11 include the target pixel row 11n.

[0101] In this embodiment, each pixel row 11 on the display panel can include multiple sub-pixels P. Multiple gate driving terminals of the gate driving circuit 20 are connected to multiple gate lines GL. Each gate driving terminal can send a gate start signal and a gate stop signal to a gate line GL. The gate start signal can activate the thin-film transistor of the sub-pixel P, thereby charging the sub-pixel P to achieve image display. The gate stop signal can turn off the thin-film transistor of the sub-pixel P, thereby turning off the sub-pixel P and preventing the charging process. During the scanning cycle of one frame, if there is no gate start signal on the gate line GL, the sub-pixel P connected to that gate line GL will remain in the state of the previous frame; that is, this portion of sub-pixels P retains the image from the previous frame.

[0102] In at least one frame of a multi-frame display, the timing controller 30 can receive only the update data of that frame and output gate start signals to the gate lines GL of a portion of the pixel rows 11, including the target pixel row 11n, within the scanning cycle of the frame. This allows only a portion of the pixel rows 11 to be refreshed, while the remaining pixel rows 11 are not refreshed. Thus, the timing controller 30 can receive update data with a smaller amount of data (i.e., not all the data of a frame), thereby reducing bandwidth usage and saving power. At the same time, it can refresh only a portion of the pixel rows 11, including the target pixel row 11n, while the remaining pixel rows 11 are not refreshed. In this way, some pixel rows 11 on the display panel do not need to undergo the process of charging the sub-pixels P, thereby saving the power consumption occupied by refreshing the display panel.

[0103] The display panel of this embodiment uses the update data of the frame as a basis. In the display, the refresh of the pixel row 11 that has been updated is retained while the refresh of the pixel row 11 that has not been updated is reduced. This makes the refresh rate of each pixel row 11 in the display panel differentiable. As the number of displayed frames increases, the difference in refresh rate can become more dynamic and refined. Therefore, the ultimate power saving effect can be achieved.

[0104] The above-described display module will now be described by way of example with reference to the accompanying drawings.

[0105] Please refer to Figures 2, 3, and 4. Figure 2 shows a schematic diagram of the layout structure of a display module, Figure 3 shows a schematic diagram of the system framework of a display module, and Figure 4 shows a schematic diagram of the structure of the array substrate in the display module. As shown in Figures 2-4, the display module of this embodiment may include the following structure:

[0106] The display panel includes multiple pixel rows 11, each pixel row 11 having at least one grid line GL;

[0107] The gate driving circuit 20 includes multiple gate driving terminals, which are respectively connected to multiple gate lines GL;

[0108] The timing controller 30, connected to the gate drive circuit 20, is configured to receive update data corresponding to the frame during the display of at least one frame, and based on the target pixel row 11n where the update data is located, control the gate drive terminal connected to the gate line GL of a portion of the pixel row 11 to output a gate start signal during the scanning period of the frame, so that a portion of the pixel row 11 is refreshed; wherein the refreshed pixel row 11 includes the target pixel row 11n.

[0109] In this embodiment, the display module can be a liquid crystal display module. Thus, the display panel can include an array substrate, a color filter substrate, and liquid crystal located between the array substrate and the color filter substrate. In some embodiments, the display module can be an organic light-emitting display module. Thus, the display panel can include an array substrate and an organic light-emitting device located on one side of the array substrate. The organic light-emitting device can include a cathode, an anode, and an organic light-emitting layer located between the cathode and the anode.

[0110] As shown in Figure 2, the display panel may include a display area AA and a non-display area NAA. The display area AA may include multiple pixel rows 11. A pixel row 11 refers to sub-pixels P located in the same row of the display panel; for example, a row of sub-pixels P can be called a pixel row 11. Each pixel row 11 may include multiple sub-pixels P, and these multiple sub-pixels P can constitute multiple pixel units. The number of sub-pixels P can be three or four times the number of pixel units. For example, if the display module is a liquid crystal display module, one pixel unit may include three sub-pixels P: a green sub-pixel P, a blue sub-pixel P, and a red sub-pixel P. If the display module is an organic light-emitting diode (OLED) display module, one pixel unit may include four sub-pixels P: a green sub-pixel P, a blue sub-pixel P, a red sub-pixel P, and a white sub-pixel P. In some examples, when the display module is an OLED display module, one pixel unit may also include three sub-pixels P: a green sub-pixel P, a blue sub-pixel P, and a red sub-pixel P.

[0111] In one embodiment, each sub-pixel P includes a pixel driving circuit Pc and an electrode PT. In a liquid crystal display module, the electrode PT can be a pixel electrode PT; in an organic light-emitting display module, the electrode PT can be an anode. The display module may include multiple gate lines GL and multiple data lines DL. One data line DL may correspond to one or more columns of sub-pixels P, and one gate line GL corresponds to all or some sub-pixels P in a pixel row 11. For example, as shown in FIG4, one gate line GL corresponds to all sub-pixels P in a pixel row 11. As shown in FIG5, FIG5 illustrates a pixel architecture diagram of a sub-pixel P. As shown in FIG5, taking a liquid crystal display device as an example, the pixel driving circuit Pc may include a thin-film transistor and a liquid crystal capacitor C. Ic Storage resistor R Ic The capacitor Cs, the gate line GL is connected to the gate of the thin-film transistor, the data line DL is connected to the source of the thin-film transistor, and the drain of the thin-film transistor is connected to a capacitor in parallel (capacitor C). Ic After connecting the capacitor Cs, it is connected to the electrode PT (pixel electrode PT or anode). When the voltage on the gate line GL is high, the source and drain of the thin-film transistor are turned on, and the voltage on the data line DL can charge the liquid crystal capacitor C within the pixel. lc and storage capacitor C s This changes the voltage between the pixel electrode PT and the common electrode PT (also known as the pixel voltage). If the voltage on the gate line GL is set low, the source and drain of the thin-film transistor are turned off, and the sub-pixel P is maintained by the liquid crystal capacitor and the storage capacitor.

[0112] A pixel row 11 may include one or more gate lines GL, as shown in Figures 2 and 3. In the case of a pixel row 11 including multiple gate lines GL, different gate lines GL can connect sub-pixels P of different colors within the pixel row 11. For example, a pixel row 11 may include three gate lines GL, corresponding to the green, blue, and red sub-pixels P in the same pixel row 11, respectively. This way, by increasing the number of gate lines GL, the number of data lines DL in the display panel can be reduced, thereby reducing the demand for data driver chips and thus lowering the cost of the display module.

[0113] The gate driving circuit 20 can be located on the array substrate in the display panel. In one example, the gate driving circuit 20 can be disposed on one side of the display area AA, or it can be disposed on opposite sides of the display area AA. For example, as shown in FIG2, the gate driving circuit 20 is disposed on the left and right sides of the display area AA, and the gate driving circuit 20 is located in the non-display area NAA.

[0114] In this embodiment, the gate driving circuit 20 may include an input side and an output side. The input side may be connected to the timing controller 30, and the output side is used to output gate driving signals and gate cut-off signals to the gate line GL. In one example, the gate driving circuit 20 may include multiple shift register units. The output side of each shift register unit may include a gate driving terminal, which may be connected to a gate line GL. Thus, the number of shift register units may be the same as the number of gate lines GL. In another example, the output side of each shift register unit may include multiple gate driving terminals, which may be connected to multiple different gate lines GL respectively. Thus, one shift register unit can drive multiple gate lines GL. In this way, the number of shift register units may be less than the number of gate lines GL, which helps to reduce the occupation of the non-display area NAA, thereby reducing the difficulty of routing on the bezel and reducing the bezel size.

[0115] Specifically, the gate start signal output from the gate drive terminal of the gate drive circuit 20 can drive the sub-pixel P to charge. Specifically, it can turn on the source and drain of the thin-film transistor in the sub-pixel P. For example, as shown in Figure 5, when the gate start signal output from the gate drive terminal is high, this high level can turn on the source and drain of the thin-film transistor. Of course, in some examples, depending on the type of thin-film transistor connected to the gate line GL, the gate start signal can also be a low-level signal.

[0116] The gate drive circuit 20 can also output a gate cutoff signal at its gate drive terminal. This gate cutoff signal can turn off the source and drain of the thin-film transistor in the sub-pixel P. For example, as shown in Figure 5, when the gate start signal output by the gate drive terminal is low, this low level can turn off the source and drain of the thin-film transistor. Of course, in some examples, depending on the type of thin-film transistor connected to the gate line GL, the gate cutoff signal can also be a high-level signal.

[0117] In this embodiment, the timing controller 30 can be electrically connected to the gate drive circuit 20. Specifically, the timing controller 30 can be connected to the input side of the gate drive circuit 20, and the signals (gate start signal and gate cut-off signal) output by the gate drive terminal of the gate drive circuit 20 are controlled by the signals input to the timing controller 30. In some examples, the timing controller 30 may include multiple clock signal lines, and one clock signal line can serve as the input to multiple shift registers. The signal input to the clock signal line can be a clock signal with alternating active and inactive levels. Through the active and inactive levels on the clock signal, each shift register is sequentially made to output the gate start signal and the gate cut-off signal.

[0118] The timing controller 30 can also be connected to the processor (also known as a system-on-a-chip) of the display module. The timing controller 30 can receive image data of the screen to be displayed from the system-on-a-chip. Since the screen is displayed frame by frame, the timing controller 30 receives the image data from the system-on-a-chip frame by frame. In this embodiment, when the system-on-a-chip sends image data for each frame to the timing controller 30, it can be data of the updated areas of the frame compared to the previous frame. It is understood that in some cases, the entire area of ​​a frame is updated compared to the previous frame, meaning the image data in each pixel row 11 changes. In other cases, a partial area of ​​a frame is updated compared to the previous frame, meaning the image data in some pixel rows 11 changes. The pixel row 11 with the changed image data is called the target pixel row 11n. For a video containing multiple frames, there will always be one or more frames whose partial areas are updated compared to the previous frame. Therefore, when the system-on-a-chip sends image data to the timing controller 30, for frames where a local area has been updated, it can send the updated data for that local area. For image data of other areas that have not been updated, it can send empty packets, for example, only data identifiers, without image data of the areas that have not been updated.

[0119] For example, please refer to Figure 6, which shows a schematic diagram of the display process. As shown in Figure 6, for a frame where a local area is updated, the system-on-a-chip can send only the update data of the local area to the timing controller 30. The timing controller 30 can control some pixel rows 11, including the target pixel row 11n, on the display panel to be refreshed in the scanning cycle of the current frame, while the remaining pixel rows 11 are not refreshed in the scanning cycle of the current frame.

[0120] For example, as shown in Figure 6, taking a liquid crystal display module as an example, if a local area of ​​a frame is updated, such as the frame of rows a to a+b being updated and the frame of rows c to c+d being updated, while the frames of the remaining adjacent rows 11m are not updated, then the system-on-a-chip sends the update data of rows a to a+b and rows c to c+d to the timing controller 30. Then, the timing controller 30 can control the gate drive terminal in the gate drive circuit 20 connected to the gate lines GL of some pixel rows 11 to output a gate start signal, such as the gate drive terminal connected to the gate lines GL of pixel rows e to e+f and g to g... The gate drive terminal connected to the gate line GL of pixel row 11 outputs a gate start signal, thereby turning on the thin film transistors of sub-pixels P in pixel rows 11 from e to e+f and from g to g+h, so that the data voltage on the data line DL can be applied to the pixel electrode PT of sub-pixels P in pixel rows 11 from e to e+f and from g to g+h, thereby changing the pixel voltage of sub-pixels P in pixel rows 11 from e to e+f and from g to g+h, and realizing the refresh of pixel rows 11 from e to e+f and from g to g+h. For the pixel rows 11 other than the e to e+f and g to g+h (referred to as the remaining pixel rows 11), the timing controller 30 can control the gate drive terminal connected to the gate line GL of the gate drive circuit 20 to output a gate cut-off signal, thereby keeping the source and drain of the thin film transistor of the sub-pixel P on the remaining pixel rows 11 off, and the voltage on the data line DL will not be applied to the pixel electrode PT of the sub-pixel P on these remaining pixel rows 11, so that the image of the remaining pixel rows 11 remains in the state of the previous frame.

[0121] In this frame, pixel rows 11 from e to e+f include target pixel rows 11m, i.e., pixel rows 11 from a to a+b, and pixel rows 11 from g to g+h include target pixel rows 11m, i.e., pixel rows 11 from c to c+d. In one example, the pixel rows 11 refreshed in this frame may only include target pixel rows 11n. For example, pixel rows 11 from e to e+f may be pixel rows 11 from a to a+b, and pixel rows 11 from g to g+h may be pixel rows 11 from c to c+d. In another example, for a frame with local updates, the pixel rows 11 refreshed in this frame may include target pixel rows 11n and other pixel rows 11m besides target pixel rows 11n. Regardless of the method, when a local area of ​​the frame is updated, the refresh of some pixel rows 11, including target pixel rows 11n, can be controlled. Therefore, the number of pixel rows 11 refreshed can be reduced according to the image to be displayed, thereby saving power consumption and increasing the standby time of the display device.

[0122] Furthermore, since the image data received by the timing controller 30 from the system-on-a-chip contains only the update data of the local area for frames with local updates, compared to image data containing the entire area, the update data only contains the image data of the local area. Therefore, the data volume is small, reducing the bandwidth occupied, thereby saving system power consumption and further increasing the standby time of the display device.

[0123] Furthermore, it is understandable that for videos with multiple frames, the changes between frames are dynamic. That is, the local areas with updated frames are constantly changing. Thus, the position and number of pixel rows 11 that are refreshed in each frame are also dynamically changing. As a result, the refresh rates of multiple pixel rows 11 are different, so overall, it is possible to achieve partitioned refresh at the granularity of pixel rows 11, which allows for more precise power saving.

[0124] In some embodiments, three partition refresh methods are provided to achieve partition refresh of multiple pixel rows 11, so as to refresh a portion of the pixel rows 11 for the target pixel row 11n that has been updated.

[0125] One approach is to group multiple pixel rows 11 into fixed groups. For a group that falls into a target pixel row 11n, the same type of gate signal (gate start signal, gate cut-off signal) is input to the group. This approach can also reduce power consumption and reduce the computational difficulty of the timing controller 30. This approach can be called the first driving mode.

[0126] Another approach 2 is to group multiple pixel rows 11 in real time based on the update data of the incoming frame. For example, the target pixel row 11n can be divided into one group, and the non-target pixel row 11m can be divided into another group; or, the target pixel row 11n and the adjacent non-target pixel row 11m can be divided into one group, and the remaining pixel rows 11 can be divided into another group. This approach 2 can flexibly group the pixels according to the update data of the incoming frame, which helps to reduce the number of pixel rows 11 that need to be refreshed. For example, only the target pixel row 11n can be divided into the group that needs to be refreshed. In this way, the ultimate power saving effect can be achieved. This approach 2 can be called the second driving mode.

[0127] In the first driving mode, the timing controller 30 can be configured to control the gate driving terminal corresponding to the pixel row 11 in the same row interval among the multiple gate driving terminals to output the same type of gate signal in each frame, so that the multiple pixel rows 11 located in the same row interval have the same refresh rate in each frame; wherein the gate signal includes a gate start signal and a gate stop signal.

[0128] In this embodiment, the pixel rows 11 within the same row interval may include multiple consecutive pixel rows 11, and the row interval includes a portion of all pixel rows 11. The timing controller 30 can control the gate driving terminals connected to the gate lines GL of the multiple pixel rows 11 within the same row interval to output the same gate signal in each frame. For example, in one frame, the gate driving terminals connected to the gate lines GL of the multiple pixel rows 11 within the row interval all output a gate start signal; in another frame, the gate driving terminals connected to the gate lines GL of the multiple pixel rows 11 within the row interval all output a gate stop signal. The output of the gate start signal or the gate stop signal can be determined based on whether the row interval is updated in the current frame. For example, if the row interval is updated in the current frame, the gate driving terminals connected to the row interval all output a gate start signal in the current frame; conversely, if the row interval is not updated in the current frame, the gate driving terminals connected to the row interval all output a gate stop signal in the current frame.

[0129] In this way, for each frame, multiple pixel rows 11 within the same row interval will either be refreshed or not refreshed, thus ensuring that the refresh rate of multiple pixel rows 11 within the same row interval is the same regardless of which frame they are in.

[0130] The refresh rate of pixel row 11 can be expressed as the percentage of time that pixel row 11 is refreshed across multiple frames. The refresh rate can be calculated cumulatively over time. Assuming the highest refresh rate of the display panel is A Hz, if pixel row 11 is on for 1 frame and off for 1 frame, then the current refresh rate of pixel row 11 is A / 2Hz; if it is on for 1 frame and off for 2 frames, then the refresh rate is A / 3Hz, and so on, if it is on for 1 frame and off for (A-1) frames, then the refresh rate is A / A Hz. In summary: a = A / (b+1);

[0131] Where a is the refresh rate of pixel row 11, A is the maximum screen refresh rate, and b is the number of frames when pixel row 11 is turned off (not refreshed).

[0132] For example, referring to FIG10a, taking a display panel with a resolution of 1080×720 as an example, including 720 pixel rows 11, for row intervals 1-240, the refresh state of all pixel rows 11 in row intervals 1-240 is consistent in each frame of frame (i-1), frame i, and frame (i+1). For row intervals 241-480, they are refreshed in frame i-1 but not in frames i and i+1, and the refresh state of all pixel rows 11 in this row interval is consistent in each frame. For row intervals 481-720, they are not refreshed in frame i-1 but are refreshed in frames i and i+1, and the refresh state of all pixel rows 11 in this row interval is consistent in each frame. Therefore, the refresh rate of multiple pixel rows 11 within a row interval is the same in each frame.

[0133] Figure 10a only schematically shows the partitioning method of row intervals. In practice, there are other partitioning methods, which will not be elaborated here. It should be noted that the more row intervals are obtained, the higher the precision of power consumption reduction.

[0134] In one embodiment of implementing the first driving mode described above, multiple pixel rows 11 can be pre-divided into multiple first pixel row groups, each first pixel row group including multiple adjacent pixel rows 11, and the information of the divided first pixel row groups can be stored in the timing controller 30. In this way, the timing controller 30 can respond to the first driving mode by controlling the gate driver terminal corresponding to the first pixel row group containing the target pixel row 11n to output a gate start signal, and controlling the gate driver terminal corresponding to the first pixel row group excluding the target pixel row 11n to output a gate cut-off signal during the frame scanning cycle.

[0135] In this embodiment, for frames where local areas are updated, the timing controller 30 can determine which first pixel row 11n is located in based on the stored information of the first pixel row group, and then control the gate driver terminal connected to the gate line GL of each pixel row 11 in that first pixel row group to output a gate start signal. For first pixel row groups that do not include the target pixel row 11n, the gate driver terminal connected to the gate line GL of each pixel row 11 in these first pixel row groups can be controlled to output a gate cut-off signal, thereby achieving the purpose of partitioned refresh based on the local area where the frame is updated.

[0136] In this context, a first pixel row group is the row interval mentioned above. In practice, a large number of first pixel row groups can be divided. The more groups there are, the less likely the entire display panel will be refreshed when there are screen updates in multiple scattered local areas.

[0137] In the second driving mode, the timing controller 30 can be configured to control the first pixel row 111 to form a pixel row group with the second pixel row 112 of different numbers and / or positions in at least two different frame scan cycles, and control the gate driving terminal corresponding to the pixel row group to output the same type of gate signal; wherein the gate signal includes a gate start signal and a gate stop signal.

[0138] In this second driving mode, the timing controller 30 determines in real time which pixel rows 11 need to be refreshed in the current frame based on the currently arriving image data (including updated data). The pixel rows 11 to be refreshed in this frame can be the target pixel row 11n, or can include the target pixel row 11n and the pixel rows 11m adjacent to the target pixel row 11n. Since there are actually at least two frames, and the size and position of the updated local area of ​​the image are different in these two frames, the position and number of the target pixel row 11n are also different. Thus, the position and number of the pixel rows 11m refreshed along with the target pixel row 11n will also change dynamically. Compared with the first driving mode, in the first driving mode, the refresh rate of multiple pixel rows 11 within the same row interval is the same in each frame, while in this second driving mode, the refresh rates of multiple pixel rows 11 within the same row interval are different in at least two frames.

[0139] Specifically, in this second driving mode, with reference to the first pixel row 111, the timing controller 30 can control the first pixel row 111 to form a pixel row group with different numbers and / or positions of the second pixel row 112 in at least two different frame scan cycles. In each of the two different frames, the second pixel row 112 combined with the first pixel row 111 outputs the same type of gate signal at the gate driving end of that frame.

[0140] In one example, the second pixel row 112 forming a pixel row group with the first pixel row 111 can be a pixel row 11 adjacent to the first pixel row 111. For example, referring to Figure 11a, in frame 1, the first pixel row 111 forms a pixel row group with two adjacent second pixel rows 112 (rows a and c). In frame 1, both the first pixel row 111 and the second pixel row 112 in this pixel group are refreshed, while rows d and e are not refreshed. Then, in frame 2, the first pixel row 111 forms a pixel row group with three subsequent adjacent second pixel rows 112 (rows c, d, and e). In frame 2, neither the first pixel row 111 nor the second pixel row 112 (rows c, d, and e) in this pixel group are refreshed, while row a and the remaining pixel rows (pixel rows other than the first pixel row 111 and the second pixel row 112) are refreshed. This results in multiple pixel rows 11 within the interval of row a to row e having different refresh rates.

[0141] In another example, the second pixel row 112 forming a pixel row group with the first pixel row 111 can be a pixel row 11 that is not adjacent to the first pixel row 111. For example, referring to Figure 11b, in frame 1, the first pixel row 111 (row c) forms a pixel row group with an adjacent second pixel row 112 (row d) and two non-adjacent second pixel rows 112 (rows g and k). In frame 1, both the first and second pixel rows 111 in this pixel group are refreshed, while the remaining pixel rows 11 are not refreshed. Then, in frame 2, the first pixel row 111 forms a pixel row group with four non-adjacent second pixel rows 112 (rows e, f, i, and j). In frame 2, neither the first nor the second pixel rows 111 in this pixel group are refreshed, while the remaining pixel rows 11 are refreshed. This results in multiple pixel rows 11 within the interval a-m having different refresh rates.

[0142] In this embodiment, the first pixel row 111 can be any pixel row 11 among a plurality of pixel rows 11, as shown in Figures 11a and 11b. In frame 1, the first pixel row 111 can be the target pixel row 11n, that is, the pixel row 11 of the screen has been updated, and in frame 2, it can be the non-target pixel row 11m.

[0143] The timing controller 30 can control the gate signal of the same type output from the gate drive terminal corresponding to the pixel row group. This can be a gate cut-off signal or a gate start signal, depending on whether the pixel row group contains a target pixel row 11n. If it contains a target pixel row 11n, a gate start signal can be output, as shown in Figure 11a. In frame 1, a gate start signal is output to refresh the first pixel row 111 and the second pixel row 112. If it does not contain a target pixel row 11n, a gate cut-off signal can be output, as shown in Figure 11a. In frame 2, a gate cut-off signal is output to prevent refreshing the first pixel row 111 and the second pixel row 112.

[0144] It should be noted that in Figures 11a and 11b, Frame 1 and Frame 2 are names of two different frames. Frame 1 and Frame 2 can be two consecutive frames, or they can be two non-consecutive frames, such as Frame 1 and Frame 2 being separated by at least one frame.

[0145] In one embodiment of the second driving mode, when the timing controller 30 groups multiple pixel rows 11 according to the update data of each frame, the number of second pixel row groups obtained in each frame can be the same, such as dividing each frame into m second pixel row groups, where m can be greater than or equal to 3. In this second driving mode, although the number of second pixel row groups obtained in different frames is the same, the division method is different, so that the same first pixel row 111 can form pixel groups with different numbers and positions of second pixel rows 112 in different frames.

[0146] In specific implementation, the timing controller 30 is specifically configured to respond to the second driving mode, divide multiple pixel rows 11 into multiple second pixel row groups based on the target pixel row 11n, and control the gate driving terminal corresponding to the second pixel row group where the target pixel row 11n is located to output a gate start signal and the gate driving terminal corresponding to the second pixel row group excluding the target pixel row 11n to output a gate cut-off signal within the scanning cycle of the frame; wherein, different frames correspond to the same number of second pixel row groups.

[0147] In this embodiment, the number of second pixel row groups divided in each frame is fixed, but the division method is not fixed. That is, the boundaries between the second pixel row groups are not fixed. Specifically, the division is based on the target pixel row 11n of each frame. Taking the target pixel row 11n as a reference, multiple pixel rows 11 can be divided into multiple second pixel row groups. The multiple second pixel row groups can be divided as a whole into a pixel row group including the target pixel row 11n and a pixel group excluding the target pixel row 11n. In frames where there is an update in a local area, the timing controller 30 can output a gate start signal to the second pixel row 112 group where the target pixel row 11n is located and output a gate stop signal to the second pixel row 112 group excluding the target pixel row 11n.

[0148] Referring to Figure 12, a schematic diagram of a fixed number of pixel groups with variable division is shown. As shown in Figure 12, taking the division of multiple pixel rows 11 into four second pixel row groups in each frame as an example, the four second pixel row groups are second pixel row group a to second pixel row group d. Taking the first pixel row 111 as the target pixel row 11n as an example, in frame 3, there are four target pixel rows 11n, which are adjacent to each other. According to the positions of the four target pixel rows 11n, the multiple pixel rows 11 are divided into four second pixel row groups, as shown in Figure 12. The timing controller 30 needs to output gate start signals to pixel group b and pixel group c in the four second pixel row groups to refresh the pixel rows 11 in these two second pixel row groups.

[0149] For example, as shown in Figure 12, in frame 4, there are four target pixel rows 11n, which are distributed at intervals. Among the four second pixel row groups, second pixel row group a and second pixel row group c include target pixel rows 11n. Then, the timing controller 30 needs to output a gate start signal to pixel group a and pixel group c so that the pixel rows 11 in the two second pixel row groups are refreshed.

[0150] Frames 3 and 4 can be consecutive or non-consecutive.

[0151] In this embodiment, for frames with locally updated regions, the display module can control the refresh of the target pixel row 11n where the updated data is located and some unupdated pixel rows 11. Since it still refreshes only some pixel rows 11, it can still save panel power consumption.

[0152] In some embodiments, for a frame where a local area is updated, when the timing controller 30 groups multiple pixel rows 11 based on the target pixel row 11n, it can divide the frame with the goal of minimizing the number of pixel rows 11 to be refreshed in the current frame. This ensures that the local area of ​​the current frame is refreshed while minimizing the number of sub-pixels P charged in the current frame, thereby further saving power consumption.

[0153] In practice, the timing controller 30 can use linear programming and other methods to solve for the optimal grouping method with the goal of minimizing the number of pixel rows 11 to be refreshed, thereby obtaining multiple second pixel row groups.

[0154] In another embodiment of implementing the second driving mode, during the scanning cycle of a frame, the timing controller 30 can control the gate driving terminal corresponding to the target pixel row 11n to output a gate start signal; and control the gate driving terminal corresponding to the pixel row 11 other than the target pixel row 11n to output a gate cut-off signal.

[0155] Among them, the gate driving terminal corresponding to the target pixel row 11n is the gate driving terminal connected to the gate line GL of the target pixel row 11n. When the target pixel row 11n includes multiple gate lines GL, the gate driving terminal can also be multiple gate driving terminals connected to the multiple gate lines GL.

[0156] For frames where local areas are updated, this display module only refreshes the target pixel row 11n where the updated data is located. Other pixel rows 11m (pixel rows 11 other than the target pixel row 11n) that have not been updated do not need to be refreshed. For example, as shown in FIG11b, in frame 1, the first pixel row 111 is the target pixel row 11n with updated data, and the second pixel row 112 combined with the first pixel row is also the target pixel row 11n that needs to be refreshed. In frame 1, the pixel group of the first pixel row 111 and the second pixel row 112 is refreshed in frame 1, that is, the timing controller 30 controls the gate driver terminal connected to the gate line GL of the pixel group to output a gate start signal, while the gate driver terminal connected to the gate line GL of the pixel row 11 other than the pixel group outputs a gate cut-off signal. In frame 2, the second pixel row 112, which is combined with the first pixel row 111, is a pixel row 11m that does not need to be refreshed, and the remaining pixel rows 11 are target pixel rows 11n. In frame 2, the timing controller 30 controls the gate drive terminal connected to the gate line GL of the first pixel row 111 and the second pixel row 112 to output a gate cut-off signal, while the gate drive terminal connected to the gate line GL of the pixel rows 11 other than this pixel group outputs a gate start signal.

[0157] Therefore, each frame only refreshes the target pixel row 11n where the updated data is located, and does not refresh the pixel row 11 that has not been updated. This allows for fine-grained control, resulting in extreme power saving.

[0158] In some embodiments, the display module can dynamically switch between a first driving mode and a second driving mode. The currently triggered driving mode can be triggered by the user or by internal logic, which can be triggered based on the power consumption rate and remaining power of the display module. Specifically, the timing controller 30 is also configured to acquire the currently triggered driving mode, and based on the currently triggered driving mode and the target pixel row 11n, divide the multiple pixel rows 11, and within the scanning cycle of the frame, control the gate driving terminal corresponding to the pixel row group where the target pixel row 11n is located to output a gate start signal; wherein, the driving mode includes a first driving mode and a second driving mode, the first driving mode is used to indicate that the multiple pixel rows 11 are divided according to a fixed boundary, and the second driving mode is used to indicate that the multiple pixel rows 11 are divided according to a non-fixed boundary; the boundary is used to distinguish different pixel row groups.

[0159] In this embodiment, the display module may further include a processor (also known as a system-on-a-chip). This processor can send update data to the timing controller, indicating that each frame is updated compared to the previous frame. When the update data indicates that a local area of ​​the frame has been updated compared to the previous frame, the timing controller can obtain the currently triggered driving mode and enter a refresh operation under the local area update condition. For example, based on the target pixel row 11n where the update data is located, multiple pixel rows 11 in the display area can be divided. This driving mode can be used for the division method. In other words, for a frame where local pixel rows are updated, the timing controller can determine which pixel rows in the current frame need to be refreshed based on the update data, thus requiring only the refresh of a portion of the pixel rows, including the target pixel row. This is a dynamic, non-fixed-frequency refresh based on the update data.

[0160] The first and second driving modes can be described with reference to the above embodiments. As can be seen from the above embodiments, in the first driving mode, the multiple pixel rows 11 of the display area AA are fixedly divided into multiple first pixel row groups. The boundary between each first pixel row group remains unchanged in any frame. Therefore, it can be said that the multiple pixel rows 11 are divided according to a fixed boundary. In the second driving mode, the multiple pixel rows 11 of the display area AA are divided into a fixed number of multiple second pixel row groups, or the display area AA is divided according to the target pixel row 11n as the boundary. The boundary between the second pixel row groups can dynamically change in multiple frames. Therefore, it can be said that the multiple pixel rows 11 are divided according to a non-fixed boundary.

[0161] It should be noted that this boundary can be used to distinguish different groups of pixel rows, and it can at least be used to distinguish between refreshed pixel rows and non-refreshed pixel rows.

[0162] It should be noted that when the update data sent by the processor to the timing controller shows that every pixel row has been updated (this may happen in keyframes), it is not necessary to distinguish the driving mode. Instead, the entire surface can be refreshed. That is, all sub-pixels P are refreshed and displayed row by row and column by column according to the data corresponding to each pixel row. In this way, the timing controller does not need to bear the computational load caused by dividing the pixel rows.

[0163] In practice, the display module can be set with a trigger button for the driving mode. This trigger button can be a physical button or a virtual button. When the corresponding button is triggered, an identification signal is sent to the timing controller 30. The timing controller 30 can then determine which driving mode is being used based on the identification signal. Then, it operates in the driving mode to refresh the pixel row 11.

[0164] In one implementation of this embodiment, the driving mode can be triggered by the user based on a trigger button, or it can be triggered by the internal logic of the display module. For example, it can be triggered by the timing controller 30 based on the power status of the display module. Specifically, the timing controller 30 can be configured to acquire the power information of the display module and, when the power information meets the switching conditions, switch the currently triggered first driving mode to the second driving mode; or, switch the currently triggered second driving mode to the first driving mode; wherein the power information includes power consumption rate and / or remaining power.

[0165] In this implementation, the power information of the display module may include power consumption rate, remaining power, or both.

[0166] Among them, if the power consumption rate exceeds the preset rate, it means that the display module is consuming power quickly. In this case, if the display module is in the second driving mode, it means that the second driving mode consumes the display module's computing resources (pixel row grouping and calculation are required in the second driving mode). Then the second driving mode can be switched to the first driving mode. If it is in the first driving mode, there is no need to switch.

[0167] In this scenario, if the remaining battery power is less than a preset level, it indicates that the display module may be low on power. In this case, if the display module is in the first driving mode, it can be switched to the second driving mode to achieve maximum power saving. Alternatively, if the display module is in the second driving mode and the user is frequently viewing the screen, it can be switched back to the first driving mode to avoid the power consumption required for pixel row grouping and calculations in the second driving mode.

[0168] Specifically, considering both remaining battery power and power consumption rate, if the power consumption rate exceeds a preset rate or the remaining battery power is less than a preset level, and the display module is in the second driving mode, it can switch from the second driving mode to the first driving mode; otherwise, it does not need to switch. Furthermore, if the power consumption rate does not exceed the preset rate and the remaining battery power is not less than the preset level, it indicates that the display module has sufficient power. If the display module is in the first driving mode, it can switch from the first driving mode to the second driving mode, thereby maximizing power consumption and extending standby time.

[0169] In some embodiments, the timing controller 30 can count the first power consumption rate and the second power consumption rate in the same video, which are operating in the second driving mode and the first driving mode respectively. By comparing the first power consumption rate and the second power consumption rate, the power consumption required for pixel row grouping and calculation can be obtained. If the power consumption for pixel row grouping and calculation is large, the first driving mode can be used for refreshing. If the power consumption for pixel row grouping and calculation is small, it means that the grouping and calculation will not cause a large power loss, and the second driving mode can be used for refreshing.

[0170] In some embodiments of the display module, as the display module continuously refreshes multiple incoming frames, there are differences in the refresh rates of different areas within the display area AA, which may cause differences in brightness between different areas within the display area AA. Therefore, the timing controller 30 in the display module of this embodiment also aims to compensate for the regional brightness differences caused by the refresh rate differences. Specifically, the timing controller 30 can determine the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row 11n and the current refresh rate of each pixel row 11. During the scanning cycle of the frame, the timing controller 30 controls the gate driver terminal corresponding to the third pixel row to output a gate start signal, and the gate driver terminal corresponding to the fourth pixel row to output a gate stop signal; wherein the third pixel row includes the target pixel row 11n.

[0171] In this embodiment, the timing controller 30 can detect the refresh rate of each pixel row 11 in each frame. Based on the refresh rate of each pixel row 11, the refresh rate difference between pixel rows 11 in the display area AA can be obtained. Based on the refresh rate difference and the target pixel row 11n that has been updated in the current frame, the third pixel row to be refreshed and the fourth pixel row that will not be refreshed in the current frame are determined. The third pixel row includes the target pixel row 11n, and the fourth pixel row does not include the target pixel row 11n.

[0172] In one implementation of this embodiment, for multiple pixel rows 11 that are adjacent to the target pixel row 11n but are not refreshed in the current frame and have a significantly different refresh rate from the target pixel row 11n, the timing controller 30 can control the gate driver terminal connected to the gate line GL of the multiple pixel rows 11 to output a gate start signal, so that the multiple pixel rows 11 can be refreshed in the current frame, thereby compensating for the brightness difference between them and the target pixel row 11n. In other words, the multiple pixel rows 11 that are adjacent to the target pixel row 11n and have a significantly different refresh rate than the target pixel row 11n and have not had any updated data are controlled to be refreshed.

[0173] In another implementation of this embodiment, for pixel row 11 (hereinafter referred to as pseudo-update pixel row 11) that is determined to be refreshed in the current frame but does not belong to the target pixel row 11n based on the first driving mode and the second driving mode, if multiple pixel rows 11Q that are adjacent to the pseudo-update pixel row 11 and have a large difference in refresh rate from the pseudo-update pixel row 11 do not refresh in the current frame, then the pseudo-update pixel row 11 can be determined as the fourth pixel row and not refreshed; or, multiple pixel rows 11Q can be determined as the third pixel row and refreshed in the current frame to compensate for the brightness difference.

[0174] In another implementation of this embodiment, the timing controller 30 can also determine a target range 60 with a large refresh rate difference within the display area AA based on the refresh rate of each pixel row 11. Part of the multiple pixel rows 11 within the target range 60 is designated as the third pixel row, and part is designated as the fourth pixel row, so that the third and fourth pixel rows are interleaved within the target range 60. This can compensate for the brightness difference between regions caused by the refresh rate difference in the current frame, that is, by allowing the pixel rows 11 that are refreshed and not refreshed between two regions with a large brightness difference, thereby appropriately reducing the refresh rate difference between the two regions and blurring the boundary between the two regions with a large brightness difference.

[0175] In one example, the timing controller 30 can acquire multiple third pixel row groups obtained by grouping multiple pixel rows 11 according to the current target pixel row 11n, and control the gate driver terminal corresponding to a portion of the pixel rows 11 within the target range 60 to output a gate start signal and the gate driver terminal corresponding to the remaining portion of the pixel rows 11 to output a gate stop signal according to the current refresh rate of each pixel row 11; wherein, the target range 60 is the adjacency area between two adjacent third pixel row groups whose refresh rate difference is greater than a preset difference, the third pixel row also includes the pixel row 11 within the target range 60 that has been output with a gate start signal, and the fourth pixel row includes the pixel row 11 within the target range 60 that has been output with a gate stop signal.

[0176] In this embodiment, the third pixel row group is a row interval. A row interval may include multiple consecutive pixel rows 11, as shown in Figures 13a and 13b. Figures 13a and 13b illustrate the boundary blurring process. The multiple third pixel row groups can be either the first pixel row group or the second pixel row group mentioned above. Alternatively, the third pixel row group can be determined by the timing controller 30 based on the refresh rate of each pixel row 11. In this case, the timing controller 30 can detect the refresh rates of adjacent pixel rows 11 and group adjacent pixel rows with similar refresh rates into a third pixel row group. For example, taking Figure 13b as an example, assuming that the refresh rates of pixel rows 1-5 are similar, then pixel rows 1-5 constitute a third pixel row group a1. Pixel row 6 has a larger refresh rate difference from pixel row 5, but a smaller difference from the refresh rates of pixel rows 7-12. Therefore, pixel rows 6-12 can be grouped as a third pixel row group a2, and so on, to unequally divide multiple pixel rows 11 into multiple row intervals.

[0177] Specifically, the refresh rate difference between any two adjacent third pixel row groups can be determined. If the third pixel row group is obtained under the first driving mode, then the refresh rates of each pixel row 11 within the third pixel row group are the same. Therefore, the refresh rate difference between any two adjacent third pixel row groups is the difference in refresh rates between pixel rows 11 within those two adjacent third pixel row groups. Taking Figure 13a as an example, assuming that row intervals a1-a3 are obtained according to the first driving mode, the refresh rate difference between row intervals a1 and a2 is the refresh rate difference between pixel row 3 and pixel row 5. If the third pixel row group is obtained under the second driving mode or is dynamically divided, then the refresh rate of each third pixel row group is the average refresh rate of each pixel row 11 within that third pixel row group.

[0178] For two adjacent third pixel row groups whose refresh rates differ by a preset amount, the adjacency area between these two adjacent third pixel row groups can be defined as the target range 60. This target range 60 includes a portion of the pixel rows 11 within each of the two adjacent third pixel row groups. In practice, the pixel rows 11 within this target range 60 can be cross-refreshed within the current frame. As shown in Figures 13a and 13b, assuming that row intervals a1 and a2 are two intervals with a large refresh rate difference, the pixel rows 11 within the target range 60 of these two row intervals can be cross-refreshed within the current frame. The pixel rows 11 within the target range 60 include a portion of the pixel rows 11 in row interval a1 and a portion of the pixel rows 11 in row interval a2. The total number of pixel rows 11 within the target range 60 can be determined based on the refresh rate difference between the two row intervals; the larger the difference, the more pixel rows 11 are within the target range 60, and vice versa.

[0179] Specifically, a portion of pixel rows 11 within the target range 60 can be designated as the third pixel row, and another portion of pixel rows 11 can be designated as the fourth pixel row, as shown in Figure 13a. Pixel rows 3 and 5 within the target range 60 can be designated as the third pixel row, and pixel rows 4 and 6 as the fourth pixel row. Alternatively, as shown in Figure 13b, pixel rows 4, 7, and 8 can be designated as the third pixel row, and pixel rows 3, 5, 6, and 9 as the fourth pixel row.

[0180] It should be noted that if the target range 60 includes target pixel row 11n, as shown in Figure 13a, and pixel row 3 within the target range 60 is target pixel row 11n, then target pixel row 11n needs to be determined as the third pixel row. In some embodiments, the target range 60 must at least include pixel row 11m that has not been updated in the current frame.

[0181] Among them, the pixel row 11 in the display area AA, excluding the target range 60, can be refreshed according to the first driving mode and the second driving mode described above.

[0182] In this embodiment, the timing controller 30 can determine the target range 60 with large brightness difference according to the refresh rate of the pixel row 11, and determine the refresh state of the pixel row 11 within the target range 60 to blur the boundary between the two row intervals with large brightness difference in the current frame, thereby eliminating the brightness difference of the display panel and making the brightness of each area uniform.

[0183] In some examples of this embodiment, the third and fourth pixel rows within the target range 60 may be staggered or periodically arranged. Specifically, at least one fourth pixel row may be spaced between two adjacent third pixel rows within the target range 60; and / or, at least one third pixel row may be spaced between two adjacent fourth pixel rows within the target range 60.

[0184] In this embodiment, at least one fourth pixel row is spaced between two adjacent third pixel rows within the target range 60, and the fourth pixel rows can be arranged adjacently. Alternatively, at least one fourth pixel row is spaced between two adjacent third pixel rows within the target range 60, and the third pixel rows can be arranged adjacently. Or, at least one third pixel row is spaced between two adjacent fourth pixel rows within the target range 60, and at least one fourth pixel row can be spaced between two adjacent third pixel rows.

[0185] For example, as shown in FIG13a, adjacent third pixel rows within the target range 60 are spaced by a fourth pixel row, and adjacent fourth pixel rows are spaced by a third pixel row. Also for example, as shown in FIG13b, adjacent third pixel rows within the target range 60 are spaced by two fourth pixel rows, partially adjacent fourth pixel rows are spaced by two third pixel rows, and partially adjacent fourth pixel rows are spaced by a third pixel row.

[0186] Within the target range 60, the number of fourth pixel rows between each group of two adjacent third pixel rows can be the same, or the number of fourth pixel rows between different groups of two adjacent third pixel rows can be different. For example, some adjacent third pixel rows may be separated by one fourth pixel row, while others may be separated by two fourth pixel rows.

[0187] In this way, within the target range of 60, the refreshed and non-refreshed pixel rows 11 intersect, thereby blurring the boundary between two third pixel row groups with large refresh rate differences.

[0188] In some examples of this embodiment, in two adjacent third pixel row groups where the difference in refresh rate is greater than a preset difference, each third pixel row group includes a third pixel row and a fourth pixel row. This allows the brightness of the area in one of the three third pixel groups near the other to gradually transition to the area of ​​the other third pixel group. For example, as shown in Figure 13a, pixel row 3 near row interval a2 in row interval a1 is a third pixel row, pixel row 4 is a fourth pixel row, and pixel row 5 near row interval a1 in row interval a2 is a third pixel row, and pixel row 6 is a fourth pixel row. As another example, as shown in Figure 13b, pixel row 4 near row interval a2 in row interval a1 is a third pixel row, and pixel rows 3 and 5 are fourth pixel rows; pixel rows 7 and 8 near row interval a1 in row interval a2 are third pixel rows, and pixel rows 6 and 9 are fourth pixel rows.

[0189] In one example, among two adjacent pixel rows 11 within the target range 60 that belong to different third pixel row groups, one pixel row 11 can be a third pixel row and the other pixel row 11 can be a fourth pixel row. For example, as shown in FIG13a, if pixel row 4 and pixel row 5 are adjacent pixel rows 11 within the target range 60 that belong to different third pixel row groups, then pixel row 4 is a fourth pixel row and pixel row 5 is a third pixel row.

[0190] In one example of this embodiment, in two adjacent third pixel row groups where the difference between refresh rates is greater than a preset difference, the density of the third pixel row within the target range 60 in the third pixel row group with the smaller refresh rate is less than the density of the third pixel row within the target range 60 in the third pixel row group with the larger refresh rate; and the density of the fourth pixel row within the target range 60 in the third pixel row group with the smaller refresh rate is less than the density of the fourth pixel row within the target range 60 in the third pixel row group with the larger refresh rate.

[0191] The density of the third pixel row within the target range 60 in the third pixel row group can be understood as the proportion of the third pixel row within the target range 60 in a given third pixel row group to all pixel rows 11 within the target range 60 in that third pixel row group. For example, as shown in Figure 13c, in the third pixel group a1, the third pixel rows within the target range 60 are pixel rows 3 and 4, and the fourth pixel row is pixel 5. The proportion of the third pixel row in the third pixel group a1 is 2 / 3.

[0192] In this embodiment, third pixel rows with lower refresh rates generally have lower brightness, while third pixel rows with higher refresh rates generally have higher brightness. Therefore, within the target range of 60, the third pixel rows with higher refresh rates can have more third pixel rows and fewer fourth pixel rows, while the third pixel rows with lower refresh rates within the target range of 60 can have fewer third pixel rows and more fourth pixel rows. This allows high-brightness areas to gradually encroach on low-brightness areas; for example, the brightness can be gradually reduced from a high-brightness area to a low-brightness area. Adding a brightness gradient area between areas with significant brightness differences can alleviate the brightness difference between the two areas.

[0193] For example, as shown in Figure 13c, if the brightness of row interval a1 is higher and the brightness of row interval a2 is lower, then the density of the third pixel row set in row interval a1 within the target range 60 is 2 / 3, the density of the third pixel row in row interval a2 is 2 / 5, the density of the fourth pixel row set in row interval a1 within the target range 60 is 1 / 3, and the density of the fourth pixel row in row interval a2 is 3 / 5. As a result, the refresh rate of the high-brightness area within the target range 60 is appropriately reduced in this frame, while the refresh rate of the low-brightness area is appropriately increased in this frame, thereby improving the brightness difference to some extent.

[0194] In some examples, a group of third pixel rows with a higher refresh rate within the target range of 60 may have more third pixel rows and fewer fourth pixel rows, while a group of third pixel rows with a lower refresh rate within the target range of 60 may have fewer third pixel rows and more fourth pixel rows. Similarly, in a group of third pixel rows with more fourth pixel rows, the fourth pixel rows within the target range of 60 may be spaced apart.

[0195] In some embodiments, the display module can be a liquid crystal display module. Since the display module contains liquid crystal, it is necessary to control the polarity of the liquid crystal to reverse during image display to prevent the liquid crystal from remaining in one orientation for an extended period, which could lead to liquid crystal molecule polarization or image retention. In the display module provided in this embodiment, because there are updated frames in a local area, some pixel rows 11 are refreshed while the remaining pixel rows 11 are not. This means that in at least one frame, the voltage on the data line DL is not applied to some pixel rows 11, causing the orientation of the liquid crystal in those pixel rows 11 to remain unchanged for multiple adjacent frames. Therefore, the timing controller 30 can also work to improve the problem of the liquid crystal in some pixel rows 11 not reversing for a long time.

[0196] In this embodiment, the display module may further include a source drive circuit 50, as shown in FIG3. The source drive circuit 50 is connected to the timing controller 30 and is configured to output source voltages of opposite polarities within the scan cycles of two adjacent frames. The timing controller 30 is also configured to record the cumulative holding time of each polarity of the line interval, and based on the time difference between the cumulative holding times of different polarities of the line interval, control the source drive circuit 50 to output source voltages of the same target polarity in the adjacent N frames after the current frame. Wherein, N is greater than or equal to 1, and the target polarity is the same as the polarity with the shorter holding time.

[0197] The source driving circuit 50 includes multiple source driving terminals, each of which can be connected to a data line DL in the display panel, thereby outputting data voltage to a column of pixels in the display panel. The source driving circuit 50 outputs data voltages with opposite polarities in adjacent frames, thus allowing the liquid crystal molecules to change orientation between adjacent frames, thereby preventing liquid crystal polarization.

[0198] Taking the display module operating in the first driving mode as an example, the timing controller 30 can record the cumulative holding time of each first pixel row group (row interval) in each polarity, and record the time difference between the cumulative holding times of two adjacent different polarities. For example, as shown in Figure 10a, if rows 1-240 are not refreshed for 5 consecutive frames, then no polarity reversal will occur for those 5 consecutive frames. The time they hold one polarity (assuming it's positive) is the refresh time of 5 frames. If a refresh is required in frame 6, then a polarity reversal occurs in frame 6, and if refreshed again in frame 7, then another polarity reversal occurs in frame 7. Therefore, the cumulative holding time of positive polarity is the scan time of 7 frames, and the cumulative holding time of negative polarity is the scan time of 1 frame. Thus, in frame 8, the time difference between the cumulative holding times of positive and negative polarities for rows 1-240 is 6 frames.

[0199] Specifically, when there are many line intervals where the time difference between the cumulative holding durations of different polarities exceeds the preset time difference, or when the time difference between the cumulative holding durations of different polarities corresponding to any line interval exceeds the preset time difference, the timing controller 30 can control the source drive circuit 50 to perform polarity compensation. Specifically, it can control the source drive circuit 50 to output a source voltage of the same target polarity in the N adjacent frames after the current frame. This target polarity can be consistent with the polarity with the smaller cumulative holding duration. Continuing with the example in Figure 10a above, if the cumulative holding duration of the positive polarity is 7 frames of scan time and the cumulative holding duration of the negative polarity is 1 frame of scan time, then the source drive circuit 50 can be controlled to output a source voltage of negative polarity in the N adjacent frames after the current frame.

[0200] For example, as shown in Figure 14, which illustrates the timing signals of the source voltages with and without polarity compensation, when performing the compensation strategy, the accumulated time difference is calculated at the beginning of the frame. At position FA1, the time difference of the accumulated holding time for different polarities is bit [30:0]. Although the set threshold is reached, if the polarity is reversed in the next frame and is positive, opposite to the current polarity, then the frame continues to wait for the holding time of the positive polarity, and polarity compensation is not triggered. At position FA2, The time difference between the cumulative holding time of different polarities reaches the set threshold of bit [30:0], and bit

[0031] is read as "0" (mostly negative polarity), which is consistent with the polarity of the current frame (also negative polarity), triggering polarity compensation. Positive polarity needs to be compensated, so positive polarity is compensated for two consecutive frames, and the current frame can be the 0th frame. In this way, the polarity of the 1st frame is reversed to positive polarity, and the polarity of the 2nd and 3rd frames is not reversed at the position of FA3, that is, the 2nd and 3rd frames maintain positive polarity. Thus, 3 frames of positive polarity are compensated.

[0201] The preset time difference can be determined based on the electrical characteristics of the display module. For example, the preset time difference can depend on how long the liquid crystal will be affected by residual charge (or polarization electric field) before polarization occurs. In other words, the threshold is determined based on the characteristics of the liquid crystal. For example, the preset time difference can be set to 20ms.

[0202] In some embodiments, the number of line intervals with the same target polarity in the current frame may be greater than the number of line intervals with different target polarities.

[0203] Since it includes multiple first pixel row groups, each first pixel row group is a row interval. Therefore, the display area AA includes multiple row intervals. Each row interval can be driven to refresh independently in this display module according to the image data. Thus, different row intervals have different cumulative holding times with positive and negative polarities. In this way, different row intervals can correspond to different time differences.

[0204] In this embodiment, to maintain the performance of the liquid crystal in the entire display panel, that is, to ensure that the cumulative holding time of the liquid crystal in the entire display panel is not significantly different for positive and negative polarities, in some examples, the cumulative holding time of positive and negative polarities in each row interval can be considered holistically. Specifically, when there are many row intervals where the time difference between the cumulative holding time of different polarities exceeds a preset time difference, it can be determined which polarity is generally held for a shorter time in multiple row intervals. For example, taking Figure 10b as an example, for instance, in multiple row intervals where the time difference exceeds the preset time difference, it is determined that the time difference between the cumulative holding time of positive and negative polarities in four row intervals exceeds the preset time difference. Among them, the row intervals with shorter holding times in the row intervals from row 1 to row 100, row intervals from row 201 to row 300, and row intervals from row 301 to row 400 are positive polarities. Therefore, the positive polarity can be positive polarity if the holding time of positive polarity is shorter in more row intervals, that is, the source drive circuit 50 is controlled to maintain positive polarity for N frames.

[0205] Thus, in the current frame, the number of first-row intervals is greater than the number of second-row intervals; specifically, the cumulative holding time of the target polarity in the first-row intervals is less than the cumulative holding time of the polarity opposite to the target polarity, and the cumulative holding time of the target polarity in the second-row intervals is not less than the cumulative holding time of the polarity opposite to the target polarity. In other words, the target polarity for compensation can be determined based on whether the cumulative holding time of the same polarity is relatively small in most row intervals; if so, then that polarity is compensated; otherwise, no compensation is needed.

[0206] In some examples, if among multiple line intervals with a time difference exceeding a preset time difference, half of the line intervals with a shorter cumulative holding time have a positive polarity and the other half of the line intervals with a shorter cumulative holding time have a negative polarity, then no compensation is required. In this case, the source voltage output by the source drive circuit 50 in the next frame can be output according to its original logic.

[0207] The connection structure between the timing controller 30 and the gate drive circuit 20 will be described below as an example.

[0208] The gate drive circuit 20 includes multiple cascaded shift register units. Each shift register unit includes one or more gate drive terminals GO (GO_1), as shown in Figure 15a. One shift register unit includes one gate drive terminal GO, as shown in Figure 16. One shift register unit includes four gate drive terminals GO.

[0209] As shown in Figures 15a and 16, the timing controller 30 includes K second cascaded clock signal terminals (CLKC1, CLKC2, CLKC3) and M second drive clock signal terminals (CLK1 to CLK12). The input side of each shift register unit includes a first cascaded clock signal terminal (CLKC) and J first drive clock signal terminals (CLK1 to CLK4). The J first drive clock signal terminals are respectively connected to J of the M second drive clock signal terminals. Each first drive clock signal terminal is connected to a gate drive terminal Out-c located on the output side; where K = M / J.

[0210] The timing controller 30 is configured to load different first clock signals CLKC onto K first cascaded clock signal terminals and load a second clock signal CLK onto the m-th second drive clock signal terminal during the scanning cycle of the frame.

[0211] Among them, the first clock signal CLKC (CLKC1 to CLKC3 in Figures 17 and 18) is a signal that alternates between active and inactive levels. The second clock signal CLK and the first clock signal CLKC are active levels in the refresh timing of the refreshed pixel row 11, and the second clock signal CLK (CLK1 to CLK12 in Figures 17 and 18) is inactive level in the refresh timing of the non-refreshed pixel row.

[0212] In this embodiment, the first clock signal CLKC input to the first cascaded clock signal terminal and the second clock signal CLK input to the first drive clock signal terminal work together to control the gate signal output by the gate drive terminal GO of the shift register unit.

[0213] As shown in Figure 15b, in some embodiments, the shift register unit may include:

[0214] The pull-up circuit is configured to respond to the signal at the input signal terminal INP and provide the signal at the input signal terminal INP to the first pull-up node PU1 and K second pull-up nodes (PU21~PU2K, as shown in Figure 15b with J=1 as an example); J is an integer greater than 0.

[0215] The reset circuit is configured to provide the reference voltage signal VREF to the first pull-up node PU1 (i.e., PU) in response to the reset signal terminal RST.

[0216] The noise reduction circuit is configured to control the signal of the pull-down node PD according to the signal of the first pull-up node PU1, and to control the signals of the first pull-up node and J second pull-up nodes (PU21 to PU2K) according to the signal of the pull-down node PD.

[0217] The cascaded circuit is configured to provide the cascaded clock signal CLKC to the cascaded output Outc in response to the signal of the first pull-up node PU1, and to provide the reference voltage signal VREF to the cascaded output Outc in response to the signal of the pull-down node PD. The cascaded output Outc is connected to the input of the next-stage shift register unit as the INP of the next-stage shift register unit, and the input of the first-stage shift register unit is connected to the STV1 signal.

[0218] There are J output circuits. In Figure 15b, taking J as 1 as an example, the j-th output circuit is coupled to the j-th second pull-up node PU2k among the N second pull-up nodes (PU21~PU2K) and the j-th drive clock signal terminal CLKk among the N drive clock signal terminals (CLK1~CLKK). The j-th output circuit 50k is configured to provide the signal of the j-th drive clock signal terminal CLKk to the j-th drive output terminal GOk in response to the signal of the j-th second pull-up node PU2k, and to provide the signal of the reference voltage signal terminal VREF to the j-th drive output terminal GOk in response to the signal of the pull-down node PD. j is an integer and 1≤j≤J.

[0219] The number of second-cascaded clock signal terminals is the ratio of the number of second-drive clock signal terminals to the number of first-drive clock signal terminals included in each shift register unit. For example, as shown in Figure 15a, if each shift register unit includes two second-drive clock signal terminals and one first-drive clock signal terminal, then it includes two second-cascaded clock signal terminals. As shown in Figure 16, if each shift register unit includes 12 second-drive clock signal terminals and four first-drive clock signal terminals, then it includes three second-cascaded clock signal terminals.

[0220] In this embodiment, the first clock signal CLKC is input from the second cascaded clock signal terminal to the first cascaded clock signal terminal of the shift register unit, and the second clock signal CLK is input from the second drive clock signal terminal to the first drive clock signal terminal of the shift register unit. A high-level pulse signal of each first clock signal CLKC corresponds to a precondition for the gate enable signal output from the J gate drive terminals in the corresponding shift register unit. This can be understood as a precondition for the thin-film transistor of sub-pixel P on pixel row 11 to be enabled. In this embodiment, when one pulse signal of the first clock signal CLKC is a high-level pulse signal, the corresponding timing pulse signal in the second clock signal CLK must be set high to enable the corresponding row.

[0221] For example, as shown in Figure 17, which uses the connection architecture of Figure 16 as an example, Figure 17 shows the timing diagram of the first clock signal CLKC and the second clock signal CLK when global display is performed in the display area AA. In Figure 16, each shift register unit includes four first drive clock signal terminals and four gate drive terminals GO (GO is not labeled in Figure 16). Each gate drive terminal GO corresponds to a gate line GL. In Figure 17, STV1 is the start trigger signal of the shift register unit. CLKC1 to 3 are the three first clock signals CLKC output by the three second cascaded clock signal terminals, and CLK1 to 12 are the 12 second clock signals CLK output by the second drive clock signal terminals. The high-level pulse signals of CLK1 to 12 control the first row, the second row, ... until the last row from left to right. The control logic is that when the corresponding CLKC and CLK signals are high at the same time, the corresponding row can be opened.

[0222] For example, as shown in Figure 18, which uses the connection architecture of Figure 16 as an example, Figure 18 shows the timing diagram of the first clock signal CLKC and the second clock signal CLK when the display area AA is partially refreshed. In Figure 18, STV1 is the start trigger signal of the shift register unit, CLKC1 to CLKC3 are the three first clock signals CLKC output by the three second cascaded clock signal terminals, and CLK1 to CLK12 are the second clock signals CLK output by the twelve second drive clock signal terminals. It can be seen that if the 13th row is not refreshed, then CKL1 is low in the timing of the 13th row. If the 26th row is not refreshed, then CKL2 is low in the timing of the 26th row, so that the sub-pixels of the 13th and 26th rows are not turned on.

[0223] For example, Figure 8 shows a schematic diagram of the change of the second clock signal CLK from refreshing the entire display area AA to refreshing a portion of the display area AA. Taking Figure 6 as an example, rows a to a+b and rows c to c+d in the display area AA are updated. It is determined that rows e to e+f and rows g to g+h need to be refreshed. Therefore, the timing of the second clock signal CLK corresponding to rows e to e+f and rows g to g+h is a high-level pulse, while the timing of other rows is a low-level pulse.

[0224] As another example, we can refer to Figures 7 and 9. Figure 9 shows a schematic diagram of the change of the second clock signal CLK in Figure 7. As shown in Figure 7, the z to z+m rows in the display area AA are updated, and it is determined that the x to x+n rows need to be refreshed. Therefore, the timing of the second clock signal CLK corresponding to the x to x+n rows is a high-level pulse, and the timing of the other rows is a low-level pulse.

[0225] As shown in Figure 19, the image data received by the timing controller 30 includes data for target pixel rows 11n and data for non-target pixel rows 11n. The Adaptive sync SDP (Secondary-Data Packet) is a synchronization data packet primarily responsible for informing the refresh rate information of the transmitted frame; the VSC SDP is a Video Stream Configuration data packet primarily responsible for informing the transmitted frame of update area information (including X and Y coordinates, update area, CRC checksum, etc.). When multiple update areas exist in the same frame, the main link is opened when sending update data. The non-updated areas are empty data packets, and although image data for these areas does not need to be sent, they still need to form a packet and be sent to the timing controller 30. In other words, the image data for each pixel row 11n forms a separate data packet. Although the non-updated pixel row 11m is an empty data packet, it needs to maintain the time required for normal transmission. Simultaneously, the main link for that pixel row 11m is closed to reduce system data transmission and achieve power saving.

[0226] In Figure 19, the VSC SDP with SU coordinates should be transmitted on the line of SU or on the line before SU, and meet the 100ns setting time. For SU regions 0 and 1 of video frame 0, the VSC SDP with CRC should be transmitted before the next active video frame time interval. The VSC SDP may also have the X and Y coordinates of the SU region of video frame 1.

[0227] For the timing controller 30, it can calculate the arrival time of each data packet (non-empty data packet) carrying image data, thereby obtaining the position of the target pixel row 11n, and then control some pixel rows 11, including the target pixel row 11n, to refresh in this frame, while the remaining pixel rows 11 maintain the state of the previous frame, ultimately forming a complete picture.

[0228] Secondly, this embodiment also provides a display driving method, which can be applied to the display module described in the first aspect above. Specifically, the display driving method can be configured into a timing controller and may include the following steps:

[0229] Step S101: Obtain image data for each frame. The image data includes update data corresponding to the target pixel row 11n. The target pixel row is the pixel row whose image data has changed compared to the previous frame.

[0230] Step S102: Based on the target pixel row 11n, determine the pixel row to be refreshed within the scanning cycle of each frame. The pixel row to be refreshed includes the target pixel row 11n. In at least one frame, the pixel row to be refreshed is a portion of the multiple pixel rows.

[0231] Step S103: Output a gate start signal to the pixel row to be refreshed so that the pixel row to be refreshed is refreshed.

[0232] In some embodiments, when determining the pixel row to be refreshed within a scan cycle of each frame based on the target pixel row 11n, at least one of the following is included:

[0233] Method 1: Among multiple first pixel row groups, determine the target pixel row 11n in the target pixel row group, and determine the target pixel row group as the pixel row to be refreshed. This method can correspond to the first driving mode described in the above embodiment.

[0234] Method 2: Based on the position of the target pixel row 11n, the multiple pixel rows are divided according to the preset number of pixel row groups to obtain multiple second pixel row groups, and the pixel rows included in the second pixel row where the target pixel row 11n is located are determined as the pixel rows to be refreshed; this method 2 can correspond to the second driving mode described in the above embodiment.

[0235] Method 3: Determine the target pixel row 11n as the pixel row to be refreshed. This method 3 can correspond to the second driving mode described in the above embodiments.

[0236] The timing controller supports modes 1 through 3, and can select which mode to use for driving the display in response to user triggers or based on the power status of the display module. For details, please refer to the description in the above-mentioned display module embodiment.

[0237] In some embodiments, when determining the pixels to be refreshed within a scan cycle of each frame based on the target pixel row, the current refresh rate of each pixel row can be obtained; based on the target pixel row 11n and the current refresh rate of each pixel row, the third pixel row to be refreshed and the fourth pixel row not to be refreshed are determined; wherein the third pixel row includes the target pixel row 11n. Accordingly, the timing controller can also control the gate drive terminal corresponding to the fourth pixel row to output a gate cutoff signal during the scan cycle of at least one frame, so that the fourth pixel row is not refreshed in the current frame.

[0238] It should be noted that the method in this embodiment can be used to compensate for the problem of large brightness differences caused by large differences in the row intervals with large refresh rates. That is, it can gradually transition from a high-brightness area to a low-brightness area. For details, please refer to the embodiment of the display module described above.

[0239] In one example of this embodiment, when determining the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row 11n and the current refresh rate of each pixel row, multiple pixel rows can be divided into multiple third pixel row groups according to the target pixel row 11n; for two adjacent third pixel row groups whose refresh rate difference is greater than a preset difference, a target range located in the boundary interval of the two adjacent third pixel row groups is determined; the target pixel row and some pixel rows located within the target range are determined as third pixel rows, and the remaining pixel rows within the target range are determined as fourth pixel rows.

[0240] The method in this example can be referred to the embodiment of the display module described above.

[0241] In one example of this embodiment, in the first driving mode, source voltages with opposite polarities can also be output to multiple pixel rows in two adjacent frames; the time difference corresponding to each first pixel row group during two adjacent polarity switching is recorded; when the time difference exceeds a preset time difference, the source driving circuit is controlled to output source voltages with the same target polarity in the N adjacent frames after the current frame; wherein, N is greater than or equal to 1, and the target polarity is the same as the polarity of at least one first pixel row group in the current frame.

[0242] Using this example method can make the cumulative holding time of positive and negative polarities in the liquid crystal display module smaller, thereby avoiding the problem of liquid crystal polarization caused by the liquid crystal being in one deflection position for too long. The method in this example can refer to the description in the above-mentioned display module embodiment.

[0243] This embodiment also provides a display device, which may include the display module shown in the first aspect above. The display device may be a liquid crystal display device or an OLED display device.

[0244] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0245] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0246] The above provides a detailed description of a display module, display driving method, and display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0247] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0248] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0249] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0250] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0251] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0252] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display module, characterized in that, include: The display panel includes multiple pixel rows, and each pixel row is provided with at least one grid line; A gate driving circuit includes multiple gate driving terminals, each of which is connected to multiple gate lines. A timing controller, connected to the gate driving circuit, is configured to receive update data corresponding to the frame during the display of at least one frame, and based on the target pixel row where the update data is located, control the gate driving terminal connected to the gate line of a portion of the pixel row to output a gate start signal during the scanning cycle of the frame, so that a portion of the pixel row is refreshed. The refreshed pixel row includes the target pixel row.

2. The display module according to claim 1, characterized in that, The timing controller is configured at least in a first driving mode to control the gate driving terminals of the plurality of gate driving terminals corresponding to the pixel rows in the same row interval to output gate signals of the same type in each frame, so that the plurality of pixel rows located in the same row interval have the same refresh rate in each frame. The gate signal includes the gate start signal and the gate stop signal.

3. The display module according to claim 2, characterized in that, The plurality of pixel rows are divided into a plurality of first pixel row groups, wherein the first pixel row group includes a plurality of adjacent pixel rows; Specifically, the timing controller is configured to respond to the first driving mode by controlling the gate driving terminal corresponding to the first pixel row group where the target pixel row is located to output the gate start signal and the gate driving terminal corresponding to the first pixel row group excluding the target pixel row to output the gate stop signal during the scanning period of the frame.

4. The display module according to claim 1, characterized in that, The timing controller is configured at least in the second driving mode to control the first pixel row to form a pixel row group with different numbers and / or positions of the second pixel row in at least two different frame scan cycles, and to control the gate driving terminal corresponding to the pixel row group to output the same type of gate signal. The gate signal includes the gate start signal and the gate stop signal.

5. The display module according to claim 4, characterized in that, The timing controller is specifically configured to respond to the second driving mode, divide the multiple pixel rows into multiple second pixel row groups based on the target pixel row, and control the gate driving terminal corresponding to the second pixel row group where the target pixel row is located to output the gate start signal and the gate driving terminal corresponding to the second pixel row group excluding the target pixel row to output the gate cut-off signal during the scanning period of the frame. In this context, different frames correspond to the same number of second pixel row groups.

6. The display module according to claim 4, characterized in that, The timing controller is specifically configured to, in response to the second driving mode, control the gate driving terminal corresponding to the target pixel row to output the gate start signal during the scanning cycle of the frame; and control the gate driving terminal corresponding to the pixel row other than the target pixel row to output the gate cut-off signal.

7. The display module according to any one of claims 1-6, characterized in that, The timing controller is further configured to determine the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row and the current refresh rate of each pixel row, and to control the gate driver terminal corresponding to the third pixel row to output the gate start signal and control the gate driver terminal corresponding to the fourth pixel row to output the gate cut-off signal during the scanning cycle of the frame. The third pixel row includes the target pixel row.

8. The display module according to claim 7, characterized in that, The timing controller is specifically configured to obtain multiple third pixel row groups obtained by grouping multiple pixel rows based on the target pixel row, and to control at least a portion of the pixel rows within the target range as the third pixel row and the remaining portion of the pixel rows within the target range as the fourth pixel row according to the current refresh rate of each pixel row. The target range is the adjacent area between two adjacent third pixel row groups whose refresh rate difference is greater than a preset difference.

9. The display module according to claim 8, characterized in that, The target range is such that at least one fourth pixel row is spaced between two adjacent third pixel rows; and / or, the target range is such that at least one third pixel row is spaced between two adjacent fourth pixel rows.

10. The display module according to claim 8, characterized in that, In two adjacent third pixel row groups where the difference between refresh rates is greater than the preset difference, each third pixel row group includes the third pixel row and the fourth pixel row.

11. The display module according to claim 8, characterized in that, In two adjacent third pixel row groups where the difference in refresh rate is greater than the preset difference, the density of the third pixel row within the target range in the third pixel row group with the smaller refresh rate is less than the density of the third pixel row within the target range in the third pixel row group with the larger refresh rate; and the density of the fourth pixel row within the target range in the third pixel row group with the smaller refresh rate is less than the density of the fourth pixel row within the target range in the third pixel row group with the larger refresh rate.

12. The display module according to claim 2 or 3, characterized in that, The display panel includes a liquid crystal display panel, and the display module further includes: The source drive circuit, connected to the timing controller, is configured to output source voltages of opposite polarity within the scan cycles of two adjacent frames. The timing controller is also configured to record the cumulative holding time of the line interval in each polarity, and based on the time difference between the cumulative holding times of the different polarities of the line interval, control the source drive circuit to output the source voltage of the same target polarity in the N adjacent frames after the current frame; Wherein, N is a positive integer greater than or equal to 1, and the target polarity is the same as the polarity with the shorter retention time.

13. The display module according to claim 12, characterized in that, In the current frame, the number of first row intervals is greater than the number of second row intervals; wherein, the cumulative holding time of the target polarity in the first row interval is less than the cumulative holding time of the polarity opposite to the target polarity, and the cumulative holding time of the target polarity in the second row interval is not less than the cumulative holding time of the polarity opposite to the target polarity.

14. The display module according to claim 1, characterized in that, The gate drive circuit includes multiple cascaded shift register units, and the input side of each shift register unit includes a first cascaded clock signal terminal and J first drive clock signal terminals; the timing controller includes K second cascaded clock signal terminals and M second drive clock signal terminals. Wherein, J of the first drive clock signal terminals are respectively connected to J of the M second drive clock signal terminals, and one of the first drive clock signal terminals is connected to a gate drive terminal located on the output side; wherein, K = M / J; K, M and J are all positive integers greater than or equal to 1; The timing controller is configured to load different first clock signals to K first cascaded clock signal terminals and load a second clock signal to the m-th second drive clock signal terminal during the scanning period of the frame. Wherein, the first clock signal is a signal that alternates between valid and invalid levels, the second clock signal and the first clock signal are valid levels in the refresh timing of the refreshed pixel row, and the second clock signal is invalid level in the refresh timing of the non-refreshed pixel row.

15. The display module according to any one of claims 1-6, characterized in that, The display module also includes: The processor, connected to the timing controller, is configured to send update data to the timing controller, which shows that each frame is newer than the previous frame. The timing controller is further configured to, when the update data indicates that some pixel rows in the current frame have been updated compared to the previous frame, obtain the currently triggered driving mode, divide the multiple pixel rows based on the currently triggered driving mode and the target pixel row where the update data is located, and control the gate driver terminal corresponding to the pixel row group where the target pixel row is located to output a gate start signal within the scanning cycle of the frame. The driving mode includes a first driving mode and a second driving mode. The first driving mode is used to indicate that the multiple pixel rows are divided according to fixed boundaries, and the second driving mode is used to indicate that the multiple pixel rows are divided according to non-fixed boundaries. The boundary is used to distinguish different pixel row groups.

16. The display module according to claim 15, characterized in that, The timing controller is specifically configured to acquire the power information of the display module, and when the power information meets the switching conditions, switch the currently triggered first driving mode to the second driving mode; or, switch the currently triggered second driving mode to the first driving mode. The power information includes power consumption rate and / or remaining power.

17. A display driving method, characterized in that, The method is applied to a display module, the display module comprising multiple pixel rows, the method comprising: Acquire image data for each frame, the image data including update data corresponding to the target pixel row, the target pixel row being the pixel row whose image data has changed compared to the previous frame; Based on the target pixel row, within the scanning cycle of each frame, a pixel row to be refreshed is determined, the pixel row to be refreshed including the target pixel row; wherein, in at least one frame, the pixel row to be refreshed is a portion of a plurality of pixel rows; A gate enable signal is output to the pixel row to be refreshed, so that the pixel row to be refreshed is refreshed.

18. The display driving method according to claim 17, characterized in that, The step of determining the pixel row to be refreshed within the scanning cycle of each frame, based on the target pixel row, includes at least one of the following: In a plurality of first pixel row groups, determine the target pixel row group in which the target pixel row is located, and determine the pixel row included in the target pixel row group as the pixel row to be refreshed; Based on the position of the target pixel row, the multiple pixel rows are divided into multiple second pixel row groups according to a preset number of pixel row groups, and the pixel rows included in the second pixel row where the target pixel row is located are determined as the pixel row to be refreshed; The target pixel row is determined as the pixel row to be refreshed.

19. The display driving method according to claim 17 or 18, characterized in that, The step of determining the pixel row to be refreshed within the scanning cycle of each frame, based on the target pixel row, includes: Get the current refresh rate for each pixel row; Based on the target pixel row and the current refresh rate of each pixel row, determine the third pixel row to be refreshed and the fourth pixel row not to be refreshed; wherein, the third pixel row includes the target pixel row; The method further includes: During the scanning cycle of at least one frame, the gate drive terminal corresponding to the fourth pixel row is controlled to output a gate cut-off signal so that the fourth pixel row is not refreshed in the current frame.

20. The display driving method according to claim 19, characterized in that, The step of determining the third pixel row to be refreshed and the fourth pixel row not to be refreshed based on the target pixel row and the current refresh rate of each pixel row includes: Based on the target pixel rows, the plurality of pixel rows are divided into a plurality of third pixel row groups; For two adjacent third pixel row groups whose refresh rates differ by a preset difference, determine the target range of the adjacency area located in the two adjacent third pixel row groups. The target pixel row and a portion of the pixel rows within the target range are defined as the third pixel row, and the remaining pixel rows within the target range are defined as the fourth pixel row.

21. The display driving method according to claim 18, characterized in that, When determining the pixel rows included in the target pixel row group in a plurality of first pixel row groups as the pixel row to be refreshed, the method further includes: In two adjacent frames, source voltages of opposite polarity are output to multiple rows of pixels; Record the cumulative duration of the row interval in each polarity; Based on the time difference between the cumulative holding times of different polarities in the line interval, the source drive circuit is controlled to output the source voltage of the same target polarity in the N adjacent frames after the current frame. Where N is greater than or equal to 1, the target polarity is the same as the polarity with the shorter retention time.

22. A display device, characterized in that, Includes the display module described in any one of claims 1-16.

Images