Array substrate, display panel, and display device

Abstract

An array substrate (100), comprising a first substrate (10), a plurality of first electrodes (11), a plurality of signal line groups (20), a plurality of third signal lines (30), a plurality of first transistors (T1), and a second electrode layer (40). Each signal line group (20) comprises a first signal line (21) and a second signal line (22), the orthographic projections of the plurality of third signal lines (30) and the plurality of signal line groups (20) on the first substrate (10) intersect with each other to form a grid structure, and one grid defines one pixel region (101). The first electrodes (11) are located in the pixel regions (101). The gates of the first transistors (T1) are electrically connected to the first signal lines (21). The second electrode layer (40) is disposed on the sides of the first signal lines (21) away from the first substrate (10), and the second electrode layer (40) is electrically connected to the second signal lines (22). The orthographic projection of the second electrode layer (40) on the first substrate (10) does not overlap with the orthographic projections of the first transistors (T1) on the first substrate (10), at least partially overlaps with the orthographic projections of the plurality of third signal lines (30) on the first substrate (10), and covers at least part of the edges of the orthographic projections of the first signal lines (21) on the first substrate (10).

Description

Array substrate, display panel and display device

[0001] This application claims priority to PCT International Patent Application No. PCT / CN2024 / 128238, filed on October 29, 2024, and Chinese Patent Application No. 202510727541.2, filed on May 30, 2025, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display devices have been widely applied, and people's requirements for display devices are also getting higher and higher. Among them, high pixel density (Pixels Per Inch; PPI for short) and high refresh rate are an important development direction of display devices. Common display devices can include liquid crystal display devices (Liquid Crystal Display; LCD for short) and organic light-emitting diode display devices (Organic Light-Emitting Diode; OLED for short). Due to the simpler pixel circuit structure of liquid crystal display devices (which can contain fewer thin film transistors and capacitors), liquid crystal display devices have more advantages in ultra-high pixel density (such as greater than or equal to 1000 PPI). In liquid crystal display devices, the charging ratio of the pixel is another very important indicator, which directly affects the brightness, transmittance, picture quality and other performance of the liquid crystal panel. With the increase of the pixel density and refresh rate of the display device, the challenge to the charging ratio is also getting bigger and bigger. How to improve the charging ratio of the pixel is a technical problem that needs to be solved urgently for high refresh rate display devices. SUMMARY

[0004] In one aspect, an array substrate is provided. The array substrate includes a first substrate, a plurality of first electrodes disposed on one side of the first substrate, and a plurality of signal line groups spaced apart along a first direction, each of the signal line groups including a first signal line and a second signal line, the first signal line and the second signal line each extending along a second direction, the first direction intersecting the second direction. The array substrate further includes a plurality of third signal lines, a plurality of first transistors, and a second electrode layer. The plurality of third signal lines are spaced apart along the second direction, each of the third signal lines extending along the first direction. The plurality of third signal lines and the plurality of signal line groups form a grid structure by their orthogonal projections on the first substrate, one grid defining one pixel region. The first electrode is located within the pixel region. The gate of the first transistor is electrically connected to the first signal line. The second electrode layer is disposed on a side of the first signal line away from the first substrate, and is electrically connected to the second signal line. The orthogonal projection of the second electrode layer on the first substrate does not overlap with the orthogonal projection of the first transistor on the first substrate, and at least partially overlaps with the orthogonal projection of the plurality of third signal lines on the first substrate, and covers at least part of the edge of the orthogonal projection of the first signal line on the first substrate.

[0005] In some embodiments, the array substrate further includes a planar layer, a first insulating layer, and a first via. The planar layer is disposed on a side of the first transistor away from the first substrate; the first insulating layer is disposed on a side of the planar layer away from the first substrate; and the first via penetrates the planar layer. In which, the first electrode is disposed between the planar layer and the first insulating layer, and the second electrode layer is disposed on a side of the first insulating layer away from the first substrate; the first electrode is electrically connected to the first transistor through the first via.

[0006] In some embodiments, the first transistor includes a source pattern and a drain pattern, the source pattern is electrically connected to the third signal line, and the drain pattern is electrically connected to the first electrode. The first via includes a first portion and a second portion, the first portion exposes at least part of the drain pattern, and the orthogonal projection of the second portion on the first substrate is located outside the orthogonal projection of the drain pattern on the first substrate.

[0007] In some embodiments, the first portion and the second portion are arranged along the first direction, and the second portion is located on a side of the first portion close to the pixel region. The first electrode includes a connecting portion, the connecting portion extends to the first portion and connects the drain pattern through the second portion.

[0008] In some embodiments, a size of a projection of the connection portion on the first substrate along the second direction is greater than a size of a projection of the first via on the first substrate along the second direction. The connection portion also covers at least one side of the first via in the second direction in the planar layer.

[0009] In some embodiments, the connection portion covers both sides of the first via in the second direction in the planar layer.

[0010] In some embodiments, an interval between an end of a projection of the connection portion on the first substrate along the second direction and a boundary of a projection of the first via on the first substrate is greater than or equal to 2.1 μm.

[0011] In some embodiments, the array substrate further includes a second via and a bridging portion. The second via penetrates the first insulating layer, and a projection of the second via on the first substrate at least partially overlaps a projection of the first via on the first substrate. The bridging portion comprises a same material as and is disposed in a same layer as the second electrode layer, and is electrically insulated from the second electrode layer. The bridging portion is connected to the first electrode through the second via.

[0012] In some embodiments, at least a portion of a projection of the second via on the first substrate is outside a projection of the first via on the first substrate.

[0013] In some embodiments, an interval between a boundary of a portion of a projection of the second via on the first substrate that is outside a projection of the first via on the first substrate and a boundary of a projection of the first via on the first substrate is greater than or equal 1 μm.

[0014] In some embodiments, the first electrode includes an electrode portion and a connection portion. The electrode portion is located within the pixel region. The connection portion is located on one side of the electrode portion along the first direction and is connected to the electrode portion. The connection portion is electrically connected to the first transistor through the first via. A projection of the bridging portion on the first substrate covers a projection of the second via on the first substrate and covers a projection of a portion of the connection portion that is away from the electrode portion on the first substrate.

[0015] In some embodiments, an interval between a boundary of a projection of the bridging portion on the first substrate and a boundary of a projection of the connection portion on the first substrate is greater than or equal to 1 μm; and / or, a size of the first via along the second direction is greater than or equal to 4 μm; and / or, a size of the second via along the second direction is greater than or equal to 4 μm.

[0016] In some embodiments, the array substrate further comprises a second insulating layer, a third via hole and a fourth via hole. The second insulating layer is between a film layer where the group of signal lines is located and a film layer where the third signal line is located. The third via hole penetrates the planar layer, and a footprint of the third via hole on the first substrate at least partially overlaps with a footprint of the second signal line on the first substrate. A footprint of the fourth via hole on the first substrate at least partially overlaps with a footprint of the third via hole on the first substrate, the fourth via hole penetrates the first insulating layer and the second insulating layer, and exposes part of the second signal line. The second electrode layer is electrically connected to the second signal line through the fourth via hole and the third via hole.

[0017] In some embodiments, the third via hole comprises a third portion and a fourth portion, a footprint of the third portion on the first substrate is within a footprint of the second signal line on the first substrate, and a footprint of the fourth portion on the first substrate does not overlap with a footprint of the second signal line on the first substrate.

[0018] In some embodiments, at least part of a footprint of the fourth via hole on the first substrate is outside a footprint of the third via hole on the first substrate.

[0019] In some embodiments, the fourth portion is located on a side of the third portion close to the first signal line. In a footprint of the fourth via hole on the first substrate, both ends along the second direction and an end along the first direction away from the first signal line are within a footprint of the third via hole on the first substrate, and an end along the first direction close to the first signal line is outside a footprint of the third via hole on the first substrate.

[0020] In some embodiments, in a footprint of the fourth via hole on the first substrate, both ends along the second direction and the end along the first direction away from the first signal line are separated from a boundary of a footprint of the third via hole on the first substrate by a distance greater than or equal to 2.1 μm. And / or, in a footprint of the third via hole on the first substrate, the end along the first direction away from the first signal line is separated from a boundary of a footprint of the third via hole on the first substrate by a distance of greater than or equal to 1 μm.

[0021] In some embodiments, the second signal line is recessed to form a first recess on a side away from the first signal line at positions of the third via hole and the fourth via hole, and the fourth via hole exposes at least part of an area of the first recess.

[0022] In some embodiments, the first signal line includes a main body portion and a plurality of protruding portions, the main body portion extends along the second direction, the plurality of protruding portions are spaced apart along the second direction, and at least part of the protruding portions are located on a side of the main body portion away from the second signal line. The protruding portions include a gate region and a pedestal region, the gate region is disposed on the side of the main body portion away from the second signal line and is configured to form a gate of the first transistor, and at least part of the pedestal region is disposed on the side of the main body portion away from the second signal line and is configured to support a spacer.

[0023] In some embodiments, the spacer includes a main spacer and a sub spacer. The plurality of protruding portions include a plurality of the pedestal regions including a first pedestal region and a second pedestal region. The first pedestal region is located on the side of the main body portion away from the second signal line and is configured to support the sub spacer. The second pedestal region is partially located on the side of the main body portion away from the second signal line and partially located on a side of the main body portion close to the second signal line, and the second pedestal region is configured to support the main spacer.

[0024] In some embodiments, a dimension of the second pedestal region along the first direction on the side of the main body portion away from the second signal line is greater than a dimension of the second pedestal region along the first direction on the side of the main body portion close to the second signal line.

[0025] In some embodiments, a portion of the second signal line opposite to the second pedestal region protrudes to a side away from the first signal line to form a winding portion. A spacing between the winding portion and the second pedestal region is equal to a spacing between the second signal line and the main body portion.

[0026] In some embodiments, the plurality of pixel regions include a red pixel region, a green pixel region, and a blue pixel region. The first pedestal region is adjacent to the red pixel region or the green pixel region, and the second pedestal region is adjacent to the blue pixel region.

[0027] In some embodiments, the gate region and the base region are arranged side-by-side along the second direction, and at least a portion of the gate region and at least a portion of the base region belonging to the same protrusion are respectively located on both sides of a third signal line. The pixel region is adjacent to one gate region and one base region belonging to two protrusions respectively, and there is a first gap between the gate region and the base region adjacent to the same pixel region. The first transistor includes a source pattern and a drain pattern, the source pattern is electrically connected to the third signal line, and the drain pattern is electrically connected to the first electrode; the drain pattern extends along the second direction, and in the orthographic projection of the drain pattern and the first signal line on the first substrate, the drain pattern is partially located within the range of the gate region and partially located within the first gap.

[0028] In some embodiments, the third signal line includes alternating first and second extension segments. In the orthographic projection of the third signal line and the signal line group onto the first substrate, the first extension segment passes through the signal line group, and the second extension segment does not coincide with the signal line group. The linewidth of the first extension segment is greater than or equal to the linewidth of the second extension segment.

[0029] In some embodiments, the linewidth of the first extension is greater than or equal to 4.5 μm; and / or, the linewidth of the second extension is 2.5 μm to 8 μm.

[0030] In some embodiments, the second signal line includes alternating third and fourth extension segments, wherein in the orthographic projection of the second signal line and the third signal line onto the first substrate, the third extension segment at least partially overlaps with the third signal line, and the fourth extension segment does not overlap with the third signal line. The linewidth of the third extension segment is less than or equal to the linewidth of the fourth extension segment.

[0031] In some embodiments, the orthographic projection of the third extension on the first substrate extends through the orthographic projection of the third signal line on the first substrate, and there is a third gap between the end of the third extension and the third signal line.

[0032] In some embodiments, the linewidth of the third extension segment is 2.5 μm to 4 μm; and / or, the linewidth of the fourth extension segment is greater than or equal to 4 μm; and / or, the third interval is greater than or equal to 1.9 μm.

[0033] On the other hand, a display panel is provided. The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0034] In some embodiments, the first signal line of the array substrate includes an integrally formed main body and a plurality of protrusions. The main body extends along a second direction, and the protrusions include a gate region and a base region. The plurality of base regions included in the plurality of protrusions include a plurality of first base regions and a plurality of second base regions. The color filter substrate includes a second substrate and a plurality of main spacers and a plurality of sub spacers disposed on one side of the second substrate. The ends of the main spacers away from the second substrate abut against the array substrate, and the ends of the sub spacers away from the second substrate abut against the array substrate or have a gap. The end face of the sub spacers away from the second substrate is a first end face, and the end face of the main spacers away from the second substrate is a second end face. The orthographic projection of the first end face on the array substrate at least partially coincides with the first base region, and the orthographic projection of the second end face on the array substrate at least partially coincides with the second base region.

[0035] In some embodiments, the boundary of the orthographic projection of the first end face on the array substrate is greater than or equal to 2 μm between the boundary of the first base plate region and the boundary of the first base plate region; and / or, the boundary of the orthographic projection of the second end face on the array substrate is greater than or equal to 4.5 μm between the boundary of the second base plate region and the boundary of the second base plate region.

[0036] In some embodiments, the color filter substrate further includes a black matrix disposed on the side of the plurality of primary spacers and the plurality of secondary spacers near the second substrate. The interval between the boundary of the orthographic projection of the first end face on the second substrate and the boundary of the orthographic projection of the black matrix on the array substrate is greater than or equal to 25 μm; and / or, the interval between the boundary of the orthographic projection of the second end face on the array substrate and the orthographic projection of the black matrix on the array substrate is greater than or equal to 28 μm.

[0037] In another aspect, a display device is provided, which includes the array substrate described in any of the above embodiments, or the display device includes the display panel described in any of the above embodiments. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 is a structural diagram of a display device according to some embodiments;

[0040] Figure 2 is a structural diagram of a display device according to some embodiments;

[0041] Figure 3 is a planar structural diagram of an array substrate according to some embodiments;

[0042] Figure 4 is a magnified view of a portion of region A1 in Figure 3;

[0043] Figure 5 is a cross-sectional view along section line B1-B1 in Figure 4;

[0044] Figure 6 is a planar structural diagram of a first transistor according to some embodiments;

[0045] Figure 7 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0046] Figure 8 is a planar structural diagram of the array substrate at the first transistor according to some embodiments;

[0047] Figure 9 is a cross-sectional view along section line B2-B2 in Figure 8;

[0048] Figure 10 is a planar structural diagram of the array substrate at the third via according to some embodiments;

[0049] Figure 11 is a cross-sectional view along section line B3-B3 in Figure 10;

[0050] Figure 12 is a cross-sectional view along section line B4-B4 in Figure 10;

[0051] Figure 13 is a planar structural diagram of the array substrate according to some embodiments when the second electrode layer is not included;

[0052] Figure 14 is another planar structure diagram of the array substrate according to some embodiments;

[0053] Figure 15 is another planar structure diagram of the array substrate according to some embodiments;

[0054] Figure 16 is a structural diagram of a display panel according to some embodiments;

[0055] Figure 17 is a projection structure diagram of the sub-spacer and black matrix on the array substrate according to some embodiments;

[0056] Figure 18 is a projection structure diagram of the main spacer and the black matrix on the array substrate according to some embodiments;

[0057] Figure 19 is a structural diagram of a signal line group and a third signal line according to some embodiments;

[0058] Figure 20 is a planar structural diagram of the array substrate when the first electrode and the signal line group are on the same layer according to some embodiments;

[0059] Figure 21 is a plan view of the first transistor with a first electrode and signal line group according to some embodiments;

[0060] Figure 22 is a cross-sectional view along section line B5-B5 in Figure 20;

[0061] Figure 23 is a magnified view of a portion of region A2 in Figure 20;

[0062] Figure 24 is a cross-sectional view along section line B6-B6 in Figure 23;

[0063] Figures 25 to 28 are process steps for fabricating an array substrate according to some embodiments. Detailed Implementation

[0064] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0065] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0066] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0067] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0068] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0069] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0070] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0071] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0072] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0073] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0074] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0075] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0076] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0077] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0078] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0079] In some embodiments, the display device 1000 described above may be a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone (phone), watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of a rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, or any other product or component with display function.

[0080] For example, the display device described above can be a display device with a high refresh rate, such as a refresh rate greater than or equal to 75Hz; or a refresh rate greater than or equal to 120Hz; or a refresh rate greater than or equal to 240Hz, etc. The embodiments of this disclosure will not be listed one by one.

[0081] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD). From the perspective of the shape of the display device 1000, the display device 1000 can be a flat panel display device or a curved panel display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The following uses a rectangular and flat liquid crystal display device as an example to illustrate some embodiments of this disclosure. However, the embodiments of this disclosure are not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0082] In some embodiments, referring to FIG2, the display device 1000 includes a display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to display images. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0083] Referring again to Figure 2, when the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight module 1200 disposed on the backlight side of the display panel 1100. For example, the backlight module 1200 may be a direct-lit backlight module or an edge-lit backlight module, etc. The backlight module 1200 is used to provide a light source for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby enabling each sub-pixel to display the same or different gray levels to achieve the purpose of image display.

[0084] Referring again to Figure 2, when the display panel 1100 is a liquid crystal display panel, it may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, as well as a liquid crystal layer 300 and a spacer PS disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may also be referred to as an opposing substrate or an encapsulation substrate. The spacer PS supports the cell thickness between the array substrate 100 and the color filter substrate 200, ensuring a stable and relatively uniform space between them to accommodate the liquid crystal layer 300. Of course, the structure of the display panel 1100 is not limited to this; it may include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.

[0085] The array substrate 100 mentioned above can be an Advanced Super Dimension Switch (ADS) type or a High-Advanced Dimension Switch (HADS) type with high aperture ratio. ADS technology places both the common electrode and pixel electrode on the array substrate. A multi-dimensional electric field is formed by the electric field generated at the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. This allows all oriented liquid crystal molecules between the slit electrodes and directly above the electrodes within the liquid crystal cell to rotate, thereby improving the working efficiency of the liquid crystal and increasing light transmittance. It also offers advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push ripples. HADS technology is an important implementation of ADS technology, with an even higher aperture ratio. HADS array substrates are generally in a normally black mode, with no light leakage in the distribution area of ​​the liquid crystal layer, forming a dark area. The size of the black matrix used to cover the data lines in the color filter substrate can be made smaller, which is beneficial for improving the aperture ratio and transmittance of the array substrate.

[0086] The color filter substrate 200 may include a light filter section and a black matrix (see below). The light filter section is used to filter the light incident on the color filter substrate 200 so that each sub-pixel emits light of a certain color (such as red, green, or blue). Different sub-pixels can emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. The black matrix is ​​used to cover the first transistors and signal lines on the array substrate to improve the contrast of the display panel (see below for the specific structure of the color filter substrate 200).

[0087] In liquid crystal display devices, the transmittance of the display panel 1100 is a crucial indicator. Improving the transmittance of the display panel 1100 not only enhances the brightness of the display device but also reduces the power consumption of the backlight module 1200, thereby lowering the overall power consumption of the display device. A conventional ADS liquid crystal display panel includes multiple signal lines on an array substrate and a black matrix on a color filter substrate. The orthographic projection of the black matrix onto the array substrate covers the multiple signal lines. Since voltage fluctuations on the signal lines can disturb the liquid crystal layer and potentially cause light leakage in areas of the display panel near the signal lines, a larger black matrix is ​​typically required to block the signal lines on the array substrate to avoid this problem. This makes it difficult to reduce the size of the black matrix and also hinders improvements in the aperture ratio and transmittance of the display panel.

[0088] To address at least one of the aforementioned technical problems and improve the aperture ratio and transmittance of the display panel, referring to Figures 3, 4, and 5, embodiments of this disclosure provide an array substrate 100. The array substrate 100 includes a first substrate 10, a plurality of first electrodes 11 disposed on one side of the first substrate 10, a plurality of signal line groups 20, a plurality of third signal lines 30, a plurality of first transistors T1, and a second electrode layer 40.

[0089] For example, the first substrate 10 can be a rigid substrate. Rigid substrates may include, but are not limited to, glass substrates or polymethyl methacrylate (PMMA) substrates. Alternatively, the first substrate 10 can also be a flexible substrate. Flexible substrates may include, but are not limited to, polyethylene terephthalate (PET) substrates, polyimide (PI) substrates, or polyethylene naphthalate (PEN) substrates. Furthermore, the first substrate 10 can also be a transparent substrate, allowing light emitted from the backlight module to pass through it, which helps improve the transmittance of the array substrate 100.

[0090] Multiple signal line groups 20 are disposed on one side of the first substrate 10, and the multiple signal line groups 20 are spaced apart along the first direction Y. Multiple third signal lines 30 are spaced apart along the second direction X, and each third signal line 30 extends along the first direction Y in general. The orthographic projections of the multiple third signal lines 30 and the multiple signal line groups 20 on the first substrate 10 intersect to form a grid structure, and each grid defines a pixel area 101. The first direction Y intersects the second direction X, for example, the first direction Y and the second direction X are perpendicular to each other.

[0091] For example, the portion of the third signal line 30 located between two adjacent signal line groups 20 can be a broken line. This portion can include multiple segments, each segment extending at an angle to the first direction Y, with adjacent segments having opposite inclination directions relative to the first direction Y. For instance, as shown in FIG3, the portion of the third signal line 30 located between two adjacent signal line groups 20 can include two segments. Similar to the extension direction of the third signal line 30, the pixel region 101 and the first electrode 11 within the pixel region 101 also extend in a bent manner in the second direction Y, thus forming a sub-pixel with a multi-domain structure. For instance, as shown in FIG3, each sub-pixel can be a dual-domain structure. For example, the pixel region 101 can include a red pixel region 102, a green pixel region 103, and a blue pixel region 104; correspondingly, the color filter substrate can include a red filter, a green filter, and a blue filter. A red filter's orthographic projection onto the array substrate 100 can at least partially overlap with a red pixel region to form a red sub-pixel, through which light rays are red. A green filter's orthographic projection onto the array substrate can at least partially overlap with a green pixel region to form a green sub-pixel, through which light rays are green. A blue filter's orthographic projection onto the array substrate can at least partially overlap with a blue pixel region to form a blue sub-pixel, through which light rays are blue.

[0092] Each of the plurality of first electrodes 11 is disposed within a pixel region 101. For example, the first electrode 11 may be a pixel electrode.

[0093] Each signal line group 20 includes a first signal line 21 and a second signal line 22. For example, each signal line group 20 includes one first signal line 21 and one second signal line 22. Both the first signal line 21 and the second signal line 22 extend along a second direction X. A pixel region 101 is also correspondingly provided with a first transistor T1. The first signal line 21 is configured to be electrically connected to the gate of the first transistor T1, or is configured to form the gate of the first transistor T1.

[0094] For example, the first transistor T1 may include a gate disposed on the same layer as the first signal line 21, a semiconductor layer ACT located on the side of the first signal line 21 away from the first substrate 10, and a source pattern 31 and a drain pattern 32 located on the side of the semiconductor layer ACT away from the first substrate 10. The first transistor T1 may be a bottom-gate transistor, that is, the semiconductor layer ACT of the first transistor T1 is disposed on the side of the gate (gate region 25) of the first transistor T1 away from the first substrate 10, and the source pattern 31 and the drain pattern 32 may be in direct contact with the semiconductor layer ACT.

[0095] A pixel region 101 can be jointly controlled by a first signal line 21 and a third signal line 30 surrounding the pixel region 101. Exemplarily, the first signal line 21 is used to transmit a scan signal, which controls the first transistor T1 to be turned on or off; the third signal line 30 can be a data signal line, configured to transmit a data signal. The gate of the first transistor T1 is electrically connected to the first signal line 21. Furthermore, the first transistor T1 can also be electrically connected to the third signal line 30 and the first electrode 11. For example, the source pattern 31 of the first transistor T1 can be electrically connected to the third signal line 30, and the drain pattern 32 of the first transistor T1 can be electrically connected to the first electrode 11. The first transistor T1 can be turned on or off under the control of the first signal line 21, and when the first transistor T1 is on, the electrical signal (data signal) transmitted on the third signal line 30 is transmitted to the first electrode 11. An electric field can be formed between the first electrode 11 and the second electrode layer 40. This electric field can drive the liquid crystal molecules in the liquid crystal layer to deflect. The deflection angle of the liquid crystal molecules is used to control the polarization direction of the light passing through the pixel area 101. The polarization direction of the light, in conjunction with the polarizer, can achieve different grayscale displays.

[0096] The second electrode layer 40 is disposed on the side of the first signal line 21 away from the first substrate 10, and the second electrode layer 40 is electrically connected to the second signal line 22. For example, the second signal line 22 can be a common voltage signal line used to transmit a constant voltage signal; in this case, the second electrode layer 40 can also be referred to as the common electrode layer. The parallel arrangement of the second signal line 22 and the second electrode layer 40 can reduce the voltage drop across the second electrode layer 40, which is beneficial for improving the voltage stability of the second electrode layer 40.

[0097] For example, the materials of the first electrode 11 and the second electrode layer 40 may both include transparent conductive materials, so that light emitted from the backlight module can pass through the first electrode 11 and the second electrode layer 40. The transparent conductive materials include, but are not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and IGZO. The materials of the first electrode 11 and the second electrode layer 40 may be the same, or the materials of the first electrode 11 and the second electrode layer 40 may be different.

[0098] In some embodiments, within the same pixel area 101, one of the first electrode 11 and the second electrode layer 40 can be a continuous block structure, and the other can be a comb-like structure, so that the array substrate 100 can form an ADS type or HADS type array substrate.

[0099] For example, as shown in Figures 3 and 4, the first electrode 11 is a continuous block structure within the pixel area 101, and the portion of the second electrode layer 40 within the pixel area 101 includes multiple elongated electrode strips with slit-shaped openings between adjacent electrode strips.

[0100] The orthographic projection of the second electrode layer 40 onto the first substrate 10 does not coincide with the orthographic projection of the first transistor T1 onto the first substrate 10. For example, the orthographic projection of the second electrode layer 40 onto the first substrate 10 may not coincide with the orthographic projection of the channel structure of the first transistor T1 (the portion located between the source pattern 31 and the drain pattern 32) onto the first substrate 10. In this way, the influence of the voltage on the second electrode layer 40 on the first transistor T1 can be reduced, which is beneficial to reducing the leakage current of the first transistor T1.

[0101] For example, as shown in FIG4, the second electrode layer 40 may include a clearance opening 42, and the first transistor T1 is disposed within the range of the clearance opening 42.

[0102] The orthographic projection of the second electrode layer 40 onto the first substrate 10 at least partially overlaps with the orthographic projections of the multiple third signal lines 30 onto the first substrate 10. The second electrode layer 40 can effectively shield the electric field generated by the third signal lines 30, reducing the impact of the electric field on the liquid crystal layer, thereby reducing the risk of light leakage near the third signal lines 30. Based on this, the size of the black matrix used to block the third signal lines 30 on the color filter substrate can be reduced, which is beneficial to improving the aperture ratio of the array substrate and improving the light extraction efficiency of the array substrate. In addition, the display panel can be set to a normally black mode, that is, when the array substrate is not working, even if the backlight module emits light, the light will not pass through the display panel. This is beneficial to further reduce the light leakage problem of the display panel near the third signal lines 30.

[0103] For example, as shown in Figures 3 and 4, the orthographic projection of the second electrode layer 40 onto the first substrate 10 can cover the portion of the third signal line 30 other than the source pattern used to form the first transistor T1. For instance, in the orthographic projection of the second electrode layer 40, the third signal line 30, and the first signal line 21 onto the first substrate 10, at least the portion where the third signal line 30 and the first signal line 21 overlap are not covered by the second electrode layer 40. Thus, the second electrode layer 40 can cover the third signal line 30 to a great extent without covering the first transistor T1.

[0104] The second electrode layer 40, when projected onto the first substrate 10, also covers at least a portion of the edge of the first signal line 21 projected onto the first substrate 10. Thus, the second electrode layer 40 can also shield the electric field generated at the edge of the first signal line 21, reducing the impact of the electric field generated by signal fluctuations in the first signal line 21 on the liquid crystal molecules in the liquid crystal layer. This reduces the disturbance of the first signal line 21 to the liquid crystal layer. Furthermore, since the HADS array substrate is in a normally black mode, the edge of the first signal line is a dark area, preventing light leakage. This helps to reduce the size of the portion of the black matrix on the color filter substrate covering the first signal line 21, thereby improving the aperture ratio and transmittance of the display panel. Furthermore, compared to covering the entire area of ​​the first signal line 21 with the second electrode layer 40, by covering at least a portion of the edge of the first signal line 21 with the second electrode layer 40, the second electrode layer 40 can shield the electric field generated by the first signal line 21 while significantly reducing the facing area between the second electrode layer 40 and the first signal line 21. This reduces the parasitic capacitance formed between the second electrode layer 40 and the first signal line 21, thereby reducing the load on the first signal line 21 and its power consumption, which in turn helps to reduce the power consumption of the power array substrate 100. In other words, the array substrate provided by the embodiments of this disclosure can balance the aperture ratio and power consumption of the array substrate.

[0105] On the one hand, the orthographic projection of the second electrode layer 40 onto the first substrate 10 at least partially overlaps with the orthographic projection of the third signal line 30 onto the first substrate 10. That is, the second electrode layer 40 and the third signal line 30 are at least partially opposite each other, resulting in a parasitic capacitance between them. This parasitic capacitance increases the load on the third signal line 30, affecting its charging efficiency. On the other hand, when the aforementioned array substrate is used in a high refresh rate display device, the charging time (1H) of a row of sub-pixels is shorter due to the higher refresh rate. Under the influence of these two factors, the charging rate of the sub-pixels decreases, meaning the first electrode is not fully charged, thereby reducing the brightness and image quality of the display panel.

[0106] To address at least one of the aforementioned technical problems, the array substrate provided in the embodiments of this disclosure, as shown in Figures 3, 4, and 5, may have a first electrode 11 disposed on the side of the film layer containing the signal line group 20 and the film layer containing the first transistor T1 away from the first substrate 10. In this case, the array substrate 100 may further include a second insulating layer GI, a planarization layer ORG, and a first insulating layer PVX. The second insulating layer GI is located between the signal line group 20 and the semiconductor layer ACT, preventing direct short circuits between the signal line group 20 and the first electrode 11 and the semiconductor layer ACT. The planarization layer ORG is disposed on the side of the first transistor T1 away from the first substrate 10, and the first insulating layer PVX is disposed on the side of the planarization layer ORG away from the first substrate 10. The first electrode 11 is disposed between the planarization layer ORG and the first insulating layer PVX, and the second electrode layer 40 is disposed on the side of the first insulating layer PVX away from the first substrate 10. In other words, the signal line group 20, the second insulating layer GI, the semiconductor layer ACT, the third signal line 30, the planarization layer ORG, the first electrode 11, the first insulating layer PVX, and the second electrode layer 40 are arranged sequentially in a direction away from the first substrate 10. In the embodiments of this disclosure, the planarization layer ORG is added between the film layer where the third signal line 30 is located and the film layer where the second electrode layer 40 is located. This helps to increase the spacing between the third signal line 30 and the second electrode layer 40, thereby reducing the parasitic capacitance between the third signal line 30 and the second electrode layer 40, reducing the load on the third signal line 30, and improving the charging efficiency on the third signal line 30. This, in turn, helps to improve the charging rate of the first electrode 41 and improve the brightness and display quality of the display panel.

[0107] The planarization layer ORG can be fabricated using organic resin materials, which facilitates the fabrication of a relatively thick planarization layer between the third signal line 30 and the second electrode layer 40. The thickness (average thickness) of the planarization layer ORG can be... For example, the thickness of the planarization layer ORG can be Alternatively, the thickness of the planarization layer ORG can be... The thickness of the planarization layer ORG can be For example, the thickness of the planarization layer ORG can be... or Examples of these will not be listed individually in the embodiments disclosed herein.

[0108] As shown in Figure 5, the first electrode 11 is disposed between the planarization layer ORG and the first insulating layer PVX, which helps to reduce the gap between the first electrode 11 and the second electrode layer 40, thereby increasing the capacitance (Cst) between the first electrode 11 and the second electrode layer 40. The array substrate 100 also includes a first via V1, which penetrates the planarization layer ORG. The first electrode 11 passes through the first via V1 and is electrically connected to the first transistor T1. For example, the first electrode 11 passes through the first via V1 and is electrically connected to the drain pattern 32 of the first transistor T1.

[0109] Referring to Figures 6 and 7, the source pattern 31 of the first transistor T1 is electrically connected to the third signal line 30, and the drain pattern 32 can be electrically connected to the first electrode 11. The first via V1 includes a first portion V11 and a second portion V12. The first portion V11 exposes at least part of the drain pattern 32, and the second portion V12 is the orthogonal projection on the first substrate 10, located outside the orthogonal projection of the drain pattern 32 on the first substrate 10. In this way, the first electrode 11 can be electrically connected to the drain pattern through the first portion V11. In addition, the size of the first via V1 can be increased, and the bottom morphology of the first via V1 has a certain undulation, which can reduce the step difference formed by the array substrate 100 at the first via V1. This is beneficial for the flow and diffusion of PI liquid (used to prepare the alignment film) in the first via V1, avoiding uneven diffusion of PI liquid at the location of the first via V1, and thus reducing Mura-type defects caused by uneven diffusion of PI liquid.

[0110] For example, as shown in FIG7, the first electrode 11 forms a semi-overlap structure with the drain pattern 32 in the first via V1, that is, part of the first electrode 11 in the first via V1 overlaps with the drain pattern 32, part is located on the surface of the second insulating layer GI, and has no contact with the drain pattern 32.

[0111] In some embodiments, the first electrode 11 includes an electrode portion 112 and a connection portion 111. The electrode portion 112 is located within the pixel region 101 and is used to form capacitance and electric field with the second electrode layer 40. The connection portion 111 is located on one side of the electrode portion 112 along the first direction Y and is connected to the electrode portion 112 so that the connection portion 111 transmits a voltage signal to the electrode portion 112. The connection portion 111 passes through the first via V1 and is electrically connected to the first transistor T1 (drain pattern 32).

[0112] The first portion V11 and the second portion V12 are arranged along the first direction Y, that is, the first via V1 extends along the first direction Y. In this way, the size of the connection portion 111 between the first via V1 and the first electrode 11 in the second direction X can be reduced, thereby increasing the space on the first signal line 21 for setting the base region and the gate region (see below). This facilitates setting the base region of the first signal line 21 on the side of the main body away from the second signal line, thereby improving the aperture ratio and transmittance of the array substrate 100.

[0113] The second portion V12 is located on the side of the first portion V11 near the pixel area 101. The first electrode 11 includes a connecting portion 111, which passes through the second portion V12 and extends to connect with the drain pattern 32 in the first portion V11. This helps to reduce the risk of the second portion V12 covering the first signal line 21, increases the spacing between the connecting portion 111 and the first signal line 21, and reduces the parasitic capacitance between the first electrode 11 and the first signal line 21.

[0114] Because the sidewall slope of the drain pattern 32 and the semiconductor layer ACT is relatively large (compared to the sidewall slope of the first via V1), during the process of the connection portion 111 climbing up the drain pattern 32 from the bottom of the first via V1 through the second insulating layer GI, the portion of the connection portion 111 covering the sidewall of the drain pattern 32 may have a smaller thickness or be broken, which may lead to a decrease in the connection reliability between the connection portion 111 and the drain pattern 32.

[0115] To address the aforementioned technical issues, referring to Figures 6-9, the dimension D1 of the orthographic projection of the connection portion 111 onto the first substrate 10 along the second direction X is larger than the dimension D2 of the orthographic projection of the first via V1 onto the first substrate 10 along the second direction X. The connection portion 111 also covers at least one side of the first via V1 along the second direction X; in other words, a portion of the connection portion 111 is located on at least one side of the first via V1 along the second direction X. Thus, in the cross-section shown in Figure 7, the connection portion 111 can form a conductive channel 113 on at least one side of the first via V1 along the second direction X. In this conductive channel 113, the connection portion 111 extends from the surface of the planarization layer ORG away from the first substrate 10 to the sidewall of the first via V1, and extends directly from the sidewall of the first via V1 to the surface of the drain pattern 32 away from the first substrate 10, thereby improving the connection reliability between the connection portion 111 and the drain pattern 32.

[0116] In the embodiments of this disclosure, the portion of the connection portion 111 located on one side of the first through hole V1 along the second direction X is referred to as the "conductive channel 113".

[0117] In some embodiments, the connection portion 111 covers a portion of the planar layer ORG located on both sides of the first via V1 in the second direction X. In this way, the connection portion 111 can form a conductive channel 113 on each side of the first via V1 along the second direction X, which greatly improves the connection reliability between the connection portion 111 and the drain pattern 32.

[0118] In other embodiments, the connection portion 111 may also be located on one side of the first via V1 in the second direction X (e.g., the side closer to the source pattern 31 or the side farther from the source pattern 31). That is, the connection portion 111 covers one side of the first via V1 in the second direction X in the planarization layer. This is beneficial to reduce the size of the connection portion 111 in the second direction X, thereby increasing the space on the first signal line 21 for setting the base region 26 and the gate region 25. It is also beneficial to set the base region 26 of the first signal line 21 on the side of the main body 23 away from the second signal line 22, thereby improving the aperture ratio and transmittance of the array substrate 100.

[0119] Referring again to Figure 6, in some embodiments, the dimension D2 of the first via V1 along the second direction X is greater than or equal to 4 μm. This ensures that the first via V1 can completely penetrate the planarization layer ORG. Exemplarily, the dimension D2 of the first via V1 along the second direction X can be 4 μm, 4.5 μm, 5 μm, 6 μm, or 6.5 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0120] In some embodiments, as shown in FIG6, the distance D3 between the end of the orthographic projection of the connection portion 111 on the first substrate 10 along the second direction X and the boundary of the orthographic projection of the first via V1 on the first substrate 10 is greater than or equal to 2.1 μm. The distance D3 is the linewidth of the conductive channel 113 formed by the connection portion 111 on the side of the first via V1 along the second direction X. Setting the distance D3 to be greater than or equal to 2.1 μm ensures that the connection portion 111 can form a conductive channel 113 on the side of the first via V1 along the second direction X, and also helps to reduce the resistance of the conductive channel 113. Exemplarily, the distance D3 can be 2.1 μm, 2.5 μm, 2.8 μm, 3 μm, or 3.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0121] In some embodiments, as shown in Figures 5, 8, and 9, the array substrate 100 further includes a second via V2 and an overlap portion 41. The second via V2 penetrates the first insulating layer PVX. The orthographic projection of the second via V2 on the first substrate 10 at least partially overlaps with the orthographic projection of the first via V1 on the first substrate 10. Thus, the first electrode 11 can be located in at least a portion of the area within the second via V2. The overlap portion 41 passes through the second via V2 and connects to the first electrode 11. The overlap portion 41 and the connection portion 111 of the first electrode 11 are arranged in parallel, which helps to improve the connection stability between the connection portion 111 and the drain pattern 32 and reduces the risk of poor connection between the connection portion 111 and the drain pattern 32.

[0122] The overlap portion 41 and the second electrode layer 40 are made of the same material and are disposed in the same layer. Therefore, it is not necessary to form the overlap portion 41 through additional process steps, which simplifies the structure and fabrication process of the array substrate 100 and reduces its fabrication cost. The overlap portion 41 is electrically insulated from the second electrode layer 40, preventing short circuits between the second electrode layer 40 and the first electrode 11 through the overlap portion 41.

[0123] Of course, in other embodiments, the overlapping portion 41 may also be located on a different film layer from the second electrode layer 40. In this case, the material, thickness and other parameters of the overlapping portion 41 can be flexibly set, which is beneficial to improve the conductivity of the overlapping portion 41 and reduce the resistance of the overlapping portion 41.

[0124] In some embodiments, as shown in Figures 8 and 9, at least a portion of the orthographic projection of the second via V2 onto the first substrate 10 is located outside the orthographic projection of the first via V1 onto the first substrate 10. In this way, a staggered via structure can be formed between the second via V2 and the first via V1, which is beneficial for the flow and diffusion of PI liquid at the locations of the second via V2 and the first via V1, avoiding uneven diffusion of PI liquid at the locations of the second via V2 and the first via V1, thereby reducing Mura-type defects caused by uneven diffusion of PI liquid.

[0125] Referring again to Figures 8 and 9, in some embodiments, the boundary of the portion of the second via V2 projected onto the first substrate 10 that is outside the portion of the first via V1 projected onto the first substrate 10, and the boundary of the first via V1 projected onto the first substrate 10, are separated by a distance D5 greater than or equal to 1 μm. This increases the distance between the boundary of the second via V2 and the boundary of the first via V1, improving the flowability of the PI liquid at the locations of the second via V2 and the first via V1, and reducing Mura-type defects caused by uneven PI liquid diffusion. Exemplarily, the distance D5 can be 1 μm, 1.5 μm, 2 μm, or 2.5 μm, etc., and will not be listed exhaustively in the embodiments of this disclosure.

[0126] In some embodiments, as shown in FIG8, the orthographic projection of the overlap portion 41 on the first substrate 10 covers the orthographic projection of the second via V2 on the first substrate 10, and also covers the portion of the connection portion 111 away from the electrode portion 112 on the orthographic projection of the connection portion 111 on the first substrate 10. In this way, the area covered by the overlap portion 41 on the connection portion 111 can be greatly increased, and the connection reliability between the connection portion 111 and the drain pattern 32 of the first transistor T1 can be greatly increased.

[0127] Exemplarily, the distance D6 between the boundary of the orthographic projection of the overlapping portion 41 on the first substrate 10 and the boundary of the orthographic projection of the connecting portion 111 on the first substrate 10 is greater than or equal to 1 μm. In this way, the overlapping portion 41 can completely cover the portion of the connecting portion 111 that is away from the electrode portion 112. Exemplarily, the distance D6 can be 1 μm, 1.5 μm, 1.8 μm, 2 μm, or 2.5 μm, etc., and will not be listed individually in the embodiments of this disclosure.

[0128] The dimension D7 of the second via V2 along the second direction X is greater than or equal to 4 μm. This increases the area of ​​the exposed connection portion 111 of the second via V2, increases the contact area between the overlapping portion 41 and the connection portion 111, and improves the connection reliability between the connection portion 111 and the drain pattern 32 of the first transistor T1. Exemplarily, the dimension D7 of the second via V2 along the second direction X can be 4 μm, 4.3 μm, 4.5 μm, 5 μm, or 5.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0129] For example, the dimension D7 of the second via V2 along the second direction X can be larger than the dimension D3 of the first via V1 along the second direction. In this way, the second via V2 can expose at least a portion of the area of ​​the connection portion 111 located on the side of the first via V1 along the second direction X. That is, the second via V2 can expose the conductive channel of the connection portion 111, and the overlapping portion 41 can overlap with the conductive channel to increase the continuity and permeability of the conductive channel.

[0130] In some embodiments, referring to Figures 10, 11, and 12, the array substrate 100 further includes a second insulating layer GI, a third via V3, and a fourth via V4. The second insulating layer GI is located between the film layer containing the signal line group 20 and the film layer containing the third signal line 30. The third via V3 penetrates the planarization layer ORG, and its orthographic projection on the first substrate 10 at least partially coincides with the orthographic projection of the second signal line 22 on the first substrate 10. The orthographic projection of the fourth via V4 on the first substrate 10 at least partially coincides with the orthographic projection of the third via V3 on the first substrate 10. The fourth via V4 penetrates the first insulating layer PVX and the second insulating layer GI, and exposes a portion of the second signal line 22. The second electrode layer 40 is electrically connected to the second signal line 22 through the fourth via V4 and the third via V3. In this way, the second signal line 22 can be arranged in parallel with the second electrode layer 40, which can reduce the voltage drop on the second electrode layer 40 and improve the voltage stability on the second electrode layer 40.

[0131] The third via V3 includes a third portion V31 and a fourth portion V32. The orthographic projection of the third portion V31 on the first substrate 10 is within the range of the orthographic projection of the second signal line 22 on the first substrate 10. The orthographic projection of the fourth portion V32 on the first substrate 10 does not coincide with the orthographic projection of the second signal line 22 on the first substrate 10. In this way, not only can the size of the third via V3 be increased, but the bottom morphology of the third via V3 also has a certain undulation, which can reduce the step difference formed by the array substrate 100 at the third via V3. This is beneficial for the flow and diffusion of PI liquid (used to prepare the alignment film) at the location of the third via V3, avoiding uneven diffusion of PI liquid at the location of the third via V3, and thus reducing Mura-type defects caused by uneven diffusion of PI liquid.

[0132] For example, the fourth portion V32 is located on the side of the third portion V31 closest to the first signal line 21 (the upper side in FIG. 10). That is, the fourth portion V32 is located in the region between the first signal line 21 and the second signal line 22. This helps to increase the distance between the pixel area 101 adjacent to the second signal line 22 and the third via V3. The boundary of the orthographic projection of the black matrix on the color filter substrate onto the array substrate 100 has a larger distance from the boundary of the third via V3, avoiding light leakage caused by Mura-type defects caused by the third via V3, and thus increasing the aperture ratio of the array substrate 100. In addition, the orthographic projection of the fourth portion V32 onto the first substrate 10 is spaced from the first signal line 21. This prevents short circuits between the second electrode layer 40 and the first signal line 21.

[0133] In some embodiments, as shown in Figures 10 and 12, at least a portion of the orthographic projection of the fourth via V4 onto the first substrate 10 lies outside the orthographic projection of the third via V3 onto the first substrate 10. A staggered via structure can be formed between the fourth via V4 and the third via V3, which facilitates the flow and diffusion of the PI liquid at the locations of the fourth via V4 and the third via V3, preventing uneven diffusion of the PI liquid at these locations, and thus reducing Mura-type defects caused by uneven PI liquid diffusion.

[0134] For example, as shown in FIG10, in the orthographic projection of the fourth via V4 on the first substrate 10, both ends (left and right ends) along the second direction X and the end (lower end) away from the first signal line 21 along the first direction Y are located within the range of the orthographic projection of the third via V3 on the first substrate 10, while the end close to the first signal line 21 along the first direction Y is located outside the range of the orthographic projection of the third via V3 on the first substrate 10.

[0135] In the orthographic projection of the fourth via V4 onto the first substrate 10, the distance D8 between its two ends along the second direction X and its end away from the first signal line 21 along the first direction Y, and the boundary of the orthographic projection of the third via V3 onto the first substrate 10, is greater than or equal to 2.1 μm. This facilitates increasing the spacing between the third via V3 and the fourth via V4, allowing the first insulating layer PVX to completely cover the sidewall of the fourth via V4. Exemplarily, the distance D8 can be 2.1 μm, 2.5 μm, 2.8 μm, or 3 μm, etc., and the embodiments of this disclosure will not be listed individually.

[0136] The distance D9 between the end of the orthographic projection of the fourth via V4 on the first substrate 10, near the first signal line 21, and the boundary of the orthographic projection of the third via V3 on the first substrate 10, is greater than or equal to 1 μm. This increases the distance between the boundaries of the fourth via V4 and the third via V3, improving the flowability of the PI liquid at the locations of the fourth via V4 and the third via V3, and reducing Mura-type defects caused by uneven PI liquid diffusion. For example, the distance D9 can be 1 μm, 1.3 μm, 1.8 μm, 2 μm, or 2.5 μm, etc., and will not be listed exhaustively in the embodiments of this disclosure.

[0137] In some embodiments, as shown in Figures 10 and 13, the second signal line 22 is recessed at the locations of the third via V3 and the fourth via V4 to form a first groove 222 away from the first signal line 21, and the fourth via V4 exposes at least a portion of the first groove 222. This helps to increase the spacing between the fourth via V4 and the first signal line 21, and also helps to increase the distance between the second electrode layer 40 and the first signal line 21, thus preventing a short circuit between the second electrode layer 40 and the first signal line 21 at the location of the fourth via V4.

[0138] In some embodiments, referring to FIG13, the first signal line 21 includes an integrally formed main body portion 23 and a plurality of protrusions 24. The main body portion 23 extends along a second direction X, and at least a portion of the plurality of protrusions 24 is located on the side of the main body portion 23 away from the second signal line 22, and the plurality of protrusions 24 are spaced apart along the second direction X. Exemplarily, the protrusions 24 may include a gate region 25 and a base region 26; the gate region 25 is used to form the gate of the first transistor T1, and the base region 26 can be used to support the spacer between the array substrate 100 and the color filter substrate.

[0139] In some embodiments, referring to FIG14, the orthographic projection of the second electrode layer 40 on the first substrate 10 covers the orthographic projection of at least a portion of the edges of the plurality of protrusions 24 away from the second signal line 22 on the first substrate 10. The edges of the protrusions 24 away from the second signal line 22 are adjacent to the pixel area 101 (the pixel area 101 located on the upper side of the protrusions 24). The distance between the edges of the protrusions 24 away from the second signal line 22 and the pixel area 101 is relatively close. The second electrode layer 40 covering at least a portion of the edges of the protrusions 24 away from the second signal line 22 can greatly reduce the influence of the first signal line 21 on the liquid crystal layer in the pixel area 101, thereby reducing the light leakage problem of the first signal line 21 on the side close to the pixel area 101. This is beneficial to reducing the size of the portion of the black matrix on the color filter substrate that covers the protrusions 24, thereby improving the aperture ratio and transmittance of the display panel.

[0140] Furthermore, as shown in FIG14, the orthographic projection of the second electrode layer 40 on the first substrate 10 does not coincide with the orthographic projection of the edge of the portion of the main body 23 away from the second signal line 22 on the first substrate 10. For example, as shown in FIG14, the orthographic projection of the second electrode layer 40 on the first substrate 10 does not coincide with the orthographic projection of the edge of the portion of the main body 23 located between two adjacent protrusions 24 away from the second signal line 22 on the first substrate 10, and also does not coincide with the orthographic projection of the edges of the protrusions 24 located on both sides in the second direction X on the first substrate 10. On the one hand, the distance between the edge of the portion of the main body 23 located between two adjacent protrusions 24 away from the second signal line 22 and the pixel area 101 is large, and it is completely blocked by the black matrix on the color filter substrate. Even if the electric field generated by the first signal line 21 at this location causes some disturbance to the liquid crystal molecules in the liquid crystal layer, there is no risk of light leakage at the edge of the pixel area 101, thus not adversely affecting the aperture ratio and transmittance of the display panel. On the other hand, it is advantageous to set other structures (overlapping portions 41) in the area between two adjacent protrusions 24 and on the second electrode layer 40, without the need to add a special film layer to set the overlapping portions 41. The second electrode layer 40 avoids the above-mentioned area, which helps to simplify the structure of the array substrate 100 and reduce the fabrication difficulty of the array substrate 100.

[0141] In some embodiments, referring to FIG15, the orthographic projection of the second electrode layer 40 on the first substrate 10 can also cover the orthographic projection of the edge of the first signal line 21 near the second signal line 22 (the lower edge of the first signal line 21 in FIG15) on the first substrate 10. In this way, the second electrode layer 40 shields the electric field generated by the first signal line 21 near the edge of the second signal line 22, reducing the disturbance caused by the first signal line 21 to the liquid crystal molecules in the pixel area 101 (the pixel area 101 below the first signal line 21) located on its side near the second signal line 22, reducing the risk of light leakage in the pixel area 101 below the first signal line 21. This reduces the size of the portion of the black matrix covering the first signal line 21 near the second signal line 22, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0142] In some embodiments, referring to FIG4, the orthographic projection of the second electrode layer 40 on the first substrate 10 can simultaneously cover the orthographic projection of the edge of the first signal line 21 near the second signal line 22 on the first substrate 10, and cover the orthographic projection of the edges of the plurality of protrusions 24 away from the second signal line 22 on the first substrate 10.

[0143] In the actual fabrication of the array substrate, the second electrode layer 40 can be configured in one of the structures shown in Figures 4, 14, or 15, or other structures can be used, as long as the same technical concept is adopted (i.e., the orthogonal projection of the second electrode layer 40 on the first substrate 10 covers the orthogonal projection of a portion of the edge of the first signal line 21 on the first substrate 10). The following embodiments of this disclosure are exemplified by using the structure shown in Figure 7 for the second electrode layer 40. It is understood that the embodiments of this disclosure are not limited to this, and other suitable embodiments can be considered.

[0144] As shown in Figure 4, in some embodiments, the portion where the orthographic projection of the first signal line 21 on the first substrate 10 coincides with the orthographic projection of the second electrode layer 40 on the first substrate 10 has a dimension D10 greater than or equal to 1.9 μm along the direction perpendicular to the boundary of the first signal line 21. That is, the edge width D10 of the first signal line 21 covered by the second electrode layer 40 is ≥ 1.9 μm. Thus, the second electrode layer 40 can significantly reduce the disturbance of the liquid crystal molecules in the liquid crystal layer caused by the electric field generated by the first signal line 21, reducing the risk of light leakage at the edge of the first signal line 21 in the display panel. This, in turn, reduces the size of the portion of the black matrix used to cover the first signal line 21, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0145] For example, the portion where the orthographic projection of the first signal line 21 on the first substrate 10 coincides with the orthographic projection of the second electrode layer 40 on the first substrate 10, along the direction perpendicular to the boundary of the first signal line 21, can have a size D10 of 1.9μm, 2.0μm, 2.2μm, or 2.3μm, etc. The embodiments of this disclosure will not be listed one by one.

[0146] In some embodiments, referring to Figures 4 and 13, the first signal line 21 includes an integrally formed body portion 23 and a plurality of protrusions 24. The body portion 23 extends along a second direction X, and the protrusions 24 include a gate region 25 and a base region 26. The gate region 25 is disposed on the side of the body portion 23 away from the second signal line 22 and is configured to form the gate of the first transistor T1; at least a portion of the base region 26 is disposed on the side of the body portion 23 away from the second signal line 22, and the base region 26 is configured to support a spacer.

[0147] In the embodiments of this disclosure, the gate region 25 and the base region 26 are disposed on the same side of the main body 23, and both are disposed on the side of the main body 23 away from the second signal line 22. In this way, the maximum span of the first signal line 21 in the first direction Y (the distance between the outermost endpoints of the first signal line 21 in the first direction Y) can be greatly reduced. Furthermore, the gate region 25 and the base region 26 can be disposed at least partially side by side in the second direction X, which is beneficial to reduce the space occupied by the first signal line 21, thereby reducing the space of the signal line group 20 in the first direction Y. It can also improve the regularity of the edges of the first signal line 21 and the second signal line 22, that is, reduce the unevenness of the edges of the first signal line 21 and the second signal line 22 in the first direction Y, which can improve the aperture ratio of the array substrate and is beneficial to reduce the size of the black matrix used to block the signal line group 20 in the first direction Y, thereby improving the aperture ratio and transmittance of the display panel.

[0148] It should be noted that in existing array substrate structure designs, the gate region and the base region on the first signal line are typically located on opposite sides of the main body in the first direction Y. This results in raised structures on both sides of the first signal line, occupying a relatively large width. Furthermore, the electric field generated at the raised locations has a significant impact on the liquid crystal layer, requiring a larger black matrix to block potential light leakage areas at the raised locations, thus limiting the improvement of the display panel's aperture ratio. This application, through the aforementioned design, can significantly improve the problems existing in the prior art, which is beneficial for improving the aperture ratio and transmittance of the display panel.

[0149] In some embodiments, referring to FIG16, the color filter substrate 200 may include a second substrate 210 and a black matrix 220 and spacers PS sequentially disposed on the second substrate 210. The spacers PS may include a main spacer PS1 and a secondary spacer PS2. The end of the main spacer PS1 that is away from the second substrate 210 abuts against the array substrate 100, and the end of the secondary spacer PS2 that is away from the second substrate 210 abuts against the array substrate 100 or has a gap.

[0150] For example, when the color filter substrate 200 and the array substrate 100 are not subjected to pressure that brings them closer together, the end of the secondary spacer PS2 away from the second substrate 210 has a gap with the array substrate 100. When the color filter substrate 200 and / or the array substrate 100 are subjected to pressure that brings them closer together, the primary spacer PS1 is compressed and deformed, and the secondary spacer PS2 can also abut against the array substrate 100, serving to support the cell thickness between the color filter substrate 200 and the array substrate 100.

[0151] For example, when the display panel is in its normal state, the main spacer PS1 provides support for the liquid crystal cell thickness. When the display panel is pressed, the color filter substrate 200 is squeezed towards the array substrate 100, the main spacer PS1 is deformed by the compression, and the secondary spacer PS2 participates in supporting the liquid crystal cell thickness, that is, the secondary spacer PS2 contacts the upper surface of the array substrate 100 (the surface near the color filter substrate). The main spacer PS1 and the secondary spacer PS2 together provide support for the liquid crystal cell thickness.

[0152] In one example, the end face of the secondary spacer PS2 furthest from the second substrate 210 is designated as the first end face S1, and the end face of the primary spacer PS1 furthest from the second substrate 210 is designated as the second end face S2. Under natural conditions (when the display panel is not under pressure), the height difference between the first end face S1 and the second end face S2 can be 0.4 μm to 0.6 μm. Exemplarily, the height difference between the first end face S1 and the second end face S2 can be 0.4 μm, 0.5 μm, or 0.6 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0153] Referring to FIG13, the plurality of protrusions 24 include a plurality of base regions 26, including a first base region 261 and a second base region 262. The first base region 261 is configured to support the secondary spacer PS2, for example, the orthographic projection of the first end face S1 on the array substrate 100 at least partially coincides with the first base region 261. The second base region 262 is configured to support the primary spacer PS1, for example, the orthographic projection of the second end face S2 on the array substrate 100 at least partially coincides with the second base region 262. Exemplarily, a portion of the orthographic projection of the first end face S1 on the array substrate 100 is located within the first base region 261, and another portion is located within the main body 23; a portion of the orthographic projection of the second end face S2 on the array substrate 100 is located within the second base region 262, and another portion is located within the main body 23.

[0154] In this configuration, the first base area 261 is located on the side of the main body 23 away from the second signal line 22. That is, the first signal line 21 is located at the first base area 261, and there is no protruding structure on the side closest to the second signal line 22. This arrangement helps to reduce the width of the first signal line 21 at the first base area 261 and improves the edge regularity at that location. It also helps to reduce the size of the black matrix along the first direction Y at the first base area 261, thereby improving the aperture ratio and transmittance of the display panel.

[0155] Part of the second base area 262 is located on the side of the main body 23 away from the second signal line 22, and part is located on the side of the main body 23 closer to the second signal line 22. That is, at the location of the second base area 262, the first signal line 21 has protruding structures on both sides in the first direction Y. This increases the area of ​​the second base area 262, thereby ensuring that the main spacer PS1 can always be in contact with the location of the second base area 262, ensuring the supporting effect of the second base area 262 on the main spacer PS1.

[0156] Referring to Figure 13, in some embodiments, the dimension D11 of the portion of the second base plate region 262 located on the side of the main body 23 away from the second signal line 22 along the first direction Y is greater than the dimension D12 of the portion of the main body 23 located on the side closer to the second signal line 22 along the first direction Y. That is, most of the second base plate region 262 is located on the upper side of the main body 23. This helps to reduce the size of the first signal line 21 protruding towards the second signal line 22, i.e., reducing the degree of unevenness of the edges of the first signal line 21 and the second signal line 22 in the first direction Y. This also helps to reduce the size of the black matrix used to block the signal line group 20 in the first direction Y, thereby improving the aperture ratio and transmittance of the display panel.

[0157] Referring again to FIG13, in some embodiments, the portion of the second signal line 22 that is disposed opposite to the second base region 262 protrudes away from the first signal line 21 to form a winding portion 221. The spacing between the winding portion 221 and the second base region 262 is equal to the spacing between the second signal line 22 and the main body portion 23. This avoids the spacing between the second signal line 22 and the second base region 262 being too small, reducing the risk of a short circuit between the second signal line 22 and the second base region 262.

[0158] In some embodiments, the first base station region 261 is adjacent to the red pixel region 102 or the green pixel region 103; the second base station region 262 is adjacent to the blue pixel region 104. Exemplarily, the first base station region 261 is adjacent to the red pixel region 102 or the green pixel region 103 located on its side away from the second signal line 22 in the first direction Y; for example, a portion of the first base station region 261 is adjacent to the red pixel region 102 located on its side away from the second signal line 22 in the first direction Y, and a portion of the first base station region 261 is adjacent to the green pixel region 103 located on its side away from the second signal line 22 in the first direction Y. Studies have found that, under the same aperture ratio and conditions (such as the same grayscale), the luminous efficiency of the blue pixel area 104 is lower than that of the red pixel area 102 and the green pixel area 103. Based on this, in the embodiments of this disclosure, the first base area 261 is adjacent to the red pixel area 102 or the green pixel area 103; the second base area 262 is adjacent to the blue pixel area 104, which is beneficial to improving the overall transmittance of the display panel.

[0159] In some embodiments, referring to FIG17, the distance D13 between the boundary of the orthographic projection of the first end face S1 of the sub-spacer PS2 onto the array substrate 100 and the boundary of the first sill region 261 is greater than or equal to 2 μm. On the one hand, this ensures that even if a certain alignment error occurs between the array substrate 100 and the color filter substrate, the sub-spacer PS2 can still be supported on the first sill region 261. On the other hand, the flatness requirement of the first sill region 261 on the array substrate 100 used to support the sub-spacer PS2 is relatively low. When the distance D13 is greater than or equal to 2 μm, not only can the design requirements be met, but it is also beneficial to reduce the area of ​​the first sill region 261 and improve the aperture ratio of the array substrate. Exemplarily, the distance D13 between the boundary of the first end face S1 and the boundary of the first sill region 261 can be 2 μm, 2.2 μm, 2.5 μm, or 3 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0160] In some embodiments, continuing to refer to FIG17, when the array substrate 100 includes a planarization layer ORG and the first electrode 11 is disposed between the planarization layer ORG and the first insulating layer PVX, the distance D14 between the boundary of the orthographic projection of the first end face S1 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 is greater than or equal to 25 μm. In this way, the sub-spacer PS2 experiences a certain degree of sliding, while the black matrix 220 can still block the location of the sub-spacer PS2, reducing the risk of light leakage around the sub-spacer PS2. Exemplarily, the distance D14 can be 25 μm, 26 μm, 28 μm, or 30 μm, etc., and the embodiments of this disclosure will not be listed individually here.

[0161] It should be noted that the orthographic projection of the black matrix 220 on the array substrate 100 is not limited to the shape and size shown in Figures 17 and 18. Figures 17 and 18 only illustrate the corresponding size and dimensions of the black matrix 220 required to cover the main spacer PS1 and the secondary spacer PS2. In order to cover other structures (such as signal line group 20 and third signal line 30), the black matrix 220 may also include other parts, and the embodiments of this disclosure do not limit this.

[0162] Referring to Figure 18, when the array substrate 100 includes a planarization layer ORG and the first electrode 11 is disposed between the planarization layer ORG and the first insulating layer PVX, the distance D15 between the boundary of the orthographic projection of the second end face S2 of the main spacer PS1 onto the array substrate 100 and the boundary of the second sill region 262 is greater than or equal to 4.5 μm. On the one hand, this ensures that even if a certain alignment error occurs between the array substrate 100 and the color filter substrate, the main spacer PS1 can still be supported on the second sill region 262, ensuring the support effect of the main spacer PS1. On the other hand, the flatness requirement of the second sill region 262 on the array substrate 100 used to support the main spacer PS1 is high. When the distance D15 is greater than or equal to 4.5 μm, the main spacer PS1 can be supported on a relatively flat surface, reducing the risk of the main spacer PS1 sliding. For example, the interval D15 between the boundary of the second end face S2 and the boundary of the second base area 262 can be 4.5μm, 5μm, 6μm or 6.5μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0163] In some embodiments, continuing to refer to FIG18, when the array substrate 100 includes a planarization layer ORG and the first electrode 11 is disposed between the planarization layer ORG and the first insulating layer PVX, the distance D16 between the boundary of the orthographic projection of the second end face S2 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 is greater than or equal to 28 μm. Thus, even if the main spacer PS1 slides a large distance (e.g., slides into the pixel area 101), the black matrix can still shield the scratched area on the array substrate 100, reducing the risk of light leakage in the display panel. Exemplarily, the distance D16 can be 28 μm, 29 μm, 30 μm, or 31 μm, etc., and the embodiments of this disclosure will not be listed individually here.

[0164] In some embodiments, as shown in FIG13, the gate region 25 and the base region 26 belonging to the same protrusion 24 are respectively located on both sides of a third signal line 30. This not only separates the gate region 25 and the base region 26 on the same protrusion 24 from each other, avoiding the spacer PS from abutting against the first transistor T1 and reducing the risk of the first transistor T1 being damaged by pressure, but also simplifies the pattern of the gate region 25 and the base region 26, reducing the fabrication difficulty of the first signal line 21. The pixel region 101 is adjacent to a gate region 25 and a base region 26 belonging to two protrusions 24 respectively, and there is a first gap L1 between the gate region 25 and the base region 26 adjacent to the same pixel region 101. In this way, the structure of the first transistor T1 can be set within the first gap L1 so that the boundary of the first transistor T1 in the first direction Y does not exceed the edge of the protrusion 24, reducing the space occupied by the first signal line 21 and the first transistor T1 in the first direction Y, thereby improving the aperture ratio of the array substrate.

[0165] For example, as shown in Figures 6 and 13, the source pattern 31 of the first transistor T1 is electrically connected to the third signal line 30, and the drain pattern 32 is electrically connected to the first electrode 11. For example, the source pattern 31 and the third signal line 30 are integrally formed, meaning they are two separate regions artificially defined on the same physical structure; in other words, they may not have a clear boundary in their actual structure. The drain pattern 32 extends along the second direction X, and in the orthographic projection of the drain pattern 32 and the first signal line 21 onto the first substrate 10, a portion of the drain pattern 32 is located within the gate region 25, and a portion is located within the first interval L1. That is, a portion of the drain pattern 32 is located on the gate region 25, and a portion extends into the first interval L1, with the portion of the drain pattern 32 extending into the first interval L1 electrically connected to the first electrode 11. This reduces the space occupied by the first transistor T1 in the first direction Y, which is beneficial for improving the aperture ratio of the array substrate. For example, the connection portion 111 of the first electrode 11 extends along the first direction Y, and the orthographic projection of the connection portion 111 on the first substrate 10 is located within the first interval L1.

[0166] In some embodiments, as shown in FIG13, when the first signal line 21 includes a main body 23 and a protrusion 24, the protrusion 24 includes a gate region 25 and a base region 26, and the array substrate 100 includes a third via V3, the third via V3 and the base region 26 are offset in the second direction X. This avoids the third via V3 and the base region 26 being aligned in the first direction Y, reducing the possibility of a protrusion forming on the side of the second signal line 22 away from the first signal line 21, and thus improving the aperture ratio of the array substrate 100.

[0167] Referring again to Figure 13, the third via V3 can be disposed opposite to the gate region 25 in the first direction Y. Since there is no protrusion structure on the side of the gate region 25 near the second signal line 22, the fact that the third via V3 is disposed opposite to the gate region 25 in the first direction Y will not cause the second signal line 22 to form a protrusion at the third via V3, which is beneficial to improving the aperture ratio of the array substrate 100.

[0168] In some embodiments, referring to FIG19, the third signal line 30 includes alternating first extension segment 33 and second extension segment 34. In the orthographic projection of the third signal line 30 and the signal line group 20 on the first substrate 10, the first extension segment 33 partially overlaps with the signal line group 20, while the second extension segment 34 does not overlap with the signal line group 20. The linewidth (dimension along the direction perpendicular to the first extension segment 33) D17 of the first extension segment 33 is greater than or equal to the linewidth (dimension along the direction perpendicular to the second extension segment 34) D18 of the second extension segment 34. Since the signal line group 20 is located on the side of the third signal line 30 closer to the first substrate 10, and the signal line group 20 has a certain thickness, the surface of the second insulating layer GI away from the first substrate 10 will form an undulating morphology at the location of the signal line group 20. The fact that the linewidth of the first extension segment 33 is greater than or equal to the linewidth of the second extension segment 34 can reduce the risk of the third signal line 30 breaking or experiencing excessive local resistance at the ramp point.

[0169] In some embodiments, the line width D17 of the first extension segment 33 is greater than or equal to 4.5 μm, which ensures that the first extension segment 33 is continuous at the location of the ramp signal line group 20 and that the resistance does not increase significantly. Exemplarily, the line width D17 of the first extension segment 33 can be 4.5 μm, 5.0 μm, 5.2 μm, 7 μm, or 8 μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0170] The linewidth D18 of the second extension segment 34 can be 2.5μm to 8μm. For example, the linewidth D9 of the second extension segment 34 can be 2.5μm to 4.5μm, or 4.5μm to 8μm. When the linewidth D18 of the second extension segment 34 is 2.5μm to 4.5μm, the linewidth D17 of the first extension segment 33 can be greater than the linewidth of the second extension segment 34. In this case, the linewidth D18 of the second extension segment 34 can be, for example, 2.5μm, 3μm, 4μm, or 4.5μm. When the linewidth D18 of the second extension segment 34 is 4.5μm to 8μm, the size of the first extension segment D17 can be equal to the size of the second extension segment 34. In this case, the linewidth D18 of the second extension segment 34 can be, for example, 4.5μm, 6μm, 7μm, or 8μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0171] In some embodiments, continuing to refer to FIG19, the second signal line 22 includes alternating third extensions 27 and fourth extensions 28. In the orthographic projection of the second signal line 22 and the third signal line 30 onto the first substrate 10, the third extension 27 at least partially overlaps with the third signal line 30, while the fourth extension 28 does not overlap with the third signal line 30. The linewidth (dimension along the direction perpendicular to the third extension 27) D19 of the third extension 27 is smaller than the linewidth D20 of the fourth extension 28. This reduces the facing area between the third signal line 30 and the second signal line 22, reduces the parasitic capacitance formed between the third signal line 30 and the second signal line 22, thereby reducing the load on the third signal line 30 and facilitating a reduction in the power consumption of the array substrate.

[0172] In some embodiments, as shown in FIG19, the orthographic projection of the third extension 27 on the first substrate 10 passes through the orthographic projection of the third signal line 30 on the first substrate 10, and there is a third gap L3 between the end of the third extension 27 and the third signal line 30. In this way, it is possible to avoid the third extension 27 not being able to be positioned opposite to the third signal line 30 due to manufacturing errors. That is, it is possible to ensure that the third signal line 30 can be positioned opposite to the third extension 27, reducing the parasitic capacitance formed between the third signal line 30 and the second signal line 22, thereby reducing the load on the third signal line 30 and helping to reduce the power consumption of the array substrate.

[0173] In some embodiments, the linewidth D20 of the fourth extension 28 of the second signal line 22 can be greater than or equal to 4.5 μm. This allows the second signal line 22 to have lower resistance, which is beneficial for reducing the voltage across the second signal line 22 and the second electrode layer 40. Exemplarily, the linewidth D20 of the fourth extension 28 can be 4.5 μm, 5.0 μm, 5.5 μm, or 6 μm, etc., and these embodiments will not be listed individually in this disclosure.

[0174] The linewidth D19 of the third extension segment 27 can be 2.5μm to 4μm. For example, the linewidth D19 of the third extension segment 27 can be 2.5μm, 3.0μm, 3.5μm, or 4.5μm, etc., and the aforementioned third interval L3 can be greater than or equal to 1.9μm. For example, the third interval L3 can be 1.9μm, 2.0μm, 2.3μm, or 2.5μm, etc. The embodiments of this disclosure will not be listed one by one.

[0175] Referring to Figures 20, 21, and 22, in some embodiments, unlike the embodiments shown in Figures 4 and 5, the first electrode 11 may also be disposed on the same film layer as the signal line group 20. In other words, the signal line group 20 and the first electrode 11 are in contact with the same layer of material located on the side of both near the first substrate 10. The spacing between the two and the first substrate 10 may be equal or unequal, but this does not mean that they are formed in the same patterning process. Exemplarily, the signal line group 20 and the first electrode 11 are formed on the same film layer (e.g., the first substrate 10) through two different processes. Based on this, their materials may also be different. For example, the material of the signal line group 20 may include a metallic conductive material to improve the conductivity of the signal line group 20 and reduce the power consumption of the array substrate, while the material of the first electrode 11 may include a transparent conductive material to improve the transmittance of the first electrode 11, thereby improving the transmittance of the array substrate.

[0176] Referring to Figure 22, the array substrate 100 further includes a second insulating layer GI and a first insulating layer PVX. The second insulating layer GI is located between the signal line group 20 and the first electrode 11 and the semiconductor layer ACT, to prevent the signal line group 20 from directly short-circuiting with the first electrode 11 and the semiconductor layer ACT. The first insulating layer PVX is located between the third signal line 30 and the second electrode layer 40. There may be no insulating layer between the third signal line 30 and the semiconductor layer ACT, for example, the third signal line 30 may be in direct contact with the semiconductor layer ACT.

[0177] In some embodiments, referring to Figures 20, 21, and 22, the orthographic projection of the drain pattern 32 on the first substrate 10 coincides with the orthographic projection of the first electrode 11 on the first substrate 10. The array substrate 100 further includes a fifth via V5 and a transition portion 43. The fifth via V5 penetrates the second insulating layer GI and the first insulating layer PVX, exposing a first region 114 of the first electrode 11 and a second region 321 of the drain pattern 32. The transition portion 43 is made of the same material as the second electrode layer 40 and is disposed in the same layer. The transition portion 43 is at least partially located within the fifth via V5 and is electrically connected to both the first electrode 11 and the drain pattern 32. Compared to the adapter 43 which is electrically connected to the first electrode and the drain pattern through two vias respectively, in the embodiments of this disclosure, the first electrode 11 and the drain pattern 32 can be exposed simultaneously through a single via (the fifth via V5). This not only reduces the number of vias but also allows the bottom morphology of the fifth via V5 to have a certain undulation, which can reduce the step difference formed on the array substrate at the fifth via V5. This is beneficial for the flow and diffusion of PI liquid in the fifth via V5, avoiding uneven diffusion of PI liquid in the fifth via V5, and thus reducing Mura-type defects caused by uneven diffusion of PI liquid.

[0178] In some embodiments, as shown in FIG21, the first region 114 and the second region 321 are arranged along the first direction Y, that is, the fifth via V5 extends along the first direction Y. In this way, the size of the fifth via V5 and the transition portion 43 in the second direction X can be reduced, thereby increasing the space for setting the base area 26. This is beneficial for setting the base area 26 of the first signal line 21 on the side of the main body 23 away from the second signal line 22, thereby improving the aperture ratio and transmittance of the array substrate 100.

[0179] In some embodiments, referring further to FIG21, the first electrode 11 includes a connection portion 111, which extends along a first direction Y. The orthographic projection of the connection portion 111 on the first substrate 10 is located within a first interval L1 and coincides with the orthographic projection portion of the drain pattern 32 on the first substrate 10.

[0180] Referring again to FIG21, in some embodiments, the dimension D21 of the first region 114 in the first direction Y is greater than or equal to 1.9 μm. This ensures that the fifth via V5 can expose the first electrode 11 and guarantees the contact area between the adapter 43 and the first electrode 11, reducing the contact resistance between the adapter 43 and the first electrode 11. Exemplarily, the dimension D21 of the first region 114 in the first direction Y can be 1.9 μm, 2.0 μm, 2.2 μm, or 2.3 μm, etc., and these embodiments of this disclosure will not be listed individually.

[0181] Referring again to Figure 21, the dimension D22 of the second region 321 in the first direction Y is greater than or equal to 2.1 μm. This ensures that the fifth via V5 can expose the drain pattern 32, and also helps to increase the contact area between the transition electrode and the drain pattern 32, thereby reducing the contact resistance between them. For example, the dimension D22 of the second region 321 in the first direction Y can be 2.1 μm, 2.2 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0182] Referring to Figures 23 and 24, in some embodiments, the array substrate 100 further includes a sixth via V6. The sixth via V6 penetrates the second insulating layer GI and the first insulating layer PVX, and exposes a portion of the second signal line 22. A portion of the second electrode layer 40 is located within the sixth via V6 and is electrically connected to the second signal line 22 through the sixth via V6. Furthermore, at least a portion of the orthographic projection of the sixth via V6 onto the first substrate 10 lies outside the range of the orthographic projection of the second signal line 22 onto the first substrate 10. Similar to the fifth via V5, the design of the sixth via V6 can create a certain undulating morphology at its bottom. This facilitates the diffusion of PI liquid within the sixth via V6, avoids uneven diffusion of PI liquid within the fifth via V5, and thus reduces Mura-type defects caused by uneven PI liquid diffusion.

[0183] Referring again to Figures 23 and 24, in some embodiments, the portion of the orthographic projection of the sixth via V6 onto the first substrate 10 is located in the region between the second signal line 22 and the first signal line 21. That is, the sixth via V6 is positioned on the side of the second signal line 22 closer to the first signal line 21. This increases the distance between the pixel region 101 adjacent to the second signal line 22 and the sixth via V6. A greater distance is maintained between the boundary of the orthographic projection of the black matrix on the color filter substrate onto the array substrate 100 and the boundary of the sixth via V6, avoiding light leakage caused by Mura-type defects due to the sixth via V6, and increasing the aperture ratio of the array substrate 100. The portion of the orthographic projection of the sixth via V6 onto the first substrate 10 located between the second signal line 22 and the first signal line 21 has a second spacing L2 with the first signal line 21. This prevents short circuits between the second electrode layer 40 and the first signal line 21.

[0184] As shown in Figure 23, the second signal line 22 is recessed (downward) at the location of the sixth via V6, forming a first groove 222 away from the first signal line 21. The sixth via V6 exposes at least a portion of the first groove 222. This helps to increase the spacing between the sixth via V6 and the first signal line 21, and helps to reduce the distance between the second electrode layer 40 and the first signal line 21, thus preventing a short circuit between the second electrode layer 40 and the first signal line 21 at the location of the sixth via V6.

[0185] Referring again to Figure 23, the portion of the sixth via V6 located outside the orthographic projection of the second signal line 22 onto the first substrate 10 has a dimension D23 greater than or equal to 1.9 μm along the first direction Y. This ensures that the sixth via V6 is partially located outside the second signal line 22, forming a step at the bottom of the sixth via V6, thus improving the flow and diffusion of the PI liquid within the sixth via V6. Exemplarily, the dimension D23 of the portion of the sixth via V6 outside the second signal line 22 along the first direction Y can be 1.9 μm, 2.1 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0186] The portion of the sixth via V6 that overlaps with the orthographic projection of the second signal line 22 on the first substrate 10 has a dimension D24 along the first direction Y greater than or equal to 2.1 μm. This ensures that the sixth via V6 exposes sufficient space for the second signal line 22, which helps increase the contact area between the second electrode layer 40 and the second signal line 22, and reduces the contact resistance between them. Exemplarily, the dimension D24 of the portion of the sixth via V6 exposing the second signal line 22 along the first direction Y can be 2.1 μm, 2.2 μm, 2.3 μm, or 2.5 μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0187] In some embodiments, when the array substrate 100 does not include the planarization layer ORG and the first electrode 11 and signal line group 20 are disposed on the same film layer (the array substrate adopts the structure shown in Figures 3 to 5), the distance between the boundary of the orthographic projection of the end face (first end face S1) of the secondary spacer PS2 away from the second substrate 210 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 can be greater than or equal to 18 μm. Exemplarily, the distance between the orthographic projections of the boundary of the first end face S1 and the boundary of the black matrix 220 on the array substrate 100 can be 18 μm, 19 μm, 20 μm, or 21 μm, etc., and the embodiments disclosed herein will not be listed one by one.

[0188] When the array substrate 100 does not include the planarization layer ORG, and the first electrode 11 and the signal line group 20 are disposed on the same film layer (the array substrate adopts the structure shown in Figures 3 to 5), the distance between the boundary of the orthographic projection of the end face of the main spacer PS1 away from the second substrate 210 (the second end face S2) on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 can be greater than or equal to 25 μm. For example, the distance between the boundary of the orthographic projection of the second end face S2 on the array substrate 100 and the boundary of the orthographic projection of the black matrix 220 on the array substrate 100 can be 25 μm, 27 μm, 28.5 μm, or 30 μm, etc., and the embodiments disclosed herein will not be listed one by one here.

[0189] Some embodiments of this disclosure also provide a method for fabricating an array substrate, used to fabricate an array substrate including a planarization layer ORG. Referring to Figures 25-28, the method may include steps S100-S600. Figures 25-28 illustrate the fabrication process of the array substrate in the cross-section shown in Figure 5.

[0190] S100, referring to FIG25, a signal line group 20 is formed on the first substrate 10. FIG25 only schematically shows the first signal line 21 of the signal line group 20.

[0191] For example, step S200 may include: forming a full-layer first conductive layer on the first substrate 10 and the first electrode 11, then patterning the first conductive layer by photolithography, removing the portion of the first conductive layer located in the pixel area, and forming a patterned first signal line 21 and a second signal line (not shown in the figure). The structure of the first signal line 21 and the second signal line may be the structure described in any of the above embodiments.

[0192] Furthermore, the material of the first conductive layer may include metallic conductive materials, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the first conductive layer may also be a metallic multilayer structure. Exemplarily, the first conductive layer may include one or a combination of the following structures: titanium-aluminum-titanium (Ti / Al / Ti) multilayer structure, molybdenum-aluminum (Mo / Al) multilayer structure, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structure, molybdenum-niobium-titanium (MoNb / Ti) multilayer structure, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structure, molybdenum-niobium-copper (MoNb / Cu) multilayer structure, molybdenum-nickel-titanium-copper (MTD / Cu) multilayer structure, molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / Cu / MTD) multilayer structure, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) multilayer structure, molybdenum-neodymium-copper multilayer structure, MoNb-copper-MoNb multilayer structure, and AlNb-molybdenum-AlNd multilayer structure.

[0193] In a specific example, the first conductive layer comprises a molybdenum-aluminum-molybdenum stacked structure, and along the direction away from the first substrate, the thicknesses of the three molybdenum-aluminum-molybdenum films are respectively: and

[0194] S200, referring to Figure 26, prepares to form the second insulating layer GI.

[0195] Exemplarily, the second insulating layer GI can be formed by a thin-film deposition process. The material of the second insulating layer GI may include at least one of silicon nitride and silicon oxide. The second insulating layer GI can be a single-layer structure or a multilayer structure, which will not be listed here. In a specific example, the second insulating layer GI may include a thickness of... Silicon nitride.

[0196] S300, continuing to refer to Figure 26, the semiconductor layer ACT and the third signal line 30 are fabricated.

[0197] For example, step S300 may include: firstly, forming a semiconductor layer and a second conductive layer sequentially through a film deposition process, wherein both the semiconductor layer and the second conductive layer are integral layer structures. A mask layer material is coated onto the second conductive layer, and a semi-transparent mask (HTM) is used to expose the mask layer material, wherein partial exposure is performed on the portion of the mask layer material located in the channel region, and then a mask layer is formed. A dry etching process is used to first pattern the second conductive layer, forming a third signal line 30 and a drain pattern 32, retaining the portion of the second conductive layer located between the third signal line 30 and the drain pattern 32 (the portion located in the channel region). Then, a wet etching process is used to pattern the semiconductor layer, etching away the areas of the semiconductor layer not covered by the second conductive layer, retaining the portion located in the channel region. Then, the mask layer is removed by ashing exposure, and a second dry etching process is used to remove the portion of the second conductive layer located in the channel region, exposing the channel region of the semiconductor layer. The above-described process for fabricating the semiconductor layer and the third signal line can reduce the use of a mask, which helps to simplify the fabrication process of the array substrate and reduce the fabrication cost of the array substrate.

[0198] The semiconductor layer material includes semiconductor materials, such as metal oxide materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth element-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), and indium oxide (InO).

[0199] The material of the second conductive layer may include a metallic conductive material. For reference on the materials of the signal line group above, the metallic conductive material will not be repeated here. The materials of the second conductive layer and the signal line group may be the same or different.

[0200] S400, see Figure 27, prepare and form a planarized layer ORG.

[0201] For example, a planarization layer can be formed first by a coating process, and then the planarization layer ORG can be patterned by a photolithography process to form a first via V1 and a third via (not shown in the figure) in the planarization layer ORG. The material of the planarization layer ORG can be, for example, an organic resin.

[0202] In some embodiments, prior to step S400, the fabrication method may further include forming a passivation layer, specifically, forming a passivation layer between the planarization layer ORG and the third signal line 30. The material of the passivation layer may include silicon nitride, and the thickness of the passivation layer may be, for example, [missing information - likely a thickness value].

[0203] S500, referring to Figure 28, multiple first electrodes 11 are fabricated on the planarized ORG layer. Figure 28 only schematically shows one first electrode 11.

[0204] For example, step S100 may include: forming a full-layer first transparent electrode layer on the planarization layer ORG, and then patterning the first transparent electrode layer by photolithography to form a plurality of first electrodes 11. The portion of each first electrode 11 within a pixel region is a continuous block structure; in other words, the portion of the first electrode 11 within the pixel region is not patterned in the photolithography process. Furthermore, the material of the first electrode 11 may include a transparent conductive material, such as ITO, and the thickness of the first electrode 11 may be [missing information].

[0205] S500, continuing to refer to Figure 28, the first insulating layer PVX is formed, and the second via V2 and the fourth via are formed (not shown in the figure).

[0206] For example, a full-layer first insulating layer PVX can be formed by a thin-film deposition process. The material of the first insulating layer PVX may include silicon nitride and / or silicon oxide, and the thickness of the first insulating layer PVX can be [missing information]. Then, the first via V1 and the second via can be formed by photolithography. The position and structure of the first via V1 and the second via can be the position and structure described in any of the above embodiments, and will not be repeated here.

[0207] S600, forming the second electrode layer 40.

[0208] Step S600 above may include: forming a solid second transparent conductive layer, and then patterning the second transparent conductive layer using a photolithography process to form a second electrode layer 40 and an overlap portion 41. Furthermore, the material of the second transparent conductive layer may include a transparent conductive material, such as ITO, and the thickness of the second transparent conductive layer may be [missing information - likely a value or specification].

[0209] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: A first substrate, a plurality of first electrodes and a plurality of signal line groups disposed on one side of the first substrate, the plurality of signal line groups being spaced apart along a first direction, and each of the signal line groups including a first signal line and a second signal line, the first signal line and the second signal line both extending along a second direction; the first direction intersects the second direction; as well as, Multiple third signal lines are distributed at intervals along the second direction, and each of the third signal lines extends along the first direction; The orthogonal projections of the plurality of third signal lines and the plurality of signal line groups on the first substrate intersect to form a grid structure, with each grid defining a pixel area; The first electrode is located within the pixel area; Multiple first transistors, the gates of the first transistors being electrically connected to the first signal line; The second electrode layer is disposed on the side of the first signal line away from the first substrate. The second electrode layer is electrically connected to the second signal line. The orthographic projection of the second electrode layer on the first substrate does not coincide with the orthographic projection of the first transistor on the first substrate, and at least partially coincides with the orthographic projections of the plurality of third signal lines on the first substrate, and covers at least a portion of the edge of the orthographic projection of the first signal line on the first substrate.

2. The array substrate according to claim 1, further comprising: A planarization layer is disposed on the side of the first transistor away from the first substrate; A first insulating layer is disposed on the side of the planar layer away from the first substrate; The first via penetrates the planarization layer; The first electrode is disposed between the planarization layer and the first insulating layer, and the second electrode layer is disposed on the side of the first insulating layer away from the first substrate; the first electrode passes through the first via and is electrically connected to the first transistor.

3. The array substrate according to claim 2, wherein, The first transistor includes a source pattern and a drain pattern, the source pattern being electrically connected to the third signal line, and the drain pattern being electrically connected to the first electrode; The first via includes a first portion and a second portion, the first portion exposing at least a portion of the drain pattern, and the second portion having an orthographic projection on the first substrate outside the orthographic projection of the drain pattern on the first substrate.

4. The array substrate according to claim 3, wherein, The first part and the second part are arranged along the first direction, and the second part is located on the side of the first part closer to the pixel area; The first electrode includes a connection portion that passes through the second portion and extends to the first portion to connect with the drain pattern.

5. The array substrate according to claim 4, wherein, The size of the orthographic projection of the connecting portion on the first substrate along the second direction is greater than the size of the orthographic projection of the first via on the first substrate along the second direction; The connecting portion also covers at least one side of the flat layer located in the second direction of the first via.

6. The array substrate according to claim 5, wherein, The connecting portion covers both sides of the first via in the second direction within the flat layer.

7. The array substrate according to claim 5 or 6, wherein, The distance between the end of the orthographic projection of the connection portion on the first substrate along the second direction and the boundary of the orthographic projection of the first via on the first substrate is greater than or equal to 2.1 μm.

8. The array substrate according to any one of claims 2 to 7, further comprising: The second via penetrates the first insulating layer, and the orthographic projection of the second via on the first substrate at least partially overlaps with the orthographic projection of the first via on the first substrate; The overlapping portion is made of the same material as the second electrode layer and is disposed in the same layer. The overlapping portion is electrically insulated from the second electrode layer and is connected to the first electrode through the second through hole.

9. The array substrate according to claim 8, wherein, At least a portion of the orthographic projection of the second via on the first substrate lies outside the orthographic projection of the first via on the first substrate.

10. The array substrate according to claim 9, wherein, The boundary of the second via's orthographic projection on the first substrate, located outside the portion of the first via's orthographic projection on the first substrate, is at a distance greater than or equal to 1 μm from the boundary of the first via's orthographic projection on the first substrate.

11. The array substrate according to any one of claims 8 to 10, wherein, The first electrode includes an electrode portion and a connecting portion. The electrode portion is located within the pixel area, and the connecting portion is located on one side of the electrode portion along the first direction and is connected to the electrode portion. The connecting portion passes through the first via and is electrically connected to the first transistor. The orthographic projection of the overlapping portion on the first substrate covers the orthographic projection of the second via on the first substrate, and also covers the orthographic projection of the portion of the connecting portion away from the electrode portion on the first substrate.

12. The array substrate according to claim 11, wherein, The distance between the boundary of the orthographic projection of the overlapping portion on the first substrate and the boundary of the orthographic projection of the connecting portion on the first substrate is greater than or equal to 1 μm; and / or, The dimension of the first via along the second direction is greater than or equal to 4 μm; and / or, The dimension of the second via along the second direction is greater than or equal to 4 μm.

13. The array substrate according to any one of claims 2 to 12, further comprising: The second insulating layer is located between the film layer containing the signal line group and the film layer containing the third signal line; The third via penetrates the planarization layer, and the orthographic projection of the third via on the first substrate at least partially coincides with the orthographic projection of the second signal line on the first substrate; The fourth via, the orthographic projection of the fourth via on the first substrate, at least partially overlaps with the orthographic projection of the third via on the first substrate, the fourth via penetrates the first insulating layer and the second insulating layer, and exposes a portion of the second signal line; The second electrode layer is electrically connected to the second signal line through the fourth via and the third via.

14. The array substrate according to claim 13, wherein, The third via includes a third part and a fourth part. The orthographic projection of the third part on the first substrate is within the range of the orthographic projection of the second signal line on the first substrate. The orthographic projection of the fourth part on the first substrate does not coincide with the orthographic projection of the second signal line on the first substrate.

15. The array substrate according to claim 14, wherein, At least a portion of the orthogonal projection of the fourth via on the first substrate lies outside the orthogonal projection of the third via on the first substrate.

16. The array substrate according to claim 15, wherein, The fourth part is located on the side of the third part closer to the first signal line; In the orthographic projection of the fourth via on the first substrate, both ends along the second direction and the end along the first direction away from the first signal line are located within the range of the orthographic projection of the third via on the first substrate, while the end along the first direction close to the first signal line is located outside the range of the orthographic projection of the third via on the first substrate.

17. The array substrate according to claim 16, wherein, In the orthographic projection of the fourth via on the first substrate, the distance between the two ends along the second direction and the end away from the first signal line along the first direction and the boundary of the orthographic projection of the third via on the first substrate is greater than or equal to 2.1 μm. And / or, In the orthographic projection of the third via on the first substrate, the distance between the end of the third via away from the first signal line along the first direction and the boundary of the orthographic projection of the third via on the first substrate is greater than or equal to 1 μm.

18. The array substrate according to any one of claims 13 to 17, wherein, The second signal line is recessed at the location of the third and fourth vias to form a first groove on the side away from the first signal line, and the fourth via exposes at least a portion of the first groove.

19. The array substrate according to any one of claims 1 to 18, wherein, The first signal line includes an integrally formed main body and a plurality of protrusions. The main body extends along the second direction, and the plurality of protrusions are spaced apart along the second direction. At least a portion of the protrusions is located on the side of the main body away from the second signal line. The protrusion includes a gate region and a base region. The gate region is disposed on the side of the main body away from the second signal line and is configured to form the gate of the first transistor. At least a portion of the base region is disposed on the side of the main body away from the second signal line and is configured to support a spacer.

20. The array substrate according to claim 19, wherein, The septum includes a primary septum and a secondary septum; The plurality of protrusions include the plurality of base regions comprising: The first base area, located on the side of the main body away from the second signal line, is configured to support the sub-septum; The second base plate area is located partly on the side of the main body away from the second signal line and partly on the side of the main body closer to the second signal line. The second base plate area is configured to support the main spacer.

21. The array substrate according to claim 20, wherein, The dimension of the portion of the second base plate region located on the side of the main body away from the second signal line along the first direction is greater than the dimension of the portion of the main body located on the side of the main body closer to the second signal line along the first direction.

22. The array substrate according to claim 20 or 21, wherein, The portion of the second signal line that is disposed opposite to the second base plate area protrudes away from the first signal line to form a winding portion; the interval between the winding portion and the second base plate area is equal to the interval between the second signal line and the main body portion.

23. The array substrate according to any one of claims 20 to 22, wherein, The plurality of pixel regions includes red pixel regions, green pixel regions, and blue pixel regions; The first base plate area is adjacent to the red pixel area or the green pixel area, and the second base plate area is adjacent to the blue pixel area.

24. The array substrate according to any one of claims 19 to 23, wherein, The gate region and the base region are arranged side by side along the second direction. At least a portion of the gate region and at least a portion of the base region belonging to the same protrusion are located on both sides of a third signal line. The pixel region is adjacent to a gate region and a base region belonging to two protrusions respectively, and there is a first interval between the gate region and the base region adjacent to the same pixel region. The first transistor includes a source pattern and a drain pattern, the source pattern being electrically connected to the third signal line, and the drain pattern being electrically connected to the first electrode; The drain pattern extends along the second direction, and in the orthographic projection of the drain pattern and the first signal line on the first substrate, the drain pattern is partially located within the range of the gate region and partially located within the first interval.

25. The array substrate according to any one of claims 1 to 24, wherein, The third signal line includes alternating first extension segments and second extension segments. In the orthographic projection of the third signal line and the signal line group on the first substrate, the first extension segment passes through the signal line group, and the second extension segment does not coincide with the signal line group. The line width of the first extension segment is greater than or equal to the line width of the second extension segment.

26. The array substrate according to claim 25, wherein, The linewidth of the first extension segment is greater than or equal to 4.5 μm; and / or, The linewidth of the second extension segment is 2.5μm to 8μm.

27. The array substrate according to any one of claims 1 to 26, wherein, The second signal line includes an alternately connected third extension and a fourth extension. In the orthographic projection of the second signal line and the third signal line onto the first substrate, the third extension at least partially overlaps with the third signal line, and the fourth extension does not overlap with the third signal line. The line width of the third extension segment is less than or equal to the line width of the fourth extension segment.

28. The array substrate according to claim 27, wherein, The orthographic projection of the third extension on the first substrate passes through the orthographic projection of the third signal line on the first substrate, and there is a third gap between the end of the third extension and the third signal line.

29. The array substrate according to claim 28, wherein, The linewidth of the third extension segment is 2.5 μm to 4 μm; and / or, The linewidth of the fourth extension segment is greater than or equal to 4 μm; and / or, The third interval is greater than or equal to 1.9 μm.

30. A display panel, comprising: The array substrate as described in any one of claims 1 to 29; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

31. The display panel according to claim 30, wherein, The first signal line of the array substrate includes an integrally formed main body and a plurality of protrusions. The main body extends along a second direction. The protrusions include a gate region and a base region. The plurality of base regions included in the plurality of protrusions include a plurality of first base regions and a plurality of second base regions. The color filter substrate includes a second substrate and a plurality of main spacers and a plurality of sub spacers disposed on one side of the second substrate. The ends of the main spacers away from the second substrate abut against the array substrate, and the ends of the sub spacers away from the second substrate abut against the array substrate or have gaps. Wherein, the end face of the secondary spacer away from the second substrate is the first end face, and the end face of the primary spacer away from the second substrate is the second end face. The orthographic projection of the first end face on the array substrate at least partially coincides with the first sill region, and the orthographic projection of the second end face on the array substrate at least partially coincides with the second sill region.

32. The display panel according to claim 31, wherein, The distance between the boundary of the orthographic projection of the first end face onto the array substrate and the boundary of the first sill region is greater than or equal to 2 μm; and / or, The distance between the boundary of the orthographic projection of the second end face onto the array substrate and the boundary of the second sill region is greater than or equal to 4.5 μm.

33. The display panel according to claim 31 or 32, wherein, The color filter substrate also includes a black matrix disposed on the side of the plurality of main spacers and the plurality of sub spacers near the second substrate; The distance between the boundary of the orthographic projection of the first end face onto the second substrate and the boundary of the orthographic projection of the black matrix onto the array substrate is greater than or equal to 25 μm. And / or, The distance between the boundary of the orthographic projection of the second end face on the array substrate and the orthographic projection of the black matrix on the array substrate is greater than or equal to 28 μm.

34. A display device, comprising: The array substrate as described in any one of claims 1 to 29; Or, the display panel as described in any one of claims 30 to 33.

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