Display substrate and display device

Abstract

Provided in at least one embodiment of the present disclosure are a display substrate and a display device. The display substrate comprises a base substrate; and a plurality of light-emitting elements and a pixel driving circuit which are arranged on the base substrate. The pixel driving circuit comprises a first conductive metal layer, a first insulating layer and a second conductive metal layer, wherein the second conductive metal layer comprises an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line which are arranged in a first direction; the initialization signal connection line, the anode connection electrode and the power supply voltage signal line all extend in a second direction intersecting the first direction; and the anode connection electrode is electrically connected to the second conductive metal layer by means of a first via hole structure arranged in the first insulating layer. The plurality of light-emitting elements comprise a first light-emitting element, wherein the first light-emitting element comprises a first anode, and an orthographic projection of the first anode on the base substrate does not overlap an orthographic projection of the first via hole structure on the base substrate. The display substrate can improve the flatness of the anode and thus reduce the risk of anode collapse.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411546838.0, filed on October 31, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0003] With the continuous development of display technology, consumers have increasingly higher demands for narrow bezel designs in display devices. Therefore, how to further reduce the bezel width of display devices has become a key focus and hot topic for researchers in the display field. Compared with traditional liquid crystal displays, organic light-emitting diodes (OLEDs), commonly used in narrow bezel designs, have been widely applied in the display technology field due to their advantages such as thinness, high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency. This has led to their widespread use in electronic devices such as mobile phones and tablets.

[0004] An OLED display panel includes a substrate, pixel driving circuitry, and light-emitting elements. The pixel driving circuitry includes conductive metal layers, which can be multi-layered. Insulating layers are provided between the different conductive metal layers of the pixel driving circuitry, and between the pixel driving circuitry and the anode of the light-emitting elements. These insulating layers serve to insulate and planarize the surface of the pixel driving circuitry, thereby improving its surface flatness. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a display substrate and a display device. The display substrate includes: a substrate; a pixel driving circuit and a plurality of light-emitting elements on the substrate; the pixel driving circuit includes a first conductive metal layer, a first insulating layer and a second conductive metal layer, the second conductive metal layer including an initialization signal connection line, an anode connection electrode and a power supply voltage signal line arranged in a first direction, the initialization signal connection line, the anode connection electrode and the power supply voltage signal line all extending along a second direction intersecting the first direction, the anode connection electrode being electrically connected to the second conductive metal layer through a first via structure disposed in the first insulating layer; the plurality of light-emitting elements includes a first light-emitting element, the first light-emitting element including a first anode, the orthographic projection of the first anode on the substrate and the orthographic projection of the first via structure on the substrate do not overlap, in the display substrate the orthographic projection of the first anode on the substrate and the orthographic projection of the first via structure on the substrate do not overlap, thereby allowing the anode not to cover the corresponding via structure, thereby improving the flatness of the first anode surface, reducing the color shift difference of the display panel, and also reducing the risk of anode collapse.

[0006] At least one embodiment of this disclosure provides a display substrate, the display substrate comprising: a substrate; a pixel driving circuit on the substrate; and a plurality of light-emitting elements located on a side of the pixel driving circuit away from the substrate; the pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer stacked thereon, the second conductive metal layer including an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged in a first direction, the initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extending along a second direction intersecting the first direction, the anode connection electrode being electrically connected to the second conductive metal layer through a first via structure disposed in the first insulating layer; the plurality of light-emitting elements includes a first light-emitting element, the first light-emitting element including a first anode, the orthographic projection of the first anode on the substrate and the orthographic projection of the first via structure on the substrate not overlapping.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of light-emitting elements include a second light-emitting element, the second light-emitting element includes a second anode, and the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure on the substrate partially overlap.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the area of ​​the overlap between the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure on the substrate is 0% to 20% of the area of ​​the first via structure.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a third gate metal layer disposed on the side of the first conductive metal layer away from the second conductive metal layer, wherein the first conductive metal layer includes a first data fan-out line extending along the first direction, the second conductive metal layer includes a second data fan-out line extending along the second direction, the third gate metal layer includes a third initialization signal line extending along the first direction, and the orthographic projection of the first data fan-out line on the substrate and the orthographic projection of the third initialization signal line on the substrate overlap.

[0010] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a first gate metal layer disposed on the side of the third gate metal layer away from the first conductive metal layer, wherein the first gate metal layer includes a first initialization signal line extending along the first direction, and the third gate metal layer further includes a second initialization signal line that is spaced apart from the third initialization signal line and extends along the second direction, wherein the orthographic projection of the first data fan-out line on the substrate and the orthographic projections of the first initialization signal line and the second initialization signal line on the substrate are all spaced apart from each other.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the first conductive metal layer includes a first initialization signal transfer line and a second initialization signal transfer line; the initialization signal connection line is electrically connected to the first initialization signal transfer line through a second via structure disposed in the first insulating layer, and is electrically connected to the second initialization signal transfer line through another second via structure disposed in the first insulating layer.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, in the second direction, the second via structure and the first via structure are respectively disposed on both sides of the first data fan-out line.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the initialization signal connection line and the first initialization signal line are electrically connected through the first initialization signal adapter line, the initialization signal connection line and the second initialization signal line are electrically connected through the second initialization signal adapter line, and the initialization signal connection line and the third initialization signal line are electrically connected to each form a mesh initialization signal structure.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive metal layer further includes a data signal line extending in the second direction, and the second data fan-out line is disposed between two adjacent data signal lines.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, two adjacent initialization signal connection lines, two adjacent anode connection electrodes, two adjacent power supply voltage signal lines, and two adjacent data signal lines are all axially symmetrical about the second data fan-out line.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the first gate metal layer further includes a first reset control signal line, and the orthographic projection of the first data fan-out line on the substrate, the orthographic projection of the third initialization signal line on the substrate, and the first reset control signal line overlap.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a second gate metal layer disposed between the third gate metal layer and the first gate metal layer, wherein the second gate metal layer includes a second electrode plate, a first shielding line and a second shielding line of a storage capacitor extending in the first direction, and the orthographic projections of the second electrode plate, the first shielding line and the second shielding line of the storage capacitor on the substrate are all spaced apart from the orthographic projections of the first data fan-out line on the substrate.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the third gate metal layer further includes a third scan signal line and a first scan signal line disposed on the side of the third initialization signal line near the second initialization signal line. The orthographic projection of the third scan signal line on the substrate and the orthographic projection of the second blocking line on the substrate overlap, and the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the first blocking line on the substrate overlap.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a seventh transistor, and an eighth transistor. The first electrode of the eighth transistor is connected to the third initialization signal line, the second electrode of the eighth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the first electrode of the first light-emitting element. The display substrate further includes a first active layer located between the substrate and the first gate metal layer. The first active layer includes a seventh active portion and an eighth active portion. The seventh active portion is used to form the channel region of the seventh transistor, and the eighth active portion is used to form the channel region of the eighth transistor. The orthographic projection of the first reset control signal line on the substrate covers the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the seventh active portion on the substrate. A portion of the structure of the first reset control signal line is used to form the gate of the seventh transistor, and a portion of the structure of the first reset control signal line is used to form the gate of the eighth transistor.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor and a sixth transistor. The first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second electrode of the eighth transistor. The first electrode of the sixth transistor is electrically connected to the second electrode of the seventh transistor. The first active layer further includes a third active portion, a fourth active portion, and a sixth active portion. The third active portion is configured to form a channel region of the driving transistor. The fourth active portion is connected to the eighth active portion, and the sixth active portion is connected to the seventh active portion.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit further includes a first transistor and a second transistor. The first electrode of the first transistor is connected to the first initialization signal line, the second electrode of the first transistor is connected to the second electrode of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor. The display substrate further includes a second active layer between the first active layer and the third gate metal layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit further includes a first transistor, a second transistor, and a ninth transistor. The first terminal of the first transistor is connected to the first initialization signal line, the second terminal of the first transistor is connected to the second terminal of the ninth transistor, the first terminal of the second transistor is connected to the second terminal of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the ninth transistor. The display substrate further includes a second active layer between the first active layer and the third gate metal layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor.

[0023] At least one embodiment of this disclosure also provides a display device, which includes the display substrate described in any of the above claims. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 is a schematic diagram of a planar structure of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 2 is a schematic cross-sectional view of a display substrate provided in at least one embodiment of the present disclosure;

[0027] Figure 3 is an equivalent circuit diagram of a pixel driving circuit provided in at least one embodiment of the present disclosure;

[0028] Figure 4 is a driving timing diagram of the pixel driving circuit shown in Figure 3;

[0029] Figure 5 is another driving timing diagram of the pixel driving circuit shown in Figure 3;

[0030] Figure 6 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure;

[0031] Figure 7 is a schematic diagram of the planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 8 is a schematic diagram of the planar structure of the first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 9 is a schematic planar structure of a display substrate with a stacked light-shielding layer and a first semiconductor layer according to at least one embodiment of the present disclosure;

[0034] Figure 10 is a schematic planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 11 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0036] Figure 12 is a schematic planar structure of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0037] Figure 13 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer, according to at least one embodiment of the present disclosure.

[0038] Figure 14 is a schematic diagram of the planar structure of the second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 15 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer, according to at least one embodiment of the present disclosure.

[0040] Figure 16 is a schematic planar structure of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0041] Figure 17 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer, according to at least one embodiment of the present disclosure.

[0042] Figure 18 is a schematic planar structure of the interlayer insulating layer of a display substrate provided in at least one embodiment of the present disclosure;

[0043] Figure 19 is a schematic planar structure diagram of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer, provided in at least one embodiment of the present disclosure.

[0044] Figure 20 is a schematic planar structure of an etching barrier layer in a display substrate provided in at least one embodiment of the present disclosure;

[0045] Figure 21 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etch barrier layer.

[0046] Figure 22 is a schematic planar structure of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 23 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, and a first conductive metal layer stacked together.

[0048] Figure 24 is a schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure;

[0049] Figure 25 is a schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0050] Figure 26 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer.

[0051] Figure 27 is a schematic planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0052] Figure 28 is a schematic planar structure of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer stacked together.

[0053] Figure 29 is a schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0054] Figure 30 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer.

[0055] Figure 31 is a schematic diagram of the planar structure of the anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0056] Figure 32 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer.

[0057] Figure 33 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure;

[0058] Figure 34 is a timing diagram of the pixel driving circuit shown in Figure 33.

[0059] Figure 35 is a schematic planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure;

[0060] Figure 36 is a schematic planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0061] Figure 37 is a schematic planar structure of a display substrate with a stacked light-shielding layer and a first semiconductor layer according to at least one embodiment of the present disclosure;

[0062] Figure 38 is a schematic planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0063] Figure 39 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer and a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0064] Figure 40 is a schematic planar structure of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0065] Figure 41 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer, according to at least one embodiment of the present disclosure.

[0066] Figure 42 is a schematic planar structure of a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0067] Figure 43 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer, according to at least one embodiment of the present disclosure.

[0068] Figure 44 is a schematic planar structure of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0069] Figure 45 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer, according to at least one embodiment of the present disclosure.

[0070] Figure 46 is a schematic planar structure of an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure;

[0071] Figure 47 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer, according to at least one embodiment of the present disclosure.

[0072] Figure 48 is a schematic planar structure of an etching barrier layer in a display substrate provided in at least one embodiment of the present disclosure;

[0073] Figure 49 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etch barrier layer, according to at least one embodiment of the present disclosure.

[0074] Figure 50 is a schematic planar structure of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0075] Figure 51 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, and a first conductive metal layer stacked together.

[0076] Figure 52 is a schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure;

[0077] Figure 53 is a schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0078] Figure 54 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer.

[0079] Figure 55 is a schematic planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0080] Figure 56 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer stacked together.

[0081] Figure 57 is a schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0082] Figure 58 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer.

[0083] Figure 59 is a schematic planar structure of the anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0084] Figure 60 is a schematic planar structure of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer.

[0085] Figure 61 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure;

[0086] Figure 62 is a schematic planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure;

[0087] Figure 63 is a schematic planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0088] Figure 64 is a schematic planar structure of a display substrate with a stacked light-shielding layer and a first semiconductor layer according to at least one embodiment of the present disclosure;

[0089] Figure 65 is a schematic planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0090] Figure 66 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer and a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0091] Figure 67 is a schematic planar structure of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0092] Figure 68 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer, according to at least one embodiment of the present disclosure.

[0093] Figure 69 is a schematic planar structure of a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0094] Figure 70 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer, according to at least one embodiment of the present disclosure.

[0095] Figure 71 is a schematic planar structure of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0096] Figure 72 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer, provided in at least one embodiment of the present disclosure.

[0097] Figure 73 is a schematic planar structure of an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure;

[0098] Figure 74 is a schematic planar structure diagram of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer, provided in at least one embodiment of the present disclosure.

[0099] Figure 75 is a schematic planar structure of an etching barrier layer in a display substrate provided in at least one embodiment of the present disclosure;

[0100] Figure 76 is a schematic planar structure of a display substrate comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etch barrier layer, according to at least one embodiment of the present disclosure.

[0101] Figure 77 is a schematic planar structure of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0102] Figure 78 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, and a first conductive metal layer stacked together.

[0103] Figure 79 is a schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure;

[0104] Figure 80 is a schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0105] Figure 81 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer.

[0106] Figure 82 is a schematic planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0107] Figure 83 is a schematic planar structure of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer stacked together.

[0108] Figure 84 is a schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0109] Figure 85 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer.

[0110] Figure 86 is a schematic planar structure of the anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0111] Figure 87 is a schematic planar structure diagram of a display substrate provided in at least one embodiment of the present disclosure, comprising a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer stacked together; and

[0112] Figure 88 is a block diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0113] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0114] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0115] Unless otherwise defined, the features such as "parallel," "perpendicular," and "identical" used in the embodiments of this invention include strictly defined cases of "parallel," "perpendicular," and "identical," as well as cases involving a certain degree of error, such as "approximately parallel," "approximately perpendicular," and "approximately identical." For example, the aforementioned "approximately" may indicate that the difference between the compared objects is within 10% or 5% of the average value of the compared objects. Unless otherwise specified in the following embodiments of this invention, the quantity of a component or element is implied to mean that the component or element may be one or more, or can be understood as at least one. "At least one" refers to one or more, and "more" refers to at least two. In the embodiments of this invention, "same-layer arrangement" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). Here, "same-layer" does not always mean that the multiple film layers have the same thickness or that the multiple film layers have the same height in a cross-sectional view.

[0116] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0117] In the accompanying drawings of embodiments of this disclosure, the thickness of the layers and the area of ​​the regions are enlarged to more clearly illustrate the layer structures in the display substrate and display device. Therefore, it is conceivable that variations in shape relative to the drawings due to, for example, fabrication techniques and / or tolerances, do not affect the essential characteristics of the display substrate and display device. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown in the embodiments of this disclosure, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings of embodiments of this disclosure are essentially schematic, and their shapes are not intended to show the actual shapes of regions of the device or apparatus, nor are they intended to limit the scope of the exemplary embodiments.

[0118] For example, in pixel driving circuits, Low Temperature Polycrystalline + Oxide (LTPO) technology can be applied to light-emitting diode (LED) displays. LTPO technology can reduce the power consumption of the display panel. The power consumption of a display panel includes driving power and emission power. LTPO-based display panels have lower driving power than LTPS-based display panels. While LTPS-based display panels require 60 Hz to display still images, LTPO-based display panels can reduce this to 1 Hz, significantly lowering the driving power.

[0119] For example, based on LTPO technology, some transistors in the display panel are oxide transistors (e.g., N-type oxide transistors). Oxide transistors have less leakage current, allowing the capacitor voltage (charge) to be maintained for one second, achieving a refresh rate of 1Hz. LTPS transistors have much greater leakage current, requiring 60Hz even to drive stationary pixels; otherwise, brightness would be significantly reduced. Therefore, LTPO technology has been widely used in display substrates.

[0120] The conductive metal layer of the pixel driving circuit can include a multilayer structure, such as a 2SD structure or a 3SD structure. The 2SD structure includes a first conductive metal layer (SD1 layer) and a second conductive metal layer (SD2 layer), with SD1 and SD2 layers stacked sequentially in a direction away from the substrate. SD1 layer can serve as the source and drain of each transistor in the pixel driving circuit, a first data fan-out line (FIP1) extending along the row direction, and signal lines such as data signal lines, power supply voltage signal lines, and a second data fan-out line (FIP2) extending along the column direction can be disposed on SD2 layer. This is merely an example, and the embodiments of this application do not impose limitations.

[0121] For example, an insulating layer can be placed between the SD1 and SD2 layers, which serves both insulating and planarizing functions. Via structures can be formed on the insulating layer, allowing the SD1 and SD2 layers to be electrically connected. Due to the dense wiring in OLED display panels, numerous via structures are placed in the insulating layers between adjacent conductive metal layers to connect the conductive metal layers on either side. The inventors of this disclosure have noted that some light-emitting elements have via structures on one side of the anode while the opposite side does not, i.e., the via structures are misaligned. This causes the anode to tilt towards the side with the via structure, leading to anode collapse and overall tilting of the anode towards the collapsed side. This affects the flatness of the anode, resulting in increased color shift differences in the display panel and a deterioration in display performance.

[0122] The inventors of this disclosure also noted the use of 2SD FIP or 3SD FIP processes in FIP (Fanout In Panel) narrow bezel technology. FIP technology integrates the edge wiring area of ​​the display panel into the display area, significantly reducing the area of ​​non-display areas and achieving extremely narrow bezels, such as around 1 mm. The display area of ​​the display panel includes a fan-out area and a normal display area outside the fan-out area, with data fan-out lines located in the fan-out area. In FIP products with two conductive metal layers, the FIP horizontal traces are located on the first conductive metal layer, and the FIP vertical traces are located on the second conductive metal layer. As the resolution of the display panel increases, the FIP horizontal traces will overlap with the GOA (Gate on Array) signal lines. If DC signal shielding is required for overlapping, for pixel circuits using new low-temperature polycrystalline silicon transistors and low-temperature polycrystalline + oxide (LTPO) transistor technologies, as well as currently mass-produced LTPO pixel circuits, at high resolution, the FIP lateral traces are routed between the source and drain of the first transistor T1 or between the source and drain of the seventh transistor T7 and the eighth transistor T8, so that adjacent initialization signal lines can be used for shielding to meet current design requirements.

[0123] At least one embodiment of this disclosure provides a display substrate, which includes: a substrate; a pixel driving circuit on the substrate; and a plurality of light-emitting elements located on the side of the pixel driving circuit away from the substrate. The pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer stacked together. The second conductive metal layer includes an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged sequentially in a first direction. The initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extend along a second direction intersecting the first direction. The anode connection electrode is electrically connected to the first conductive layer through a first via structure disposed in the first insulating layer. The plurality of light-emitting elements includes a first light-emitting element, and the first light-emitting element includes a first anode. The orthographic projection of the first anode on the substrate and the orthographic projection of the first via structure on the substrate do not overlap, so that the anode does not need to cover the corresponding via structure, thereby improving the flatness of the first anode surface and reducing the color shift difference of the display panel.

[0124] For example, in embodiments of this disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. It should be noted that, in embodiments of this disclosure, the channel region refers to the region through which current primarily flows.

[0125] For example, in embodiments of this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged.

[0126] For example, in embodiments of this disclosure, "electrical connection" includes the case where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0127] For example, Figure 1 is a schematic diagram of a planar structure of a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 1, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. Each pixel unit P includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel includes a circuit unit and a light-emitting unit. The circuit unit includes at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting control signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting control signal line. The light-emitting unit includes a light-emitting element, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting element is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0128] For example, in at least one embodiment of this disclosure, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. In exemplary embodiments, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, hexagonal, or diamond-shaped, and the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 may be arranged in a horizontal, vertical, or square manner, etc., and the embodiments of this disclosure do not limit this arrangement.

[0129] For example, in another embodiment of this disclosure, each pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc. The embodiments of this disclosure do not limit this arrangement.

[0130] For example, FIG2 is a cross-sectional structural schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG2, the display substrate 100 includes a substrate 101, which is divided into a display area and a peripheral area surrounding the display area. For example, the cross-sectional structural schematic diagram in FIG2 shows the structure of four sub-pixels in the display area. As shown in FIG2, on a plane perpendicular to the display substrate, the display substrate 100 may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. For example, in other embodiments, the display substrate may also include other film layers, such as a touch structure layer, etc., which are not limited in the embodiments of the present disclosure.

[0131] For example, in an embodiment of this disclosure, the peripheral area includes a lead area and a bonding area. The lead area includes multiple leads, and the bonding area is used to bond with an external driving circuit or driving chip. In this case, the multiple leads can be electrically connected to multiple signal lines and extend to the bonding area, thereby bonding the pixel structure with the external driving circuit or driving chip.

[0132] For example, in at least one embodiment of this disclosure, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include a light-emitting element. The light-emitting element includes at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to form a stacked structure of inorganic / organic / inorganic materials, thereby ensuring that external moisture and oxygen cannot enter the light-emitting structure layer 103 to protect the light-emitting element.

[0133] For example, in embodiments of this disclosure, when the substrate is a rigid substrate, the rigid substrate includes one of a glass substrate and a quartz substrate. When the substrate is a flexible substrate, the material of the flexible substrate includes one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0134] For example, in embodiments of this disclosure, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's waterproof and oxygen-permeable capabilities. The first and second inorganic material layers may also be referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si), etc.

[0135] For example, in an embodiment of this disclosure, a driving circuit layer 102, a light-emitting structure layer 103, and an encapsulation structure layer 104 are disposed on the main surface of the substrate. On a plane parallel to the main surface of the substrate, the driving circuit layer 102 may include multiple circuit units constituting multiple cell rows and multiple cell columns. Each circuit unit includes a pixel driving circuit, configured to output a corresponding current to a light-emitting element connected thereto. The light-emitting structure layer 103 may include multiple light-emitting units, each light-emitting unit including a light-emitting element. The light-emitting element is connected to the pixel driving circuit of its corresponding circuit unit, and the light-emitting element is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit connected thereto.

[0136] It should be noted that, in the embodiments of this disclosure, the circuit unit refers to the area divided according to the pixel driving circuit, and the light-emitting unit refers to the area divided according to the light-emitting element. In the embodiments of this disclosure, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0137] For example, Figure 3 is an equivalent circuit diagram of a pixel driving circuit provided in at least one embodiment of this disclosure. As shown in Figure 3, the pixel driving circuit is a 9T1C structure, which includes nine transistors (first transistor T1 to ninth transistor T9) and one storage capacitor C. Each pixel driving circuit is connected to 12 signal lines, including a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a fifth scan signal line S5, a first light emission control signal line EM1, a second light emission control signal line EM2, a first initialization signal line INIT1, a second initialization signal line INIT2, a third initialization signal line INIT3, a data signal line DATA, and a power supply voltage signal line VDD. The fourth scan signal line is also the first reset control signal line.

[0138] For example, in at least one embodiment of this disclosure, each pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting element EL, respectively. The fifth node N5 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9, respectively.

[0139] For example, in at least one embodiment of this disclosure, the first plate of the storage capacitor C in the pixel driving circuit is connected to the first node N1, and the second plate of the storage capacitor C is connected to the power supply voltage signal line VDD. For example, the first plate and the second plate are disposed opposite to each other, and the orthographic projection of the first plate on the main surface of the substrate and the orthographic projection of the second plate on the main surface of the substrate at least partially overlap.

[0140] For example, in at least one embodiment of this disclosure, the first transistor T1 is a first initialization transistor, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor T1 is connected to the fifth node N5 and also to the second electrode of the driving transistor.

[0141] For example, in at least one embodiment of this disclosure, the second transistor T2 is a compensation transistor, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the fifth node N5 and also to the gate of the driving transistor, and the second electrode of the second transistor T2 is connected to the third node N3 and also to the second electrode of the driving transistor.

[0142] For example, in at least one embodiment of this disclosure, the third transistor T3 is a driving transistor, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0143] For example, in at least one embodiment of this disclosure, the fourth transistor T4 is a data write transistor, the gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2, that is, it is also electrically connected to the second electrode of the eighth transistor.

[0144] For example, in at least one embodiment of this disclosure, the fifth transistor T5 is a first light-emitting control transistor, the gate electrode of the fifth transistor T5 is connected to the first light-emitting control signal line EM1, the first electrode of the fifth transistor T5 is connected to the power supply voltage signal line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0145] For example, the second electrode of the first light-emitting control transistor T5 and the second electrode of the third initialization transistor T8 are connected to the first electrode of the driving transistor T3. The second node electrode N2 is connected to the first electrode of the driving transistor T3, the second electrode of the first light-emitting control transistor T5 and the second electrode of the third initialization transistor T8, respectively. The orthographic projection of the second node electrode N2 on the substrate overlaps at least partially with the orthographic projection of the first initialization signal line INIT1 on the substrate.

[0146] For example, in at least one embodiment of this disclosure, the sixth transistor T6 is the second light-emitting control transistor, the gate electrode of the sixth transistor T6 is connected to the second light-emitting control signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3 and is also electrically connected to the second electrode of the seventh transistor, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0147] For example, in at least one embodiment of this disclosure, the seventh transistor T7 is a second initialization transistor, the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, the second electrode of the seventh transistor T7 is connected to the fourth node N4, and is connected to the first electrode of the first light-emitting element.

[0148] For example, in at least one embodiment of this disclosure, the eighth transistor T8 is a third initialization transistor, the gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5, the first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, the second electrode of the eighth transistor T8 is connected to the second node N2, and is connected to the first electrode of the driving transistor T3.

[0149] For example, the first active layer is located between the substrate and the first gate metal layer. The first active layer includes a seventh active portion and an eighth active portion. The seventh active portion is used to form the channel region of the seventh transistor, and the eighth active portion is used to form the channel region of the eighth transistor. The orthogonal projection of the first reset control signal line on the substrate covers the orthogonal projection of the eighth active portion on the substrate and the orthogonal projection of the seventh active portion on the substrate. A portion of the structure of the first reset control signal line is used to form the gate of the seventh transistor, and a portion of the structure of the first reset control signal line is used to form the gate of the eighth transistor.

[0150] For example, the first active layer also includes a third active portion, a fourth active portion, a sixth active portion and a ninth active portion, wherein the third active portion is configured to form a channel region of a driving transistor, the fourth active portion and the eighth active portion are connected, and the sixth active portion and the seventh active portion are connected.

[0151] For example, the display substrate further includes a second active layer between the first active layer and the third gate metal layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor.

[0152] For example, in at least one embodiment of this disclosure, the ninth transistor T9 is an isolation transistor, the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the first node N1.

[0153] For example, the second terminal of the first initialization transistor T1 is connected to the first terminal of the compensation transistor T2 and the first terminal of the isolation transistor T9. The second terminal of the isolation transistor T9 is connected to the gate electrode of the driving transistor T3, and the second terminal of the compensation transistor T2 is connected to the second terminal of the driving transistor T3. The channel region of the isolation transistor T9 is located between the channel region of the compensation transistor T2 and the channel region of the data writing transistor T4.

[0154] For example, in at least one embodiment of this disclosure, the first electrode of the light-emitting element EL is connected to the fourth node N4, and the second electrode of the light-emitting element EL is connected to the second power line VSS. In one example, the light-emitting element EL is an organic light-emitting diode (OLED) comprising a first electrode (anode), an organic light-emitting functional layer, and a second electrode (cathode) stacked together; or in another example, the light-emitting element EL is a quantum dot light-emitting diode (QLED) comprising a first electrode, a quantum dot light-emitting layer, and a second electrode stacked together.

[0155] For example, in at least one embodiment of this disclosure, the power supply voltage signal line VDD is a continuously supplied high-level signal, and the second power supply line VSS is a continuously supplied low-level signal.

[0156] For example, in some embodiments of this disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may be a P-type transistor or an N-type transistor. In other embodiments of this disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may include both P-type and N-type transistors.

[0157] For example, in at least one embodiment of this disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit can be a low-temperature polycrystalline silicon (LTPS) transistor, or a metal-oxide-semiconductor (MODS) transistor, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the MODS transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while MODS transistors have advantages such as low leakage current. Integrating LTPS transistors and MODS transistors onto a single display substrate forms a display substrate using both LTPS and MODS (Low Temperature Polycrystalline + Oxide, LTPO) technology. This leverages the advantages of both technologies to achieve low-frequency driving, thereby reducing power consumption and improving the display quality of the display electrode.

[0158] For example, as shown in Figure 3, the first transistor T1 and the second transistor T2 in the pixel driving circuit can be metal-oxide transistors (N-type transistors), and the third transistor T3 to the ninth transistor T9 can be low-temperature polysilicon transistors (P-type transistors).

[0159] For example, Figure 4 is a driving timing diagram of the pixel driving circuit shown in Figure 3. As shown in Figure 4, the operation of this pixel driving circuit may include:

[0160] The first stage, A1, can be referred to as the reset stage for the second node N2 and the fourth node N4. The signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are low-level signals, while the signals on the second scan signal line S2, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are high-level signals. This causes the seventh transistor T7 and the eighth transistor T8 to conduct, while the other transistors are turned off.

[0161] The seventh transistor T7 is turned on, providing the signal of the second initialization signal line INIT2 to the fourth node N4, initializing (resetting) the first terminal of the light-emitting element EL, clearing the original charge in the first terminal of the light-emitting element EL, and setting the potential of the fourth node N4 to Vinit2. The eighth transistor T8 is turned on, providing the signal of the third initialization signal line INIT3 to the second node N2, initializing (resetting) the second node N2, so that the potential of the second node N2 is Vinit3.

[0162] The second stage, A2, can be called the first node N1 reset stage. The signal on the first scan signal line S1 is a low-level signal. The signal on the second scan signal line S2 appears low-level twice and high-level for the rest of the time. The signals on the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are high-level signals, so that the first transistor T1 is turned on, the fourth transistor T4 and the ninth transistor T9 are turned on twice, and the other transistors are turned off.

[0163] The first transistor T1 is turned on, providing the signal of the first initialization signal line INIT1 to the fifth node N5. When the fourth transistor T4 and the ninth transistor T9 are turned on, the signal of the first initialization signal line INIT1 is provided to the first node N1 to initialize (reset) the first node N1, clearing the original charge in the first node N1. The potential of the first node N1 is Vinit1. Since the ninth transistor T9 is a low-temperature polysilicon transistor, before the ninth transistor T9 is turned on for the first time, it is affected by the potential of the first node N1 and the gate bias voltage. The potential of the first node N1 is related to the data voltage of the previous stage, so the characteristics of the ninth transistor T9 are affected by the previous stage. After the ninth transistor T9 is turned on for the first time, the potential of the first node N1 is reset to Vinit1. The gate voltage of the ninth transistor T9 is relatively fixed whether it is high or low. Therefore, after the first turn-on and turn-off, the influence of the previous stage data on the characteristics of the ninth transistor T9 can be cleared. When the ninth transistor T9 is turned on for the second time, the potential of the first node N1 is reset to Vinit1 again. The embodiments of this disclosure, by resetting the first node N1 twice consecutively, can better eliminate the influence of the data voltage in the previous stage on the characteristics of the ninth transistor T9, thereby improving image retention and low grayscale image quality. Furthermore, due to the two turns on of the fourth transistor T4 in this stage, the data signal line DATA writes the data voltage of the first few cell rows to the second node N2. This changes the potential of the second node N2, thus changing the gate-source voltage of the third transistor T3. The characteristics of the third transistor T3 are reset, which can further improve image retention.

[0164] The third stage, A3, can be called the third node N3 reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light emission control signal line EM1, and the second light emission control signal line EM2 are high-level signals, so that the first transistor T1 and the second transistor T2 are turned on, and the other transistors are turned off.

[0165] The second transistor T2 turns on, causing the third node N3 and the fifth node N5 to turn on. The first transistor T1 turns on, causing the signal of the first initialization signal line INIT1 to be provided to the third node N3, initializing (resetting) the third node N3, clearing the original charge in the third node N3, and making the potential of the third node N3 Vinit1.

[0166] The fourth stage, A4, can be called the data writing stage. The signal on the third scan signal line S3 is a low-level signal, the signal on the second scan signal line S2 is a low-level signal for a short period of time, and the signals on the first scan signal line S1, the fourth scan signal line S4, the fifth scan signal line S5, the first light emission control signal line EM1, and the second light emission control signal line EM2 are high-level signals, which turns on the second transistor T2, the fourth transistor T4, and the ninth transistor T9, while turning off the other transistors.

[0167] The conduction of the second transistor T2 turns on the third node N3 and the fifth node N5, and the conduction of the ninth transistor T9 turns on the first node N1 and the fifth node N5. Since the third transistor T3 remains on during this stage, the fourth transistor T4 turns on, allowing the data signal output from the data signal line DATA to be supplied to the first node N1 via the second node N2, the conducting third transistor T3, the third node N3, the conducting second transistor T2, the fifth node N5, and the conducting ninth transistor T9. The difference between the data voltage output from the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the first node N1 is Vd1 - |Vth|, where Vd is the data voltage output from the data signal line DATA, and Vth is the threshold voltage of the third transistor T3. When the ninth transistor T9 is off, the storage capacitor C maintains the data voltage.

[0168] The fifth stage, A5, can be referred to as the reset stage for the second node N2, the third node N3, and the fourth node N4. The signals on the first scan signal line S1 and the third scan signal line S3 are low-level signals. The signals on the fourth scan signal line S4 and the fifth scan signal line S5 are successively low-level signals for a short period. The signals on the second scan signal line S2, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are high-level signals, turning on the seventh transistor T7 and the eighth transistor T8, while turning off the other transistors.

[0169] The seventh transistor T7 turns on, providing the signal of the second initialization signal line INIT2 to the fourth node N4. Since the third transistor T3 remains on during this stage, the eighth transistor T8 turns on, providing the signal of the third initialization signal line INIT3 to the second node N2 and the third node N3, resetting the second node N2, the third node N3, and the fourth node N4 respectively. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. This stage of resetting the second node N2, the third node N3, and the fourth node N4 can improve and reduce hysteresis deviation caused by grayscale differences between adjacent pixels. It can also periodically reset the OLED anode to improve low-frequency flicker.

[0170] The sixth stage, A6, can be referred to as the reset stage of the second node N2 and the third node N3. The signals of the first scan signal line S1, the third scan signal line S3, and the first light emission control signal line EM1 are low-level signals, while the signals of the second scan signal line S2, the fourth scan signal line S4, the fifth scan signal line S5, and the second light emission control signal line EM2 are high-level signals, turning on the fifth transistor T5 and turning off the other transistors.

[0171] When the fifth transistor T5 is turned on, the power supply voltage Vdd output from the power supply voltage signal line VDD is provided to the second node N2 and the third node N3, resetting the second node N2 and the third node N3, that is, resetting the first and second terminals of the third transistor T3.

[0172] The seventh stage, A7, can be called the light-emitting stage. The signals of the first scan signal line S1, the third scan signal line S3, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are low-level signals, while the signals of the second scan signal line S2, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals, which turns on the fifth transistor T5 and the sixth transistor T6, while turning off the other transistors.

[0173] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power supply voltage output from the power supply voltage signal line VDD provides a driving voltage to the first terminal of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting element EL to emit light.

[0174] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is:

[0175] I = K * (Vgs - Vth) 2=K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0176] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element EL, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0177] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 in each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product, and improving the display effect of the entire display product.

[0178] For example, Figure 5 is another driving timing diagram of the pixel driving circuit shown in Figure 3. The operation process of the pixel driving circuit shown in Figure 5 is basically the same as that of the pixel driving circuit shown in Figure 4, except that: in the first stage A1, the signals of the fourth scan signal line S4 and the fifth scan signal line S5 are high-level signals, the seventh transistor T7 and the eighth transistor T8 are off, and the second node N2 and the fourth node N4 are not reset in this stage. In the fifth stage A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is a low-level signal for a short period of time, the fourth transistor T4 and the ninth transistor T9 are turned on again, the fourth transistor T4 turns on so that the data voltage of the next unit row resets the second node N2 and the third node N3, the ninth transistor T9 turns on so that the first node N1 and the fifth node N5 are turned on, after the charge of the two nodes is neutralized, there is no longer a potential difference between the two nodes.

[0179] For example, the following explanation combines a planar structural diagram of each film layer and a structural diagram of multiple film layers stacked together. It uses a pixel driving circuit that includes a storage capacitor and multiple transistors. The storage capacitor includes a first electrode and a second electrode stacked together. Among the multiple transistors, the first transistor T1 serves as the first initialization transistor, the second transistor T2 as the compensation transistor, the third transistor T3 as the driving transistor, the fourth transistor T4 as the data writing transistor, the fifth transistor T5 as the first light-emitting control transistor, the sixth transistor T6 as the second light-emitting control transistor, the seventh transistor T7 as the second initialization transistor, the eighth transistor T8 as the third initialization transistor, and the ninth transistor T9 as the isolation transistor. Furthermore, the first transistor T1 and the second transistor T2 are metal-oxide transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polycrystalline silicon transistors.

[0180] For example, in the display substrate provided in the embodiments of this disclosure, the display substrate further includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driving circuit and a control signal line, the control signal line being configured to provide a control signal to the pixel driving circuit. For example, FIG6 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of this disclosure. FIG6 shows the pixel driving circuit of the (n-1)th unit row and the pixel driving circuit of the nth unit row, which are arranged sequentially in the second direction Y. In FIG6, the direction intersecting the second direction Y is the first direction X. The structure of the pixel driving circuit of the (n-1)th unit row and the pixel driving circuit of the nth unit row can be referred to the pixel driving circuit structure diagram shown in FIG3 above.

[0181] For example, the pixel driving circuit includes a driving transistor T3, a first control transistor T5 / T8, and a second control transistor T6 / T7. The first control transistor T5 / T8 and the second control transistor T6 / T7 are respectively connected to the driving transistor T3, and the first control transistor T5 / T8 and the second control transistor T6 / T7 connected to the same driving transistor T3 are respectively disposed on both sides of the driving transistor T3 in the column direction. The first control transistor T5 / T8 is electrically connected to the control signal line in the previous cell row, and the second control transistor T6 / T7 is electrically connected to the control signal line in the current cell row. The control signal lines include scan control signal lines. The first control transistor includes a third initialization transistor T8. The second control transistors T6 / T7 include a second initialization transistor T7. The first terminal of the second initialization transistor T7 is connected to the second initialization signal line INT2. The second terminal of the second initialization transistor T7 is connected to the second terminal of the driving transistor T3 through the second light-emitting control transistor T6. The first terminal of the third initialization transistor T8 is connected to the third initialization signal line INT3. The second terminal of the third initialization transistor T8 is connected to the first terminal of the driving transistor T3. The gate electrode of the third initialization transistor T8 is connected to the scan signal line in the previous cell row. The gate electrode of the second initialization transistor T7 is connected to the scan signal line in the current cell row.

[0182] For example, the second initialization transistor T7 and the third initialization transistor T8, which are connected to the same driving transistor T3, are respectively disposed on both sides of the cell column direction of the driving transistor T3.

[0183] For example, in at least one embodiment of this disclosure, the control signal line includes a light-emitting control signal line, the first control transistor includes a first light-emitting control transistor T5, the second control transistor includes a second light-emitting control transistor T6, the first electrode of the first light-emitting control transistor T5 is connected to the power supply voltage signal line, the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T3, and the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T3. For example, the gate electrode of the first light-emitting control transistor T5 is connected to the light-emitting control signal line in the previous cell row, and the gate electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line in the current cell row.

[0184] For example, in at least one embodiment of this disclosure, the second initialization transistor T7 includes a second initialization active layer, and the third initialization transistor T8 includes a third initialization active layer; in at least one pixel driving circuit of at least one cell row, the third initialization active layer is disposed in the circuit cell of the previous cell row, and the second initialization active layer is disposed in the circuit cell of the current cell row.

[0185] For example, in at least one embodiment of this disclosure, in at least one pixel driving circuit of at least one cell row, a third initialization active layer is disposed on one side of the cell row direction of the second initialization active layer of the pixel driving circuit in the previous cell row.

[0186] For example, in at least one embodiment of this disclosure, the first region of the second initialization active layer is connected to the second initialization signal line INIT2 in the current cell row, and the first region of the third initialization active layer is connected to the third initialization signal line INIT2 in the previous cell row.

[0187] For example, as shown in Figure 6, the gate electrode of the fifth transistor T5 in the pixel driving circuit of the nth unit row is connected to the first light emission control signal line EM1 of the same unit row, and the gate electrode of the sixth transistor T6 is connected to the second light emission control signal line EM2 of the same unit row. The second light emission control signal line EM2 of the (n-1)th unit row is interconnected with the first light emission control signal line EM1 of the nth unit row, that is, the second light emission control signal line EM2 of the (n-1)th unit row and the first light emission control signal line EM1 of the nth unit row are the same light emission control signal line, and the sixth transistor T6 of the (n-1)th unit row and the fifth transistor T5 of the nth unit row share the same light emission control signal line. The fourth scan signal line S4 of the (n-1)th unit row is connected to the fifth scan signal line S5 of the nth unit row. That is, the fourth scan signal line S4 of the (n-1)th unit row and the fifth scan signal line S5 of the nth unit row are the same scan signal line. The seventh transistor T7 of the (n-1)th unit row and the eighth transistor T8 of the nth unit row share the same scan signal line, and n is a positive integer greater than 1.

[0188] For example, in at least one embodiment of this disclosure, in at least one pixel driving circuit, a fifth transistor T5 and a sixth transistor T6 connected to the same third transistor T3 can be respectively disposed on both sides of the third transistor T3 in the cell column direction (second direction Y). For example, in a pixel driving circuit of the nth cell row, the fifth transistor T5 can be disposed on the side of the third transistor T3 opposite to the second direction Y, and the sixth transistor T6 can be disposed on the side of the third transistor T3 along the second direction Y.

[0189] For example, in another embodiment of this disclosure, the fourth scan signal line S4 and the fifth scan signal line S5 of each cell row may not use cascaded signals, but may use the same control signal. The fourth scan signal line S4 and the fifth scan signal line S5 of each cell row may be the same control signal. The embodiments of this disclosure do not limit this.

[0190] For example, in another embodiment of this disclosure, the first scan signal line S1 and the third scan signal line S3 of each cell row may be provided by different gate drive circuits, or cascaded signals may be used, and the embodiments of this disclosure do not limit this.

[0191] For example, in at least one embodiment of this disclosure, the fifth transistor T5 includes a fifth active layer, and the sixth transistor T6 includes a sixth active layer. The fifth active layer can serve as the first light-emitting control active layer in an embodiment of this disclosure, and the sixth active layer can serve as the second light-emitting control active layer in an embodiment of this disclosure. In at least one pixel driving circuit of at least one unit row, the fifth active layer can be disposed in the circuit unit of the previous unit row, and the sixth active layer can be disposed in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the fifth active layer can be disposed in the circuit unit of the (n-1)th unit row, and the sixth active layer can be disposed in the circuit unit of the nth unit row.

[0192] For example, in at least one embodiment of this disclosure, in at least one pixel driving circuit of at least one cell row, the fifth active layer may be disposed on one side of the first direction X (cell row direction) of the sixth active layer of the pixel driving circuit in the previous cell row. For example, in a pixel driving circuit of the nth cell row, the fifth active layer may be disposed on one side of the first direction X of the sixth active layer of the pixel driving circuit in the (n-1)th cell row.

[0193] For example, in at least one embodiment of this disclosure, in the pixel driving circuit, the gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5 in the same cell row. In the previous cell row, in at least one pixel driving circuit in at least one cell row, the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4 in the same cell row. For example, the gate electrode of the eighth transistor T8 of the pixel driving circuit in the nth cell row is connected to the fifth scan signal line S5 in the nth cell row, and the gate electrode of the seventh transistor T7 of the pixel driving circuit in the (n-1)th cell row is connected to the fourth scan signal line 24 in the nth cell row. The fourth scan signal line S4 and the fifth scan signal line S5 are connected.

[0194] For example, in at least one embodiment of this disclosure, in a pixel driving circuit, a seventh transistor T7 and an eighth transistor T8 connected to the same third transistor T3 can be respectively disposed on both sides of the third transistor T3 along the second direction Y. For example, in a pixel driving circuit of the nth unit row, the eighth transistor T8 can be disposed on the side opposite to the second direction Y of the third transistor T3, and the seventh transistor T7 can be disposed on the side of the third transistor T3 along the second direction Y.

[0195] For example, in at least one embodiment of this disclosure, the seventh transistor T7 includes a seventh active layer, and the eighth transistor T8 includes an eighth active layer. The seventh transistor T7 can serve as the second initialization active layer in an embodiment of this disclosure, and the eighth active layer can serve as the third initialization active layer in an embodiment of this disclosure. In a pixel driving circuit, the eighth active layer can be disposed in the circuit unit of the previous unit row, and the seventh active layer can be disposed in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the eighth active layer can be disposed in the circuit unit of the (n-1)th unit row, and the seventh active layer can be disposed in the circuit unit of the nth unit row.

[0196] For example, in at least one embodiment of this disclosure, in a pixel driving circuit, the eighth active layer may be disposed on one side of the seventh active layer of the pixel driving circuit in the previous cell row, in the first direction X (cell row direction). For example, in a pixel driving circuit of the nth cell row, the eighth active layer may be disposed on one side of the seventh active layer of the pixel driving circuit in the (n-1)th cell row, in the first direction X.

[0197] For example, in at least one embodiment of this disclosure, in a pixel driving circuit, the first region of the seventh active layer is connected to the second initialization signal line INIT2 in the same cell row, and the first region of the eighth active layer is connected to the third initialization signal line INIT3 in the same cell row. For example, in a pixel driving circuit of the nth cell row, the first region of the seventh active layer is connected to the second initialization signal line INIT2 in the nth cell row, and the first region of the eighth active layer is connected to the third initialization signal line INIT3 in the (n-1)th cell row.

[0198] For example, the following description uses four circuit units arranged in the same row as an example to briefly describe the layer structure of the display substrate in the embodiments of this disclosure.

[0199] It should be noted that in some exemplary embodiments, the corresponding structure can be changed according to actual needs, and the embodiments of this disclosure do not limit this. The structure of the above display substrate is described using the pixel circuit of the above 9T1C as an example. In other exemplary embodiments, the pixel circuit can also be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, etc., and the embodiments of this disclosure do not limit this.

[0200] For example, Figure 7 is a schematic planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 7, the light-shielding layer 201 may be a bottom light-shielding metal (BSM) layer.

[0201] For example, as shown in Figure 7, the pattern of the light-shielding layer includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and a light-shielding electrode 2013, with multiple light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is approximately rectangular, and the corners of the rectangle can be chamfered. The shape of the first light-shielding connecting line 2011 can be a straight line or a broken line extending along the second direction Y. The first light-shielding connecting line 2011 can be respectively disposed on both sides of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013 respectively. The shape of the second light-shielding connecting line 2012 can be a straight line or a broken line extending along the first direction X. The second light-shielding connecting line 2012 can be disposed on both sides of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013 respectively, thereby forming a mesh structure in the pattern of the light-shielding layer.

[0202] For example, as shown in Figure 7, in a cell row, the second light-shielding connection line 2012 in two adjacent circuit cells in the first direction X can be connected to form an interconnected integral structure.

[0203] For example, in other embodiments of this disclosure, the first light-shielding connection lines 2011 in two adjacent circuit units in the second direction Y can be connected in a unit column to form an interconnected integral structure, that is, the light-shielding layers in the unit row and unit column are connected as one unit, thereby ensuring that the light-shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the display of the subsequently formed display panel, so as to avoid display defects of the display panel and ensure the display effect of the display panel.

[0204] For example, forming a pattern for the light-shielding layer includes: depositing a light-shielding layer thin film on a substrate, and patterning the light-shielding layer thin film using a patterning process to form a light-shielding layer pattern. The material of the light-shielding layer can be a light-shielding metal material.

[0205] It should be noted that the "patterning process" mentioned in the embodiments of this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, processes such as depositing a film layer, coating a film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating an organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. The embodiments of this disclosure do not limit this. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In the embodiments of this disclosure, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the main surface of the display substrate. In the embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B, which will not be elaborated further below.

[0206] For example, FIG8 is a schematic planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG8, the first semiconductor layer 202 can form the third active layer 23 of the third transistor T3 to the ninth active layer 29 of the ninth transistor T9.

[0207] For example, as shown in Figure 8, the third active layer 23, the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 are interconnected as a single structure, while the eighth active layer 28 and the ninth active layer 29 are set separately.

[0208] For example, the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor), and the ninth active layer 29 is the channel region of the ninth transistor T9 (isolation transistor).

[0209] For example, Figure 9 is a schematic planar structure of a stacked light-shielding layer and a first semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 9, the orthographic projection of the third active layer 23 on the substrate and the orthographic projection of the light-shielding electrode 2013 on the substrate at least partially overlap. The light-shielding electrode 2013 serves as the light-shielding layer of the third transistor T3, blocking the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0210] For example, in an embodiment of this disclosure, in the pixel driving circuit of this circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the first direction X, and the sixth active layer 26 may be located on the opposite side of the third active layer 23 in the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the second direction Y. The ninth active layer 29 is located on the opposite side of the fourth active layer 24 in the second direction Y.

[0211] For example, as shown in Figures 8 and 9, the third active layer 23 can be in the shape of an inverted "Ω", the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the ninth active layer 29 can be in the shape of a strip extending along the second direction Y of the main body, the seventh active layer 27 can be in the shape of an inverted "L", and the eighth active layer 28 can be in the shape of an "L".

[0212] For example, as shown in Figure 8, the third active layer 23 to the ninth active layer 29 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 25a of the seventh active layer 27, the first region 28a of the eighth active layer 28, the second region 28b of the eighth active layer 28, the first region 29a of the ninth active layer 29, and the second region 29b of the ninth active layer 29 can be set individually.

[0213] For example, as shown in Figure 8, in a cell column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit cell can be set in the circuit cell of the previous cell row, and the third active layer 23, the fourth active layer 24, the sixth active layer 26, the seventh active layer 27 and the ninth active layer 29 can be set in this circuit cell.

[0214] For example, as shown in Figure 8, the fifth active layer 25 of the pixel driving circuit in the current unit row is located on one side of the sixth active layer 26 of the pixel driving circuit in the previous unit row, in the first direction X. This allows the fifth active layer 25 and the sixth active layer 26 of the two unit rows to share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 in the current unit row and the fifth transistor T5 in the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the nth unit row is located in the circuit unit of the (n-1)th unit row, allowing the fifth active layer 25 of the pixel driving circuit in the nth unit row and the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row to share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 in the nth unit row and the sixth transistor T6 in the (n-1)th unit row.

[0215] For example, in at least one embodiment of this disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of this unit row is located on one side of the seventh active layer 28 of the pixel driving circuit in the circuit unit of the previous unit row, such that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of this unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the (n-1)th unit row, such that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of the (n-1)th unit row and the eighth transistor T8 of the nth unit row.

[0216] For example, in at least one embodiment of this disclosure, the first semiconductor layer 202 is formed of polycrystalline silicon (p-Si), i.e., the third transistor T3 to the ninth transistor T9 are LTPS transistors.

[0217] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor thin film, and then patterning the first semiconductor thin film using a patterning process. For example, the process of patterning the first semiconductor thin film using a patterning process includes: first forming an amorphous silicon (a-Si) thin film, performing a dehydrogenation treatment on the amorphous silicon thin film, performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film, and then patterning the polycrystalline silicon thin film to form the pattern of the first semiconductor layer.

[0218] For example, Figure 10 is a schematic planar structure of a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 11 is a schematic planar structure of a stacked light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 10, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scan signal line 2031, a fourth scan signal line 2032, a light emission control signal line 2033, a first initialization signal line 2034, and a first electrode 2035 of a storage capacitor.

[0219] For example, as shown in Figure 11, the first electrode 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode 2035 can simultaneously serve as an electrode of a storage capacitor and the gate electrode of the third transistor T3.

[0220] For example, as shown in Figure 11, the orthographic projection of the first electrode plate 2035 on the substrate overlaps at least partially with the orthographic projection of the light-shielding electrode 2013 on the substrate.

[0221] For example, as shown in Figure 11, the shape of the second scan signal line 2031 is a straight line or a broken line extending along the first direction X of the main body. The second scan signal line 2031 is located on the side opposite to the second direction Y of the first electrode plate 2035. The area where the second scan signal line 2031 overlaps with the fourth active layer 24 can be used as the gate electrode of the fourth transistor T4. The area where the second scan signal line 2031 overlaps with the ninth active layer 29 can be used as the gate electrode of the ninth transistor T9.

[0222] For example, as shown in Figure 11, the fourth scan signal line 2032 is a straight line or a broken line whose main body extends along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode plate 2035 in the second direction Y. The area where the fourth scan signal line 2032 of this unit row overlaps with the seventh active layer 27 of the pixel driving circuit in this unit row serves as the gate electrode of the seventh transistor T7 in this unit row. The area where the fourth scan signal line 2032 of this unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the eighth transistor T8 in the nth unit row.

[0223] For example, as shown in Figure 11, the shape of the light-emitting control signal line 2033 is a straight line or a broken line extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode plate 2035 and the fourth scan signal line 2032. The area where the light-emitting control signal line 2033 of this unit row overlaps with the sixth active layer 26 of the pixel driving circuit in this unit row can be used as the gate electrode of the sixth transistor T6 of this unit row. The area where the light-emitting control signal line 2033 of this unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can be used as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the (n-1)th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row can be used as the gate electrode of the sixth transistor T6 of the (n-1)th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can be used as the gate electrode of the fifth transistor T5 of the nth unit row.

[0224] For example, as shown in Figure 11, the shape of the first initialization signal line 2034 is a straight line or a broken line extending along the first direction X. The first initialization signal line 2034 is located on the side of the second scan signal line 2031 away from the first electrode plate 2035. The first initialization signal line 2031 is configured to be connected to the first region of the first active layer mentioned later.

[0225] For example, as shown in Figure 11, the second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the first initialization signal line 2034 have different widths in the second direction Y. The second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the first initialization signal line 2034 can be arranged to facilitate the layout of the pixel structure, and the parasitic capacitance between the signal lines can be reduced. The embodiments of this disclosure do not limit this.

[0226] For example, as shown in Figure 11, the second scan signal line 2031, the fourth scan signal line 2032, and the light emission control signal line 2033 include regions that overlap with the first semiconductor layer and regions that do not overlap with the first semiconductor layer. The width of the signal line in the region that overlaps with the first semiconductor layer can be greater than the width of the signal line in the region that does not overlap with the first semiconductor layer.

[0227] For example, as shown in Figure 11, after the pattern of the first gate metal layer is formed, the first gate metal layer can be used as a shielding layer to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first gate metal layer forms the channel region of the third transistor T3 to the ninth transistor T9. The first semiconductor layer in the area not shielded by the first gate metal layer is conducted, that is, the first region and the second region of the first electrode 2035, the third active layer 23 to the ninth active layer 29 are all conducted.

[0228] For example, in an embodiment of this disclosure, the process of forming the first gate metal layer includes: depositing a second insulating layer thin film and a first conductive metal thin film sequentially on a substrate on which a light-shielding layer and a first semiconductor layer are formed; patterning the first conductive metal thin film by a patterning process to form a second insulating layer covering the pattern of the first semiconductor layer; and a pattern of the first gate metal layer disposed on the second insulating layer. For example, the first gate metal layer may be referred to as the GATE1 layer.

[0229] For example, in embodiments of this disclosure, the material of the first gate metal layer 203 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate metal layer 203 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0230] For example, Figure 12 is a schematic planar structure of a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 13 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the second gate metal layer can be referred to as the GATE2 layer.

[0231] For example, in at least one embodiment of this disclosure, the pattern of the second gate metal layer 204 of each circuit unit includes: a second electrode 2041 of a storage capacitor, a first shielding line 2042, and a second shielding line 2043.

[0232] For example, as shown in Figures 12 and 13, the outline of the second electrode plate 2041 is rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 2041 on the substrate overlaps at least partially with the orthographic projection of the first electrode plate 2035 on the substrate. The second electrode plate 2041 can serve as another electrode plate of the storage capacitor. The first electrode plate 2035 and the second electrode plate 2041 constitute the storage capacitor of the pixel driving circuit.

[0233] For example, as shown in Figures 12 and 13, the second electrode plate 2041 has an opening 2041a. The opening 2041a can be rectangular in shape and can be located in the middle region of the second electrode plate 2041, making the second electrode plate 2041 form a ring structure. The opening 2041a exposes the third insulating layer covering the first electrode plate 2035, and the orthogonal projection of the first electrode plate 2035 on the substrate covers the orthogonal projection of the opening 2041a on the substrate.

[0234] For example, as shown in Figures 12 and 13, the second electrode plate 2041 includes an electrode plate 2041b. The shape of the electrode plate 2041b can be a strip shape extending along the first direction X.

[0235] For example, as shown in Figures 12 and 13, the shape of the first shielding line 2042 can be a straight line or a broken line extending along the first direction X of the main body. The first shielding line 2042 can be located between the first electrode plate 2035 and the second scan signal line 2031. The first shielding line 2042 is configured as a light shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the second transistor T2.

[0236] For example, as shown in Figures 12 and 13, the shape of the second shielding line 2043 is a straight line or a broken line extending along the first direction X of the main body. The second shielding line 2043 is located between the second scan signal line 2031 and the first initialization signal line 2034. The second shielding line 2043 is configured as a light shielding layer of the first transistor T1, shielding the channel region of the first transistor T1, ensuring the electrical performance of the first transistor T1 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the first transistor T1.

[0237] For example, as shown in Figures 12 and 13, the first blocking line 2042 and the second blocking line 2043 can be designed with non-equal widths, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines.

[0238] For example, the process of forming a pattern of the second gate metal layer includes: depositing a third insulating film and a second conductive metal film sequentially on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer and a first gate metal layer is formed; patterning the second conductive metal film using a patterning process to form a third insulating layer covering the first gate metal layer, and a pattern of the second gate metal layer disposed on the third insulating layer.

[0239] For example, in embodiments of this disclosure, the material of the second gate metal layer 204 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second gate metal layer 204 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0240] For example, Figure 14 is a schematic planar structure of a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. Figure 15 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. For example, a first active layer of a first transistor T1 and a second active layer of a second transistor T2 are disposed on the second semiconductor layer.

[0241] For example, as shown in Figures 14 and 15, the pattern of the second semiconductor layer 205 of each circuit unit includes at least: a first active layer 21 of the first transistor T1 and a second active layer 22 of the second transistor T2.

[0242] For example, as shown in Figures 14 and 15, the first active layer 21 and the second active layer 22 are strip-shaped with the main part extending along the second direction Y. The orthographic projection of the first active layer 21 on the substrate overlaps at least partially with the orthographic projection of the second shielding line 2043 on the substrate. The orthographic projection of the second active layer 22 on the substrate overlaps at least partially with the orthographic projection of the first shielding line 2042 on the substrate.

[0243] For example, as shown in Figures 14 and 15, the first region 21a of the first active layer 21 is located on the side of the second shielding line 2043 away from the second electrode plate 2041, and the second region 22b of the second active layer 22 is located on the side of the first shielding line 2042 close to the second electrode plate 2041. The second region 21b of the first active layer 21 is connected to the first region 22a of the second active layer 22, and the second region 21b of the first active layer 21 serves as the first region 22a of the second active layer 22.

[0244] For example, as shown in Figures 14 and 15, the first active layer 21 and the second active layer 22 are an integral structure that is interconnected.

[0245] For example, as shown in Figure 15, the ninth active layer 29 is located between the second active layer 22 and the fourth active layer 24, that is, the channel region of the ninth transistor T9 is located between the channel region of the second transistor T2 and the channel region of the fourth transistor T4.

[0246] For example, as shown in FIG15, the second semiconductor layer 205 is formed using a metal oxide material, i.e., the first transistor T1 and the second transistor T2 are metal oxide thin film transistors. For example, in an embodiment of this disclosure, the second semiconductor thin film can be formed using a metal oxide material such as indium gallium zinc oxide (IGZO), and the electron mobility of the metal oxide material is higher than that of amorphous silicon.

[0247] For example, the process of forming the pattern of the second semiconductor layer 205 includes: depositing an insulating layer thin film and a second semiconductor thin film sequentially on a substrate on which a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer are formed; patterning the second semiconductor thin film by a patterning process to form an insulating layer covering the substrate and a pattern of the second semiconductor layer disposed on the insulating layer.

[0248] For example, Figure 16 is a schematic planar structure of a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 17 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the third gate metal layer can be referred to as the GATE3 layer.

[0249] For example, as shown in Figures 16 and 17, the pattern of the third gate metal layer 206 of each circuit unit includes at least: a first scan signal line 2061, a third scan signal line 2062, a second initialization signal line 2063, and a third initialization signal line 2064. That is, as shown in Figure 17, the third gate metal layer 206 also includes a third scan signal line 2062 and a first scan signal line 2061 disposed on the side of the third initialization signal line 2064 near the second initialization signal line 2063. The orthographic projection of the first scan signal line 2061 on the substrate overlaps with the orthographic projection of the first blocking line 2042 on the substrate, and the orthographic projection of the third scan signal line 2062 on the substrate overlaps with the orthographic projection of the second blocking line 2043 on the substrate.

[0250] For example, as shown in Figures 16 and 17, the shape of the first scan signal line 2061 is a straight line or a broken line extending along the first direction X. The first scan signal line 2061 is located on the side of the first electrode plate 2035 away from the second scan signal line 2031. The area where the first scan signal line 2061 overlaps with the first active layer 21 can be used as the gate electrode of the first transistor T1.

[0251] For example, as shown in Figures 16 and 17, the orthographic projection of the first scan signal line 2061 on the substrate and the orthographic projection of the first blocking line 2042 on the substrate at least partially overlap. The first scan signal line 2061 and the first blocking line 2042 are connected to the same signal source, so that the first blocking line 2042 serves as the bottom gate electrode of the first transistor T1 and the first scan signal line 2061 serves as the top gate electrode of the first transistor T1, thereby forming a dual-gate structure first transistor T1.

[0252] For example, as shown in Figures 16 and 17, the shape of the third scan signal line 2062 is a straight line or a broken line extending along the first direction X. The third scan signal line 2062 is located on the side of the second scan signal line 2031 away from the first scan signal line 2061. The area where the third scan signal line 2062 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0253] For example, as shown in Figures 16 and 17, the orthographic projection of the third scan signal line 2062 on the substrate and the orthographic projection of the second blocking line 2043 on the substrate at least partially overlap. The third scan signal line 2062 and the second blocking line 2043 can be connected to the same signal source, so that the second blocking line 2043 serves as the bottom gate electrode of the second transistor T2 and the third scan signal line 2062 serves as the top gate electrode of the second transistor T2, thereby forming a dual-gate structure second transistor T2.

[0254] For example, as shown in Figures 16 and 17, the shape of the second initialization signal line 2063 is a straight line or a broken line extending along the first direction X. The second initialization signal line 2063 is located on the side of the third scan signal line 2062 away from the second electrode plate 2041. The second initialization signal line 2063 of this cell row is configured to be connected to the first region 27a of the seventh active layer 27 of the pixel driving circuit in the circuit unit of this cell row.

[0255] For example, as shown in Figure 17, the orthographic projection of the third initialization signal line 2064 on the substrate and the orthographic projection of the fourth scan signal line 2032 on the substrate overlap at least partially, so that the third initialization signal line 2064 with a constant potential can effectively shield the influence of the voltage jump of the fourth scan signal line 2032 on the pixel driving circuit.

[0256] For example, as shown in Figure 17, the second initialization signal line 2063 is a straight line or a broken line whose main body extends along the first direction X. The second initialization signal line 2063 is located between the second electrode plate 2041 and the third initialization signal line 2064. The third initialization signal line 2064 of this unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the next unit row. For example, the third initialization signal line 2064 of the (n-1)th unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the nth unit row.

[0257] For example, in an embodiment of this disclosure, the process of forming the pattern of the third gate metal layer 206 includes: depositing an insulating layer thin film and a third gate metal thin film sequentially on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer and a second semiconductor layer is formed; and performing a patterning process on the third gate metal thin film to form an insulating layer covering the second semiconductor layer and a pattern of the third gate metal layer disposed on the insulating layer.

[0258] For example, in embodiments of this disclosure, the material of the third gate metal layer 206 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third gate metal layer 206 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0259] For example, as shown in Figures 16 and 17, the third gate metal layer 206 is disposed between the first conductive metal layer and the first gate metal layer 203 (mentioned later), and is also disposed on the side of the first conductive metal layer (mentioned later) away from the second conductive metal layer.

[0260] For example, Figure 18 is a schematic planar structure of an interlayer insulating layer in a display substrate according to at least one embodiment of the present disclosure. Figure 19 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate according to at least one embodiment of the present disclosure.

[0261] For example, as shown in Figures 18 and 19, a plurality of first-type via structures are provided in the interlayer insulating layer 207, and the first conductive metal layer and the first semiconductor layer 202 involved thereafter are electrically connected through the first-type via structures.

[0262] It should be noted that although the term "interlayer insulating layer" is used to represent multiple type-1 via structures, it actually represents a portion of a via structure that passes through multiple insulating layers disposed between adjacent layers in the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the materials of the insulating layers between the adjacent layers and the interlayer insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and the insulating layers and interlayer insulating layers can be single-layer, multi-layer, or composite layer structures.

[0263] For example, as shown in Figure 18, the multiple first-type via structures in each circuit unit include at least the following: first-type fourth via structure V74, first-type fifth via structure V75, first-type sixth via structure V76, first-type seventh via structure V77, first-type eighth via structure V78, first-type ninth via structure V79, first-type tenth via structure V710, first-type eleventh via structure V711, first-type twelfth via structure V712, first-type thirteenth via structure V713, first-type fourteenth via structure V714, first-type fifteenth via structure V715, first-type sixteenth via structure V716, and first-type seventeenth via structure V717.

[0264] For example, as shown in Figures 18 and 19, the orthographic projection of the first type fourth via structure V74 on the substrate is located within the range of the orthographic projection of the first region of the third active layer (that is, the second region of the fourth active layer) on the substrate. The first type fourth via structure V74 exposes the surface of the first region of the third active layer (that is, the second region of the fourth active layer). The first type fourth via structure V74 is configured to connect the subsequently formed first conductive metal layer to the first region of the third active layer (that is, the second region of the fourth active layer).

[0265] For example, as shown in Figures 18 and 19, the orthographic projection of the first type fifth via structure V75 on the substrate is located within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) on the substrate. The first type fifth via structure V75 exposes the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The first type fifth via structure V75 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the third active layer (which is also the first region of the sixth active layer).

[0266] For example, as shown in Figures 18 and 19, the orthographic projection of the first type of sixth via structure V76 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate. The first type of sixth via structure V76 exposes the surface of the first region of the fourth active layer. The first type of sixth via structure V76 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the fourth active layer.

[0267] For example, as shown in Figures 18 and 19, the orthographic projection of the first type seventh via structure V77 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate. The first type seventh via structure V77 exposes the surface of the first region of the fifth active layer. The first type seventh via structure V77 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the fifth active layer.

[0268] For example, as shown in Figures 18 and 19, the pixel driving circuits of two adjacent circuit units in the first direction X can share a first type seventh via structure V77.

[0269] For example, as shown in Figures 18 and 19, the orthographic projection of the first type eighth via structure V78 on the main surface of the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the main surface of the substrate. The first type eighth via structure V78 exposes the surface of the second region of the fifth active layer. The first type eighth via structure V78 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the fifth active layer.

[0270] For example, as shown in Figures 18 and 19, the orthographic projection of the first type ninth via structure V79 on the main surface of the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) on the main surface of the substrate. The first type ninth via structure V79 exposes the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The first type ninth via structure V79 is configured to connect the subsequently formed first conductive metal layer to the second region of the sixth active layer (which is also the second region of the seventh active layer).

[0271] For example, as shown in Figures 18 and 19, the orthographic projection of the first type tenth via structure V710 on the main surface of the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the main surface of the substrate. The first type tenth via structure V710 exposes the surface of the first region of the seventh active layer. The first type tenth via structure V710 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the seventh active layer.

[0272] For example, as shown in Figures 18 and 19, the orthographic projection of the first type eleventh via structure V711 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate. The first type eleventh via structure V711 exposes the surface of the first region of the eighth active layer. The first type eleventh via structure V711 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the eighth active layer.

[0273] For example, as shown in Figures 18 and 19, the orthographic projection of the first type twelfth via structure V712 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate. The first type twelfth via structure V712 exposes the surface of the second region of the eighth active layer. The first type twelfth via structure V712 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the eighth active layer.

[0274] For example, as shown in Figures 18 and 19, the orthographic projection of the first type thirteenth via structure V713 on the substrate is within the range of the orthographic projection of the first region of the ninth active layer on the substrate. The first type thirteenth via structure V713 exposes the surface of the first region of the ninth active layer. The first type thirteenth via structure V713 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the ninth active layer.

[0275] For example, as shown in Figures 18 and 19, the orthographic projection of the first type fourteenth via structure V714 on the substrate is within the range of the orthographic projection of the second region of the ninth active layer on the substrate. The first type fourteenth via structure V714 exposes the surface of the second region of the ninth active layer. The first type fourteenth via structure V714 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the ninth active layer.

[0276] For example, as shown in Figures 18 and 19, the orthographic projection of the first type fifteenth via structure V715 on the substrate is within the range of the orthographic projection of the opening 2041a on the substrate. The first type fifteenth via structure V715 exposes the surface of the first electrode plate 2035. The first type fifteenth via structure V715 is configured to connect the structure in the subsequently formed first conductive metal layer to the first electrode plate 2035.

[0277] For example, as shown in Figures 18 and 19, the orthographic projection of the first type sixteenth via structure V716 on the substrate is within the range of the orthographic projection of the second electrode plate 2041 on the substrate. The first type sixteenth via structure V716 exposes the surface of the second electrode plate 2041. The first type sixteenth via structure V716 is configured to connect the structure in the subsequently formed first conductive metal layer to the second electrode plate 2041.

[0278] For example, as shown in Figures 18 and 19, the orthographic projection of the first type seventeenth via structure V717 on the substrate is within the range of the orthographic projection of the first initialization signal line 2034 on the substrate. The first type seventeenth via structure V717 exposes the surface of the first initialization signal line 2034. The first type seventeenth via structure V717 is configured to connect the structure in the subsequently formed first conductive metal layer to the first initialization signal line 2034.

[0279] For example, Figure 20 is a schematic planar structure of an etch barrier layer in a display substrate according to at least one embodiment of the present disclosure. Figure 21 is a schematic planar structure of a stack of light-shielding layer, first semiconductor layer, first gate metal layer, second gate metal layer, second semiconductor layer, third gate metal layer, and interlayer insulating layer / etch barrier layer in a display substrate according to at least one embodiment of the present disclosure.

[0280] For example, as shown in Figures 20 and 21, the etch barrier layer 208 is provided with a plurality of second-type via structures, and the first conductive metal layer and the second semiconductor layer 205 involved thereafter are electrically connected through the second-type via structures.

[0281] It should be noted that although etch stop layers are used to represent multiple second-type via structures, the etch stop layer actually represents another portion of the via structure that passes through the insulating layer disposed between adjacent layers in the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the materials of the insulating layer and the etch stop layer between the adjacent layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and the insulating layer and the etch stop layer can be a single-layer, multi-layer, or composite layer structure. For example, the interlayer insulating layer and the etch stop layer can be disposed in the same layer.

[0282] For example, as shown in Figures 20 and 21, the multiple second-type via structures in each circuit unit include: second-type first via structure V81, second-type second via structure V82, second-type third via structure V83, second-type eighteenth via structure V818, and second-type nineteenth via structure V819.

[0283] For example, as shown in Figures 19, 20 and 21, the orthographic projection of the second type of first via structure V81 on the substrate is within the range of the orthographic projection of the first region of the first active layer on the substrate. The second type of first via structure V81 exposes the surface of the first region of the first active layer. The second type of first via structure V81 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the first active layer.

[0284] For example, as shown in Figures 19, 20 and 21, the orthographic projection of the second type of second via structure V82 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) on the substrate. The second type of second via structure V82 exposes the surface of the second region of the first active layer (which is also the first region of the second active layer). The second type of second via structure V82 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the first active layer (which is also the first region of the second active layer).

[0285] For example, as shown in Figures 19, 20 and 21, the orthographic projection of the second type third via structure V83 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate. The second type third via structure V83 exposes the surface of the second region of the second active layer. The second type third via structure V83 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the second active layer.

[0286] For example, as shown in Figures 19, 20 and 21, the orthographic projection of the second type eighteenth via structure V818 on the substrate is within the range of the orthographic projection of the second initialization signal line 2063 on the substrate. The second type eighteenth via structure V818 exposes the surface of the second initialization signal line 2063. The second type eighteenth via structure V818 is configured to connect the structure in the subsequently formed first conductive metal layer to the second initialization signal line 2063.

[0287] For example, as shown in Figures 19, 20 and 21, the orthographic projection of the second type nineteenth via structure V819 on the substrate is within the range of the orthographic projection of the third initialization signal line 2064 on the substrate. The second type nineteenth via structure V819 exposes the surface of the third initialization signal line 2064. The second type nineteenth via structure V819 is configured to connect the structure in the subsequently formed first conductive metal layer to the third initialization signal line 2064.

[0288] For example, Figure 22 is a schematic planar structure of a first conductive metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 23 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, and a first conductive metal layer in a display substrate according to at least one embodiment of the present disclosure.

[0289] For example, as shown in Figures 22 and 23, the first conductive metal layer 209 of each circuit unit can be referred to as the first source-drain metal (SD1) layer. The first conductive metal layer 209 of each circuit unit includes at least: a first connection electrode 91, a second connection electrode 92, a third connection electrode 93, a fourth connection electrode 94, a fifth connection electrode 95, a sixth connection electrode 96, a seventh connection electrode 97, an eighth connection electrode 98, a ninth connection electrode 99, a tenth connection electrode 910, and an eleventh connection electrode 911. The first source-drain metal layer also includes a first data fan-out line 51, a first connection structure 56, a second connection structure 57, and a third connection structure 55.

[0290] For example, in embodiments of this disclosure, the material of the first conductive metal layer 209 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first conductive metal layer 209 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The first conductive metal layer 209 can also be a multilayer alloy structure, such as a multilayer TiAlTi structure.

[0291] For example, as shown in Figures 22 and 23, the first end of the first connecting electrode 91 is connected to the second region of the ninth active layer through a fourteenth via structure V714 of the first type. The second end of the first connecting electrode 91 extends along the second direction Y and is connected to the first electrode plate 2035 through a fifteenth via structure V715 of the first type. For example, since the first electrode plate 2035 also serves as the gate electrode of the third transistor T3, the first connecting electrode 91 makes the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first electrode plate 2035 have the same potential to form the first node N1 in the pixel driving circuit.

[0292] For example, as shown in Figures 22 and 23, the second connecting electrode 92 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 92 is connected to the second region of the second active layer through a second type third via structure V83. After the second end of the second connecting electrode 92 extends along the second direction Y, it is connected to the second region of the third active layer (which is also the first region of the sixth active layer) through a first type fifth via structure V75. For example, the second connecting electrode 92 makes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential, forming the third node N3 of the pixel driving circuit.

[0293] For example, as shown in Figures 22 and 23, the third connecting electrode 93 is in the shape of a block and is connected to the first region of the fourth active layer through the first type of sixth via structure V76. The third connecting electrode 93 is configured to be connected to the data signal line formed subsequently.

[0294] For example, as shown in Figures 22 and 23, the first end of the fourth connecting electrode 94 is connected to the first region of the fifth active layer through the first type of seventh via structure V77.

[0295] For example, as shown in Figures 22 and 23, the fourth connection electrodes 94 of two adjacent circuit units in the first direction X are interconnected as an integral structure, and are connected to the first region of the fifth active layer of the two circuit units through a shared first type seventh via structure V77.

[0296] For example, as shown in Figures 22 and 23, since the fifth active layer of the pixel driving circuit in this unit row is located in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 94 in this unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 94 is connected to the second electrode plate 2041 of the pixel driving circuit in this unit row. For example, the first end of the fourth connecting electrode 94 in the (n-1)th unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the nth unit row, and the second end is connected to the second electrode plate 2041 of the pixel driving circuit in the (n-1)th unit row.

[0297] For example, as shown in Figures 22 and 23, the fifth connecting electrode 95 is shaped like a strip extending along the second direction Y. The first end of the fifth connecting electrode 95 is connected to the second region of the fifth active layer via a first-type eighth via structure V78. The second end of the fifth connecting electrode 95 extends along the second direction Y and is then connected to the second region of the eighth active layer via a first-type eleventh via structure V711. For example, the fifth connecting electrode 95 causes the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3 to have the same potential, forming the second node N2 of the pixel driving circuit. In an exemplary embodiment, the fifth connecting electrode 95 can serve as the second node electrode in an embodiment of this disclosure.

[0298] For example, as shown in Figures 22 and 23, the sixth connecting electrode 96 is elongated and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a first-type ninth via structure V79. For example, the sixth connecting electrode 96 is configured to connect to the subsequently formed anode connecting electrode to form the fourth node N4 of the pixel driving circuit.

[0299] For example, as shown in Figures 22 and 23, the seventh connecting electrode 97 is a strip shape in which the main body extends along the first direction X. The first end of the seventh connecting electrode 97 is connected to the first region of the first active layer through a second type of first via structure V81, and the second end of the seventh connecting electrode 97 is connected to the first initialization signal line 2034 through a first type of seventeenth via structure V717. For example, the seventh connecting electrode 97 realizes the connection between the first initialization signal line 2034 and the first electrode of the first transistor T1, and the first initialization signal line 2034 can write the transmitted first initial signal into the first electrode of the first transistor T1.

[0300] For example, as shown in Figures 22 and 23, the eighth connecting electrode 98 is a strip shape in which the main body extends along the second direction Y. The first end of the eighth connecting electrode 98 is connected to the first region of the seventh active layer through a first type tenth via structure V710, and the second end of the eighth connecting electrode 98 is connected to the second initialization signal line 2063 through a second type eighteenth via structure V818. For example, the eighth connecting electrode 98 realizes the connection between the second initialization signal line 2063 and the first terminal of the seventh transistor T7, and the second initialization signal line 2063 can write the transmitted second initial signal into the first terminal of the seventh transistor T7.

[0301] For example, as shown in Figures 22 and 23, the ninth connecting electrode 99 is a strip shape in which the main body extends along the second direction Y, and the ninth connecting electrode 99 is connected to the third initialization signal line 2064 through the second type nineteenth via structure V819.

[0302] For example, as shown in Figures 22 and 23, since the eighth active layer of the pixel driving circuit in this unit row is located in the circuit unit of the previous unit row, the first end of the ninth connecting electrode 99 in this unit row is connected to the first region of the eighth active layer of the pixel driving circuit in the next unit row, and the second end of the ninth connecting electrode 99 is connected to the third initialization signal line 2064 in this unit row. For example, for the ninth connecting electrode 99 in the (n-1)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the nth unit row, and its second end is connected to the third initialization signal line 2064 in the (n-1)th unit row.

[0303] For example, as shown in Figures 22 and 23, the tenth connecting electrode 910 is shaped like a strip extending along the second direction Y. The first end of the tenth connecting electrode 910 is connected to the second region of the first active layer (which is also the first region of the second active layer) through a second type of second via structure V82. The second end of the tenth connecting electrode 910 is connected to the first region of the ninth active layer through a first type of thirteenth via structure V713. For example, the tenth connecting electrode 910 connects the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9, forming the fifth node N5 of the pixel driving circuit.

[0304] For example, as shown in Figures 22 and 23, the third connection structure 55 can serve as a first initialization signal adapter. The initialization signal connection line and the first initialization signal line 2034, which are subsequently disposed on the second conductive metal layer 212, are electrically connected through this first initialization signal adapter 55.

[0305] For example, as shown in Figures 22 and 23, the first conductive metal layer 209 also includes a second initialization signal adapter 913. The initialization signal connection line and the second initialization signal line 2063, which are subsequently disposed on the second conductive metal layer 212, are electrically connected through the second initialization signal adapter 913.

[0306] For example, the initialization signal connection line is also electrically connected to the third initialization signal line 2064, thereby making the initialization signal connection line electrically connected to the first initialization signal line 2034, the second initialization signal line 2063 and the third initialization signal line 2064 to form a mesh initialization signal structure.

[0307] For example, as shown in Figures 22 and 23, the orthographic projection of the first data fan-out line 51 on the substrate and the orthographic projections of the first initialization signal line 2034 and the second initialization signal line 2063 on the substrate are all spaced apart from each other.

[0308] For example, as shown in Figures 22 and 23, the first data fan-out line 51 covers the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8. The orthographic projection of the first data fan-out line 51 on the substrate overlaps with the orthographic projection of the third initialization signal line 2064 on the substrate. Therefore, the third initialization signal line 2064 can be used to shield the first data fan-out line 51. This routing method avoids the overlap of the first data fan-out line 51 with the first scan signal line, the light emission control signal line, the first initialization signal line, etc., and can reduce the impact of signal transitions on the data signal on these signal lines. Although this routing method has the phenomenon of overlap between the third initialization signal line 2064 and the first data fan-out line 51, the third initialization signal line 2064 is used to shield the first data fan-out line 51, thereby minimizing the impact of signal transitions on the third initialization signal line 2064 on the data signal.

[0309] For example, as shown in Figure 23, the fourth scan signal line 2032, which is also the first reset control signal line, overlaps with the orthographic projection of the first data fan-out line 51 on the substrate, the orthographic projection of the third initialization signal line 2064 on the substrate, and the first reset control signal line 2032.

[0310] For example, as shown in Figure 23, the orthographic projections of the second plate 2041, the first shielding line 2042, and the second shielding line 2043 of the storage capacitor on the substrate are all spaced apart from the orthographic projection of the first data fan-out line 51 on the substrate, thereby avoiding the influence of the first shielding line 2042 and the second shielding line 2043 on the data signal transition.

[0311] For example, Figure 24 is a schematic planar structure of a passivation layer in a display substrate according to at least one embodiment of the present disclosure. Figure 25 is a schematic planar structure of a first planarization layer in a display substrate according to at least one embodiment of the present disclosure. Figure 26 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate according to at least one embodiment of the present disclosure.

[0312] For example, as shown in Figures 24 and 25, multiple third-type via structures are provided in the passivation layer 210 and the first planarization layer 211, and the second conductive metal layer and the first conductive metal layer involved thereafter are electrically connected through the third-type via structures.

[0313] For example, as shown in Figures 24-26, the multiple third-type via structures in each circuit unit include: the second-twentieth type via structure V922, the twenty-third type via structure V923, the twenty-fourth type via structure V924, the twenty-fifth type via structure V925, the twenty-sixth type via structure V926, and the twenty-eighth type via structure V928.

[0314] For example, as shown in Figures 24-26, the orthographic projection of the third type twenty-two via structure V922 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 94 on the substrate. The passivation layer and the first planarization layer in the third type twenty-two via structure V922 are etched away, exposing the surface of the fourth connection electrode 94. The third type twenty-two via structure V922 is configured to connect the subsequently formed power supply voltage signal line to the fourth connection electrode 94.

[0315] For example, as shown in Figures 24-26, the orthographic projection of the third type twenty-third via structure V923 on the substrate is located within the range of the orthographic projection of the third connection electrode 93 on the substrate. The passivation layer and the first planarization layer in the third type twenty-third via structure V923 are etched away, exposing the surface of the third connection electrode 93. The third type twenty-third via structure V923 is configured to connect the subsequently formed data signal line to the third connection electrode 93.

[0316] For example, as shown in Figures 24-26, the orthogonal projections of the third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 on the substrate are located within the range of the orthogonal projection of the eleventh connecting electrode 911 on the substrate. The passivation layer and the first planarization layer in the third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 are etched away, exposing the surface of the eleventh connecting electrode 911. The third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 are configured to connect the subsequently formed second conductive metal layer to the eleventh connecting electrode 911.

[0317] For example, as shown in Figures 24-26, the orthographic projection of the third type twenty-sixth via structure V926 on the substrate is within the range of the orthographic projection of the twelfth connecting electrode 912 on the substrate. The passivation layer and the first planarization layer in the third type twenty-sixth via structure V926 are etched away, exposing the surface of the twelfth connecting electrode 912. The third type twenty-sixth via structure V926 is configured to connect the subsequently formed second conductive metal layer to the twelfth connecting electrode 912.

[0318] For example, as shown in Figures 24-26, the orthographic projection of the third type twenty-eighth via structure V928 on the substrate is within the range of the orthographic projection of the sixth connection electrode 96 on the substrate. The passivation layer and the first planarization layer in the third type twenty-eighth via structure V928 are etched away, exposing the surface of the sixth connection electrode 96. The third type twenty-eighth via structure V928 is configured to connect the subsequently formed anode connection electrode to the sixth connection electrode 96.

[0319] For example, the process of forming the passivation layer and the first planarization layer pattern includes: coating a passivation layer film and a first planarization layer film on a substrate having a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer and a first conductive metal layer; patterning the passivation layer film and the first planarization layer film using a patterning process to form a passivation layer and a first planarization layer that cover the pattern of the first conductive metal layer; and providing a plurality of third-type via structures on the passivation layer and the first planarization layer.

[0320] For example, the first planarization layer can be formed using an organic material, such as a resin. The passivation layer can be formed using an inorganic insulating material, such as silicon nitride, silicon oxynitride, or silicon dioxide.

[0321] For example, Figure 27 is a schematic planar structure of a second conductive metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 28 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate according to at least one embodiment of the present disclosure.

[0322] For example, as shown in Figures 27 and 28, the second conductive metal layer 212 of each circuit unit includes: a power supply voltage signal line 212a, a data signal line 212b, an anode connection electrode 212c, an initialization signal connection line 212d, and a second data fan-out line 212e. The second conductive metal layer 212 can serve as a second source-drain metal (SD2) layer.

[0323] For example, as shown in Figures 27 and 28, the power supply voltage signal line 212a is a straight line or a broken line whose main body extends along the second direction Y. The power supply voltage signal line 212a is connected to the fourth connection electrode 94 through the third type of twenty-second via structure V922. The fourth connection electrode 94 is connected to the first electrode of the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor, respectively. Thus, the power supply voltage signal line 212a writes the first power signal into the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor.

[0324] For example, as shown in Figures 27 and 28, the power supply voltage signal line 212a can be a non-uniform width polygonal line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the power supply voltage signal line and the data signal line.

[0325] For example, as shown in Figures 27 and 28, the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. This allows the power supply voltage signal line 212a to block the first and second active layers, thus preventing the light emitted by the light-emitting element and the reflected light from the film layer from illuminating the first and second oxide transistors T1 and T2. This prevents the oxide transistors from experiencing characteristic drift due to light exposure and improves the electrical characteristics of the oxide transistors.

[0326] For example, as shown in Figures 27 and 28, the orthographic projection of the power supply voltage signal line 212a on the substrate overlaps at least partially with the orthographic projection of the first connecting electrode 91 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node N1, and improve the driving performance of the pixel driving circuit.

[0327] For example, as shown in Figures 27 and 28, the orthographic projection of the power supply voltage signal line 212a on the substrate overlaps at least partially with the orthographic projections of the second connecting electrode 92 and the tenth connecting electrode 910 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on each node in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the node potential, and improve the driving performance of the pixel driving circuit.

[0328] For example, as shown in Figures 27 and 28, the data signal line 212b can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 212b is connected to the third connection electrode 93 through a third type twenty-third via structure V923. Since the third connection electrode 93 is connected to the first region of the fourth active layer through the via, the connection between the data signal line 212b and the first electrode of the fourth transistor T4 is realized, and the data signal line 212b can write data signals to the first electrode of the fourth transistor T4.

[0329] For example, as shown in Figures 27 and 28, the anode connecting electrode 212c is elongated and connected to the sixth connecting electrode 96 via a third type twenty-eighth via structure V928. The anode connecting electrode 212c is configured to connect with the subsequently formed anode. Since the sixth connecting electrode 96 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequent anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting element to emit light.

[0330] For example, the process of forming the second conductive metal layer includes: depositing a second conductive metal thin film on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer is formed; and patterning the second conductive metal thin film using a patterning process to form a second conductive metal layer disposed on the first planarization layer.

[0331] For example, the material of the second conductive metal layer 212 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second conductive metal layer 212 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The second conductive metal layer 212 can also be a multilayer alloy structure, such as a multilayer TiAlTi structure.

[0332] For example, as shown in Figures 27 and 28, the initialization signal connection line 212d is electrically connected to the first initialization signal adapter line 55 through a second via structure V926 disposed in the first insulating layer, and is also electrically connected to the second initialization signal adapter line 913 disposed in another second via structure V926 disposed in the first insulating layer. For example, the first insulating layer includes a passivation layer and a first planarization layer, and the second via structure is a hole structure that penetrates the passivation layer and the first planarization layer. For example, in the second direction Y, the second via structure V926 and the first via structure V928 mentioned later are respectively disposed on both sides of the first data fan-out line 51. This can increase the distance between the first via structure V928 and the second via structure V926, thereby reducing the length of the connection between the first initialization signal line and the second initialization signal line accessing the network, which is beneficial to reducing the load on the first initialization signal line and the second initialization signal line. Furthermore, due to the downward shift of the position of the first via structure, the first via structure corresponding to the N4 node can be moved outward, increasing the distance between the first via structure and the corresponding anode, thereby improving the flatness of the anode in the corresponding sub-pixel.

[0333] For example, as shown in Figures 27 and 28, the second data fan-out line 212e is disposed between two adjacent data signal lines 212b.

[0334] For example, as shown in Figures 27 and 28, the two adjacent initialization signal connection lines 212d, the two adjacent anode connection electrodes 212c, the two adjacent power supply voltage signal lines 212a, and the two adjacent data signal lines 212b are all axially symmetrical about the second data fan-out line 212e.

[0335] For example, Figure 29 is a schematic planar structure of a second planarization layer in a display substrate according to at least one embodiment of the present disclosure. Figure 30 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate according to at least one embodiment of the present disclosure.

[0336] For example, as shown in Figures 29 and 30, a second planarization layer 213 is disposed on the entire substrate. The second planarization layer 213 has a plurality of fourth-type via structures 213a / 213b / 213c / 213d, which expose the anode connection electrode. These plurality of fourth-type via structures 213a / 213b / 213c / 213d can enable the subsequent anode to be connected to the anode connection electrode in the second conductive metal layer.

[0337] For example, the second planarization layer can be formed using organic materials, such as resins.

[0338] For example, the fourth type of via structure 213a / 213b / 213c / 213d can be used as an anode connection hole, the first insulating layer includes the second planarization layer 212 mentioned above, and the fourth type of via structure 213a / 213b / 213c / 213d is disposed in the second planarization layer 212.

[0339] For example, Figure 31 is a schematic planar structure of an anode layer in a display substrate according to at least one embodiment of the present disclosure. Figure 32 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer in a display substrate according to at least one embodiment of the present disclosure.

[0340] For example, as shown in Figures 31 and 32, an anode layer 214 is disposed on the second planarization layer 213. This anode layer 214 includes multiple anode electrodes 214a / 214b / 214c / 214d. Anode electrode 214a can be an electrode corresponding to the first sub-pixel P1, anode electrode 214b can be an electrode corresponding to the second sub-pixel P2, anode electrode 214c can be an electrode corresponding to the third sub-pixel P3, and anode electrode 214d can be an electrode corresponding to the fourth sub-pixel P4. Anode electrodes 214a, 214b, 214c, and 214d are respectively connected to the anode connection electrode in the second conductive metal layer through fourth-type via structures 213a, 213b, 213c, and 213d.

[0341] For example, in one example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 are green sub-pixels (G) that emit green light, and the third sub-pixel P3 is a blue sub-pixel (B) that emits blue light. The embodiments of this disclosure are not limited in this respect.

[0342] For example, referring to Figures 2 to 32, the display substrate includes: a substrate 101, a driving circuit layer 102 on the substrate 101, the driving circuit layer 102 including a pixel driving circuit, and a plurality of light-emitting elements disposed on the side of the pixel driving circuit away from the substrate 101; the pixel driving circuit includes a first conductive metal layer 209, a first insulating layer 210 / 211 and a second conductive metal layer 212 stacked thereon, the second conductive metal layer 212 including an initialization signal connection line 212d arranged in the first direction X and an anode connection electrode 212. c and power supply voltage signal line 212a, initialization signal connection line 212d, anode connection electrode 212c and power supply voltage signal line 212a all extend along a second direction Y intersecting the first direction X. The anode connection electrode 212c is electrically connected to the first conductive metal layer 209 through a first via structure disposed in the first insulating layer 210 / 211. Multiple light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and the orthographic projection of the first anode on the substrate 101 and the orthographic projection of the first via structure on the substrate 101 do not overlap. The first via structure is the third type of via structure V928 of the third type of via structure in the first planarization layer in FIG25.

[0343] For example, the first anode can be the anode corresponding to the red sub-pixel. The orthographic projection of the anode corresponding to the red sub-pixel on the substrate 101 and the orthographic projection of the first via structure V928 on the substrate 101 do not overlap. That is, the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the red sub-pixel.

[0344] For example, in one example, multiple light-emitting elements include a second light-emitting element, which includes a second anode. The orthographic projection of the second anode onto the substrate overlaps with the orthographic projection of the first via structure V928 onto the substrate. For example, the second anode may be the anode corresponding to the blue sub-pixel, and the orthographic projection of the anode corresponding to the blue sub-pixel onto the substrate 101 overlaps with the orthographic projection of the first via structure V928 onto the substrate 101, that is, a portion of the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the blue sub-pixel.

[0345] For example, in one instance, the area of ​​the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure V928 on the substrate overlaps by 5% to 20% of the area of ​​the first via structure, that is, the area covered by the second anode on the first via structure V928 does not exceed 1 / 5 of the area of ​​the first via structure V928.

[0346] For example, the second conductive metal layer 212 also includes a second data fan-out line 212e, which extends along the second direction Y and has a break in the middle region. The second data fan-out line 212e is connected at one end of the break through a third type twenty-fourth via structure V924 and an eleventh connection electrode 911, and at the other end of the break through a third type twenty-fifth via structure V925 and an eleventh connection electrode 911.

[0347] Figure 33 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure, and Figure 34 is a driving timing diagram of the pixel driving circuit shown in Figure 33. As shown in Figure 33, the pixel driving circuit is an 8T1C structure, which may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. Each pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and power supply voltage signal line VDD).

[0348] For example, in the embodiments of this disclosure, the connection structure of the first transistor T1 to the eighth transistor T8 and the storage capacitor C in the pixel driving circuit shown in FIG33 is basically the same as the structure in the pixel driving circuit shown in FIG4. The difference is that the pixel driving circuit shown in FIG33 does not have a ninth transistor. Therefore, the first node N1 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the gate electrode of the third transistor T3 and the first terminal of the storage capacitor C, respectively. That is, the second terminal of the first transistor T1 is connected to the first node N1, and the first terminal of the second transistor T2 is connected to the first node N1.

[0349] For example, as shown in FIG33, in an embodiment of the present disclosure, the first transistor T1 and the second transistor T2 in the pixel driving circuit can be oxide transistors (N-type transistors), and the third transistor T3 to the eighth transistor T8 can be low-temperature polysilicon transistors (P-type transistors).

[0350] For example, Figure 34 is a timing diagram of the pixel driving circuit shown in Figure 33. The operation of the pixel driving circuit shown in Figure 34 is basically the same as that of the pixel driving circuit shown in Figure 4. The difference is that in the operation of the pixel driving circuit shown in Figure 34, the second scan signal line S2 in the second stage A2 is a high-level signal, and the first transistor T1 is turned on, so that the signal of the first initial signal line INIT1 is provided to the first node N1 to initialize (reset) the first node N1. In the fifth stage A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is a low-level signal for a short period of time, and the fourth transistor T4 is turned on again. The turning on of the fourth transistor T4 resets the data voltage of the next cell row to the second node N2 and the third node N3.

[0351] For example, as shown in Figure 33, the pixel driving circuit includes a storage capacitor and a plurality of transistors. The storage capacitor may include a first electrode plate and a second electrode plate disposed opposite to each other. The plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. The first transistor T1 and the second transistor T2 are oxide transistors, and the third transistor T3 to the eighth transistor T8 are low-temperature polysilicon transistors.

[0352] For example, Figure 35 is a schematic planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 35, the light-shielding layer 201 may be a bottom light-shielding metal (BSM) layer.

[0353] For example, as shown in Figure 35, the pattern of the light-shielding layer includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and a light-shielding electrode 2013, with multiple light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is approximately rectangular, and the corners of the rectangle can be chamfered. The shape of the first light-shielding connecting line 2011 can be a straight line or a broken line extending along the second direction Y. The first light-shielding connecting line 2011 can be respectively disposed on both sides of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013 respectively. The shape of the second light-shielding connecting line 2012 can be a straight line or a broken line extending along the first direction X. The second light-shielding connecting line 2012 can be disposed on both sides of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013 respectively, thereby forming a mesh structure in the pattern of the light-shielding layer.

[0354] For example, as shown in Figure 35, in a cell row, the second light-shielding connection lines 2012 in two adjacent circuit cells in the first direction X can be connected to form an interconnected integral structure.

[0355] For example, in other embodiments of this disclosure, the first light-shielding connection lines 2011 in two adjacent circuit units in the second direction Y can be connected in a unit column to form an interconnected integral structure, that is, the light-shielding layers in the unit row and unit column are connected as one unit, thereby ensuring that the light-shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the display of the subsequently formed display panel, so as to avoid display defects of the display panel and ensure the display effect of the display panel.

[0356] For example, forming a pattern for the light-shielding layer includes: depositing a light-shielding layer thin film on a substrate, and patterning the light-shielding layer thin film using a patterning process to form a light-shielding layer pattern. The material of the light-shielding layer can be a light-shielding metal material.

[0357] It should be noted that the "patterning process" mentioned in the embodiments of this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, processes such as depositing a film layer, coating a film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating an organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. The embodiments of this disclosure do not limit this. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In the embodiments of this disclosure, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the main surface of the display substrate. In the embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B, which will not be elaborated further below.

[0358] For example, Figure 36 is a schematic planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 36, the first semiconductor layer 202 can form the third active layer 23 of the third transistor T3 to the eighth active layer 28 of the eighth transistor T8.

[0359] For example, as shown in Figure 36, the third active layer 23, the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 are interconnected as a single structure, while the eighth active layer 28 is set separately.

[0360] For example, the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), and the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor).

[0361] For example, Figure 37 is a schematic planar structure of a stacked light-shielding layer and a first semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 37, the orthographic projection of the third active layer 23 on the substrate and the orthographic projection of the light-shielding electrode 2013 on the substrate at least partially overlap. The light-shielding electrode 2013 serves as the light-shielding layer of the third transistor T3, blocking the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0362] For example, in an embodiment of this disclosure, in the pixel driving circuit of this circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the first direction X, and the sixth active layer 26 may be located on the opposite side of the third active layer 23 in the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the second direction Y.

[0363] For example, as shown in Figures 36 and 37, the third active layer 23 can be in the shape of an inverted "Ω", the fourth active layer 24, the fifth active layer 25 and the sixth active layer 26 can be in the shape of a strip extending along the second direction Y of the main body, the seventh active layer 27 can be in the shape of an inverted "L", and the eighth active layer 28 can be in the shape of an "L".

[0364] For example, as shown in Figure 36, the third active layer 23 to the eighth active layer 28 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 25a of the seventh active layer 27, the first region 28a of the eighth active layer 28, and the second region 28b of the eighth active layer 28 can be set individually.

[0365] For example, as shown in Figure 36, in a cell column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit cell can be set in the circuit cell of the previous cell row, and the third active layer 23, the fourth active layer 24, the sixth active layer 26 and the seventh active layer 27 can be set in this circuit cell.

[0366] For example, as shown in Figure 36, the fifth active layer 25 of the pixel driving circuit in the circuit unit of this unit row is located on one side of the first direction X of the sixth active layer 26 of the pixel driving circuit in the circuit unit of the previous unit row, so that the fifth active layer 25 and the sixth active layer 26 of the two unit rows can share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of this unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the (n-1)th unit row, so that the fifth active layer 25 of the pixel driving circuit in the nth unit row and the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row can share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the nth unit row and the sixth transistor T6 of the (n-1)th unit row.

[0367] For example, in at least one embodiment of this disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of this unit row is located on one side of the seventh active layer 28 of the pixel driving circuit in the circuit unit of the previous unit row, such that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of this unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the (n-1)th unit row, such that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of the (n-1)th unit row and the eighth transistor T8 of the nth unit row.

[0368] For example, in at least one embodiment of this disclosure, the first semiconductor layer 202 is formed of polysilicon (p-Si), i.e., the third transistor T3 to the eighth transistor T8 are LTPS transistors.

[0369] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor thin film, and then patterning the first semiconductor thin film using a patterning process. For example, the process of patterning the first semiconductor thin film using a patterning process includes: first forming an amorphous silicon (a-Si) thin film, performing a dehydrogenation treatment on the amorphous silicon thin film, performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film, and then patterning the polycrystalline silicon thin film to form the pattern of the first semiconductor layer.

[0370] For example, Figure 38 is a schematic planar structure of a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 39 is a schematic planar structure of a stacked light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 38, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scan signal line 2031, a fourth scan signal line 3032, a light emission control signal line 2033, a first initialization signal line 2034, and a first electrode 2035 of a storage capacitor.

[0371] For example, as shown in Figure 39, the first electrode 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode 2035 can simultaneously serve as an electrode of a storage capacitor and the gate electrode of the third transistor T3.

[0372] For example, as shown in Figure 39, the orthographic projection of the first electrode plate 2035 on the substrate overlaps at least partially with the orthographic projection of the light-shielding electrode 2013 on the substrate.

[0373] For example, as shown in Figure 39, the shape of the second scan signal line 2031 is a straight line or a broken line extending along the first direction X of the main body. The second scan signal line 2031 is located on the side opposite to the second direction Y of the first electrode plate 2035. The area where the second scan signal line 2031 overlaps with the fourth active layer 24 can serve as the gate electrode of the fourth transistor T4.

[0374] For example, as shown in Figure 39, the fourth scan signal line 2032 is a straight line or a broken line whose main body extends along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode plate 2035 in the second direction Y. The area where the fourth scan signal line 2032 of this unit row overlaps with the seventh active layer 27 of the pixel driving circuit in this unit row serves as the gate electrode of the seventh transistor T7 in this unit row. The area where the fourth scan signal line 2032 of this unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the eighth transistor T8 in the nth unit row.

[0375] For example, as shown in Figure 39, the shape of the light-emitting control signal line 2033 is a straight line or a broken line extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode plate 2035 and the fourth scan signal line 2032. The area where the light-emitting control signal line 2033 of this unit row overlaps with the sixth active layer 26 of the pixel driving circuit in this unit row can be used as the gate electrode of the sixth transistor T6 of this unit row. The area where the light-emitting control signal line 2033 of this unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can be used as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the (n-1)th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row can be used as the gate electrode of the sixth transistor T6 of the (n-1)th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can be used as the gate electrode of the fifth transistor T5 of the nth unit row.

[0376] For example, as shown in FIG39, the shape of the first initialization signal line 2034 is a straight line or a broken line extending along the first direction X of the main body. The first initialization signal line 2034 is located on the side of the second scan signal line 2031 away from the first electrode plate 2035. The first initialization signal line 2031 is configured to be connected to the first region of the first active layer mentioned later.

[0377] For example, as shown in Figure 39, the second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the first initialization signal line 2034 have different widths in the second direction Y. The second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the first initialization signal line 2034 can be arranged to facilitate the layout of the pixel structure and can reduce the parasitic capacitance between the signal lines. The embodiments of this disclosure do not limit this.

[0378] For example, as shown in Figure 39, the second scan signal line 2031, the fourth scan signal line 2032, and the light emission control signal line 2033 include regions that overlap with the first semiconductor layer and regions that do not overlap with the first semiconductor layer. The width of the signal line in the region that overlaps with the first semiconductor layer can be greater than the width of the signal line in the region that does not overlap with the first semiconductor layer.

[0379] For example, as shown in Figure 39, after the pattern of the first gate metal layer is formed, the first gate metal layer can be used as a shielding layer to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first gate metal layer forms the channel region of the third transistor T3 to the eighth transistor T8. The first semiconductor layer in the area not shielded by the first gate metal layer is conducted, that is, the first region and the second region of the first electrode 2035, the third active layer 23 to the eighth active layer 28 are all conducted.

[0380] For example, in an embodiment of this disclosure, the process of forming the first gate metal layer includes: depositing a second insulating layer thin film and a first conductive metal thin film sequentially on a substrate on which a light-shielding layer and a first semiconductor layer are formed; patterning the first conductive metal thin film by a patterning process to form a second insulating layer covering the pattern of the first semiconductor layer; and a pattern of the first gate metal layer disposed on the second insulating layer. For example, the first gate metal layer may be referred to as the GATE1 layer.

[0381] For example, in embodiments of this disclosure, the material of the first gate metal layer 203 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate metal layer 203 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0382] For example, Figure 40 is a schematic planar structure of a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 41 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the second gate metal layer can be referred to as the GATE2 layer.

[0383] For example, in at least one embodiment of this disclosure, the pattern of the second gate metal layer 204 of each circuit unit includes: a second electrode 2041 of a storage capacitor, a first shielding line 2042, and a second shielding line 2043.

[0384] For example, as shown in Figures 40 and 41, the outline of the second electrode plate 2041 is rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 2041 on the substrate overlaps at least partially with the orthographic projection of the first electrode plate 2035 on the substrate. The second electrode plate 2041 can serve as another electrode plate of the storage capacitor. The first electrode plate 2035 and the second electrode plate 2041 constitute the storage capacitor of the pixel driving circuit.

[0385] For example, as shown in Figures 40 and 41, an opening 2041a is provided on the second electrode plate 2041. The opening 2041a can be rectangular in shape and can be located in the middle region of the second electrode plate 2041, so that the second electrode plate 2041 forms a ring structure. The opening 2041a exposes the third insulating layer covering the first electrode plate 2035, and the orthogonal projection of the first electrode plate 2035 on the substrate covers the orthogonal projection of the opening 2041a on the substrate.

[0386] For example, as shown in Figures 40 and 41, the second electrode plate 2041 includes an electrode plate 2041b. The shape of the electrode plate 2041b can be a strip shape extending along the first direction X.

[0387] For example, as shown in Figures 40 and 41, the shape of the first shielding line 2042 can be a straight line or a broken line extending along the first direction X of the main body. The first shielding line 2042 can be located between the first electrode plate 2035 and the second scan signal line 2031. The first shielding line 2042 is configured as a light-shielding layer of the second transistor T2 mentioned later, shielding the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the second transistor T2.

[0388] For example, as shown in Figures 40 and 41, the shape of the second shielding line 2043 is a straight line or a broken line extending along the first direction X of the main body. The second shielding line 2043 is located between the second scan signal line 2031 and the first initialization signal line 2034. The second shielding line 2043 is configured as a light shielding layer of the first transistor T1 mentioned later, shielding the channel region of the first transistor T1, ensuring the electrical performance of the first transistor T1 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the first transistor T1.

[0389] For example, as shown in Figures 40 and 41, the first blocking line 2042 and the second blocking line 2043 can be designed with non-equal widths, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines.

[0390] For example, the process of forming a pattern of the second gate metal layer includes: depositing a third insulating film and a second conductive metal film sequentially on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer and a first gate metal layer is formed; patterning the second conductive metal film using a patterning process to form a third insulating layer covering the first gate metal layer, and a pattern of the second gate metal layer disposed on the third insulating layer.

[0391] For example, in embodiments of this disclosure, the material of the second gate metal layer 204 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second gate metal layer 204 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0392] For example, Figure 42 is a schematic planar structure of a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. Figure 43 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. For example, a first active layer of a first transistor T1 and a second active layer of a second transistor T2 are disposed on the second semiconductor layer.

[0393] For example, as shown in Figures 42 and 43, the pattern of the second semiconductor layer 205 of each circuit unit includes at least: a first active layer 21 of the first transistor T1 and a second active layer 22 of the second transistor T2.

[0394] For example, as shown in Figures 42 and 43, the first active layer 21 and the second active layer 22 are strip-shaped with the main part extending along the second direction Y. The orthographic projection of the first active layer 21 on the substrate overlaps at least partially with the orthographic projection of the second shielding line 2043 on the substrate. The orthographic projection of the second active layer 22 on the substrate overlaps at least partially with the orthographic projection of the first shielding line 2042 on the substrate.

[0395] For example, as shown in Figures 42 and 43, the first region 21a of the first active layer 21 is located on the side of the second shielding line 2043 away from the second electrode plate 2041, and the second region 22b of the second active layer 22 is located on the side of the first shielding line 2042 close to the second electrode plate 2041. The second region 21b of the first active layer 21 is connected to the first region 22a of the second active layer 22, and the second region 21b of the first active layer 21 serves as the first region 22a of the second active layer 22.

[0396] For example, as shown in Figures 42 and 43, the first active layer 21 and the second active layer 22 are an integral structure that is interconnected.

[0397] For example, as shown in FIG43, the second semiconductor layer 205 is formed using a metal oxide material, i.e., the first transistor T1 and the second transistor T2 are metal oxide thin film transistors. For example, in an embodiment of this disclosure, the second semiconductor thin film can be formed using a metal oxide material such as indium gallium zinc oxide (IGZO), and the electron mobility of the metal oxide material is higher than that of amorphous silicon.

[0398] For example, the process of forming the pattern of the second semiconductor layer 205 includes: depositing an insulating layer thin film and a second semiconductor thin film sequentially on a substrate on which a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer are formed; patterning the second semiconductor thin film by a patterning process to form an insulating layer covering the substrate and a pattern of the second semiconductor layer disposed on the insulating layer.

[0399] For example, Figure 44 is a schematic planar structure of a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 45 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the third gate metal layer can be referred to as the GATE3 layer.

[0400] For example, as shown in Figures 44 and 45, the pattern of the third gate metal layer 206 of each circuit unit includes at least: a first scan signal line 2061, a third scan signal line 2062, a second initialization signal line 2063, and a third initialization signal line 2064. That is, as shown in Figure 45, the third gate metal layer 206 also includes a third scan signal line 2062 and a first scan signal line 2061 disposed on the side of the third initialization signal line 2064 near the second initialization signal line 2063. The orthographic projection of the first scan signal line 2061 on the substrate overlaps with the orthographic projection of the first blocking line 2042 on the substrate, and the orthographic projection of the third scan signal line 2062 on the substrate overlaps with the orthographic projection of the second blocking line 2043 on the substrate.

[0401] For example, as shown in Figures 44 and 45, the shape of the first scan signal line 2061 is a straight line or a broken line extending along the first direction X. The first scan signal line 2061 is located on the side of the first electrode plate 2035 away from the second scan signal line 2031. The area where the first scan signal line 2061 overlaps with the first active layer 21 can be used as the gate electrode of the first transistor T1.

[0402] For example, as shown in Figures 44 and 45, the orthographic projection of the first scan signal line 2061 on the substrate and the orthographic projection of the first blocking line 2042 on the substrate at least partially overlap. The first scan signal line 2061 and the first blocking line 2042 are connected to the same signal source, so that the first blocking line 2042 serves as the bottom gate electrode of the first transistor T1 and the first scan signal line 2061 serves as the top gate electrode of the first transistor T1, thereby forming a dual-gate structure first transistor T1.

[0403] For example, as shown in Figures 44 and 45, the shape of the third scan signal line 2062 is a straight line or a broken line extending along the first direction X. The third scan signal line 2062 is located on the side of the second scan signal line 2031 away from the first scan signal line 2061. The area where the third scan signal line 2062 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0404] For example, as shown in Figures 44 and 45, the orthographic projection of the third scan signal line 2062 on the substrate and the orthographic projection of the second blocking line 2043 on the substrate at least partially overlap. The third scan signal line 2062 and the second blocking line 2043 can be connected to the same signal source, so that the second blocking line 2043 serves as the bottom gate electrode of the second transistor T2 and the third scan signal line 2062 serves as the top gate electrode of the second transistor T2, thereby forming a dual-gate structure second transistor T2.

[0405] For example, as shown in Figures 44 and 45, the shape of the second initialization signal line 2063 is a straight line or a broken line whose main body extends along the first direction X. The second initialization signal line 2063 is located on the side of the third scan signal line 2062 away from the second electrode plate 2041. The second initialization signal line 2063 of this cell row is configured to be connected to the first region 27a of the seventh active layer 27 of the pixel driving circuit in the circuit unit of this cell row.

[0406] For example, as shown in Figure 45, the orthographic projection of the third initialization signal line 2064 on the substrate and the orthographic projection of the fourth scan signal line 2032 on the substrate at least partially overlap, so that the third initialization signal line 2064 with a constant potential can effectively shield the influence of the voltage jump of the fourth scan signal line 2032 on the pixel driving circuit.

[0407] For example, as shown in Figure 45, the second initialization signal line 2063 is a straight line or a broken line whose main body extends along the first direction X. The second initialization signal line 2063 is located between the second electrode plate 2041 and the third initialization signal line 2064. The third initialization signal line 2064 of this unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the next unit row. For example, the third initialization signal line 2064 of the (n-1)th unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the nth unit row.

[0408] For example, in an embodiment of this disclosure, the process of forming the pattern of the third gate metal layer 206 includes: depositing an insulating layer thin film and a third gate metal thin film sequentially on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer and a second semiconductor layer is formed; and performing a patterning process on the third gate metal thin film to form an insulating layer covering the second semiconductor layer and a pattern of the third gate metal layer disposed on the insulating layer.

[0409] For example, in embodiments of this disclosure, the material of the third gate metal layer 206 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third gate metal layer 206 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0410] For example, as shown in Figures 44 and 45, the third gate metal layer 206 is disposed between the first conductive metal layer and the first gate metal layer 203 (mentioned later), and is also disposed on the side of the first conductive metal layer (mentioned later) away from the second conductive metal layer.

[0411] For example, Figure 46 is a schematic planar structure of an interlayer insulating layer in a display substrate according to at least one embodiment of the present disclosure. Figure 47 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate according to at least one embodiment of the present disclosure.

[0412] For example, as shown in Figures 46 and 47, a plurality of first-type via structures are provided in the interlayer insulating layer 207, and the first conductive metal layer and the first semiconductor layer 202 involved thereafter are electrically connected through the first-type via structures.

[0413] It should be noted that although the term "interlayer insulating layer" is used to represent multiple type-1 via structures, it actually represents a portion of a via structure that passes through multiple insulating layers disposed between adjacent layers in the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the materials of the insulating layers between the adjacent layers and the interlayer insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and the insulating layers and interlayer insulating layers can be single-layer, multi-layer, or composite layer structures.

[0414] For example, as shown in Figure 46, the multiple first-type via structures in each circuit unit include at least the following: first-type fourth via structure V74, first-type fifth via structure V75, first-type sixth via structure V76, first-type seventh via structure V77, first-type eighth via structure V78, first-type ninth via structure V79, first-type tenth via structure V710, first-type eleventh via structure V711, first-type twelfth via structure V712, first-type thirteenth via structure V713, first-type fourteenth via structure V714, first-type fifteenth via structure V715, first-type sixteenth via structure V716, and first-type seventeenth via structure V717.

[0415] For example, as shown in Figures 46 and 47, the orthographic projection of the first type fourth via structure V74 on the substrate is located within the range of the orthographic projection of the first region of the third active layer (that is, the second region of the fourth active layer) on the substrate. The first type fourth via structure V74 exposes the surface of the first region of the third active layer (that is, the second region of the fourth active layer). The first type fourth via structure V74 is configured to connect the subsequently formed first conductive metal layer to the first region of the third active layer (that is, the second region of the fourth active layer).

[0416] For example, as shown in Figures 46 and 47, the orthographic projection of the first type fifth via structure V75 on the substrate is located within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) on the substrate. The first type fifth via structure V75 exposes the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The first type fifth via structure V75 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the third active layer (which is also the first region of the sixth active layer).

[0417] For example, as shown in Figures 46 and 47, the orthographic projection of the first type of sixth via structure V76 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate. The first type of sixth via structure V76 exposes the surface of the first region of the fourth active layer. The first type of sixth via structure V76 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the fourth active layer.

[0418] For example, as shown in Figures 46 and 47, the orthographic projection of the first type seventh via structure V77 on the substrate is within the range of the orthographic projection of the first region of the fifth active layer on the substrate. The first type seventh via structure V77 exposes the surface of the first region of the fifth active layer. The first type seventh via structure V77 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the fifth active layer.

[0419] For example, as shown in Figures 46 and 47, the pixel driving circuits of two adjacent circuit units in the first direction X can share a first type seventh via structure V77.

[0420] For example, as shown in Figures 46 and 47, the orthographic projection of the first type eighth via structure V78 on the main surface of the substrate is within the range of the orthographic projection of the second region of the fifth active layer on the main surface of the substrate. The first type eighth via structure V78 exposes the surface of the second region of the fifth active layer. The first type eighth via structure V78 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the fifth active layer.

[0421] For example, as shown in Figures 46 and 47, the orthographic projection of the first type ninth via structure V79 on the main surface of the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) on the main surface of the substrate. The first type ninth via structure V79 exposes the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The first type ninth via structure V79 is configured to connect the subsequently formed first conductive metal layer to the second region of the sixth active layer (which is also the second region of the seventh active layer).

[0422] For example, as shown in Figures 46 and 47, the orthographic projection of the first type tenth via structure V710 on the main surface of the substrate is within the range of the orthographic projection of the first region of the seventh active layer on the main surface of the substrate. The first type tenth via structure V710 exposes the surface of the first region of the seventh active layer. The first type tenth via structure V710 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the seventh active layer.

[0423] For example, as shown in Figures 46 and 47, the orthographic projection of the first type eleventh via structure V711 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate. The first type eleventh via structure V711 exposes the surface of the first region of the eighth active layer. The first type eleventh via structure V711 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the eighth active layer.

[0424] For example, as shown in Figures 46 and 47, the orthographic projection of the first type twelfth via structure V712 on the substrate is within the range of the orthographic projection of the second region of the eighth active layer on the substrate. The first type twelfth via structure V712 exposes the surface of the second region of the eighth active layer. The first type twelfth via structure V712 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the eighth active layer.

[0425] For example, as shown in Figures 46 and 47, the orthographic projection of the first type fifteenth via structure V715 on the substrate is within the range of the orthographic projection of the opening 2041a on the substrate. The first type fifteenth via structure V715 exposes the surface of the first electrode plate 2035. The first type fifteenth via structure V715 is configured to connect the structure in the subsequently formed first conductive metal layer to the first electrode plate 2035.

[0426] For example, as shown in Figures 46 and 47, the orthographic projection of the first type sixteenth via structure V716 on the substrate is within the range of the orthographic projection of the second electrode plate 2041 on the substrate. The first type sixteenth via structure V716 exposes the surface of the second electrode plate 2041. The first type sixteenth via structure V716 is configured to connect the structure in the subsequently formed first conductive metal layer to the second electrode plate 2041.

[0427] For example, as shown in Figures 46 and 47, the orthographic projection of the first type seventeenth via structure V717 on the substrate is within the range of the orthographic projection of the first initialization signal line 2034 on the substrate. The first type seventeenth via structure V717 exposes the surface of the first initialization signal line 2034. The first type seventeenth via structure V717 is configured to connect the structure in the subsequently formed first conductive metal layer to the first initialization signal line 2034.

[0428] For example, Figure 48 is a schematic planar structure of an etch barrier layer in a display substrate according to at least one embodiment of the present disclosure. Figure 49 is a schematic planar structure of a stack of light-shielding layer, first semiconductor layer, first gate metal layer, second gate metal layer, second semiconductor layer, third gate metal layer, and interlayer insulating layer / etch barrier layer in a display substrate according to at least one embodiment of the present disclosure.

[0429] For example, as shown in Figures 48 and 49, a plurality of second-type via structures are provided in the etch barrier layer 208, and the first conductive metal layer and the second semiconductor layer 205 involved thereafter are electrically connected through the second-type via structures.

[0430] It should be noted that although etch stop layers are used to represent multiple second-type via structures, the etch stop layer actually represents another portion of the via structure that passes through the insulating layer disposed between adjacent layers in the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the materials of the insulating layer and the etch stop layer between the adjacent layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and the insulating layer and the etch stop layer can be a single-layer, multi-layer, or composite layer structure. For example, the interlayer insulating layer and the etch stop layer can be disposed in the same layer.

[0431] For example, as shown in Figures 48 and 49, the multiple second-type via structures in each circuit unit include: second-type first via structure V81, second-type second via structure V82, second-type third via structure V83, second-type eighteenth via structure V818, and second-type nineteenth via structure V819.

[0432] For example, as shown in Figures 48 and 49, the orthographic projection of the second type of first via structure V81 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate. The second type of first via structure V81 exposes the surface of the first region of the first active layer. The second type of first via structure V81 is configured to connect the structure in the subsequently formed first conductive metal layer to the first region of the first active layer.

[0433] For example, as shown in Figures 48 and 49, the orthographic projection of the second type of second via structure V82 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) on the substrate. The second type of second via structure V82 exposes the surface of the second region of the first active layer (which is also the first region of the second active layer). The second type of second via structure V82 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the first active layer (which is also the first region of the second active layer).

[0434] For example, as shown in Figures 48 and 49, the orthographic projection of the second type third via structure V83 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate. The second type third via structure V83 exposes the surface of the second region of the second active layer. The second type third via structure V83 is configured to connect the structure in the subsequently formed first conductive metal layer to the second region of the second active layer.

[0435] For example, as shown in Figures 48 and 49, the orthographic projection of the second type eighteenth via structure V818 on the substrate is within the range of the orthographic projection of the second initialization signal line 2063 on the substrate. The second type eighteenth via structure V818 exposes the surface of the second initialization signal line 2063. The second type eighteenth via structure V818 is configured to connect the structure in the subsequently formed first conductive metal layer to the second initialization signal line 2063.

[0436] For example, as shown in Figures 48 and 49, the orthographic projection of the second type nineteenth via structure V819 on the substrate is within the range of the orthographic projection of the third initialization signal line 2064 on the substrate. The second type nineteenth via structure V819 exposes the surface of the third initialization signal line 2064. The second type nineteenth via structure V819 is configured to connect the structure in the subsequently formed first conductive metal layer to the third initialization signal line 2064.

[0437] For example, Figure 50 is a schematic planar structure of a first conductive metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 51 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, and a first conductive metal layer in a display substrate according to at least one embodiment of the present disclosure.

[0438] For example, as shown in Figures 50 and 51, the first conductive metal layer 209 of each circuit unit can be referred to as the first source-drain metal (SD1) layer. The first conductive metal layer 209 of each circuit unit includes at least: a first connection electrode 91, a second connection electrode 92, a third connection electrode 93, a fourth connection electrode 94, a fifth connection electrode 95, a sixth connection electrode 96, a seventh connection electrode 97, an eighth connection electrode 98, a ninth connection electrode 99, a tenth connection electrode 910, and an eleventh connection electrode 911. The first source-drain metal also includes a first data fan-out line 51 and a first connection structure 56, a second connection structure 57, and a third connection structure 55.

[0439] For example, in embodiments of this disclosure, the material of the first conductive metal layer 209 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first conductive metal layer 209 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The first conductive metal layer 209 can also be a multilayer alloy structure, such as a multilayer TiAlTi structure.

[0440] For example, as shown in Figures 50 and 51, the second connecting electrode 92 can be a strip shape extending along the second direction Y of the main body. The first end of the second connecting electrode 92 is connected to the second region of the second active layer through a second type third via structure V83. After the second end of the second connecting electrode 92 extends along the second direction Y, it is connected to the second region of the third active layer (which is also the first region of the sixth active layer) through a first type fifth via structure V75. For example, the second connecting electrode 92 makes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential, forming the third node N3 of the pixel driving circuit.

[0441] For example, as shown in Figures 50 and 51, the third connecting electrode 93 is in the shape of a block and is connected to the first region of the fourth active layer through the first type of sixth via structure V76. The third connecting electrode 93 is configured to be connected to the data signal line formed subsequently.

[0442] For example, as shown in Figures 50 and 51, the first end of the fourth connecting electrode 94 is connected to the first region of the fifth active layer through a first type of seventh via structure V77.

[0443] For example, as shown in Figures 50 and 51, the fourth connection electrodes 94 of two adjacent circuit units in the first direction X are interconnected as an integral structure, and are connected to the first region of the fifth active layer of the two circuit units through a shared first type seventh via structure V77.

[0444] For example, as shown in Figures 50 and 51, since the fifth active layer of the pixel driving circuit in this unit row is located in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 94 in this unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 94 is connected to the second electrode plate 2041 of the pixel driving circuit in this unit row. For example, the first end of the fourth connecting electrode 94 in the (n-1)th unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the nth unit row, and the second end is connected to the second electrode plate 2041 of the pixel driving circuit in the (n-1)th unit row.

[0445] For example, as shown in Figures 50 and 51, the fifth connecting electrode 95 is shaped like a strip extending along the second direction Y. The first end of the fifth connecting electrode 95 is connected to the second region of the fifth active layer via a first-type eighth via structure V78. The second end of the fifth connecting electrode 95 extends along the second direction Y and is then connected to the second region of the eighth active layer via a first-type eleventh via structure V711. For example, the fifth connecting electrode 95 causes the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3 to have the same potential, forming the second node N2 of the pixel driving circuit. In an exemplary embodiment, the fifth connecting electrode 95 can serve as the second node electrode in an embodiment of this disclosure.

[0446] For example, as shown in Figures 50 and 51, the sixth connecting electrode 96 is an obliquely extending strip, and it is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a first-type ninth via structure V79. For example, the sixth connecting electrode 96 is configured to connect to the subsequently formed anode connecting electrode to form the fourth node N4 of the pixel driving circuit.

[0447] For example, as shown in Figures 50 and 51, the seventh connecting electrode 97 is a strip shape in which the main body extends along the first direction X. The first end of the seventh connecting electrode 97 is connected to the first region of the first active layer through a second type of first via structure V81, and the second end of the seventh connecting electrode 97 is connected to the first initialization signal line 2034 through a first type of seventeenth via structure V717. For example, the seventh connecting electrode 97 realizes the connection between the first initialization signal line 2034 and the first electrode of the first transistor T1, and the first initialization signal line 2034 can write the transmitted first initial signal into the first electrode of the first transistor T1.

[0448] For example, as shown in Figures 50 and 51, the eighth connection electrode 98 is a block-shaped part extending along the second direction Y. The first end of the eighth connection electrode 98 is connected to the first region of the seventh active layer through a first type tenth via structure V710, and the second end of the eighth connection electrode 98 is connected to the second initialization signal line 2063 through a second type eighteenth via structure V818. For example, the eighth connection electrode 98 realizes the connection between the second initialization signal line 2063 and the first terminal of the seventh transistor T7, and the second initialization signal line 2063 can write the transmitted second initial signal into the first terminal of the seventh transistor T7.

[0449] For example, as shown in Figures 50 and 51, the ninth connecting electrode 99 is a strip shape in which the main body extends along the second direction Y, and the ninth connecting electrode 99 is connected to the third initialization signal line 2064 through the second type nineteenth via structure V819.

[0450] For example, as shown in Figures 50 and 51, since the eighth active layer of the pixel driving circuit in this unit row is located in the circuit unit of the previous unit row, the first end of the ninth connecting electrode 99 in this unit row is connected to the first region of the eighth active layer of the pixel driving circuit in the next unit row, and the second end of the ninth connecting electrode 99 is connected to the third initialization signal line 2064 in this unit row. For example, for the ninth connecting electrode 99 in the (n-1)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the nth unit row, and its second end is connected to the third initialization signal line 2064 in the (n-1)th unit row.

[0451] For example, as shown in Figures 50 and 51, the tenth connecting electrode 910 is a strip shape in which the main body extends along the second direction Y, and is inverted S-shaped. The first end of the tenth connecting electrode 910 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second type of second via structure V82.

[0452] For example, as shown in Figures 50 and 51, in the structure of the display substrate, the first conductive metal layer 209 includes a first data fan-out line 51, a first connection structure 56, a second connection structure 57, and a third connection structure 55. The first data fan-out line 51 extends along a first direction X, and the first connection structure 56 extends along a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is a horizontal direction, and the second direction Y is a vertical direction.

[0453] For example, as shown in Figures 50 and 51, in the structure of the display substrate, the first connection structure 56 is disposed between the first data fan-out line 51 and the first initialization signal line 2034.

[0454] For example, as shown in Figures 50 and 51, the first data fan-out line 51 is a continuous structure without any breaks in the middle.

[0455] For example, in other embodiments, the first data fan-out line 51 extends along the first direction X, and the first data fan-out line 51 may also include two or more breaks, which are located below the power supply voltage signal line or the anode to be blocked.

[0456] For example, as shown in Figures 50 and 51, the third connection structure 55 can serve as a first initialization signal adapter. The initialization signal connection line and the first initialization signal line 2034, which are subsequently disposed on the second conductive metal layer 212, are electrically connected through this first initialization signal adapter 55.

[0457] For example, as shown in Figures 50 and 51, the first conductive metal layer 209 also includes a second initialization signal adapter 913. The initialization signal connection line and the second initialization signal line 2063, which are subsequently disposed on the second conductive metal layer 212, are electrically connected through the second initialization signal adapter 913.

[0458] For example, the initialization signal connection line is also electrically connected to the third initialization signal line 2064, thereby making the initialization signal connection line electrically connected to the first initialization signal line 2034, the second initialization signal line 2063 and the third initialization signal line 2064 to form a mesh initialization signal structure.

[0459] For example, as shown in Figures 50 and 51, the orthographic projection of the first data fan-out line 51 on the substrate and the orthographic projections of the first initialization signal line 2034 and the second initialization signal line 2063 on the substrate are all spaced apart from each other.

[0460] For example, as shown in Figures 50 and 51, the first data fan-out line 51 covers the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8. The orthographic projection of the first data fan-out line 51 on the substrate overlaps with the orthographic projection of the third initialization signal line 2064 on the substrate. Therefore, the third initialization signal line 2064 can be used to shield the first data fan-out line 51. This routing method avoids the overlap of the first data fan-out line 51 with the first scan signal line, the light emission control signal line, the first initialization signal line, etc., and can reduce the impact of signal transitions on the data signal on these signal lines. Although this routing method has the phenomenon of overlap between the third initialization signal line 2064 and the first data fan-out line 51, the third initialization signal line 2064 is used to shield the first data fan-out line 51, thereby minimizing the impact of signal transitions on the third initialization signal line 2064 on the data signal.

[0461] For example, as shown in Figure 51, the fourth scan signal line 2032, which is also the first reset control signal line, overlaps with the orthographic projection of the first data fan-out line 51 on the substrate, the orthographic projection of the third initialization signal line 2064 on the substrate, and the first reset control signal line 2032.

[0462] For example, as shown in Figure 51, the orthographic projections of the second plate 2041, the first shielding line 2042, and the second shielding line 2043 of the storage capacitor on the substrate are all spaced apart from the orthographic projection of the first data fan-out line 51 on the substrate, thereby avoiding the influence of the first shielding line 2042 and the second shielding line 2043 on the data signal transition.

[0463] For example, Figure 52 is a schematic planar structure of a passivation layer in a display substrate according to at least one embodiment of the present disclosure. Figure 53 is a schematic planar structure of a first planarization layer in a display substrate according to at least one embodiment of the present disclosure. Figure 54 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate according to at least one embodiment of the present disclosure.

[0464] For example, as shown in Figures 52 and 53, the passivation layer 210 and the first planarization layer 211 are provided with a plurality of third-type via structures, and the second conductive metal layer and the first conductive metal layer involved thereafter are electrically connected through the third-type via structures.

[0465] For example, as shown in Figures 52-54, the multiple third-type via structures in each circuit unit include: the second-twentieth-type via structure V922, the twenty-third-type via structure V923, the twenty-fourth-type via structure V924, the twenty-fifth-type via structure V925, the twenty-sixth-type via structure V926, and the twenty-eighth-type via structure V928.

[0466] For example, as shown in Figures 52-54, the orthographic projection of the third type twenty-two via structure V922 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 94 on the substrate. The passivation layer and the first planarization layer in the third type twenty-two via structure V922 are etched away, exposing the surface of the fourth connection electrode 94. The third type twenty-two via structure V922 is configured to connect the subsequently formed power supply voltage signal line to the fourth connection electrode 94.

[0467] For example, as shown in Figures 52-54, the orthographic projection of the third type twenty-third via structure V923 on the substrate is located within the range of the orthographic projection of the third connection electrode 93 on the substrate. The passivation layer and the first planarization layer in the third type twenty-third via structure V923 are etched away, exposing the surface of the third connection electrode 93. The third type twenty-third via structure V923 is configured to connect the subsequently formed data signal line to the third connection electrode 93.

[0468] For example, as shown in Figures 52-54, the orthogonal projections of the third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 on the substrate are located within the range of the orthogonal projection of the second connection structure 57 on the substrate. The passivation layer and the first planarization layer in the third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 are etched away, exposing the surface of the second connection structure 57. The third type twenty-fourth via structure V924 and the third type twenty-fifth via structure V925 are configured to connect the subsequently formed second conductive metal layer to the second connection structure 57.

[0469] For example, as shown in Figures 52-54, the orthographic projection of the third type 26 via structure V926 on the substrate is within the range of the orthographic projection of the third connection structure 55 on the substrate. The passivation layer and the first planarization layer in the third type 26 via structure V926 are etched away, exposing the surface of the third connection structure 55. The third type 26 via structure V926 is configured to connect the subsequently formed second conductive metal layer to the third connection structure 55.

[0470] For example, as shown in Figures 52-54, the orthographic projection of the third type twenty-eighth via structure V928 on the substrate is within the range of the orthographic projection of the sixth connection electrode 96 on the substrate. The passivation layer and the first planarization layer in the third type twenty-eighth via structure V928 are etched away, exposing the surface of the sixth connection electrode 96. The third type twenty-eighth via structure V928 is configured to connect the subsequently formed anode connection electrode to the sixth connection electrode 96.

[0471] For example, the process of forming the passivation layer and the first planarization layer pattern includes: coating a passivation layer film and a first planarization layer film on a substrate having a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer and a first conductive metal layer; patterning the passivation layer film and the first planarization layer film using a patterning process to form a passivation layer and a first planarization layer that cover the pattern of the first conductive metal layer; and providing a plurality of third-type via structures on the passivation layer and the first planarization layer.

[0472] For example, the first planarization layer can be formed using an organic material, such as a resin. The passivation layer can be formed using an inorganic insulating material, such as silicon nitride, silicon oxynitride, or silicon dioxide.

[0473] For example, Figure 55 is a schematic planar structure of a second conductive metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 56 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate according to at least one embodiment of the present disclosure.

[0474] For example, as shown in Figures 55 and 56, the second conductive metal layer 212 of each circuit unit includes: a power supply voltage signal line 212a, a data signal line 212b, an anode connection electrode 212c, an initialization signal connection line 212d, and a second data fan-out line 212e. The second conductive metal layer 212 can serve as a second source-drain metal (SD2) layer.

[0475] For example, as shown in Figures 55 and 56, the power supply voltage signal line 212a is a straight line or a broken line whose main body extends along the second direction Y. The power supply voltage signal line 212a is connected to the fourth connection electrode 94 through the third type of twenty-second via structure V922. The fourth connection electrode 94 is connected to the first electrode of the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor, respectively. Thus, the power supply voltage signal line 212a writes the first power signal into the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor.

[0476] For example, as shown in Figures 55 and 56, the power supply voltage signal line 212a can be a non-uniform width polygonal line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the power supply voltage signal line and the data signal line.

[0477] For example, as shown in Figures 55 and 56, the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. This allows the power supply voltage signal line 212a to block the first and second active layers, thereby preventing the light emitted by the light-emitting element and the reflected light from the film layer from illuminating the first and second oxide transistors T1 and T2. This prevents the oxide transistors from experiencing characteristic drift due to light exposure and improves the electrical characteristics of the oxide transistors.

[0478] For example, as shown in Figures 55 and 56, the orthographic projection of the power supply voltage signal line 212a on the substrate overlaps at least partially with the orthographic projection of the first connecting electrode 91 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node N1, and improve the driving performance of the pixel driving circuit.

[0479] For example, as shown in Figures 55 and 56, the orthographic projection of the power supply voltage signal line 212a on the substrate overlaps at least partially with the orthographic projections of the second connecting electrode 92 and the tenth connecting electrode 910 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on each node in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the node potential, and improve the driving performance of the pixel driving circuit.

[0480] For example, as shown in Figures 55 and 56, the data signal line 212b can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 212b is connected to the third connection electrode 93 through a third type twenty-third via structure V923. Since the third connection electrode 93 is connected to the first region of the fourth active layer through the via, the connection between the data signal line 212b and the first electrode of the fourth transistor T4 is realized, and the data signal line 212b can write data signals to the first electrode of the fourth transistor T4.

[0481] For example, as shown in Figures 55 and 56, the anode connecting electrode 212c is a long strip extending in the second direction Y. The anode connecting electrode 212c is connected to the sixth connecting electrode 96 via a third type twenty-eighth via structure V928. The anode connecting electrode 212c is configured to connect with the subsequently formed anode. Since the sixth connecting electrode 96 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, allowing the pixel driving circuit to drive the light-emitting element to emit light.

[0482] For example, the process of forming the second conductive metal layer includes: depositing a second conductive metal thin film on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer is formed; and patterning the second conductive metal thin film using a patterning process to form a second conductive metal layer disposed on the first planarization layer.

[0483] For example, the material of the first conductive metal layer 212 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second conductive metal layer 212 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The second conductive metal layer 212 can also be a multilayer alloy structure, such as a multilayer TiAlTi structure.

[0484] For example, as shown in Figures 55 and 56, the initialization signal connection line 212d is electrically connected to the first initialization signal adapter line 55 through a second via structure V926 disposed in the first insulating layer, and is also electrically connected to the second initialization signal adapter line 913 through another second via structure V926 disposed in the first insulating layer. For example, the first insulating layer includes a passivation layer and a first planarization layer, and the second via structure is a hole structure that penetrates the passivation layer and the first planarization layer. For example, in the second direction Y, the second via structure V926 and the first via structure V928 mentioned later are respectively disposed on both sides of the first data fan-out line 51. This can increase the distance between the first via structure V928 and the second via structure V926, thereby reducing the length of the connection between the first initialization signal line and the second initialization signal line accessing the network, which is beneficial to reducing the load on the first initialization signal line and the second initialization signal line. Furthermore, due to the downward shift of the position of the first via structure, the first via structure corresponding to the N4 node can be moved outward, increasing the distance between the first via structure and the corresponding anode, thereby improving the flatness of the anode in the corresponding sub-pixel.

[0485] For example, as shown in Figures 55 and 56, the second data fan-out line 212e is disposed between two adjacent data signal lines 212b.

[0486] For example, as shown in Figures 55 and 56, the two adjacent initialization signal connection lines 212d, the two adjacent anode connection electrodes 212c, the two adjacent power supply voltage signal lines 212a, and the two adjacent data signal lines 212b are all axially symmetrical about the second data fan-out line 212e.

[0487] For example, Figure 57 is a schematic planar structure of a second planarization layer in a display substrate according to at least one embodiment of the present disclosure. Figure 58 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate according to at least one embodiment of the present disclosure.

[0488] For example, as shown in Figures 57 and 58, a second planarization layer 213 is disposed on the entire substrate. The second planarization layer 213 has a plurality of fourth-type via structures 213a / 213b / 213c / 213d, which expose the anode connection electrode. These plurality of fourth-type via structures 213a / 213b / 213c / 213d can enable the subsequent anode to be connected to the anode connection electrode in the second conductive metal layer.

[0489] For example, the second planarization layer can be formed using organic materials, such as resins.

[0490] For example, the fourth type of via structure 213a / 213b / 213c / 213d can be used as an anode connection hole, the first insulating layer includes the second planarization layer 212 mentioned above, and the fourth type of via structure 213a / 213b / 213c / 213d is disposed in the second planarization layer 212.

[0491] For example, Figure 59 is a schematic planar structure of an anode layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 60 is a schematic planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etch barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer in a display substrate provided in at least one embodiment of the present disclosure.

[0492] For example, as shown in Figures 59 and 60, an anode layer 214 is disposed on the second planarization layer 213. This anode layer 214 includes multiple anode electrodes 214a / 214b / 214c / 214d. Anode electrode 214a may be an electrode corresponding to the first sub-pixel P1, anode electrode 214b may be an electrode corresponding to the second sub-pixel P2, anode electrode 214c may be an electrode corresponding to the third sub-pixel P3, and anode electrode 214d may be an electrode corresponding to the fourth sub-pixel P4. Anode electrodes 214a, 214b, 214c, and 214d are respectively connected to the anode connection electrode in the second conductive metal layer through fourth-type via structures 213a, 213b, 213c, and 213d.

[0493] For example, in one example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 are green sub-pixels (G) that emit green light, and the third sub-pixel P3 is a blue sub-pixel (B) that emits blue light. The embodiments of this disclosure are not limited in this respect.

[0494] For example, referring to Figures 33 to 60, the display substrate includes: a substrate 101, a driving circuit layer 102 on the substrate 101, the driving circuit layer 102 including a pixel driving circuit, and a plurality of light-emitting elements disposed on the side of the pixel driving circuit away from the substrate 101; the pixel driving circuit includes a first conductive metal layer 209, a first insulating layer 210 / 211 and a second conductive metal layer 212 stacked together, the second conductive metal layer 212 including an initialization signal connection line 212d arranged in the first direction X and an anode connection electrode 21 2c and power supply voltage signal line 212a, initialization signal connection line 212d, anode connection electrode 212c and power supply voltage signal line 212a all extend along a second direction Y intersecting the first direction X. The anode connection electrode 212c is electrically connected to the first conductive metal layer 209 through a first via structure disposed in the first insulating layer 210 / 211. Multiple light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and the orthographic projection of the first anode on the substrate 101 and the orthographic projection of the first via structure on the substrate 101 do not overlap. The first via structure is the third type twenty-eighth via structure V928 in the third type of via structure in the first planarization layer in FIG. 25.

[0495] For example, the first anode can be the anode corresponding to the red sub-pixel. The orthographic projection of the anode corresponding to the red sub-pixel on the substrate 101 and the orthographic projection of the first via structure V928 on the substrate 101 do not overlap. That is, the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the red sub-pixel.

[0496] For example, in one example, multiple light-emitting elements include a second light-emitting element, which includes a second anode. The orthographic projection of the second anode onto the substrate overlaps with the orthographic projection of the first via structure V928 onto the substrate. For example, the second anode may be the anode corresponding to the blue sub-pixel, and the orthographic projection of the anode corresponding to the blue sub-pixel onto the substrate 101 overlaps with the orthographic projection of the first via structure V928 onto the substrate 101, that is, a portion of the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the blue sub-pixel.

[0497] For example, in one instance, the area of ​​the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure V928 on the substrate overlaps by 5% to 20% of the area of ​​the first via structure, that is, the area covered by the second anode on the first via structure V928 does not exceed 1 / 5 of the area of ​​the first via structure V928.

[0498] For example, the second conductive metal layer 212 also includes a second data fan-out line 212e, which extends along the second direction Y and has a break in the middle region. The second data fan-out line 212e is connected at one end of the break through a third type twenty-fourth via structure V924 and an eleventh connection electrode 911, and at the other end of the break through a third type twenty-fifth via structure V925 and an eleventh connection electrode 911.

[0499] Figure 61 is an equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure. As shown in Figure 61, the pixel driving circuit is an 8T1C structure, which may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. Each pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and power supply voltage signal line VDD).

[0500] For example, in an embodiment of this disclosure, the connection structure of the first transistor T1 to the eighth transistor T8 and the storage capacitor C in the pixel driving circuit shown in FIG. 61 differs from the structure of the pixel driving circuit shown in FIG. 33 in that: in the pixel driving circuit shown in FIG. 61, the first transistor T1 is connected to the third node, and the N3 node is between the first transistor T1 and the second transistor T2.

[0501] Furthermore, in the pixel driving circuit shown in Figure 61, the active layer of the first transistor T1 is made of low-temperature polycrystalline silicon, and the first transistor T1 can be a low-temperature polycrystalline silicon transistor (P-type transistor); the active layer of the second transistor T2 is made of conductive metal oxide, and the second transistor T2 can be an oxide transistor (N-type transistor), that is, the active layers of the first transistor T1 and the second transistor T2 are located in different layers.

[0502] For example, as shown in Figure 61, the pixel driving circuit includes a storage capacitor and a plurality of transistors. The storage capacitor may include a first electrode plate and a second electrode plate disposed opposite to each other. The plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. The second transistor T2 is an oxide transistor, and the first transistor T1 and the third transistors T3 to the eighth transistors T8 are low-temperature polysilicon transistors.

[0503] For example, Figure 62 is a schematic diagram of the planar structure of a light-shielding layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in Figure 62, the light-shielding layer 201 may be a bottom light-shielding metal (BSM) layer.

[0504] For example, as shown in Figure 62, the pattern of the light-shielding layer 201 includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and light-shielding electrodes 2013, with multiple light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is approximately rectangular, and the corners of the rectangle can be chamfered. The shape of the first light-shielding connecting line 2011 can be a straight line or a broken line extending along the second direction Y. The first light-shielding connecting line 2011 can be respectively disposed on both sides of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013 respectively. The shape of the second light-shielding connecting line 2012 can be a straight line or a broken line extending along the first direction X. The second light-shielding connecting line 2012 can be disposed on both sides of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013 respectively, thereby forming a mesh structure in the pattern of the light-shielding layer.

[0505] For example, as shown in Figure 62, in a cell row, the second light-shielding connection lines 2012 in two adjacent circuit cells in the first direction X can be connected to form an interconnected integral structure.

[0506] For example, in other embodiments of this disclosure, the first light-shielding connection lines 2011 in two adjacent circuit units in the second direction Y can be connected in a unit column to form an interconnected integral structure, that is, the light-shielding layers in the unit row and unit column are connected as one unit, thereby ensuring that the light-shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the display of the subsequently formed display panel, so as to avoid display defects of the display panel and ensure the display effect of the display panel.

[0507] For example, forming a pattern for the light-shielding layer includes: depositing a light-shielding layer thin film on a substrate, and patterning the light-shielding layer thin film using a patterning process to form a light-shielding layer pattern. The material of the light-shielding layer can be a light-shielding metal material.

[0508] It should be noted that the "patterning process" mentioned in the embodiments of this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, processes such as depositing a film layer, coating a film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating an organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. The embodiments of this disclosure do not limit this. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In the embodiments of this disclosure, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the main surface of the display substrate. In the embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B, which will not be elaborated further below.

[0509] For example, FIG63 is a schematic planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG63, the first semiconductor layer 202 can form the first active layer 21 of the first transistor T1, the third active layer 23 of the third transistor T3 to the eighth active layer 28 of the eighth transistor T8.

[0510] For example, as shown in Figure 63, the third active layer 23, the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 are interconnected as a single structure, while the first active layer 21 and the eighth active layer 28 are set separately.

[0511] For example, the first active layer 21 is the channel region of the first transistor T1 (first initialization transistor), the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), and the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor).

[0512] For example, Figure 64 is a schematic planar structure of a stacked light-shielding layer and a first semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 64, the orthographic projection of the third active layer 23 on the substrate and the orthographic projection of the light-shielding electrode 2013 on the substrate at least partially overlap. The light-shielding electrode 2013 serves as the light-shielding layer of the third transistor T3, blocking the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0513] For example, in an embodiment of this disclosure, in the pixel driving circuit of this circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the first direction X, and the sixth active layer 26 may be located on the opposite side of the third active layer 23 in the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the second direction Y.

[0514] For example, as shown in Figures 63 and 64, the third active layer 23 can be in the shape of an inverted "Ω", the fourth active layer 24, the fifth active layer 25 and the sixth active layer 26 can be in the shape of a strip extending along the second direction Y of the main body, the seventh active layer 27 can be in the shape of an inverted "L", and the eighth active layer 28 can be in the shape of an inverted "S".

[0515] For example, as shown in Figure 63, the first active layer 21, the third active layer 23 to the eighth active layer 28 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 21a of the first active layer 21, the second region 21b of the first active layer 21, the first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 27a of the seventh active layer 27, the first region 28a of the eighth active layer 28, and the second region 28b of the eighth active layer 28 can be set individually.

[0516] For example, as shown in Figure 63, in a cell column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit cell can be set in the circuit cell of the previous cell row, and the first active layer 21, the third active layer 23, the fourth active layer 24, the sixth active layer 26 and the seventh active layer 27 can be set in this circuit cell.

[0517] For example, as shown in Figure 63, the fifth active layer 25 of the pixel driving circuit in the current unit row is located on one side of the sixth active layer 26 of the pixel driving circuit in the previous unit row, in the first direction X. This allows the fifth active layer 25 and the sixth active layer 26 of the two unit rows to share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 in the current unit row and the fifth transistor T5 in the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the nth unit row is disposed in the circuit cell of the (n-1)th unit row, allowing the fifth active layer 25 of the pixel driving circuit in the nth unit row and the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row to share a single light-emitting control signal line. This single light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 in the nth unit row and the sixth transistor T6 in the (n-1)th unit row.

[0518] For example, in at least one embodiment of this disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of this unit row is located on one side of the seventh active layer 27 of the pixel driving circuit in the circuit unit of the previous unit row, such that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of this unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the (n-1)th unit row, such that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row can share a single scan signal line, which can simultaneously control the conduction and disconnection of the seventh transistor T7 of the (n-1)th unit row and the eighth transistor T8 of the nth unit row.

[0519] For example, in at least one embodiment of this disclosure, the first semiconductor layer 202 is formed of polysilicon (p-Si), i.e., the first transistor T1, the third transistor T3 to the eighth transistor T8 are LTPS transistors.

[0520] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor thin film, and then patterning the first semiconductor thin film using a patterning process. For example, the process of patterning the first semiconductor thin film using a patterning process includes: first forming an amorphous silicon (a-Si) thin film, performing a dehydrogenation treatment on the amorphous silicon thin film, performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film, and then patterning the polycrystalline silicon thin film to form the pattern of the first semiconductor layer.

[0521] For example, Figure 65 is a schematic planar structure of a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 66 is a schematic planar structure of a stacked light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 65, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scan signal line 2031, a fourth scan signal line 2032, a light-emitting control signal line 2033, a third scan signal line 2062, and a first electrode 2035 of a storage capacitor.

[0522] For example, as shown in Figure 66, the first electrode 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode 2035 can simultaneously serve as an electrode of a storage capacitor and the gate electrode of the third transistor T3.

[0523] For example, as shown in Figure 66, the orthographic projection of the first electrode plate 2035 on the substrate overlaps at least partially with the orthographic projection of the light-shielding electrode 2013 on the substrate.

[0524] For example, as shown in Figure 66, the shape of the second scan signal line 2031 is a straight line or a broken line extending along the first direction X of the main body. The second scan signal line 2031 is located on the side opposite to the second direction Y of the first electrode plate 2035. The area where the second scan signal line 2031 overlaps with the fourth active layer 24 can be used as the gate electrode of the fourth transistor T4.

[0525] For example, as shown in Figure 66, the fourth scan signal line 2032 is a straight line or a broken line whose main body extends along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode plate 2035 in the second direction Y. The area where the fourth scan signal line 2032 of this unit row overlaps with the seventh active layer 27 of the pixel driving circuit in this unit row serves as the gate electrode of the seventh transistor T7 in this unit row. The area where the fourth scan signal line 2032 of this unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the eighth transistor T8 in the nth unit row.

[0526] For example, as shown in Figure 66, the shape of the light-emitting control signal line 2033 is a straight line or a broken line extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode plate 2035 and the fourth scan signal line 2032. The area where the light-emitting control signal line 2033 of this unit row overlaps with the sixth active layer 26 of the pixel driving circuit in this unit row can be used as the gate electrode of the sixth transistor T6 of this unit row. The area where the light-emitting control signal line 2033 of this unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can be used as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the (n-1)th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the (n-1)th unit row can be used as the gate electrode of the sixth transistor T6 of the (n-1)th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can be used as the gate electrode of the fifth transistor T5 of the nth unit row.

[0527] For example, as shown in Figure 66, the shape of the first scan signal line 2061 is a straight line or a broken line extending along the first direction X. The third scan signal line 2062 is located on the side of the second scan signal line 2031 away from the first electrode plate 2035. The area where the third scan signal line 2062 of this unit row overlaps with the first active layer 21 of the pixel driving circuit in this unit row can be used as the gate electrode of the first transistor T1 of this unit row.

[0528] For example, as shown in FIG66, the second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the third scan signal line 2062 have different widths in the second direction Y. The second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the third scan signal line 2062 can be arranged to facilitate the layout of the pixel structure, and can reduce the parasitic capacitance between the signal lines. The embodiments of this disclosure do not limit this.

[0529] For example, as shown in Figure 66, the second scan signal line 2031, the fourth scan signal line 2032, the light emission control signal line 2033, and the third scan signal line 2062 include regions that overlap with the first semiconductor layer and regions that do not overlap with the first semiconductor layer. The width of the signal line in the region that overlaps with the first semiconductor layer can be greater than the width of the signal line in the region that does not overlap with the first semiconductor layer.

[0530] For example, as shown in Figure 66, after the pattern of the first gate metal layer is formed, the first gate metal layer can be used as a shielding layer to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first gate metal layer forms the channel region of the first transistor T1, the third transistor T3 to the eighth transistor T8. The first semiconductor layer in the area not shielded by the first gate metal layer is conducted, that is, the first region and the second region of the first electrode 2035, the first active layer 21, the third active layer 23 to the eighth active layer 28 are all conducted.

[0531] For example, in an embodiment of this disclosure, the process of forming the first gate metal layer includes: depositing a second insulating layer thin film and a first conductive metal thin film sequentially on a substrate on which a light-shielding layer and a first semiconductor layer are formed; patterning the first conductive metal thin film by a patterning process to form a second insulating layer covering the pattern of the first semiconductor layer; and a pattern of the first gate metal layer disposed on the second insulating layer. For example, the first gate metal layer may be referred to as the GATE1 layer.

[0532] For example, in embodiments of this disclosure, the material of the first gate metal layer 203 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate metal layer 203 can be a single-layer metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0533] For example, Figure 67 is a schematic planar structure of a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. Figure 68 is a schematic planar structure of a stacked layer of a light-shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the second gate metal layer can be referred to as the GATE2 layer.

[0534] For example, in at least one embodiment of this disclosure, the pattern of the second gate metal layer 204 of each circuit unit includes: a second electrode 2041 of a storage capacitor, a first initialization signal line 2034, and a second shielding line 2043.

[0535] For example, as shown in Figures 67 and 68, the outline of the second electrode plate 2041 is rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 2041 on the substrate overlaps at least partially with the orthographic projection of the first electrode plate 2035 on the substrate. The second electrode plate 2041 can serve as another electrode plate of the storage capacitor. The first electrode plate 2035 and the second electrode plate 2041 constitute the storage capacitor of the pixel driving circuit.

[0536] For example, as shown in Figures 67 and 68, an opening 2041a is provided on the second electrode plate 2041. The opening 2041a can be rectangular in shape and can be located in the central region of the second electrode plate 2041, so that the second electrode plate 2041 forms a ring structure. The opening 2041a exposes the third insulating layer covering the first electrode plate 2035, and the orthogonal projection of the first electrode plate 2035 on the substrate covers the orthogonal projection of the opening 2041a on the substrate.

[0537] For example, as shown in Figures 67 and 68, the second electrode plate 2041 includes an electrode plate 2041b. The shape of the electrode plate 2041b can be a strip shape extending along the first direction X.

[0538] For example, as shown in Figures 67 and 68, the shape of the second shielding line 2043 can be a straight line or a broken line extending along the first direction X of the main body. The second shielding line 2043 can be located between the first electrode plate 2035 and the second scan signal line 2031. The second shielding line 2043 is configured as a light-shielding layer of the second transistor T2 mentioned later, shielding the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the second transistor T2.

[0539] For example, as shown in Figures 67 and 68, the first initialization signal line 2034 and the second blocking line 2043 can be designed with non-uniform widths, which not only facilitates the layout of pixel structures but also reduces parasitic capacitance between signal lines.

[0540] For example, the process of forming a pattern of the second gate metal layer includes: depositing a third insulating film and a second conductive metal film sequentially on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer and a first gate metal layer is formed; patterning the second conductive metal film using a patterning process to form a third insulating layer covering the first gate metal layer, and a pattern of the second gate metal layer disposed on the third insulating layer.

[0541] For example, in embodiments of th...

Claims

1. A display substrate, comprising: Substrate; A pixel driving circuit on the substrate, and a plurality of light-emitting elements located on the side of the pixel driving circuit away from the substrate; The pixel driving circuit includes a first conductive metal layer, a first insulating layer and a second conductive metal layer stacked together. The second conductive metal layer includes an initialization signal connection line, an anode connection electrode and a power supply voltage signal line arranged in a first direction. The initialization signal connection line, the anode connection electrode and the power supply voltage signal line all extend along a second direction intersecting the first direction. The anode connection electrode is electrically connected to the second conductive metal layer through a first via structure disposed in the first insulating layer. The plurality of light-emitting elements include a first light-emitting element, the first light-emitting element including a first anode, wherein the orthographic projection of the first anode on the substrate and the orthographic projection of the first via structure on the substrate do not overlap.

2. The display substrate according to claim 1, wherein, The plurality of light-emitting elements include a second light-emitting element, the second light-emitting element including a second anode, the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure on the substrate partially overlap.

3. The display substrate according to claim 2, wherein, The area of ​​the intersection of the orthographic projection of the second anode on the substrate and the orthographic projection of the first via structure on the substrate is 0% to 20% of the area of ​​the first via structure.

4. The display substrate according to any one of claims 1 to 3, further comprising a third gate metal layer disposed on the side of the first conductive metal layer away from the second conductive metal layer, wherein, The first conductive metal layer includes a first data fan-out line extending along the first direction, and the second conductive metal layer includes a second data fan-out line extending along the second direction; The third gate metal layer includes a third initialization signal line extending along the first direction; The orthographic projection of the first data fan-out line on the substrate and the orthographic projection of the third initialization signal line on the substrate overlap.

5. The display substrate according to claim 4, further comprising a first gate metal layer disposed on the side of the third gate metal layer away from the first conductive metal layer, wherein, The first gate metal layer includes a first initialization signal line extending along the first direction, and the third gate metal layer includes a second initialization signal line that is spaced apart from the third initialization signal line and extends along the second direction. The orthographic projection of the first data fan-out line on the substrate and the orthographic projections of the first initialization signal line and the second initialization signal line on the substrate are all spaced apart from each other.

6. The display substrate according to claim 5, wherein, The first conductive metal layer includes a first initialization signal adapter and a second initialization signal adapter; The initialization signal connection line is electrically connected to the first initialization signal adapter line through a second via structure disposed in the first insulating layer, and is electrically connected to the second initialization signal adapter line through another second via structure disposed in the first insulating layer.

7. The display substrate according to claim 6, wherein, In the second direction, the second via structure and the first via structure are respectively disposed on both sides of the first data fan-out line.

8. The display substrate according to claim 6 or 7, wherein, The initialization signal connection line and the first initialization signal line are electrically connected through the first initialization signal adapter line, the initialization signal connection line and the second initialization signal line are electrically connected through the second initialization signal adapter line, and the initialization signal connection line and the third initialization signal line are electrically connected to each form a mesh initialization signal structure.

9. The display substrate according to claim 8, wherein, The second conductive metal layer also includes a data signal line extending in the second direction, and the second data fan-out line is disposed between two adjacent data signal lines.

10. The display substrate according to claim 9, wherein, The two adjacent initialization signal connection lines, the two adjacent anode connection electrodes, the two adjacent power supply voltage signal lines, and the two adjacent data signal lines are all axially symmetrical about the second data fan-out line.

11. The display substrate according to claim 10, wherein, The first gate metal layer further includes a first reset control signal line, and the orthographic projection of the first data fan-out line on the substrate, the orthographic projection of the third initialization signal line on the substrate, and the first reset control signal line overlap.

12. The display substrate according to any one of claims 5 to 11, further comprising a second gate metal layer disposed between the third gate metal layer and the first gate metal layer, wherein, The second gate metal layer includes a second plate of a storage capacitor extending in the first direction, a first shielding line and a second shielding line, wherein the orthographic projections of the second plate of the storage capacitor, the first shielding line and the second shielding line on the substrate are all spaced apart from the orthographic projections of the first data fan-out line on the substrate.

13. The display substrate according to claim 12, wherein, The third gate metal layer further includes a third scan signal line and a first scan signal line disposed on the side of the third initialization signal line close to the second initialization signal line. The orthographic projection of the third scan signal line on the substrate and the orthographic projection of the second shielding line on the substrate overlap. The orthographic projection of the first scan signal line on the substrate and the orthographic projection of the first shielding line on the substrate overlap.

14. The display substrate according to claim 9 or 10, wherein, The pixel driving circuit includes a driving transistor, a seventh transistor, and an eighth transistor. The first electrode of the eighth transistor is connected to the third initialization signal line, the second electrode of the eighth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the first electrode of the first light-emitting element. The display substrate further includes: a first active layer located between the substrate and the first gate metal layer, the first active layer including a seventh active portion and an eighth active portion, the seventh active portion being used to form the channel region of the seventh transistor, and the eighth active portion being used to form the channel region of the eighth transistor; The orthographic projection of the first reset control signal line on the substrate covers the orthographic projections of the eighth active portion and the seventh active portion on the substrate. A portion of the structure of the first reset control signal line is used to form the gate of the seventh transistor, and a portion of the structure of the first reset control signal line is used to form the gate of the eighth transistor.

15. The display substrate according to claim 14, wherein, The pixel driving circuit further includes a fourth transistor and a sixth transistor. The first terminal of the fourth transistor is connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the second terminal of the eighth transistor. The first terminal of the sixth transistor is electrically connected to the second terminal of the seventh transistor. The first active layer further includes a third active portion, a fourth active portion, and a sixth active portion. The third active portion is configured to form the channel region of the driving transistor. The fourth active portion is connected to the eighth active portion, and the sixth active portion is connected to the seventh active portion.

16. The display substrate according to claim 15, wherein, The pixel driving circuit further includes a first transistor and a second transistor. The first terminal of the first transistor is connected to the first initialization signal line, the second terminal of the first transistor is connected to the second terminal of the driving transistor, the first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor. The display substrate further includes a second active layer between the first active layer and the third gate metal layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor.

17. The display substrate according to claim 15, wherein, The pixel driving circuit further includes a first transistor, a second transistor, and a ninth transistor. The first terminal of the first transistor is connected to the first initialization signal line, the second terminal of the first transistor is connected to the second terminal of the ninth transistor, the first terminal of the second transistor is connected to the second terminal of the driving transistor, and the second terminal of the second transistor is connected to the second terminal of the ninth transistor. The display substrate further includes a second active layer between the first active layer and the third gate metal layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor, and the second active portion is used to form the channel region of the second transistor.

18. A display device comprising a display substrate according to any one of claims 1 to 17.

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