Display substrate and display device

Abstract

A display substrate, comprising a substrate, a plurality of first light-emitting elements arranged on the substrate, a plurality of first pixel circuits, a plurality of second pixel circuits, a plurality of second light-emitting elements, and a plurality of first auxiliary traces. The plurality of first light-emitting elements are located in a first active area, and the plurality of first pixel circuits, the plurality of second pixel circuits, and the plurality of second light-emitting elements are located in a second active area. The second active area comprises a first sub-area located on at least one side of the first active area and a second sub-area located on at least one side of the first sub-area. The plurality of first pixel circuits are located in the first sub-area, and at least one first pixel circuit is connected to at least one first light-emitting element by means of at least one conductive connection line. The plurality of first auxiliary traces are located in the second sub-area, at least one first auxiliary trace and at least one conductive connection line are arranged in the same layer, and the plurality of first auxiliary traces are configured to receive a constant voltage signal.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411554445.4, filed on November 1, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a display substrate and a display device.

[0006] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of light-emitting elements, a plurality of pixel circuits, and a plurality of first auxiliary traces disposed on the substrate. The substrate includes a first display area and a second display area located at least one side of the first display area. The second display area includes: a first sub-area located at least one side of the first display area and a second sub-area located at least one side of the first sub-area. The plurality of light-emitting elements includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area. The plurality of first pixel circuits are located in the first sub-area. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements through at least one conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements. The at least one conductive connection line extends from the first sub-area to the first display area. Multiple first auxiliary traces are located in the second sub-area of ​​the second display area. At least one of the multiple first auxiliary traces is disposed on the same layer as the at least one conductive connection line, and the multiple first auxiliary traces are configured to receive constant voltage signals.

[0007] In some exemplary embodiments, at least one of the plurality of first auxiliary traces extends in the same direction as the at least one conductive connection line.

[0008] In some exemplary embodiments, the display substrate further includes: a plurality of second auxiliary traces located in the second sub-region, the extension directions of the plurality of second auxiliary traces intersecting the extension directions of the plurality of first auxiliary traces, and the plurality of second auxiliary traces and the plurality of first auxiliary traces being connected to form a mesh structure.

[0009] In some exemplary embodiments, the first auxiliary trace includes: a first main body extending along a first direction, a plurality of first extensions and a plurality of second extensions extending along a second direction, and a plurality of first auxiliary connection electrodes, wherein the second direction intersects the first direction; the plurality of second extensions are connected to the plurality of first auxiliary connection electrodes in a one-to-one correspondence, the plurality of first extensions and the plurality of second extensions are connected to the same side of the first main body and are arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary trace extending along the second direction.

[0010] In some exemplary embodiments, the plurality of second auxiliary traces and the plurality of first auxiliary traces are located on different conductive layers, and at least one insulating layer is disposed between the conductive layer where the first auxiliary traces are located and the conductive layer where the second auxiliary traces are located. The second auxiliary trace includes a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction. The second auxiliary connection electrode of the second auxiliary trace is connected to the first auxiliary connection electrode of the first auxiliary trace through an auxiliary transition hole formed in the insulating layer.

[0011] In some exemplary embodiments, the first sub-area is located on both sides of the first display area along the first direction, and the second sub-area includes: a first partition and a second partition located on both sides of the first sub-area along the first direction, and a third partition and a fourth partition located on both sides of the first display area along the second direction, wherein a plurality of auxiliary adapter holes in the first partition, the second partition, the third partition and the fourth partition are arranged in a V-shape.

[0012] In some exemplary embodiments, the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the first and second partitions along the first direction is greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the third and fourth partitions along the first direction; the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the first and second partitions along the second direction is greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the third and fourth partitions along the second direction.

[0013] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer and at least two conductive connection layers sequentially disposed on the substrate, wherein the material of the at least two conductive connection layers includes a transparent conductive material; the at least two conductive connection layers are provided with the at least one conductive connection line, and the first auxiliary trace and the second auxiliary trace are located in the two conductive connection layers and are located in different layers.

[0014] In some exemplary embodiments, the at least two conductive interconnect layers include: a first conductive interconnect layer, a second conductive interconnect layer, and a third conductive interconnect layer disposed sequentially along a direction away from the substrate; the first auxiliary trace is located in the first conductive interconnect layer, and the second auxiliary trace is located in the second conductive interconnect layer.

[0015] In some exemplary embodiments, multiple pixel circuits arranged along a first direction constitute a row of pixel circuits, and multiple pixel circuits arranged along a second direction constitute a column of pixel circuits, with the first direction intersecting the second direction. The circuit structure layer includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer sequentially disposed on the substrate. The first gate metal layer includes: multiple scan lines connected to a row of pixel circuits; the second gate metal layer includes: multiple first initial signal lines connected to a row of pixel circuits; the third source / drain metal layer includes: multiple data lines and multiple first data transfer lines, the multiple data lines and the multiple first data transfer lines being arranged at intervals along the first direction; the data lines are connected to a column of pixel circuits, and the orthographic projection of the first data transfer lines on the substrate overlaps with the orthographic projection of the column of pixel circuits on the substrate. The first auxiliary trace includes a first main body extending along the first direction, the orthographic projection of the first main body on the substrate located between the orthographic projections of the scan lines and the first initial signal lines connected to the row of pixel circuits on the substrate. The second auxiliary trace includes a second main body extending along the second direction, at least a portion of which, in the orthographic projection of the substrate, is located between the data line connected to a column of pixel circuits and a first data transfer line that overlaps with the orthographic projection of the column of pixel circuits on the substrate.

[0016] In some exemplary embodiments, the substrate further includes: a first frame region located on one side of the second display area, the first frame region being provided with a first peripheral power line and a plurality of power transfer electrodes, the plurality of second auxiliary traces being connected to the first peripheral power line through the plurality of power transfer electrodes.

[0017] In some exemplary embodiments, the display substrate further includes: a plurality of first power lines located in the second display area, the plurality of first power lines being arranged along a first direction and extending along a second direction, the first direction intersecting the second direction. The plurality of pixel circuits further includes: a plurality of invalid pixel circuits located in the second display area; the plurality of invalid pixel circuits arranged along the second direction form a column of invalid pixel circuits, the plurality of second pixel circuits arranged along the second direction form a column of second pixel circuits, and the plurality of first pixel circuits arranged along the second direction form a column of first pixel circuits. The power transfer electrode connected to the second auxiliary trace is located between the first power line connected to the column of invalid pixel circuits and the first power line connected to an adjacent column of second pixel circuits, or, located between the first power line connected to the column of invalid pixel circuits and the column of first pixel circuits aligned along the second direction and the first power line connected to an adjacent column of second pixel circuits.

[0018] In some exemplary embodiments, the substrate further includes a border region located on at least one side of the second display area, and the display substrate further includes a third auxiliary trace located in the border region, the third auxiliary trace being connected to the plurality of first auxiliary traces and configured to transmit a constant voltage signal.

[0019] In some exemplary embodiments, the at least one conductive connection line includes: a third main body portion extending along a first direction and a conductive connection portion extending along a second direction, the first direction intersecting the second direction; the conductive connection portion is connected to the first pixel circuit in the first sub-region, and the third main body portion is connected to the first light-emitting element in the first display area. The display substrate further includes: a plurality of fourth auxiliary traces located in the first sub-region and extending along the first direction, the plurality of fourth auxiliary traces being disposed on the same layer as the at least one conductive connection line, and the plurality of fourth auxiliary traces satisfying at least one of the following: located between the conductive connection portions of adjacent conductive connection lines, or located between the third main body portions of adjacent conductive connection lines.

[0020] On the other hand, this embodiment provides a display device, including a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the substrate of the display substrate at least partially overlaps with the orthographic projection of the first display area of ​​the display substrate onto the substrate.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0022] Overview of the attached figures

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 is a schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0026] Figure 3 is a schematic diagram of the pixel circuit layout of the second display area according to at least one embodiment of the present disclosure;

[0027] Figure 4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0028] Figure 5 is a partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 6A is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second sub-region of the second display area according to at least one embodiment of the present disclosure;

[0030] Figure 6B is a partial schematic diagram of the second sub-region of the second display area after the second gate metal layer is formed according to at least one embodiment of the present disclosure;

[0031] Figure 6C is a partial schematic diagram of the second sub-region of the second display area after the first source / drain metal layer is formed according to at least one embodiment of the present disclosure;

[0032] Figure 6D is a schematic diagram of the second sub-region of the second display area after the formation of the second source / drain metal layer in at least one embodiment of the present disclosure;

[0033] Figure 6E is a schematic diagram of the second sub-region of the second display area after the formation of the third source / drain metal layer in at least one embodiment of the present disclosure;

[0034] Figure 7A is a partial schematic diagram of the second sub-region of the second display area after the first conductive connection layer is formed according to at least one embodiment of the present disclosure;

[0035] Figure 7B is a schematic diagram of the first conductive connection layer in Figure 7A;

[0036] Figure 7C is a partial schematic diagram of the second sub-region of the second display area after the formation of the second conductive connection layer in at least one embodiment of the present disclosure;

[0037] Figure 7D is a schematic diagram of the second conductive connection layer in Figure 7C;

[0038] Figure 7E is a partial schematic diagram of the second sub-region of the second display area after the formation of the third conductive connection layer in at least one embodiment of the present disclosure;

[0039] Figure 8 is a partial schematic diagram of the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer of the second sub-region of at least one embodiment of the present disclosure;

[0040] Figure 9 is a schematic diagram of the arrangement of multiple auxiliary transition holes in the second sub-region of at least one embodiment of the present disclosure;

[0041] Figure 10A is a partial schematic diagram of the boundary between the display area and the first border area according to at least one embodiment of the present disclosure;

[0042] Figure 10B is a schematic diagram of the first gate metal layer and the second gate metal layer in the first border region B1 of Figure 10A;

[0043] Figure 10C is a schematic diagram of the second source / drain metal layer in Figure 10A;

[0044] Figure 10D is a schematic diagram of the second and third source / drain metal layers in Figure 10A;

[0045] Figure 10E is a schematic diagram of the third source / drain metal layer in Figure 10A;

[0046] Figure 10F is a schematic diagram of the second source / drain metal layer, the third source / drain metal layer and the first conductive connection layer in Figure 10A.

[0047] Figure 10G is a schematic diagram of the first conductive connection layer in Figure 10A;

[0048] Figure 10H is a schematic diagram of the second source / drain metal layer, the third source / drain metal layer, the first conductive connection layer and the second conductive connection layer in Figure 10A.

[0049] Figure 10I is a schematic diagram of the second conductive connection layer in Figure 10A;

[0050] Figure 11 is another partial plan view of the second display area according to at least one embodiment of the present disclosure;

[0051] Figure 12 is a partial plan view of the first sub-area of ​​the second display area of ​​at least one embodiment of the present disclosure;

[0052] Figure 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0053] Detailed Explanation

[0054] The embodiments of this application will now be described in detail with reference to the accompanying drawings. This application describes multiple embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0055] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0056] Furthermore, in describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0057] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0058] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly defined.

[0059] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the meaning of the above terms in this application according to the circumstances.

[0060] In this application, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0061] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0062] In this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the region through which current primarily flows.

[0063] In this application, the first electrode can be the drain and the second electrode can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this application, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control electrode.

[0064] In this application, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0065] In this application, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0066] In this application, "light transmittance" refers to the ability of light to pass through a medium, which is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0067] In this application, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this application, "same" means that the values ​​differ by no more than 10%.

[0068] In this application, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this application, "A extends along direction B" refers to "the main part of A extends along direction B."

[0069] With the continuous development of display technology, cameras are typically installed on display devices to meet the needs of photography or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, waterdrop displays, and in-display punch-hole displays have emerged. These technologies reduce the area occupied by the camera by creating a hole in a portion of the display area and placing the camera below the hole, thereby increasing the screen-to-body ratio. However, these technologies require removing part of the display area, resulting in some areas of the display being unreadable, thus hindering further improvements in screen-to-body ratio. To avoid punching holes in the display area and to make a true full-screen display possible while ensuring the practicality of the display substrate, an external pixel circuitry method is typically used in the under-display camera area. The external pixel circuitry method involves placing the pixel circuitry connected to the light-emitting element in the under-display camera area within the normal display area. By arranging the light-emitting element and pixel circuitry separately, the light transmittance of the under-display camera area is improved. Since no pixel circuitry is located in the under-display camera area, this area has no light-shielding layer other than the anode of the light-emitting element, achieving high light transmittance. However, the multiple light-emitting elements in the under-display camera area need to be connected to the multiple pixel circuits in the normal display area through multiple conductive connection lines. The environment of the multiple conductive connection lines varies depending on the setting position, which is not conducive to the uniformity of the arrangement of the conductive connection lines. In addition, there are problems such as poor etching uniformity and complicated signal compensation.

[0070] This embodiment provides a display substrate, including: a substrate, a plurality of light-emitting elements, a plurality of pixel circuits, and a plurality of first auxiliary traces disposed on the substrate. The substrate includes a first display area and a second display area located at least one side of the first display area. The second display area includes: a first sub-area located at least one side of the first display area, and a second sub-area located at least one side of the first sub-area. The plurality of light-emitting elements includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the second display area. The plurality of first pixel circuits are located in the first sub-area. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements through at least one conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements. The at least one conductive connection line extends from the first sub-area to the first display area. The plurality of first auxiliary traces are located in the second sub-area of ​​the second display area. At least one of the plurality of first auxiliary traces is disposed on the same layer as the at least one conductive connection line, and the plurality of first auxiliary traces are configured to receive a constant voltage signal.

[0071] In some examples, the first sub-region of the second display area can also be referred to as a transition area. Multiple first pixel circuits can be disposed in the first sub-region and electrically connected to multiple first light-emitting elements within the first display area via multiple conductive connection lines. The multiple conductive connection lines connected to the multiple first pixel circuits can extend from the first sub-region to the first display area and connect to the multiple first light-emitting elements within the first display area. In other words, multiple conductive connection lines can be disposed in both the first sub-region and the first display area.

[0072] The display substrate provided in this embodiment, by arranging multiple first auxiliary traces in the second sub-region of the second display area and disposed on the same layer as the conductive connection lines, can improve the uniformity of the trace etching of the conductive layer where the conductive connection lines are located, and help stabilize the circuit below the conductive layer where the conductive connection lines are located.

[0073] In some exemplary embodiments, at least one of the plurality of first auxiliary traces extends in the same direction as at least one conductive connection line. In some examples, the display substrate may include a plurality of conductive connection lines extending in the same direction, and the extension directions of the plurality of first auxiliary traces may be the same as the extension directions of the plurality of conductive connection lines. For example, both the plurality of first auxiliary traces and the plurality of conductive connection lines may extend along a first direction. In other examples, the display substrate may include a plurality of conductive connection lines extending in the same direction, and the extension directions of the plurality of first auxiliary traces may be different from the extension directions of the plurality of conductive connection lines. For example, the plurality of conductive connection lines may extend along a second direction, and the plurality of first auxiliary traces may extend along the first direction, with the first direction intersecting the second direction, for example, the first direction being perpendicular to the second direction. In still other examples, the display substrate may include two sets of conductive connection lines with intersecting extension directions, and the extension directions of the plurality of first auxiliary traces may be the same as the extension direction of one of the sets of conductive connection lines.

[0074] In some exemplary embodiments, the display substrate may further include: a plurality of second auxiliary traces located in the second sub-region, the extension directions of the plurality of second auxiliary traces intersecting the extension directions of the plurality of first auxiliary traces, and the plurality of second auxiliary traces and the plurality of first auxiliary traces may be connected to form a mesh structure. For example, the plurality of first auxiliary traces may extend along a first direction, and the plurality of second auxiliary traces may extend along a second direction. In this example, the plurality of first auxiliary traces and the plurality of second auxiliary traces are connected to form a mesh structure, which can improve the uniformity of trace etching in the conductive layer where the conductive interconnects are located.

[0075] In some exemplary embodiments, the first auxiliary trace may include: a first main body extending along a first direction, a plurality of first extensions and a plurality of second extensions extending along a second direction, and a plurality of first auxiliary connection electrodes, wherein the second direction intersects the first direction. The plurality of second extensions are connected one-to-one with the plurality of first auxiliary connection electrodes, and the plurality of first extensions and the plurality of second extensions are connected to the same side of the first main body and arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary trace extending along the second direction. In some examples, at least one insulating layer may be provided between the conductive layer containing the first auxiliary trace and the conductive layer containing the second auxiliary trace; the second auxiliary trace includes: a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction; the second auxiliary connection electrode of the second auxiliary trace can be connected to the first auxiliary connection electrode of the first auxiliary trace through an auxiliary transition hole formed in the insulating layer. This example, by providing an auxiliary transition hole, can improve the situation where the excessive gaps in the vias formed in the insulating layer within the second display area lead to inconsistent environments.

[0076] In some exemplary embodiments, the substrate may further include a border region located on at least one side of the second display area, and the display substrate may further include a third auxiliary trace located in the border region, the third auxiliary trace being connected to the plurality of first auxiliary traces and configured to transmit a constant voltage signal. This example, by providing a constant voltage signal to the plurality of first auxiliary traces through a third auxiliary trace in the border region, can help stabilize the underlying circuitry of the film layer containing the plurality of first auxiliary traces and the plurality of conductive interconnects.

[0077] In some exemplary embodiments, at least one conductive connection line may include: a third main body portion extending along a first direction and a conductive connection portion extending along a second direction; the conductive connection portion is connected to a first pixel circuit in a first sub-region, and the third main body portion is connected to a first light-emitting element in a first display area. The display substrate may further include: a plurality of fourth auxiliary traces located in the first sub-region and extending along the first direction, the plurality of fourth auxiliary traces being disposed on the same layer as the plurality of conductive connection lines, and the plurality of fourth auxiliary traces satisfying at least one of the following: located between the conductive connection portions of adjacent conductive connection lines, or located between the third main body portions of adjacent conductive connection lines. For example, the plurality of fourth auxiliary traces may be located between the conductive connection portions of adjacent conductive connection lines, or between the third main body portions of adjacent conductive connection lines, or between the conductive connection portions of adjacent conductive connection lines and between the third main body portions of adjacent conductive connection lines. This example, by arranging the fourth auxiliary traces within the intervals between conductive connection lines, can improve the consistency of the surrounding environment of the conductive connection lines, which is beneficial for optimizing the compensation rules for the conductive connection lines and improving the etching uniformity of the conductive connection lines.

[0078] The following examples illustrate the solution of this embodiment.

[0079] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the border area BB may include a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4 located around the display area AA. The first border area B1 and the second border area B2 may be located on opposite sides of the display area AA along a second direction D2, and the third border area B3 and the fourth border area B4 may be located on opposite sides of the display area AA along a first direction D1. Wherein, the first direction D1 intersects the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2. In some examples, the first border area B1 may be the lower border of the display substrate, the second border area B2 may be the upper border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate.

[0080] In some examples, as shown in Figure 1, the display area AA may include a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located at the top center of the display area AA, and the second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left or upper right corner of the display area AA, and the second display area A2 may surround at least one side of the first display area A1.

[0081] In some examples, as shown in Figure 1, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be a circle or an ellipse. However, this embodiment is not limited to this. For example, the first display area A1 can be a rectangle, a semicircle, a pentagon, or other shapes.

[0082] In some examples, the first display area A1 can be a light-transmitting display area, also known as an under-display camera (FDC) area, configured for image display and light transmission; the second display area A2 can be known as a normal display area, configured for image display. For example, the orthographic projection of a sensor (e.g., a camera, infrared sensor, etc.) onto the display substrate can be at least partially located within the first display area A1 of the display substrate. In some examples, as shown in FIG1, the first display area A1 can be circular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0083] In some examples, as shown in Figure 1, the pixel density of the first display area A1 may be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 may be approximately 0.8 to 1.2. This embodiment is not limited in this respect.

[0084] In some examples, the display substrate may include at least: a plurality of first light-emitting elements 31 located in the first display area A1, a plurality of second light-emitting elements 32 located in the second display area A2, and a plurality of pixel circuits. The plurality of pixel circuits located in the second display area A2 may include: a plurality of first pixel circuits 41, a plurality of second pixel circuits 42, and a plurality of invalid pixel circuits.

[0085] In some examples, at least one of the plurality of first pixel circuits 41 can be electrically connected to at least one of the plurality of first light-emitting elements 31 via conductive connection lines 51. The first pixel circuit 41 can be configured to provide a driving signal to the connected first light-emitting element 31 to drive the corresponding first light-emitting element 31 to emit light. For example, the plurality of first pixel circuits 41 and the plurality of first light-emitting elements 31 can have a one-to-one driving relationship or a one-to-many driving relationship. Since the first light-emitting elements 31 and the first pixel circuits 41 are located in different regions, the orthographic projection of at least one first pixel circuit 41 onto the substrate and the orthographic projection of at least one first light-emitting element 31 onto the substrate may not overlap.

[0086] In some examples, at least one of the plurality of second pixel circuits 42 may be electrically connected to at least one of the plurality of second light-emitting elements 32, and the orthographic projection of at least one second pixel circuit 42 onto the substrate and the orthographic projection of at least one second light-emitting element 32 onto the substrate may at least partially overlap. The second pixel circuit 42 may be configured to provide a driving signal to the connected second light-emitting element 32 to drive the corresponding second light-emitting element 32 to emit light. For example, the plurality of second pixel circuits 42 and the plurality of second light-emitting elements 32 may have a one-to-one driving relationship or a one-to-many driving relationship.

[0087] Figure 2 is a schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 3 is a schematic diagram of the pixel circuit arrangement of a second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 2 and 3, the second display area A2 may include: a first sub-area A21 and a second sub-area A22. The first sub-area A21 may be located on both sides of the first display area A1 along a first direction D1, and the second sub-area A22 may surround the first sub-area A1. The second sub-area A22 may include: a first partition A221 and a second partition A222 located on both sides of the second sub-area A21 along the first direction D1, and a third partition A223 and a fourth partition A224 located on both sides of the first sub-area A21 along a second direction D2. The third partition A223 and the fourth partition A224 are located on both sides of the first display area A1 along the second direction D2.

[0088] In some examples, the multiple pixel circuits of the second display area A2 may include: multiple first pixel circuits 41, multiple invalid pixel circuits 43, and multiple second pixel circuits 42. The multiple first pixel circuits 41 and multiple invalid pixel circuits 43 may be arranged at intervals along a first direction D1 between the multiple second pixel circuits 42. The multiple first pixel circuits 41 may be located in a first sub-region A21. The first sub-region A21 may also be referred to as a transition region. This example, by providing multiple invalid pixel circuits 43 in the second display area A2, can help improve the uniformity of components in multiple film layers during the etching process. For example, the invalid pixel circuit 43 may have a structure substantially the same as the first pixel circuit 41 in its row or column, except that it is not electrically connected to any light-emitting element.

[0089] In some examples, at least one first pixel circuit 41 can be electrically connected to at least one first light-emitting element 31 via conductive connection lines 51, and is configured to drive the at least one first light-emitting element 31 to emit light. For example, a single first light-emitting element 31 emitting a first color light (e.g., green G) within the first display area A1 can be driven by one first pixel circuit 41, a single first light-emitting element 31 emitting a second color light (e.g., red R) within the first display area A1 can be driven by one first pixel circuit 41, and a single first light-emitting element 31 emitting a third color light (e.g., blue B) within the first display area A1 can be driven by one first pixel circuit 41. In some examples, the first pixel circuit driving the first area light-emitting element 31 emitting the first color light can be located on the side of the first pixel circuit driving the first area light-emitting element 31 emitting the second and third color lights closer to the first display area A1. In some examples, the conductive connection lines 51 can be made of a transparent conductive material to improve the light transmittance of the display substrate. For example, multiple conductive connection lines 51 can be arranged within at least one conductive connection layer. In other examples, the two first light-emitting elements 31 that emit a first color light (e.g., green G) within the first display area A1 can be driven by the same first pixel circuit 41.

[0090] In some examples, since the second display area A2 is provided with not only a second pixel circuit 42 electrically connected to the second light-emitting element 32, but also a first pixel circuit 41 electrically connected to the first light-emitting element 31, the number of pixel circuits in the second display area A2 is greater than the number of second light-emitting elements 32. In some examples, the area for setting the newly added pixel circuit (including the first pixel circuit 41 and the invalid pixel circuit 43) can be obtained by reducing the size of the second pixel circuit 42 in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second light-emitting element in the first direction D1.

[0091] In this example, the multiple pixel circuits within the second display area A2 can be arranged in an array along the first direction D1 and the second direction D2. The original column of 'a' pixel circuits can be compressed along the first direction D1, thereby adding space for one more pixel circuit column. The space occupied by the original 'a' pixel circuit columns and the compressed 'a+1' pixel circuit columns can be the same. Here, 'a' can be an integer greater than 1. In some examples, 'a' can equal 4. That is, along the first direction D1, every four second pixel circuit columns 420 can be arranged with one first pixel circuit column 410 or one invalid pixel circuit column 430. However, this embodiment is not limited to this. For example, 'a' can equal 2 or 3.

[0092] In other examples, the original b pixel circuit rows can be compressed along the second direction D2 to add space for one more pixel circuit row, and the space occupied by the original b pixel circuit rows and the compressed b+1 pixel circuit rows is the same. Here, b can be an integer greater than 1. Alternatively, the area for setting the new pixel circuit can be obtained by reducing the size of the second pixel circuit along the first direction D1 and the second direction D2. In this example, the first sub-region can be located on both sides of the first display area along the second direction.

[0093] In this example, a pixel circuit column may include multiple pixel circuits arranged sequentially along the second direction D2. A pixel circuit row may include multiple pixel circuits arranged sequentially along the first direction D1. The multiple pixel circuits in a pixel circuit row may all be connected to the same gate line.

[0094] In some examples, within the second display area A2, multiple second pixel circuit columns 420, multiple first pixel circuit columns 410, and multiple invalid pixel circuit columns 430 can be arranged at intervals along a first direction D1. Each second pixel circuit column 420 (also referred to as a column of second pixel circuits) includes multiple second pixel circuits 42 arranged sequentially along a second direction D2; each first pixel circuit column 410 (also referred to as a column of first pixel circuits) includes multiple first pixel circuits 41 arranged sequentially along the second direction D2; and each invalid pixel circuit column 430 (also referred to as a column of invalid pixel circuits) includes multiple invalid pixel circuits 43 arranged sequentially along the second direction D2. For example, within the first sub-area A21, a first pixel circuit column 410 can be arranged at intervals of four second pixel circuit columns 420, and within the second sub-area A22, an invalid pixel circuit column 430 can be arranged at intervals of four second pixel circuit columns 420. Multiple invalid pixel circuit columns 430 in the third partition A223 and the fourth partition A224 of the second sub-region A22 can be aligned and arranged along the second direction D2, and multiple first pixel circuit columns 410 in the first sub-region A21 can be aligned and arranged along the second direction D2 with some invalid pixel circuit columns 430 in the third partition A223 and the fourth partition A224.

[0095] In some examples, multiple conductive connection lines 51 may extend at least along a first direction D1. The multiple conductive connection lines 51 may extend from the first display area A1 to a first sub-area A21 of the second display area A2 and connect to multiple first pixel circuits 41 within the first sub-area A21.

[0096] Figure 4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is illustrated using a 7T1C structure as an example. In some examples, as shown in Figure 4, the pixel circuit of this example may include a first transistor (also referred to as a first reset transistor) T1, a second transistor (also referred to as a threshold compensation transistor) T2, a third transistor (also referred to as a driving transistor) T3, a fourth transistor (also referred to as a data writing transistor) T4, a fifth transistor (also referred to as a first light-emitting control transistor) T5, a sixth transistor (also referred to as a second light-emitting control transistor) T6, a seventh transistor (also referred to as a second reset transistor) T7, and a storage capacitor Cst. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0097] In some examples, as shown in Figure 4, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 may be configured to provide a constant first power signal VDD to the pixel circuit, and the second power line PL2 may be configured to provide a constant second power signal VSS to the cathode of the light-emitting element EL, wherein the first power signal VDD is greater than the second power signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the pixel circuit in row j and the first reset control line RST1 electrically connected to the pixel circuit in row j+1 can be a single integrated structure. Here, j is an integer greater than 0. This reduces the number of signal lines on the display substrate, enabling a narrow bezel design.

[0098] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first power supply signal VDD and the second power supply signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0099] In some examples, as shown in Figure 4, the third transistor T3 is electrically connected to the light-emitting element EL and outputs a drive current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first power signal VDD, and second power signal VSS. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan line GL, the second terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the first terminal of the second transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The gates of the first transistor T1 and the third transistor T3 are electrically connected, and the third transistor T3 is configured to reset its gate. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL, and the seventh transistor T7 is configured to reset its anode. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0100] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0101] The operation of the pixel circuit illustrated in Figure 4 will be explained below. The explanation will take the example where all the transistors in the pixel circuit shown in Figure 4 are P-type transistors. In some examples, the operation of the pixel circuit during a single frame display period may include: a first stage, a second stage, and a third stage.

[0102] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting element EL does not emit light.

[0103] The second stage is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data line DL outputs the data signal DATA. During this stage, since the first electrode of the storage capacitor Cst is low, the third transistor T3 is turned on. The low-level scan signal SCAN turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage Vdata output by the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting element EL. This initializes (resets) the anode of the light-emitting element EL, clearing its internal pre-stored voltage and completing the initialization process, ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first transistor T1 to turn off. The light emission control signal EM provided by the light emission control line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0104] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control line EML is low-level, the fifth transistor T5 and the sixth transistor T6 are turned on. The first power supply signal VDD output by the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0105] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0106] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0107] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first power signal output by the first power line PL1.

[0108] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0109] Figure 5 is a partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 5 illustrates the structure of a second light-emitting element and a second pixel circuit in the second display area as an example. In this example, the multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit may all be low-temperature polycrystalline silicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OTS). In other examples, the multiple transistors in the pixel circuit may be both LPS and OTS.

[0110] In some examples, as shown in Figure 5, the second display area of ​​the display substrate may include, in a direction perpendicular to the display substrate, a substrate 10, and a circuit structure layer 11, three conductive connection layers 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 11 of the second display area may include at least a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of invalid pixel circuits, each pixel circuit including a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 of the second display area may include at least a plurality of second light-emitting elements.

[0111] In some examples, Figure 5 illustrates a second pixel circuit comprising a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first and second gate metal layers; an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 104 and a first planarization layer 105 may be disposed between the first and second source / drain metal layers; a second planarization layer 106 may be disposed between the second and third source / drain metal layers; and a third planarization layer 107 may be disposed on the side of the third source / drain metal layer away from the substrate 10. In this embodiment, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 can be inorganic insulating layers, while the first planarization layer 105, the second planarization layer 106, and the third planarization layer 107 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer. In other examples, the circuit structure layer may omit the third source / drain metal layer, or the circuit structure layer may include a fourth source / drain metal layer located on the side of the third source / drain metal layer away from the substrate.

[0112] In some examples, as shown in Figure 5, the three conductive interconnect layers 12 may include a first conductive interconnect layer, a second conductive interconnect layer, and a third conductive interconnect layer disposed sequentially along the direction of the substrate 10. A fourth planarization layer 108 may be disposed between the first and second conductive interconnect layers, a fifth planarization layer 109 may be disposed between the second and third conductive interconnect layers, and a sixth planarization layer 110 may be disposed on the side of the third conductive interconnect layer away from the substrate 10. The fourth planarization layer 108, the fifth planarization layer 109, and the sixth planarization layer 110 may be organic insulating layers. In some examples, the first, second, and third conductive interconnect layers may be made of transparent conductive materials, such as indium tin oxide (ITO).

[0113] In some examples, as shown in FIG5, the semiconductor layer of the second display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 10 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 104 and the first planarization layer 105. The third source-drain metal layer may include at least a second transition electrode 232, which can be connected to the first transition electrode 231 through a fourth pixel via formed by the second planarization layer 106. The first conductive connection layer may include at least a third transition electrode 233, which can be connected to the second transition electrode 232 through a fifth pixel via formed by the third planarization layer 107. The second conductive connection layer may include at least a fourth transition electrode 234, which can be connected to the third transition electrode 233 through a sixth pixel via formed by the fourth planarization layer 108. The third conductive connection layer may include at least a fifth transition electrode 235, which can be connected to the fourth transition electrode 234 through a seventh pixel via formed by the fifth planarization layer 109. In some examples, the orthographic projection of the fifth pixel via, the sixth pixel via, and the seventh pixel via onto the substrate can be rectangular or circular.For example, the orthographic projections of the seventh pixel via and the fifth pixel via on the substrate may coincide, while the orthographic projections of the sixth pixel via and the seventh pixel via on the substrate may not coincide. This example can achieve the electrical connection between the pixel circuit and the light-emitting element through a second source / drain metal layer, a third source / drain metal layer, and three conductive connection layers. However, this embodiment is not limited to this. In other examples, the number of conductive connection layers may be one, two, or more.

[0114] In some examples, the orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can be rectangular. The orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can overlap, and can at least partially overlap with the orthographic projection of the second adapter electrode 232 onto the substrate.

[0115] In some examples, as shown in FIG5, the light-emitting structure layer 13 of the display area may include: a pixel definition layer 304 and a plurality of light-emitting elements (e.g., a plurality of second light-emitting elements located in the second display area and a plurality of first light-emitting elements located in the first display area). For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. For example, the first electrode 301 of the second light-emitting element located in the second display area A2 may be disposed on the fifth planarization layer 110 and electrically connected to the fifth transition electrode 235 through an eighth pixel via formed in the fifth planarization layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth planarization layer 110. The pixel definition layer 304 may have a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of the corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer can also be provided on the side of the pixel definition layer 304 away from the substrate 10, and the isolation pillar layer can include multiple isolation pillars (PS).

[0116] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0117] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0118] In some examples, as shown in Figure 5, the encapsulation structure layer 14 may include a first encapsulation layer 1401, a second encapsulation layer 1402, and a third encapsulation layer 1403 stacked together. The first encapsulation layer 1401 and the third encapsulation layer 1403 may be made of inorganic materials, while the second encapsulation layer 1402 may be made of organic materials. The second encapsulation layer 1402 may be disposed between the first encapsulation layer 1401 and the third encapsulation layer 1403 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0119] The following is an example illustrating the film structure of the second sub-region of the second display area. Figures 6A to 7D illustrate a row (e.g., row j) and three columns (e.g., columns i-1 to i+1) of pixel circuits in the second sub-region of the second display area. Figures 6A to 7D can be magnified views of region S1 in Figure 1. Columns i-1 to i+1 are all second pixel circuit columns, where i is a positive integer. In this example, within the second display area, every four columns of second pixel circuits are arranged a column of first pixel circuits or a column of invalid pixel circuits. The equivalent circuit diagram of the second pixel circuit can be shown in Figure 4, and may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0120] Figure 6A is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second sub-region of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6A, the semiconductor layer of the second sub-region may include: an active layer of multiple transistors of multiple second pixel circuits (e.g., an active layer including first transistor T1 to seventh transistor T7). The active layers of the first transistors T1 to seventh transistor T7 of a single second pixel circuit may be an integral structure interconnected with each other.

[0121] In some examples, as shown in FIG6A, the first gate metal layer of the second sub-region may include: gates of multiple transistors of multiple second pixel circuits (e.g., gates of first transistor T1 to seventh transistor T7), multiple scan lines (e.g., scan line GL(j)), multiple first reset control lines (e.g., first reset control line RST1(j)), and multiple light emission control lines (e.g., light emission control line EML(j)). The scan line GL(j), the first reset control line RST1(j), and the light emission control line EML(j) may all extend along the first direction D1; for example, the scan line GL(j) and the first reset control line RST1(j) may be zigzag lines extending along the first direction D1, and the light emission control line EML(j) may be a straight line extending along the first direction D1.

[0122] In some examples, the first reset control line RST1(j) connected to the pixel circuit in row j can serve as the second reset control line connected to the pixel circuit in row (j-1). The scan line GL(j), the gate of the second transistor T2, and the gate of the fourth transistor T4 in the second pixel circuit located in row j can be an integrally connected structure. The first reset control line RST1(j) and the gate of the first transistor T1 in the second pixel circuit located in row j can be an integrally connected structure. The light emission control line EML(j), the gate of the fifth transistor T5, and the gate of the sixth transistor T6 in the second pixel circuit located in row j can be an integrally connected structure. The gate of the third transistor T3 in the second pixel circuit can simultaneously serve as the first electrode of the storage capacitor in the second pixel circuit.

[0123] Figure 6B is a partial schematic diagram of a second sub-region of a second display area after the formation of a second gate metal layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6B, the second gate metal layer of the second sub-region may include: multiple first initial signal lines (e.g., including first initial signal line INIT1(j)), multiple second initial signal lines (e.g., including second initial signal line INIT2(j-1)), and the second electrodes of the storage capacitors Cst of multiple second pixel circuits located in the same row. The second electrodes of the storage capacitors Cst of multiple second pixel circuits located in the same row may be an integral structure interconnected with each other. The multiple first initial signal lines and the multiple second initial signal lines may extend along a first direction D1, for example, they may be zigzag lines extending along the first direction D1.

[0124] Figure 6C is a partial schematic diagram of a second sub-region of a second display area after the formation of a first source / drain metal layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6C, the first source / drain metal layer of the second sub-region may include: a plurality of pixel connection electrodes (e.g., including first pixel connection electrodes 401 to sixth pixel connection electrodes 406) and a plurality of first transmission lines 55.

[0125] In some examples, the first transmission line 55 may be located between two adjacent rows of pixel circuits (e.g., row j and row j+1 pixel circuits) and extend along the first direction D1. The first transmission line 55 may be connected to the pixel connection electrode to which the invalid pixel circuit is connected to form a power transmission network to facilitate electrostatic discharge in the second display area.

[0126] In some examples, the active layer of the first transistor T1 in the second pixel circuit located in row j can be connected to the first initial signal line INIT1(j) through the first pixel connection electrode 401; the gate of the third transistor T3 can be connected to the active layer of the second transistor T2 through the second pixel connection electrode 402; the active layer of the fourth transistor T4 can be connected to the fourth pixel connection electrode 404; the active layer of the fifth transistor T5 can be connected to the second electrode of the storage capacitor Cst through the third pixel connection electrode 403; and the active layer of the sixth transistor T6 can be connected to the fifth pixel connection electrode 405. The active layer of the seventh transistor T7 in the second pixel circuit located in row j-1 can be connected to the second initial signal line INIT2(j-1) through the sixth pixel connection electrode 406.

[0127] In some examples, the orthographic projection of the first pixel connection electrode 401 onto the substrate can be approximately rectangular and annular. The orthographic projection of the second pixel connection electrode 402 onto the substrate can be approximately a broken line extending along the second direction D2. The orthographic projection of the third pixel connection electrode 403 onto the substrate can be approximately a strip extending along the second direction D2. The orthographic projection of the fourth pixel connection electrode 404 onto the substrate can be approximately rectangular. The orthographic projection of the fifth pixel connection electrode 405 onto the substrate can be approximately rectangular. The orthographic projection of the sixth pixel connection electrode 406 onto the substrate can be approximately a dumbbell shape extending along the second direction D2. In this example, the shapes of the multiple pixel connection electrodes connected to the invalid pixel circuit can be approximately the same as the shapes of the multiple pixel connection electrodes connected to the second pixel circuit, thereby improving the uniformity of the first source / drain metal layer during the etching process.

[0128] Figure 6D is a schematic diagram of a second sub-region of a second display area after the formation of a second source / drain metal layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6D, the second source / drain metal layer of the second sub-region may include: multiple first power lines (e.g., first power line PL1a) and multiple transition electrodes (e.g., including a first transition electrode 231 and a sixth transition electrode 236). The multiple first power lines PL1a may extend along the second direction D2, for example, they may be in a zigzag shape extending along the second direction D2. For example, a first power line PL1a may be connected to a third pixel connection electrode 403 to achieve connection with the second electrode of the active layer of the fifth transistor T5 of the second pixel circuit and the storage capacitor Cst. A first power line connected to an invalid pixel circuit may be connected to a first transmission line 55 to form a power transmission network.

[0129] In some examples, the sixth transition electrode 236 can be connected to the fourth pixel connection electrode 404 to achieve an active layer connection with the fourth transistor T4 of the second pixel circuit. The first transition electrode 231 can be connected to the fifth pixel connection electrode 405 to achieve an active layer connection with the sixth transistor T4 of the second pixel circuit.

[0130] Figure 6E is a schematic diagram of a second sub-region of the second display area after the formation of the third source / drain metal layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6E, the third source / drain metal layer of the second sub-region may include: multiple first data transfer lines 56, multiple data lines (e.g., including data line DLa), and multiple transfer electrodes (e.g., including second transfer electrodes 232). The multiple first data transfer lines 56 and the multiple data lines DLa may extend along the second direction D2 and be spaced apart along the first direction D1. For example, the data line DLa may be connected to the sixth transfer electrode 236 to achieve electrical connection with the second pixel circuit and be configured to provide data signals to the second pixel circuit.

[0131] In some examples, the first data adapter cable 56 can be connected to a second data adapter cable extending along the first direction D1, and connected to data lines near the third or fourth bezel area via the second data adapter cable extending along the first direction D1. This allows data lines near the third or fourth bezel area to access the first bezel area from a position away from the third or fourth bezel area via the second data adapter cable and the first data adapter cable 56. For example, the second data adapter cable can be located between adjacent row pixel circuits. The first data adapter cable 56 extends to the first bezel area, allowing the traces transmitting data signals within the first bezel area to be centrally arranged in the middle of the display substrate, thereby reducing the size of the first bezel area and facilitating a narrow bezel design.

[0132] In some examples, the second adapter electrode 232 can be connected to the first adapter electrode 231 to achieve an electrical connection with the second pixel circuit. In this example, the second adapter electrode 232 can be connected to the anode of the second light-emitting element to achieve an electrical connection between the second pixel circuit and the second light-emitting element.

[0133] Figure 7A is a partial schematic diagram of the second sub-region of the second display area after the formation of the first conductive connection layer according to at least one embodiment of the present disclosure. Figure 7B is a schematic diagram of the first conductive connection layer in Figure 7A. Figure 7C is a partial schematic diagram of the second sub-region of the second display area after the formation of the second conductive connection layer according to at least one embodiment of the present disclosure. Figure 7D is a schematic diagram of the second conductive connection layer in Figure 7C. Figure 7E is a partial schematic diagram of the second sub-region of the second display area after the formation of the third conductive connection layer according to at least one embodiment of the present disclosure. Figure 8 is a partial schematic diagram of the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer of the second sub-region according to at least one embodiment of the present disclosure.

[0134] In some examples, as shown in Figures 7A, 7B, and 8, the first conductive connection layer of the second sub-region may include: multiple first auxiliary traces 61 and multiple transition electrodes (e.g., including a third transition electrode 233). The multiple first auxiliary traces 61 are arranged along a second direction D2. Each first auxiliary trace 61 may include: a first main body portion 611 extending along a first direction D1, multiple first extension portions 612 and multiple second extension portions 613 extending along the second direction D2, and multiple first auxiliary connection electrodes 614. The multiple first extension portions 612 may be connected one-to-one with the multiple first auxiliary connection electrodes 614. The multiple first extension portions 612, multiple second extension portions 613, and multiple first auxiliary connection electrodes 614 may be connected to the same side of the first main body portion 611 along the second direction D2. The first main body portion 611, the multiple first extension portions 612, the multiple second extension portions 613, and the multiple first auxiliary connection electrodes 614 are an integral structure.

[0135] In some examples, the orthographic projection of the first extension 612 and the second extension 613 onto the substrate can be approximately a broken line extending along the second direction D2. The orthographic projection of the first auxiliary connection electrode 614 onto the substrate can be approximately rectangular. The first extension 612 and the second extension 613 of the same first auxiliary trace 61 can be arranged at intervals along the first direction D2. Along the second direction D2, the first extensions 612 and the second extensions 613 of multiple first auxiliary traces 61 can be aligned.

[0136] In some examples, as shown in Figures 7A and 7B, the orthographic projection of the first main body 611 onto the substrate can lie between the orthographic projections of the scan line GL(j) and the first initial signal line INIT1(j) onto the substrate, and the orthographic projections of the first main body 611 and the first initial signal line INIT1(j) onto the substrate can partially overlap. In other examples, the orthographic projections of the first main body 611 and the first initial signal line INIT1(j) onto the substrate may not overlap. This arrangement can reduce the increased trace load caused by trace overlap.

[0137] In some examples, as shown in Figures 7A, 7B, and 8, the orthographic projection of the first extension 612 (or the second extension 613) onto the substrate may partially overlap with the orthographic projection of the storage capacitor Cst of the second pixel circuit onto the substrate. The orthographic projection of the first auxiliary connection electrode 614 onto the substrate may at least partially overlap with the orthographic projection of the connection location of the fifth transistor and the first power line PL1a of the second pixel circuit onto the substrate.

[0138] In some examples, as shown in Figure 7A, a single first auxiliary connection electrode 614 can be located between two adjacent third transition electrodes 233 along a first direction D1. The first auxiliary connection electrode 614 can be aligned with the adjacent third connection electrode 233 along the first direction D1. The third transition electrode 233 can be connected to the second transition electrode 232 to achieve electrical connection with the pixel circuit.

[0139] In some examples, as shown in Figures 7C, 7D, and 8, the second conductive connection layer of the second sub-region may include: multiple second auxiliary traces 62 and multiple transition electrodes (e.g., including a fourth transition electrode 234). As shown in Figures 7E and 8, the third conductive connection layer of the second sub-region may include: multiple transition electrodes (e.g., including a fifth transition electrode 235).

[0140] In some examples, as shown in Figures 7C, 7D, and 8, multiple second auxiliary traces 62 can extend along a second direction D2 and be arranged along a first direction D1. The second auxiliary traces 62 can include a second main body 621 extending along the second direction D2 and multiple second auxiliary connection electrodes 622. The second main body 621 and the multiple second auxiliary connection electrodes 622 are an integral structure. The orthographic projection of the second main body 621 onto the substrate can be a broken line extending along the second direction D2. The orthographic projection of the second main body 621 onto the substrate can lie between the orthographic projections of the data line DLa connected to a second pixel circuit column and the first data transfer line 56 arranged in the second pixel circuit column onto the substrate. The orthographic projection of the second main body 621 onto the substrate and the orthographic projections of the data line DLa connected to the second pixel circuit column and the first data transfer line 56 arranged in the second pixel circuit column onto the substrate may not overlap. This example arrangement can reduce the increased trace load caused by trace overlap.

[0141] In some examples, the orthographic projection of the second auxiliary connection electrode 622 onto the substrate can be rectangular. A single second auxiliary connection electrode 622 can be located between two adjacent fourth transition electrodes 234 along the first direction D1. The second auxiliary connection electrode 622 can be aligned with the adjacent fourth transition electrodes 234 along the first direction D1. The orthographic projection of the second auxiliary connection electrode 622 onto the substrate can cover the orthographic projection of the first auxiliary connection electrode 614 onto the substrate. The fourth transition electrode 234 can be connected to the third transition electrode 233 to achieve electrical connection with the pixel circuit.

[0142] In some examples, multiple first auxiliary traces 61 and multiple second auxiliary traces 62 can be connected in a mesh structure in the second sub-region A22. The insulating layer disposed between the second conductive connection layer and the first conductive connection layer can be a fourth planarization layer 108 (as shown in Figure 5). The fourth planarization layer 108 can be provided with multiple auxiliary transition holes K1. The second auxiliary connection electrode 621 can be electrically connected to the first auxiliary connection electrode 614 through at least one auxiliary transition hole K1.

[0143] Figure 9 is a schematic diagram of the arrangement of multiple auxiliary adapter holes in the second sub-region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 9, the first sub-region A21 is located on both sides of the first display area A1 along the first direction D1. The second sub-region A22 may include: a first partition A221 and a second partition A222 located on both sides of the second sub-region A21 along the first direction D1, and a third partition A223 and a fourth partition A224 located on both sides of the first sub-region A21 along the second direction D2. The third partition A223 and the fourth partition A224 are located on both sides of the first display area A1 along the second direction D2.

[0144] In some examples, within the first partition A221 and the second partition A222, multiple auxiliary adapter holes K1 can be arranged in a V-shape; the V-shaped arrangement of the multiple auxiliary adapter holes K1 within the first partition A221 and the second partition A222 is roughly the same. Within the third partition A223 and the fourth partition A224, multiple auxiliary adapter holes K1 can be arranged in a V-shape, and the V-shaped arrangement of the multiple auxiliary adapter holes K1 within the third partition A223 is roughly the same. The size of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 within the first partition A221 can be larger than the size of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 within the third partition A223. In this example, the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 in the first partition A221 along the first direction D1 can be greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 in the third partition A223 along the first direction D1; similarly, the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 in the first partition A221 along the second direction D2 can be greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes K1 in the third partition A223 along the second direction D2. This configuration ensures that the first auxiliary traces corresponding to each row of pixel circuits in the second sub-region can be connected to the same number of second auxiliary traces. That is, each row of pixel circuits can correspond to an adjacent number of auxiliary adapter holes, thus ensuring the uniformity of the arrangement of auxiliary adapter holes in the second sub-region.

[0145] This example uses multiple auxiliary adapter holes to not only achieve a mesh connection of multiple first auxiliary traces and multiple second auxiliary traces, but also to improve the situation where the via gaps between adjacent third adapter electrodes (or fourth adapter electrodes, or fifth adapter electrodes) located on the same conductive connection layer in each row of pixel circuits are too large, resulting in inconsistent opening environments.

[0146] Figure 10A is a partial schematic diagram of the boundary between the display area and the first border area according to at least one embodiment of the present disclosure. Figure 10A can be a partially enlarged schematic diagram of region S2 in Figure 1. Figure 10A illustrates the second source / drain metal layer, the third source / drain metal layer, the first conductive connection layer, the second conductive connection layer, and the third conductive connection layer as examples, omitting the other film layers. Figure 10A illustrates a portion of the film layers corresponding to two rows (e.g., row j-1 and row j) and nine columns (e.g., columns i-2 to i+6) of pixel circuits in the second sub-region of the second display area. For example, the pixel circuits in columns i-2 and i+3 include multiple invalid pixel circuits, and the pixel circuits in columns i-1 to i+2 and columns i+4 to i+6 include multiple second pixel circuits. In this example, every four columns of second pixel circuits can be arranged with one invalid pixel circuit column or one first pixel circuit column. For example, the pixel circuits in columns i-2 and i+3 can be invalid pixel circuit columns located in the first partition of the second sub-region of the second display area. In some examples, the data lines connected to the first pixel circuit column in the first sub-region and the data lines connected to the invalid pixel circuit column aligned in the second sub-region can be disconnected. The data lines connected to the first pixel circuit column can be jumpered to the data lines connected to a second pixel circuit column aligned in the second direction with the first light-emitting element connected to the first pixel circuit column. The first pixel circuit column in the first sub-region and the invalid pixel circuit column aligned in the second sub-region can be connected to the same first power line.

[0147] Figure 10B is a schematic diagram of the first and second gate metal layers in the first border region B1 of Figure 10A. Figure 10C is a schematic diagram of the second source / drain metal layer in Figure 10A. Figure 10D is a schematic diagram of the second and third source / drain metal layers in Figure 10A. Figure 10E is a schematic diagram of the third source / drain metal layer in Figure 10A. Figure 10F is a schematic diagram of the second, third, and first conductive interconnect layers in Figure 10A. Figure 10G is a schematic diagram of the first conductive interconnect layer in Figure 10A. Figure 10H is a schematic diagram of the second, third, first, and second conductive interconnect layers in Figure 10A. Figure 10I is a schematic diagram of the second conductive interconnect layer in Figure 10A.

[0148] In some examples, as shown in Figures 10A and 10B, the first gate metal layer of the first border region B1 may include multiple first data leads 581, and the second gate metal layer of the first border region B1 may include multiple second data leads 582. The multiple first data leads 581 and the multiple second data leads 582 may be arranged at intervals along a first direction D1. The orthographic projections of the multiple first data leads 581 onto the substrate and the orthographic projections of the multiple second data leads 582 onto the substrate may not overlap.

[0149] In some examples, as shown in Figures 10A and 10C, the second source / drain metal layer may include: multiple first power lines (e.g., first power lines PL1a and PL1b) located in the second sub-region, multiple transition electrodes (e.g., first transition electrode 231 and sixth transition electrode 236), and a first peripheral power line 71, multiple first power connection electrodes 711, multiple second power connection electrodes 712, and multiple data transition electrodes 731a and 731b located in the first border region B1. The first peripheral power line 71 may be configured to transmit a first power signal.

[0150] In some examples, first power lines PL1a and PL1b may extend along the second direction D2. First power line PL1a may be connected to a second pixel circuit column, and first power line PL1b may be connected to an invalid pixel circuit column, or a first pixel circuit column and an aligned invalid pixel circuit column. For example, a first pixel circuit column located in the first sub-region and an invalid pixel circuit column aligned within the third and fourth sub-regions may be connected to the same first power line PL1b. First power lines PL1a and PL1b may extend to the first border region B1 and connect to the first peripheral power line 71. The first peripheral power line 71 may extend at least along the first direction D1. First power line PL1a and the first peripheral power line 71 may be an integral structure, and first power line PL1b and the first peripheral power line 71 may be an integral structure.

[0151] In some examples, the first power line PL1b can be connected to a first power connection electrode 711 in the first border region B1. For example, the first power line PL1b and the first power connection electrode 711 can be an integral structure. The orthographic projection of the first power connection electrode 711 onto the substrate can be a rectangle extending along the first direction D1. The first power connection electrode 711 can be located between the connected first power line PL1b and an adjacent first power line PL1a along the first direction D1.

[0152] In some examples, the second power connection electrode 712 may be connected to the first peripheral power line 71. For example, the second power connection electrode 712 and the first peripheral power line 71 may be an integral structure. The orthographic projection of the second power connection electrode 712 onto the substrate may be a rectangle extending along the second direction D2. The second power connection electrode 712 may be located between the first power line PL1b and the adjacent first power line PL1a along the first direction D1, and on the side of the first power connection electrode 711 away from the display area.

[0153] In some examples, within the first border region B1, multiple data transfer electrodes 731a and 731b may be located on the side of the first peripheral power line 71 closest to the display area. Two data transfer electrodes 731a and 731b may be disposed between two adjacent first power lines PL1a, or between a first power line PL1a and an adjacent first power line PL1b along the first direction D1. The two data transfer electrodes 731a and 731b may be arranged along the second direction D2.

[0154] In some examples, data transfer electrode 731a can be connected to the first data lead 581 located on the second gate metal layer through vias formed in the interlayer insulating layer 103 (as shown in FIG. 5), and data transfer electrode 731b can be connected to the second data lead 582 located on the first gate metal layer through vias formed in the interlayer insulating layer 103 and the second gate insulating layer 102 (as shown in FIG. 5). In this way, multiple data transfer electrodes 731a can be connected to multiple first data leads 581 located on the second gate metal layer, and multiple data transfer electrodes 731b can be connected to multiple second data leads 582 located on the first gate metal layer, thereby realizing the transmission of data signals.

[0155] In some examples, as shown in Figures 10A, 10D, and 10E, the third source / drain metal layer may include: multiple data lines (e.g., data lines DLa and DLb) located in the second sub-region, multiple first data transfer lines 56, multiple invalid data transfer lines 57, multiple transfer electrodes (e.g., second transfer electrode 232), and a second peripheral power line 72 and multiple third power connection electrodes 713 located in the first border region B1. The second peripheral power line 72 is configured to transmit a second power signal. The second peripheral power line 72 may extend at least along a first direction D1 within the first border region B1. The orthographic projection of the second peripheral power line 72 onto the substrate may at least partially overlap with the orthographic projection of the first peripheral power line 71 onto the substrate.

[0156] In some examples, data lines DLa and DLb may extend along the second direction D2. Data line DLa may be connected to a column of second pixel circuits, and data line DLb may be connected to a column of invalid pixel circuits. Data lines DLa and DLb may extend to the first border region B1. Data line DLa may be electrically connected to the data transfer electrode 731a (or 731b) within the first border region B1.

[0157] In some examples, the orthographic projection of the first data transfer line 56 onto the substrate may overlap with the orthographic projection of a column of second pixel circuits onto the substrate, and the orthographic projection of the invalid data transfer line 57 onto the substrate may overlap with the orthographic projection of a column of invalid pixel circuits onto the substrate. The first data transfer line 56 and the invalid data transfer line 57 may extend to the first border region B1, and the first data transfer line 56 may be electrically connected to the data transfer electrode 731b (or 731a) within the first border region B1.

[0158] In some examples, the data line DLb connected to a column of invalid pixel circuits and the invalid data transfer line 57 overlapping with the orthographic projection of the column of invalid pixel circuits on the substrate can be connected in the first border region B1 and electrically connected to the first power line PL1b connected to the column of invalid pixel circuits via the first power connection electrode 711. The data line DLb connected to a column of invalid pixel circuits and the invalid data transfer line 57 overlapping with the orthographic projection of the column of invalid pixel circuits on the substrate can be an integral structure.

[0159] In some examples, the data line DLa connected to the i-th column pixel circuit can be connected to a data transfer electrode 731b in the first border area B1, and the first data transfer line 56 located in the i-th column pixel circuit can be connected to a data transfer electrode 731a in the first border area B1.

[0160] In some examples, the orthographic projection of the third power connection electrode 713 onto the substrate can be a rectangle extending along the second direction D2. The third power connection electrode 713 can be electrically connected to the second power connection electrode 712.

[0161] In some examples, as shown in Figures 10A, 10F, and 10G, the first conductive connection layer may include: multiple first auxiliary traces 61 located in the second sub-region, multiple transition electrodes (e.g., including a third transition electrode 233), and multiple fourth power connection electrodes 714 located in the first border region B1. The orthographic projection of the fourth power connection electrode 714 onto the substrate is a rectangle extending along the first direction D1. The fourth power connection electrode 714 may be electrically connected to the third power connection electrode 713.

[0162] In some examples, as shown in Figures 10A, 10H, and 10I, the second conductive connection layer may include: multiple second auxiliary traces 62 located in the second sub-region, multiple transition electrodes (e.g., including a fourth transition electrode 234), and multiple power connection lines 715 located in the first border region B1. The power connection lines 715 may extend along a third direction that intersects both the first direction D1 and the second direction D2. The power connection lines 715 are connected to the second auxiliary traces 62 and the fourth power connection electrode 714. The power connection lines 715 and the second auxiliary traces 62 may be an integral structure and connected to the fourth power connection electrode 714 through a via formed in the fourth planarization layer between the second conductive connection layer and the first conductive connection layer. The second auxiliary traces 62 may be electrically connected to the first peripheral power line 71 through the power connection lines 715, the fourth power connection electrode 714, the third power connection electrode 713, and the second power connection electrode 712, such that the mesh structure formed by the second auxiliary traces 62 and the first auxiliary traces 61 receives a constant first power signal. In this example, the multiple power transfer electrodes connected to the second auxiliary trace 62 may include a second power connection electrode, a third power connection electrode, and a fourth power connection electrode. For example, the second power connection electrode 712, the third power connection electrode 713, and the fourth power connection electrode 714 may be located between the first power line PL1b connected to a column of invalid pixel circuits (e.g., the i-2th column) (or a column of invalid pixel circuits aligned along the second direction and a column of first pixel circuits) and the adjacent first power line PL1a along the first direction D1. The second auxiliary trace 62 may be located within the area of ​​a column of second pixel circuits (e.g., the i-th column). In other examples, the power transfer electrodes connected to the second auxiliary trace 62 may include a second power connection electrode, and the fourth and third power connection electrodes may be omitted. The power connection line 715 located in the second conductive connection layer may be directly electrically connected to the second power connection electrode located in the second source / drain metal layer through vias formed in the fourth planarization layer, the third planarization layer, and the second planarization layer. This embodiment is not limited in this respect.

[0163] In some examples, as shown in Figure 10A, the third conductive connection layer may include a plurality of transition electrodes (e.g., including a fifth transition electrode 235) located in the second sub-region. The fifth transition electrode 235 may be connected to the fourth transition electrode 234.

[0164] In this example, the mesh structure formed by connecting multiple first auxiliary lines 61 and multiple second auxiliary lines 62 is connected to the first peripheral power line 71 and configured to receive a constant voltage first power signal. In other examples, the mesh structure formed by connecting multiple first auxiliary lines and multiple second auxiliary lines can be connected to the second peripheral power line and configured to receive a constant voltage second power signal.

[0165] The arrangement of multiple first auxiliary traces and multiple second auxiliary traces in this example can help improve the circuit stability beneath the conductive interconnect layer. Furthermore, the placement of the second to fourth power connection electrodes between the first power line connected to a column of invalid pixel circuits (or a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction) and the first power line connected to an adjacent column of second pixel circuits can compensate for uneven via density in the planarization layer between the first power line connected to the column of invalid pixel circuits (or a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction) and the first power line connected to the adjacent column of second pixel circuits, thereby reducing the risk of defects.

[0166] Figure 11 is another partial planar schematic diagram of the second display area according to at least one embodiment of the present disclosure. Figure 11 can be a partially enlarged schematic diagram of region S3 in Figure 1. Figure 11 illustrates a conductive connection layer (e.g., a third conductive connection layer) of the second sub-region as an example. In some examples, as shown in Figure 11, the third conductive connection layer may include: a plurality of transition electrodes (e.g., a fifth transition electrode 235) and a plurality of first auxiliary traces 61 located in the second sub-region A22, and a third auxiliary trace 63 located in the third border region B3. The plurality of first auxiliary traces 61 may extend along a first direction D1 and be arranged sequentially along a second direction D2. The third auxiliary trace 63 may extend around the edge of the second sub-region A22. The plurality of first auxiliary traces 61 may extend to the third border region B3 and connect to the third auxiliary trace 63. The third auxiliary trace 63 may be configured to transmit a constant voltage signal so that all the plurality of first auxiliary traces 61 are connected to the constant voltage signal. For example, the constant voltage signal may be a first power signal or a second power signal. The third auxiliary trace 63 may be a loop trace located in the border region. For example, the third auxiliary trace 63 and the multiple first auxiliary traces 61 can be an integral structure. However, this embodiment is not limited to this. In other examples, the third auxiliary trace and the multiple first auxiliary traces can be located on different conductive connection layers. For example, the multiple first auxiliary traces can be located on the third conductive connection layer, and the third auxiliary trace can be located on the first conductive connection layer or the second conductive connection layer.

[0167] In some examples, each conductive interconnect layer may have multiple first auxiliary traces 61 located in the second sub-region A22 and a third auxiliary trace 63 located in the bezel region. In other examples, the display substrate includes multiple conductive interconnect layers, and one of the conductive interconnect layers may have multiple first auxiliary traces located in the second sub-region and a third auxiliary trace located in the bezel region.

[0168] In some examples, the spacing between adjacent first auxiliary traces along the second direction D2 can be determined based on the spacing between adjacent conductive connection lines along the second direction D2. For example, the spacing between adjacent first auxiliary traces along the second direction D2 can be the same as the spacing between adjacent conductive connection lines along the second direction D2.

[0169] In some examples, the linewidth (i.e., the length of the trace perpendicular to the extension direction) of the first auxiliary trace 61 can be determined based on the linewidth of the conductive connecting line. For example, the linewidth of the first auxiliary trace 61 can be the same as the linewidth of the conductive connecting line.

[0170] This example demonstrates how setting multiple first auxiliary traces in the second sub-region and a third auxiliary trace in the border region, with the third auxiliary trace and multiple first auxiliary traces connected to a constant voltage signal, can enable the constant voltage signal to be laid out across the entire surface of the display substrate, which is beneficial for stabilizing the circuit structure beneath the conductive interconnect layer.

[0171] Figure 12 is a partial planar schematic diagram of the first sub-region of the second display area according to at least one embodiment of the present disclosure. Figure 12 can be a partially enlarged schematic diagram of region S4 in Figure 1. Figure 12 illustrates a conductive connection layer (e.g., a third conductive connection layer) of the first sub-region as an example. In some examples, as shown in Figure 12, the third conductive connection layer of the first sub-region may include: multiple conductive connection lines 51, and multiple fourth auxiliary lines 64a and 64b. The conductive connection lines 51 may include: a third main body portion 511 extending along a first direction D1 and a conductive connection portion 512 extending along a second direction D2. The third main body portion 511 and the conductive connection portion 512 are integrally formed. The third main body portion 511 may extend to the first display area and be connected to the anode of the first light-emitting element in the first display area; the conductive connection portion 512 may be connected to the second pixel circuit in the first sub-region. The multiple fourth auxiliary lines 64a and 64b may extend along the first direction D1 and be arranged sequentially along the second direction D2. Multiple fourth auxiliary lines 64a may be provided between the conductive connection portions 512 of adjacent conductive connection lines 51; at least one fourth auxiliary line 64b may be provided between the third main body portions 511 of adjacent conductive connection lines 51, or no fourth auxiliary line may be provided.

[0172] In some examples, the spacing between adjacent fourth auxiliary traces along the second direction D2 can be determined based on the spacing between the third main body portions 511 of adjacent conductive connection lines 51 along the second direction D2. For example, the spacing between adjacent fourth auxiliary traces along the second direction D2 can be the same as the spacing between the third main body portions 511 of adjacent conductive connection lines 51 along the second direction D2.

[0173] In some examples, the line width of the fourth auxiliary trace (i.e., the trace length perpendicular to the extension direction) can be determined based on the line width of the conductive connection line 51. For example, the line width of the fourth auxiliary trace can be the same as the line width of the conductive connection line 51.

[0174] This example demonstrates how setting multiple fourth auxiliary traces in the first sub-region can maintain the consistency of the surrounding environment of the conductive connection lines, which is beneficial for optimizing the cumbersome compensation rules of the conductive connection lines and improving the etching uniformity of the conductive connection lines.

[0175] Figure 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 13, this embodiment provides a display device including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may at least partially overlap with a first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 may be located within the range of the first display area A1. In some examples, the sensor 92 may be a camera or an infrared sensor.

[0176] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following: microdisplay, VR device or AR device containing a microdisplay, etc.

[0177] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0178] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area located at least one side of the first display area, the second display area including: a first sub-area located at least one side of the first display area, and a second sub-area located at least one side of the first sub-area; Multiple light-emitting elements, including multiple first light-emitting elements located in the first display area and multiple second light-emitting elements located in the second display area; The system includes multiple pixel circuits, including multiple first pixel circuits and multiple second pixel circuits located in the second display area. The multiple first pixel circuits are located in the first sub-area. At least one of the multiple first pixel circuits is connected to at least one of the multiple first light-emitting elements through at least one conductive connection line. At least one of the multiple second pixel circuits is connected to at least one of the multiple second light-emitting elements. The at least one conductive connection line extends from the first sub-area to the first display area. Multiple first auxiliary traces are located in the second sub-area of ​​the second display area. At least one of the multiple first auxiliary traces is disposed on the same layer as the at least one conductive connection line, and the multiple first auxiliary traces are configured to receive constant voltage signals.

2. The display substrate according to claim 1, wherein, At least one of the plurality of first auxiliary traces extends in the same direction as the at least one conductive connection line.

3. The display substrate according to claim 1 or 2, further comprising: The second auxiliary traces are located in the second sub-region. The extension directions of the second auxiliary traces intersect the extension directions of the first auxiliary traces. The second auxiliary traces and the first auxiliary traces are connected to form a mesh structure.

4. The display substrate according to claim 3, wherein, The first auxiliary trace includes: a first main body extending along a first direction, a plurality of first extensions and a plurality of second extensions extending along a second direction, and a plurality of first auxiliary connection electrodes, wherein the second direction intersects the first direction; the plurality of second extensions are connected to the plurality of first auxiliary connection electrodes in a one-to-one correspondence, the plurality of first extensions and the plurality of second extensions are connected to the same side of the first main body and are arranged at intervals along the first direction; the first auxiliary connection electrode is connected to a second auxiliary trace extending along the second direction.

5. The display substrate according to claim 4, wherein, The plurality of second auxiliary traces and the plurality of first auxiliary traces are located in different conductive layers, and at least one insulating layer is provided between the conductive layer where the first auxiliary traces are located and the conductive layer where the second auxiliary traces are located. The second auxiliary trace includes: a second main body extending along the second direction and at least one second auxiliary connection electrode extending along the first direction; The second auxiliary connection electrode of the second auxiliary trace is connected to the first auxiliary connection electrode of the first auxiliary trace through the auxiliary transition hole opened in the insulating layer.

6. The display substrate according to claim 5, wherein, The first sub-area is located on both sides of the first display area along the first direction. The second sub-area includes: a first partition and a second partition located on both sides of the first sub-area along the first direction, and a third partition and a fourth partition located on both sides of the first display area along the second direction. The multiple auxiliary adapter holes in the first partition, the second partition, the third partition and the fourth partition are arranged in a V-shape.

7. The display substrate according to claim 6, wherein, The maximum length of the V-shape formed by the arrangement of multiple auxiliary transition holes in the first and second partitions along the first direction is greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary transition holes in the third and fourth partitions along the first direction. The maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the first and second partitions along the second direction is greater than the maximum length of the V-shape formed by the arrangement of multiple auxiliary adapter holes in the third and fourth partitions along the second direction.

8. The display substrate according to any one of claims 3 to 7, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a circuit structure layer and at least two conductive connection layers sequentially disposed on the substrate, wherein the material of the at least two conductive connection layers includes a transparent conductive material; the at least two conductive connection layers are provided with the at least one conductive connection line, wherein the first auxiliary trace and the second auxiliary trace are located in the at least two conductive connection layers and are located in different layers.

9. The display substrate according to claim 8, wherein, The at least two conductive interconnect layers include: a first conductive interconnect layer, a second conductive interconnect layer, and a third conductive interconnect layer disposed sequentially along a direction away from the substrate; the first auxiliary trace is located in the first conductive interconnect layer, and the second auxiliary trace is located in the second conductive interconnect layer.

10. The display substrate according to claim 9, wherein, Multiple pixel circuits arranged along the first direction form a row of pixel circuits, and multiple pixel circuits arranged along the second direction form a column of pixel circuits, with the first direction intersecting the second direction. The circuit structure layer includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer sequentially disposed on the substrate; The first gate metal layer includes multiple scan lines connected to the row of pixel circuits; the second gate metal layer includes multiple first initial signal lines connected to the row of pixel circuits; the third source / drain metal layer includes multiple data lines and multiple first data transfer lines, the multiple data lines and the multiple first data transfer lines being arranged at intervals along the first direction; the data lines are connected to the column of pixel circuits, and the orthographic projection of the first data transfer lines on the substrate overlaps with the orthographic projection of the column of pixel circuits on the substrate; The first auxiliary trace includes a first main body extending along the first direction, and the first main body, in its orthographic projection on the substrate, is located between the scan line connected to the row pixel circuit and the first initial signal line in the orthographic projection on the substrate. The second auxiliary trace includes a second main body extending along the second direction, at least a portion of which, in the orthographic projection of the substrate, is located between the data line connected to the column of pixel circuits and the first data transfer line overlapping with the orthographic projection of the column of pixel circuits on the substrate in the orthographic projection of the substrate.

11. The display substrate according to any one of claims 3 to 10, wherein, The substrate further includes: a first frame area located on one side of the second display area, the first frame area being provided with a first peripheral power line and a plurality of power conversion electrodes, the plurality of second auxiliary traces being connected to the first peripheral power line through the plurality of power conversion electrodes.

12. The display substrate according to claim 11, further comprising: Multiple first power lines are located in the second display area. The multiple first power lines are arranged along a first direction and extend along a second direction, and the first direction and the second direction intersect. The plurality of pixel circuits further includes: a plurality of invalid pixel circuits located in the second display area; The multiple invalid pixel circuits arranged along the second direction form a column of invalid pixel circuits, the multiple second pixel circuits arranged along the second direction form a column of second pixel circuits, and the multiple first pixel circuits arranged along the second direction form a column of first pixel circuits. The power transfer electrode connected to the second auxiliary trace is located between the first power line connected to a column of invalid pixel circuits and the first power line connected to an adjacent column of second pixel circuits, or between the first power line connected to a column of invalid pixel circuits and a column of first pixel circuits aligned along the second direction and the first power line connected to an adjacent column of second pixel circuits.

13. The display substrate according to any one of claims 1 to 12, wherein, The substrate further includes a border area located on at least one side of the second display area, and the display substrate further includes a third auxiliary trace located in the border area, the third auxiliary trace being connected to the plurality of first auxiliary traces and configured to transmit a constant voltage signal.

14. The display substrate according to any one of claims 1 to 13, wherein, The at least one conductive connection line includes: a third main body portion extending along a first direction and a conductive connection portion extending along a second direction, the first direction intersecting the second direction; the conductive connection portion is connected to the first pixel circuit in the first sub-region, and the third main body portion is connected to the first light-emitting element in the first display area; The display substrate further includes: a plurality of fourth auxiliary traces located in the first sub-region and extending along the first direction, wherein the plurality of fourth auxiliary traces are disposed on the same layer as the at least one conductive connection line, and the plurality of fourth auxiliary traces satisfy at least one of the following: located between the conductive connection portions of adjacent conductive connection lines, or located between the third main body portions of adjacent conductive connection lines.

15. A display device comprising a display substrate as claimed in any one of claims 1 to 14, and a sensor located on a non-display side of the display substrate, wherein the orthographic projection of the sensor onto the substrate of the display substrate at least partially overlaps with the orthographic projection of a first display area of ​​the display substrate onto the substrate.

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