Macro cell layout method and related apparatus

Abstract

A macro cell layout method and a related apparatus, relating to the technical field of electronic design automation. The method comprises: acquiring connection relationship information and alternative layouts of t macro cells; inputting the connection relationship information and position information into an indicator prediction model so as to output predicted values of evaluation indicators; and obtaining a target layout of the t macro cells on the basis of the predicted values of the evaluation indicators and the alternative layouts. In the present application, the evaluation indicators may be any indicators, such as worst negative slack, total negative slack, half-perimeter wirelength, and degree of congestion. The problem that existing macro cell layout methods mainly focus on optimizing intermediate proxy indicators which are easy to acquire at a current stage and ignore cross-stage indicators which truly reflect final chip quality is solved and the timing performance of a circuit is optimized, ensuring that the circuit has a higher design quality and higher manufacturability. In the present application, the objective of improving evaluation indicators of a circuit in an "end-to-end" manner is achieved, manual intervention is not needed, costs are lower, and efficiency is higher.

Description

Macrocell layout method and related devices

[0001] This application claims priority to Chinese Patent Application No. 202411541194.6, filed on October 31, 2024, entitled "Macrocell Layout Method and Related Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic design automation technology, and in particular to macrocell placement methods and related devices. Background Technology

[0003] The modern VLSI design flow includes multiple processes such as logic synthesis and physical design. Among these, the macrocell placement problem is a crucial step in the physical design process. For a long time, the macrocell placement process has heavily relied on engineers' experience, often taking weeks or even months. Therefore, a macrocell placement methodology is needed. Summary of the Invention

[0004] To address the aforementioned issues, embodiments of this application provide a macrocell layout method and related apparatus, which improve the layout efficiency of macrocells and reduce the reliance on manual layout during the macrocell layout process.

[0005] Therefore, the following technical solutions are adopted in the embodiments of this application:

[0006] In a first aspect, embodiments of this application provide a macrocell layout method, comprising: obtaining connection relationship information of t macrocells and their candidate layouts, wherein the candidate layouts include position information of t macrocells, where t is an integer greater than or equal to 2; inputting the connection relationship information and position information into an indicator prediction model to output predicted values ​​of evaluation indicators, wherein the evaluation indicators represent several indicators used to evaluate at least one of the performance, power consumption, and area of ​​the circuit formed by the candidate layouts; and obtaining a target layout of t macrocells based on the predicted values ​​of the evaluation indicators and the candidate layouts.

[0007] In this embodiment, the predicted values ​​of the evaluation metrics output by the metric prediction model can be any metric, such as worst-case negative timing margin, total negative timing margin, half-cycle length, congestion, etc. This solves the problem that existing macrocell placement methods mainly focus on optimizing easily obtainable intermediate proxy metrics (such as macrocell half-cycle length and congestion) at the current stage, while ignoring cross-stage metrics (such as worst-case negative timing margin and total negative timing margin) that truly reflect the final chip quality. This means that the final circuit has significantly optimized timing performance, ensuring higher design quality and manufacturability. In this embodiment, after inputting the candidate layout into the metric prediction model, the metric prediction model can directly output the predicted values ​​of the evaluation metrics of the circuit formed by the candidate layout, thereby achieving the goal of improving the circuit's evaluation metrics "end-to-end". This enables high-precision estimation of evaluation metrics with lower computational cost, improves the iteration cycle of circuit design, shortens the design cycle, and improves design efficiency. The entire metric prediction process requires no manual intervention, improving the placement efficiency of macrocells, reducing reliance on manual placement, and resulting in lower costs and higher efficiency. In this embodiment, the metric prediction model is applicable to the prediction of multiple evaluation metrics, essentially functioning as a multi-task learning framework. Furthermore, it can be fine-tuned to predict evaluation metrics for new tasks, enhancing the model's adaptability to different design tasks. In other words, the metric prediction model exhibits strong adaptability when handling circuit designs of different types and scales, consistently outputting high-quality placement results. This generalization ability of the metric prediction model has broader applicability in practical applications, enabling it to cope with ever-changing design requirements.

[0008] In one possible implementation, the above-mentioned indicator prediction model is modeled based on a preset algorithm, which represents an algorithm for fitting the connection relationship between the evaluation indicator and the connection relationship information and location information.

[0009] In this implementation, a nonlinear relationship exists between the macrocell layout and the actual values ​​of the circuit's evaluation metrics, based on a pre-defined algorithm. The purpose of the metric prediction model is to learn this nonlinear relationship, thereby outputting predicted values ​​of the circuit's evaluation metrics after inputting the macrocell layout. The pre-defined algorithm can be any algorithm that fits the connection relationship between the evaluation metrics and connectivity and positional information.

[0010] In one possible implementation, the preset algorithm is a polynomial algorithm, which includes a power polynomial and its coefficients. The power polynomial represents the k-th power of the distance information between t macrocells, where k is a natural number. The process of inputting connectivity and location information into the indicator prediction model to output predicted values ​​for the evaluation indicator includes: obtaining polynomial coefficients based on connectivity information; obtaining a power polynomial based on location information; and combining the polynomial coefficients to obtain the predicted values ​​for the evaluation indicator.

[0011] In this implementation, the indicator prediction model can simulate a power polynomial based on the positions of several macrocells; the indicator prediction model can simulate polynomial coefficients based on the connection relationships between macrocells; the indicator prediction model then fits the power polynomial and polynomial coefficients to obtain the expression of the polynomial algorithm, and the calculation result of the polynomial algorithm is the predicted value of the evaluation indicator.

[0012] In one possible implementation, the indicator prediction model includes a graph neural network. The process of obtaining the polynomial coefficients based on connection information includes: obtaining a graph structure based on the connection information, the graph structure comprising several nodes and several connecting edges, where nodes represent macrounits and connecting edges represent the connections between macrounits; inputting the graph structure into the graph neural network to output a node representation for each node; and obtaining the polynomial coefficients based on the node representations.

[0013] In this implementation, the graph neural network has a good learning ability for node representations of graph structures, and can learn node representations from connection relationship information to polynomial coefficients.

[0014] In one possible implementation, the metric prediction model includes a multinomial fitting network. The process described above, obtaining a power-order polynomial based on location information and combining the polynomial coefficients to obtain the predicted value of the evaluation metric, includes: determining the distance information between t macrounits based on location information; and inputting the polynomial coefficients and distance information into the multinomial fitting network to output the predicted value of the evaluation metric.

[0015] In this implementation, the polynomial fitting network can learn the power polynomial in the Laurent polynomial, such as the power k of the positions of several macrocells, and thus obtain the power polynomial; combined with the polynomial coefficients, the predicted value of the evaluation index is obtained.

[0016] In one possible implementation, the polynomial algorithm is the Laurent polynomial algorithm.

[0017] In this implementation, according to the principle of Laurent polynomials, the equation of a nonlinear relationship can be expanded into the sum of power series of unknowns. Therefore, at the algorithm level, the index prediction model needs to learn the power polynomials in the Laurent polynomials, such as the powers of the positions of several macrocells; the index prediction model also needs to learn the polynomial coefficients in the Laurent polynomials, such as the node representations obtained based on the connection relationships between several macrocells.

[0018] In one possible implementation, multiple candidate layouts are set, and these multiple candidate layouts are obtained by adjusting the positions of t macrocells. The above-mentioned process of obtaining the target layout of t macrocells based on the predicted values ​​of the evaluation metrics and the candidate layouts includes: obtaining the target layout of t macrocells from the multiple candidate layouts based on the predicted values ​​of the evaluation metrics of each candidate layout.

[0019] In this implementation, based on the aforementioned metric prediction model, the layout problem of t macrocells can be represented as an optimization problem of the positions of t macrocells. For example, assuming that the smaller the evaluation metric, the better the layout quality of the integrated circuit, the macrocell layout problem can be transformed into: finding the optimal positions of t macrocells by minimizing the weighted sum of the predicted values ​​of all evaluation metrics. This is equivalent to obtaining the target layout of t macrocells from multiple candidate layouts with different positions, based on the principle of minimizing the weighted sum of the predicted values ​​of all evaluation metrics.

[0020] In one possible implementation, the target layout is selected from multiple candidate layouts based on a preset optimization algorithm.

[0021] In this implementation, the preset optimization algorithm can be any algorithm, such as black-box optimization or white-box optimization. For example, using a black-box optimization algorithm, the predicted values ​​of evaluation metrics for multiple candidate layouts can be input into the black-box optimization module. The black-box optimization module then sorts the candidate layouts according to the algorithm; based on the sorting result, the target layout of t macrocells can be obtained. For example, in a white-box optimization algorithm, the relationship between the predicted values ​​of the evaluation metrics and the position information of the t macrocells is explicit, meaning the polynomial coefficients and power polynomials in the Laurent polynomials are known; the optimal solution for the positions of the t macrocells can be obtained by combining gradient descent.

[0022] In one possible implementation, the target layout of the t macrocells is the layout of the first t macrocells obtained in the t-th step of the greedy strategy, and the alternative layouts of the t macrocells are obtained by placing the t-th macrocell in the layout of the first t-1 macrocells.

[0023] In this implementation, a sequential greedy strategy automates the layout process. Each step makes optimal decisions based on the estimation results of a metric prediction model, ensuring that every step in the layout process moves towards the global optimum. This automation significantly reduces the need for manual intervention, allowing designers to focus more on high-level design optimization while ensuring the high quality of the final layout.

[0024] In one possible implementation, obtaining the target layout of t macrocells based on the predicted values ​​of the evaluation metrics and the candidate layouts includes: determining the reward score of the candidate layouts based on the predicted values ​​of the evaluation metrics; the candidate layouts being the predicted layouts of the t macrocells output when the input of the reinforcement learning network is the connection relationship information of the t macrocells; and inputting the reward scores into the reinforcement learning network to output the target layout of the t macrocells.

[0025] In this implementation, the embodiments of this application can be combined with a reinforcement learning architecture. Specifically, after the reinforcement learning architecture outputs candidate layouts, the metric prediction model can generate predicted values ​​for the evaluation metrics based on the candidate layouts. Then, the reinforcement learning architecture can adjust its parameters based on the reward signal of the predicted evaluation metrics, resulting in shorter training time and faster convergence.

[0026] In one possible implementation, the evaluation metrics include cross-stage metrics, which represent metrics related to multiple stages in the process of evaluating alternative layouts forming circuits.

[0027] In this implementation, the embodiments of this application can estimate cross-stage metrics in real time during the placement process. Compared with traditional placement methods, the embodiments of this application show significant improvements in several key metrics. This means that the timing performance of the circuit is significantly optimized, ensuring higher design quality and manufacturability.

[0028] In one possible implementation, the cross-stage metric includes a time-series metric, which includes at least one of worst-case negative time-series margin and total negative time-series margin.

[0029] In this implementation, the cross-stage metrics include at least one of worst-case negative timing margin and total negative timing margin, which significantly improves the timing performance of the circuit in terms of timing delay.

[0030] In one possible implementation, the connection relationship information is obtained through the netlist data of t macrocells. The netlist data is used to characterize the connection relationship of several cells to be laid out, which include t macrocells.

[0031] In this implementation, the netlist includes information on various types of units (standard units, ports, macro units, etc.) and the connection relationships between these units. The connection relationship information of t macro units can be obtained from the netlist data.

[0032] In one possible implementation, the indicator prediction model is obtained by training on a training dataset. The loss function of the training process of the indicator prediction model includes the indicator fitting error, which characterizes the error between the predicted value of the evaluation indicator output by the indicator prediction model and the true value of the evaluation indicator.

[0033] In this implementation, the parameters of the indicator prediction model can be adjusted based on the indicator fitting error to reduce the output error of the predicted value of the evaluation indicator.

[0034] In one possible implementation, the loss function of the training process of the indicator prediction model also includes the ranking error, which represents the error between the predicted values ​​of the ranking of several training samples in the training dataset and the true values ​​of the ranking. The ranking prediction values ​​are obtained by ranking several training samples according to the predicted values ​​of the evaluation indicators output by the indicator prediction model.

[0035] In this implementation, the parameters of the indicator prediction model can be adjusted based on the indicator fitting error and the ranking error. This reduces the output error of the indicator prediction value and improves the accuracy of the indicator prediction model's output results from both the accuracy of the predicted value and the ranking results.

[0036] In one possible implementation, the training dataset includes several training samples, which are obtained by constructing different macrocell layouts for each netlist sample in several netlist samples.

[0037] In this implementation, the netlist examples include information on various types of units (standard units, ports, macrounits, etc.) and the connection relationships between these units. Therefore, by changing the position of macrounits using netlist examples, training samples can be obtained; and by using several netlist examples, richer training samples can be constructed to obtain a training dataset.

[0038] In one possible implementation, the indicator prediction model is further obtained by fine-tuning the dataset, which is based on newly added indicators in addition to the existing evaluation indicators.

[0039] In this implementation, when a new indicator prediction task requires using the indicator prediction model, the model can be fine-tuned. The fine-tuned model can then be applied to the new task, providing new indicators for the alternative layouts of macrocells. Fine-tuning is less costly, the indicator prediction model is more efficiently adapted to new tasks, and it exhibits excellent generalization.

[0040] Secondly, this application provides a macrocell layout apparatus, comprising: an acquisition module, configured to acquire connection relationship information of t macrocells and their candidate layouts, wherein the candidate layouts include position information of t macrocells, and t is an integer greater than or equal to 2; a processing module, configured to input the connection relationship information and position information into an indicator prediction model to output predicted values ​​of evaluation indicators, wherein the evaluation indicators represent several indicators used to evaluate at least one of the performance, power consumption, and area of ​​the circuit formed by the candidate layouts; and, based on the predicted values ​​of the evaluation indicators and the candidate layouts, to obtain a target layout of t macrocells.

[0041] In one possible implementation, the above-mentioned indicator prediction model is modeled based on a preset algorithm, which represents an algorithm for fitting the connection relationship between the evaluation indicator and the connection relationship information and location information.

[0042] In one possible implementation, the preset algorithm is a polynomial algorithm, which includes a power polynomial and its coefficients. The power polynomial represents the k-th power of the distance information between t macrocells, where k is a natural number. Specifically, the processing module is used to: obtain the polynomial coefficients based on the connectivity information; obtain the power polynomial based on the location information; and combine the polynomial coefficients to obtain the predicted value of the evaluation metric.

[0043] In one possible implementation, the indicator prediction model includes a graph neural network. Specifically, the aforementioned processing module is used to: obtain a graph structure based on connection relationship information, the graph structure including several nodes and several connecting edges, where nodes represent macrounits and connecting edges represent the connection relationships between macrounits; input the graph structure into the graph neural network to output the node representation of each node; and obtain the polynomial coefficients based on the node representations.

[0044] In one possible implementation, the metric prediction model includes a multinomial fitting network. Specifically, the aforementioned processing module is used to: determine the distance information between t macrounits based on location information; input the multinomial coefficients and distance information into the multinomial fitting network to output the predicted value of the evaluation metric.

[0045] In one possible implementation, the polynomial algorithm is the Laurent polynomial algorithm.

[0046] In one possible implementation, multiple candidate layouts are set, and these multiple candidate layouts are obtained by adjusting the positions of t macrocells. The aforementioned processing module is specifically used to: obtain the target layout of t macrocells from the multiple candidate layouts based on the predicted values ​​of the evaluation metrics of each candidate layout.

[0047] In one possible implementation, the target layout is selected from multiple candidate layouts based on a preset optimization algorithm.

[0048] In one possible implementation, the target layout of the t macrocells is the layout of the first t macrocells obtained in the t-th step of the greedy strategy, and the alternative layouts of the t macrocells are obtained by placing the t-th macrocell in the layout of the first t-1 macrocells.

[0049] In one possible implementation, the above processing module is specifically used to: determine the reward score of the candidate layout based on the predicted value of the evaluation index; when the candidate layout is the connection relationship information of t macro units as input to the reinforcement learning network, output the prediction result of the layout of t macro units; input the reward score into the reinforcement learning network to output the target layout of t macro units.

[0050] In one possible implementation, the evaluation metrics include cross-stage metrics, which represent metrics related to multiple stages in the process of evaluating alternative layouts forming circuits.

[0051] In one possible implementation, the cross-stage metric includes a time-series metric, which includes at least one of worst-case negative time-series margin and total negative time-series margin.

[0052] In one possible implementation, the connection relationship information is obtained through the netlist data of t macrocells. The netlist data is used to characterize the connection relationship of several cells to be laid out, which include t macrocells.

[0053] In one possible implementation, the indicator prediction model is obtained by training on a training dataset. The loss function of the training process of the indicator prediction model includes the indicator fitting error, which characterizes the error between the predicted value of the evaluation indicator output by the indicator prediction model and the true value of the evaluation indicator.

[0054] In one possible implementation, the loss function of the training process of the indicator prediction model also includes the ranking error, which represents the error between the predicted values ​​of the ranking of several training samples in the training dataset and the true values ​​of the ranking. The ranking prediction values ​​are obtained by ranking several training samples according to the predicted values ​​of the evaluation indicators output by the indicator prediction model.

[0055] In one possible implementation, the training dataset includes several training samples, which are obtained by constructing different macrocell layouts for each netlist sample in several netlist samples.

[0056] In one possible implementation, the indicator prediction model is further obtained by fine-tuning the dataset, which is based on newly added indicators in addition to the existing evaluation indicators.

[0057] Thirdly, this application provides a chip system including a processor and a power supply circuit, the power supply circuit being used to supply power to the processor, and the processor being used to execute the method described in any possible implementation of the first aspect and / or the algorithmic functions embodied by the apparatus described in any possible implementation of the second aspect.

[0058] Fourthly, this application provides a computing device including a processor and a memory. The processor is used to execute instructions stored in the memory to cause the computing device to perform the methods described in any possible implementation of the first aspect and / or the algorithmic functions embodied by the means described in any possible implementation of the second aspect.

[0059] Fifthly, this application provides a computing device cluster, including at least one computing device, each computing device including a processor and a memory; the processor of the at least one computing device is used to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster performs the method described in any possible implementation of the first aspect and / or the algorithmic function embodied by the apparatus described in any possible implementation of the second aspect.

[0060] In a sixth aspect, this application provides a computer-readable storage medium including computer program instructions that, when executed by a cluster of computing devices, cause the cluster of computing devices to perform the method described in any possible implementation of the first aspect and / or the algorithmic function embodied by the apparatus described in any possible implementation of the second aspect, wherein the cluster of computing devices includes at least one computing device.

[0061] In a seventh aspect, this application provides a computer program product containing instructions that, when executed by a cluster of computing devices, cause the cluster of computing devices to perform the method described in any possible implementation of the first aspect and / or the algorithmic function embodied by the apparatus described in any possible implementation of the second aspect, wherein the cluster of computing devices includes at least one computing device.

[0062] It is understood that the beneficial effects of the second to seventh aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0063] The accompanying drawings used in the embodiments or technical description are briefly introduced below.

[0064] Figure 1a is a schematic diagram of the layout process of the integrated circuit provided in an embodiment of this application;

[0065] Figure 1b is a schematic diagram of the application scenario of the index prediction model in the layout process of integrated circuits provided in the embodiments of this application;

[0066] Figure 2 is a schematic diagram of a macro-unit layout architecture provided in an embodiment of this application;

[0067] Figure 3 is a flowchart illustrating a macrocell layout method provided in an embodiment of this application;

[0068] Figure 4 is a schematic diagram of an example of the netlist, graph structure, and node representation provided in an embodiment of this application;

[0069] Figure 5 is a schematic diagram of two strategies for determining the target layout provided in the embodiments of this application;

[0070] Figure 6 is a schematic diagram of an example of combining the indicator prediction model with a greedy strategy provided in the embodiments of this application;

[0071] Figure 7 is a schematic diagram of an example of the indicator prediction model provided in the embodiments of this application outputting predicted values ​​of multiple evaluation indicators and applied to the prediction task of a newly added indicator;

[0072] Figure 8 is a schematic diagram of the training and inference phases of the indicator prediction model provided in the embodiments of this application;

[0073] Figure 9 is a flowchart illustrating a training method for an indicator prediction model provided in an embodiment of this application;

[0074] Figure 10 is a schematic diagram of the construction process of the training dataset provided in the embodiments of this application;

[0075] Figure 11 is a schematic diagram of an example of the training process of the index prediction model provided in the embodiments of this application;

[0076] Figure 12 is a schematic diagram illustrating an example of the layout effect and congestion graph display of different schemes on the netlist of the first dataset provided in the embodiments of this application;

[0077] Figure 13 is a schematic diagram of an example of the layout diagram timing path of different schemes on the netlist of the second dataset provided in the embodiments of this application;

[0078] Figure 14 is a schematic diagram of the composition of a macrocell layout device provided in an embodiment of this application;

[0079] Figure 15 is a schematic diagram of the composition of a training device for an index prediction model provided in an embodiment of this application;

[0080] Figure 16 is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0081] Figure 17 is a schematic diagram of the structure of a computing device cluster provided in an embodiment of this application;

[0082] Figure 18 is a schematic diagram of another computing device cluster provided in an embodiment of this application. Detailed Implementation

[0083] In this article, the term "and / or" describes the connection relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The symbol " / " in this article indicates that the related objects have an "or" relationship; for example, A / B means A or B.

[0084] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0085] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0086] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0087] To facilitate understanding of the solutions provided in the embodiments of this application, a brief introduction to some of the terms involved in this solution will be given first.

[0088] Circuit placement includes macrocell placement and standard cell placement. Circuit placement techniques involve the rational allocation of physical coordinates for a large number of basic cells (standard cells) and macrocells in a circuit. This ensures that all basic cells and macrocells (commonly referred to as nodes) have their own space without overlap in a specified area. Furthermore, it requires that the relative positions of interconnected nodes be minimized, the total connection length be minimized, and the performance of electrical signals on them meet the timing requirements of the circuit.

[0089] Macrocells: These mainly refer to the devices that are the main functional modules of an integrated circuit, including memory, processors, etc.

[0090] Standard unit: mainly refers to the device that implements the underlying electronic logic function, including AND, OR, NOT gates, flip-flops, latches, etc.

[0091] Netlist: A netlist includes information about various types of units (standard units, ports, macro units, etc.) and the connections between these units. For example, the connection between two macro units includes the number of paths between the two macro units, the number of standard units on each path, and other information. The connection relationships between several macro units are obtained through netlist information, and these connections include at least the connections between macro units and other macro units.

[0092] PPA (Power, Performance, Area) metrics refer to the performance indicators that meet the requirements in terms of power, performance, and area. The chip placement problem can be described as, given the size and connectivity of standard cells and macrocells, and timing constraints, solving for the location of chip modules. Its ultimate goal is to optimize the chip's final PPA metrics.

[0093] Half-Perimeter Wire Length (HPWL): A method for estimating wire length; HPWL is an approximation of wire length. For example, assuming a circuit board is divided into n wireframes, the HPWL of a wire mesh is half the perimeter of the wireframe through which the wire mesh passes.

[0094] Congestion: In chip design or Field-Programmable Gate Array (FPGA) design, hardware resources can be divided into logic resources and routing resources. When the design project is large or complex, the logic resources may still be within a reasonable range, but the routing resources may exceed the inherent resources or be unreasonable. This can lead to congestion, which is caused by a shortage of routing resources. The congestion degree represents the degree of congestion. For example, assuming a circuit board is divided into n wireframes, the congestion degree of the i-th wireframe can be simulated by the bus length of all nets passing through the i-th wireframe.

[0095] Worst Negative Slack (WNS): Characterizes the timing margin of the worst-case path in the designed circuit. If WNS is positive, it means that the setup time requirement is met; if WNS is negative, it means that there is a problem with the setup time timing.

[0096] Total Negative Slack (TNS): This is the sum of all negative timing slack paths. If TNS is positive, it means that the setup time requirement is met; if TNS is negative, it means that there is a problem with the setup time timing.

[0097] Worst Hold Slack (WHS): A positive WHS indicates that the hold time requirement is met, while a negative WHS indicates that there is a problem with the hold timing.

[0098] Total Hold Slack (THS): The sum of all negative hold slack paths. In other words, for setup time, the signal must stabilize a certain time before setup; the exact amount of this stabilization is measured by the setup slack (WNS) and time slack (TNS). For hold time, the signal must remain held for a certain period before transitioning; the amount of this delay is measured by the hold slack (WHS) and hold slack (THS).

[0099] Intermediate proxy metrics: These refer to metrics that are readily available at the current stage and are key optimization metrics in some macrocell placement methods, such as half-perimeter length (HPWL) and congestion. Taking half-perimeter length (HPWL) as an example, it can be directly calculated after routing.

[0100] Cross-stage metrics refer to metrics that need to be obtained in multiple stages, such as WNS, TNS, WHS, and THS. These cross-stage metrics directly affect the chip's performance, power consumption, and area (PPA). Generally, cross-stage metrics are ignored in some macrocell placement methods. The embodiments of this application take these cross-stage metrics into account, thereby improving the overall quality of the chip after circuit placement.

[0101] Constraints: Constraints are applied during circuit placement to ensure that the placed circuit meets certain requirements. For example, periodic constraints are basic timing constraints added to the clock network to ensure that the timing of all synchronous components within the clock region meets the requirements; offset constraints are also a type of basic timing constraint, specifying the relative timing relationship between the external clock and data input / output pins.

[0102] Electronic Design Automation (EDA) is a technology that automatically places electronic components in a given space according to the design rules required for integrated circuit manufacturing. It is applied to the layout design of large-scale circuit chips.

[0103] Laurent series, also known as Laurent polynomials, are sums of power series of any function f(z). For example, a Laurent series can be represented as:

[0104] Greedy algorithms, also known as greedy strategies, are a simpler and faster design technique for solving certain optimal problems. The characteristic of greedy algorithms is that they proceed step-by-step, making the optimal choice based on the current situation and a certain optimization metric, without considering all possible overall scenarios. Greedy algorithms save the significant time spent exhaustively searching for the optimal solution. They employ a top-down, iterative approach, making successive greedy choices. Each greedy choice simplifies the problem into a smaller subproblem. Through each greedy choice, an optimal solution can be obtained. Although each step aims to achieve a locally optimal solution, the resulting global solution may not always be optimal. Therefore, greedy algorithms should not backtrack.

[0105] Black-box optimization (BBO) refers to optimization problems where the objective function is difficult to express mathematically, lacks directly usable gradient information, and can only use the objective function input and corresponding output function values ​​to search for the optimal solution.

[0106] Mask: A mask can be a constraint, such as a region where macrocells cannot be placed. For example, a region that cannot be placed can be assigned a value of -1. A mask can also represent layout guidance information, such as assigning a value to each grid point within the range [0, 1], and placing macrocells at the optimal position based on the optimal value, where the optimal value is either the maximum or minimum. The method in this application is equivalent to a macrocell position optimization method that can be learned through an index prediction model, also known as L-mask (Learning mask).

[0107] The modern VLSI design flow includes multiple processes such as logic synthesis and physical design. Among these, the macrocell placement of integrated circuits (e.g., chips) is a crucial step in the physical design process. For a long time, the macrocell placement process has heavily relied on engineers' experience, often taking weeks or even months in VLSI circuit design. There is an urgent need for efficient automated macrocell placement methods to address these issues. Therefore, a macrocell placement method is required.

[0108] In some technical solutions, a macrocell layout method includes: first determining the macrocell layout; then, based on the existing macrocell layout, obtaining the final integrated circuit layout by simulating the entire integrated circuit layout process; calculating the indicators of a certain stage of the integrated circuit generation process, and then optimizing the macrocell layout.

[0109] In these solutions, the optimization process targets limited metrics, resulting in poor performance of the final integrated circuit on the unoptimized metrics, leading to poor overall performance. Furthermore, these solutions require simulating the entire integrated circuit placement process, which is inefficient and time-consuming, resulting in lengthy evaluation times for macrocell placement. For example, completing a single macrocell placement optimization process can take several hours to obtain evaluation metrics.

[0110] For example, these solutions primarily focus on optimizing easily obtainable intermediate proxy metrics at a specific stage, such as macrocell half-perimeter wire length (mHPWL) and congestion, neglecting cross-stage metrics that truly reflect the final chip quality, such as worst-case negative timing margin (WNS) and total negative timing margin (TNS). These cross-stage metrics directly affect the chip's power, power consumption, and area—its PPA (Power, Power, Area) metrics. However, due to high computational costs, these solutions struggle to evaluate and optimize these cross-stage metrics in real-time during the placement process. This limitation makes it difficult for these solutions to achieve performance improvements in practical applications and may even lead to manufacturing feasibility issues.

[0111] In view of this, embodiments of this application propose a macrocell placement method, which can predict PPA indicators using a trained indicator prediction model during the macrocell placement stage, and optimize macrocell placement based on the predicted PPA indicator values. The PPA indicator can include intermediate surrogate indicators, such as mHPWL or HPWL, congestion, etc.; or cross-stage indicators, such as worst-case negative time margin (WNS), total negative time margin (TNS), etc.

[0112] Referring to Figure 1a, Figure 1a is a schematic diagram of the layout process of an integrated circuit provided in an embodiment of this application. In this embodiment, as shown in Figure 1a, the layout process of the integrated circuit includes: macrocell layout, standard cell layout, setting constraints such as clock tree constraints, layout optimization, and routing of the optimized chip layout. An integrated circuit is also called a circuit; in one example, an integrated circuit is specifically a chip.

[0113] In other words, the chip placement problem can be described as follows: In the placement space, given the size and connection relationship of standard cells and macro cells, and given timing constraints, the position of chip modules (such as standard cells and macro cells) is solved. The ultimate goal of this process is to optimize the final power consumption, performance, and area of ​​the chip, i.e., the PPA index.

[0114] Referring to Figure 1b, Figure 1b is a schematic diagram of the application scenario of the indicator prediction model in the layout process of integrated circuits provided in the embodiments of this application. In the embodiments of this application, as shown in Figure 1b, the macrocell layout is used as the input of the indicator prediction model, and the indicator prediction model outputs the predicted value of the evaluation indicator; based on the predicted value of the evaluation indicator, the macrocell layout is optimized to obtain the target layout of macrocells that meets the requirements.

[0115] In this embodiment, the predicted values ​​of the evaluation metrics output by the metric prediction model can be any PPA metric, such as metric 1, metric 2, metric 3, ..., metric n at different stages as shown in Figure 1b. For example, the evaluation metrics can include intermediate surrogate metrics, such as half-cycle length (HPWL) and congestion; the evaluation metrics can also include cross-stage metrics, such as worst-case negative timing margin (WNS) and total negative timing margin (TNS). This solves the problem of poor circuit performance due to poor cross-stage metrics when performing layout optimization based on intermediate surrogate metrics.

[0116] In this embodiment, some macrocell placement methods often optimize surrogate metrics in the intermediate process, making it difficult to directly optimize the final PPA of the chip. This embodiment constructs a PPA predictor, or metric prediction model, to predict the final circuit PPA metric generated by the placement, and performs macrocell placement optimization based on the predictor, achieving long-chain optimization across stages and realizing the goal of improving the chip PPA end-to-end.

[0117] It is understood that in this embodiment, the macrocell layout is optimized based on the predicted values ​​of the evaluation metrics to obtain a target layout that meets the requirements. This optimizes both intermediate proxy metrics and cross-stage metrics, thereby improving the PPA (Power, Process, and Area) metrics upon completion of the circuit layout and ultimately enhancing the overall quality of the final chip. For example, this embodiment utilizes a multinomial fitting method and a metric prediction model to predict the PPA metrics after the circuit layout is completed, obtaining predicted values ​​for the PPA metrics. Based on these predicted values, the macrocell layout is optimized, achieving end-to-end optimization of the PPA metrics. Therefore, this embodiment can optimize key metrics such as cross-stage metrics, thereby better improving the final PPA performance of the chip layout.

[0118] In this embodiment, the optimization of macrocell layout does not require simulating the entire integrated circuit layout process, resulting in high efficiency and a shorter time to obtain macrocell layout evaluation metrics. For example, the time to complete one macrocell layout optimization and obtain macrocell layout evaluation metrics may be on the order of minutes or seconds.

[0119] In other words, extensive evaluation is required during the macrocell placement stage, and existing algorithms are inefficient. For example, it may be necessary to simulate a certain stage of the circuit formation process to obtain the index values ​​for that stage before optimizing the macrocell placement; or, it may be necessary to simulate the entire circuit formation process to obtain the final circuit, and then optimize the macrocell placement based on the index values ​​of the final circuit. This application's embodiments transform the macrocell placement optimization problem into a polynomial optimization problem, thereby formulating a greedy strategy for efficient optimization, significantly improving the optimization efficiency of the macrocell placement stage.

[0120] For example, embodiments of this application can combine reinforcement learning architectures. Specifically, the reinforcement learning architecture outputs alternative layouts; the metric prediction model can output predicted values ​​of evaluation metrics based on the alternative layouts; and then the reinforcement learning architecture can adjust its parameters based on the reward signal of the predicted evaluation metrics. Therefore, embodiments of this application enable shorter training time and faster convergence for the reinforcement learning architecture.

[0121] In this embodiment, when a new metric needs to be predicted using the metric prediction model, the metric prediction model can be fine-tuned. The fine-tuned metric prediction model can be applied to the new task, providing new metrics for the alternative layouts of macrocells. Fine-tuning is less costly, and the metric prediction model is more efficiently applied to new tasks, exhibiting excellent generalization. In contrast, reinforcement learning-based solutions have poor generalization and still require extensive training and fine-tuning on new circuits.

[0122] In this embodiment of the application, when the number of indicators is large, the number of labels used for training increases, while the number of training samples remains unchanged or does not change much. Therefore, the training time does not increase linearly with the increase of the prediction task.

[0123] This application provides a performance indicator prediction model. The performance indicator prediction model is equivalent to a performance indicator predictor, which can predict the evaluation performance indicators of the integrated circuit ultimately formed by any macrocell layout, thereby achieving an end-to-end improvement in the chip's power performance area (PPA).

[0124] In this embodiment, a PPA-oriented chip macrocell layout optimization framework based on polynomial fitting is proposed, using an index prediction model. This framework trains an index prediction model from chip layout to the final chip PPA index. The index prediction model is represented as a polynomial function of macrocell position, and the coefficients of the polynomial are learned. Based on this index prediction model, the chip macrocell layout problem is modeled as a polynomial function optimization problem. Based on the learnable optimization objective, an optimization strategy (such as a greedy strategy) is formulated to efficiently optimize chip layout and macrocell layout, thereby improving the final chip performance.

[0125] In this embodiment, the aforementioned chip macrocell layout optimization framework can be applied to any optimization algorithm framework. For example, black-box optimization, reinforcement learning, and other deep optimization learning methods. For instance, in a black-box optimization framework, multiple layouts are input into a metric prediction model, which outputs a predicted value for the evaluation metric of each layout. The predicted values ​​of the evaluation metrics of multiple layouts can be used as input to a black-box optimization algorithm, outputting a ranking result of the multiple layouts to select the optimal layout. In a reinforcement learning algorithm, the layout before optimization is input into a metric prediction model, which outputs a predicted value for the evaluation metric of the layout before optimization. The predicted value of the evaluation metric of the layout before optimization can be used as a reward score input to a reinforcement learning model to guide its learning. The reinforcement learning model refers to a neural network model based on a reinforcement learning algorithm. In other words, the embodiments of this application do not limit the role and application scenarios of the indicator prediction model; for example, any other products or application scenarios that are theoretically feasible, have weaker performance, higher cost, or are scalable can be combined with the indicator prediction model to optimize the macrocell layout problem and reduce the design cost of the final circuit through the performance of the final circuit.

[0126] In some examples, embodiments of this application introduce a PPA predictor, i.e., an index prediction model, based on Laurent polynomial fitting, in the macrocell layout; and utilize a graph neural network to learn the parameters of this predictor. Based on this, the layout process is optimized using a sequential greedy strategy, achieving significant improvements in chip design performance, power consumption, and area (PPA) metrics.

[0127] In some examples, by using a metric prediction model based on Laurent polynomials, embodiments of this application are able to estimate cross-stage design metrics in real time during the placement process, such as worst-case negative float (WNS) and total negative float (TNS). Experimental results show that, compared with traditional placement methods, embodiments of this application achieve significant improvements in several key metrics, with WNS and TNS improved by 51.4% and 32.6%, respectively. This means that the final chip has optimized timing performance, ensuring higher design quality and manufacturability.

[0128] In some examples, traditional methods require significant computational resources and time to optimize layouts. However, this application's embodiments, by introducing a Laurent polynomial-based predictor, can achieve high-precision metric estimation at a lower computational cost. Experiments show that this application's embodiments can reduce layout computation time by more than 30% while maintaining high-quality layouts, thereby significantly shortening the design cycle and improving design efficiency.

[0129] In some examples, embodiments of this application utilize a multi-task learning framework, improving the model's adaptability to different design tasks through shared representations and task-specific optimization. Experimental results show that embodiments of this application exhibit strong adaptability when handling circuit designs of different types and scales, consistently outputting high-quality layout results. This generalization ability makes embodiments of this application more widely applicable in practical applications, capable of addressing ever-changing design requirements.

[0130] In some examples, this application's embodiments automate the layout process through a sequential greedy strategy. Each step makes optimal decisions based on the estimation results of a metric prediction model, ensuring that every step in the layout process moves towards the global optimum. This automation greatly reduces the need for manual intervention, allowing designers to focus more on high-level design optimization while ensuring the high quality of the final layout.

[0131] Referring to Figure 2, Figure 2 is a schematic diagram of the composition of a macro-unit layout architecture provided in an embodiment of this application. In this embodiment, a macro-unit layout optimization architecture 200 may include a terminal 210 and a server 220. The server 220 may include one or more servers (Figure 2 illustrates this with one server as an example), and the server 220 may provide the methods or apparatus provided in this embodiment to one or more terminals.

[0132] Optionally, a relevant application can be installed on the terminal 210. This application or webpage can provide an interface, allowing the terminal 210 to receive netlist data and other related information input by the user on the interface. The netlist data includes data such as the connection relationships of macrocells. The terminal 210 sends the netlist data and other related information to the server 220. The server 220 deploys the metric prediction model and layout optimization module of this embodiment. The layout optimization module can determine candidate layouts based on the netlist data; input the candidate layouts into the metric prediction model, which outputs the predicted values ​​of the evaluation metrics for the candidate layouts; the layout optimization module can optimize the candidate layouts based on the predicted values ​​of the evaluation metrics until a target layout that meets the requirements is output. Optionally, the server 220 can also return the target layout to the terminal 210; the user obtains the target layout through the terminal 210. The layout optimization module can be a module based on any optimization algorithm, such as a black-box optimization algorithm or reinforcement learning methods; this embodiment does not limit this.

[0133] It should be understood that in some optional implementations, terminal 210 may also deploy the indicator prediction model and layout optimization module of this application embodiment and complete the macro-unit layout optimization work on its own, without the need for the cooperation of server 220. This application embodiment is not limited in this respect. In other optional implementations, server 220 may also rely on received netlist data or other relevant information from other devices besides the terminal or locally stored, without the need for the cooperation of terminal 210. This application embodiment is not limited in this respect.

[0134] The product form of terminal 210 in Figure 1 will be described next. In this embodiment, terminal 210 can be a mobile phone, tablet computer, wearable device, in-vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc. This embodiment does not impose any limitations on this.

[0135] The product form of server 220 in Figure 1 will be described next. It can be further understood that server 220 can be various types of servers, such as x89 architecture servers, specifically rack servers, blade servers, high-density servers, platform servers, or high-performance servers. In other words, this application embodiment does not specifically limit the specific category of the server. Furthermore, it can be understood that the server structure shown in Figure 1 does not constitute a limitation on the server structure; a server may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0136] Furthermore, server 220 can be configured as an independent physical server, or as a server cluster or distributed system consisting of multiple physical servers. It can also be configured as a cloud server or cloud server cluster that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms. The cloud server cluster is deployed in several cloud data centers. The software can be an application that implements object control methods, etc., but is not limited to the above forms.

[0137] Next, the communication connection method between terminal 210 and server 220 is described. For example, terminal 210 and server 220 are connected via a network, enabling terminal 210 to access the cloud management platform deployed on the cloud server cluster. The network can be a wired network or a wireless network. For example, a wired network can be a cable network, fiber optic network, Digital Data Network (DDN), etc., while a wireless network can be a telecommunications network, intranet, Internet, Local Area Network (LAN), Wide Area Network (WAN), Wireless Local Area Network (WLAN), Metropolitan Area Network (MAN), Public Service Telephone Network (PSTN), Bluetooth network, ZigBee network, Global System for Mobile Communications (GSM), CDMA (Code Division Multiple Access) network, CPRS (General Packet Radio Service) network, etc., or any combination thereof.

[0138] Understandably, a network can use any known network communication protocol to enable communication between different terminal layers and gateways. These network communication protocols can be various wired or wireless communication protocols, such as Ethernet, Universal Serial Bus (USB), FireWire, Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), New Radio (NR), Bluetooth, Wireless Fidelity (Wi-Fi), and other communication protocols.

[0139] In one possible scenario, server 220 can function as a cloud platform (a software platform employing application virtualization technology, integrating multiple functions such as software search, download, use, management, and backup). In practical use, server 220 can deploy a cloud management platform and a data center, with terminal 210 interacting with the cloud through the cloud management platform. Additionally, the data center can deploy nodes, which can be virtual machine instances, container instances, physical servers, etc.

[0140] In another possible scenario, the method provided in this application embodiment can be implemented by software. The software has a terminal and a server; the terminal 210 runs the software, and the server 220 runs the software's server. While the terminal 210 is running the software, it can call the server running on the server 220 to implement the method provided in this application embodiment.

[0141] In other words, the method provided in this application embodiment can be applied to the terminal 210 and the server 220. In specific implementation, it can run as software on the terminal 210 or the server 220; for example, the software can be a service or an application. This application embodiment can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application embodiment can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can reside in local and remote computer storage media, including storage devices.

[0142] Furthermore, the systems that can implement the technical solutions of the embodiments of this application include cloud servers, web pages, application programming interfaces (APIs), mobile application software, etc. The indicator prediction model of the embodiments of this application can be deployed on the server side, website, or mobile application software to meet the text generation needs of enterprise users and individual users, and can also be used by developers for secondary development through open API interfaces. Furthermore, the implementation of the embodiments of this application mainly involves deploying the relevant platforms and applications of the indicator prediction model of the embodiments of this application, such as cloud platforms, websites, and applications (APPs).

[0143] The above is an introduction to a macrocell layout optimization architecture 200 provided by the embodiments of this application. Next, based on the above content, a macrocell layout method provided by the embodiments of this application will be introduced. It is understood that the above macrocell layout method is based on the macrocell layout optimization architecture 200 described above, and some or all of the content of the above macrocell layout method can be found in the above description of the macrocell layout optimization architecture 200.

[0144] For example, Figure 3 shows a flowchart of a macrocell layout method provided in an embodiment of this application. It can be understood that this method is executed by a computing device, which can be implemented by any device, equipment, platform, or device cluster with computing and processing capabilities, such as the server 220 shown in Figure 2. As shown in Figure 3, a macrocell layout method mainly includes the following steps:

[0145] Step S310: Obtain the connection relationship information of t macrocells and their alternative layouts. The alternative layouts include the position information of t macrocells, where t is an integer greater than or equal to 2.

[0146] For example, Figure 4 shows a schematic diagram of an example of the netlist, graph structure, and node representation provided in an embodiment of this application. The connection relationship between several macrocells refers to the connection relationship between a macrocell and other cells. Other cells can be any cell in the circuit, such as standard cells, ports, other macrocells, etc.

[0147] In one possible implementation, the connection relationships of several macrocells are obtained through netlist information. The netlist information is used to characterize the connection relationships of several cells to be placed, which include the macrocells.

[0148] In other words, the connection relationships between several macrocells can be determined based on the input netlist information. The netlist includes information on various types of units (standard units, ports, macrocells, etc.) and the connection relationships between these units. For example, the connection relationship between two macrocells includes information such as the number of paths between the two macrocells using different standard units and the number of standard units on each path.

[0149] Furthermore, the connection relationships between several macrocells include at least the connection relationships between macrocells and other macrocells. Optionally, the connection relationships between several macrocells also include the connection relationships between macrocells connected through several standard cells; optionally, the connection relationships between several macrocells also include the connection relationships between a macrocell and a standard cell individually, that is, the standard cell is not connected to other macrocells; optionally, the connection relationships between several macrocells also include the connection relationships between a macrocell and a port.

[0150] In the first example, as shown in Figure 4, the connections between several macrocells include the connections between macrocells themselves. In the netlist, the connection is "macrocell-macrocell"; in the graph structure, it is represented as "node-edge-node", where a node represents a macrocell and an edge represents the connection between macrocells; in the node representation, the node representation of each macrocell node includes the representation of the connection between that macrocell node and other macrocell nodes, which is the polynomial coefficients corresponding to the k-th power of the distance between that macrocell node and other macrocell nodes.

[0151] In the second example, as shown in Figure 4, the connection relationships between several macrocells include the path between macrocells connecting to standard cells. In the netlist, the connection relationship is "macrocell-standard cell-macrocell"; in the graph structure, it is represented as "node-connection edge-node", where a node represents a macrocell, and a connection edge represents several paths connecting macrocells and standard cells to several standard cells; in the node representation, the node representation of each macrocell node includes the representation of several paths connecting that macrocell node to other macrocell nodes to several standard cells, which is the polynomial coefficient corresponding to the k-th power of the distance between that macrocell node and other macrocell nodes.

[0152] In the third example, as shown in Figure 4, the connections between several macrocells include the connections between macrocells and standard cells, while the standard cells are not connected to other macrocells. In the netlist, the connection is "macrocell-standard cell"; in the graph structure, it is represented as "node-connection edge-node", where nodes represent macrocells and standard cells, and connection edges represent the connection between macrocells and standard cells. In the node representation, the node representation of a macrocell node includes the representation of the connection between that macrocell node and the standard cell node, which is reflected in the polynomial coefficients corresponding to the k-th power of the distance between the macrocell node and the standard cell node; the node representation of a standard cell node includes the representation of the connection between that standard cell node and the macrocell node, which is reflected in the polynomial coefficients corresponding to the k-th power of the distance between the standard cell node and the macrocell node.

[0153] In the fourth example, as shown in Figure 4, the connection relationships between several macrocells include the connection relationships between macrocells and ports. In the netlist, the connection relationship is "macrocell-port"; in the graph structure, it is represented as "node-connection edge-node", where nodes represent macrocells and ports, and connection edges represent the connection relationships between macrocells and ports. In the node representation, the node representation of a macrocell node includes the representation of the connection relationship between that macrocell node and the port, which is reflected in the polynomial coefficients corresponding to the k-th power of the distance between that macrocell node and the port node; the node representation of a port node includes the representation of the connection relationship between that port node and the macrocell node, which is reflected in the polynomial coefficients corresponding to the k-th power of the distance between that port node and the macrocell node.

[0154] It should be noted that in practical applications, the connection relationships between several macrocells may include at least one of the four examples mentioned above, and this application embodiment does not limit this. In this application embodiment, some examples and formulas are illustrated using the connection relationship of "macrocell-macrocell" as an example, which is merely exemplary. That is to say, the connection relationship of "macrocell-macrocell" can also be extended to other examples in the four examples mentioned above, all of which are within the protection scope of this application embodiment. For example, the input of the index prediction model is the data of "macrocell-macrocell" connection and "macrocell-port" connection; the graph structure consists of macrocell nodes, port nodes, and connection edges; the distance between nodes includes the distance between macrocells, the distance between macrocells and ports, etc.; furthermore, in the optimization process of the index prediction model, the position of the port is a known item, and the position of the macrocell is an unknown quantity. The index prediction model can predict the predicted value of the PPA evaluation index of the final circuit, thereby determining the optimal position of the macrocell.

[0155] Step S320: Input the connection relationship information and location information into the indicator prediction model to output the predicted values ​​of the evaluation indicators. Here, the evaluation indicators represent several metrics used to evaluate at least one of the performance, power consumption, and area of ​​the circuit formed by the candidate layout. The predicted values ​​of the evaluation indicators represent the predicted values ​​of several metrics used to evaluate a specific circuit, which refers to a circuit obtained through several steps including the candidate layout.

[0156] In one possible implementation, the predicted value of the evaluation metric represents the predicted value of several metrics used to evaluate the circuit. The several metrics include at least one of intermediate surrogate metrics and cross-stage metrics. The intermediate surrogate metrics represent metrics related to one stage in the circuit formation process, and the cross-stage metrics represent metrics related to multiple stages in the circuit formation process.

[0157] In one possible implementation, the intermediate proxy metric includes at least one of line length and congestion degree; the cross-stage metric includes a time-series metric, which includes at least one of worst-case negative time-series margin and total negative time-series margin.

[0158] In one possible implementation, the index prediction model is derived based on Laurent polynomial modeling. The Laurent polynomial includes a power polynomial and polynomial coefficients; the power polynomial relates to the positions of several macrocells, and the polynomial coefficients relate to the connectivity between macrocells in the candidate layout. In other implementations, the index prediction model can also be derived based on other algorithms, such as Taylor series.

[0159] Understandably, the quality of macrocell placement directly affects the quality of the final integrated circuit. Therefore, there is a certain non-linear relationship between macrocell placement and the actual values ​​of integrated circuit evaluation metrics. The purpose of the metric prediction model is to learn this non-linear relationship, so that it can output predicted values ​​of integrated circuit evaluation metrics after taking macrocell placement as input.

[0160] Furthermore, according to the principle of Laurent polynomials, equations of nonlinear relationships can be expanded into the summation of power series of unknowns. Therefore, at the algorithmic level, the index prediction model needs to learn the power series polynomials in the Laurent polynomials, such as the powers of the positions of several macrocells; the index prediction model also needs to learn the polynomial coefficients in the Laurent polynomials, such as the node representations obtained based on the connection relationships between several macrocells.

[0161] In other words, the indicator prediction model can simulate a power polynomial based on the positions of several macrocells; it can also simulate polynomial coefficients based on the connection relationships between macrocells; and then fit the power polynomial and polynomial coefficients to obtain the expression of the Laurent polynomial. The result of the Laurent polynomial is the predicted value of the evaluation indicator.

[0162] In one possible implementation, the metric prediction model includes a first network and a second network. The candidate layouts include first information and second information; the first information represents the connection relationships between several macrocells, and the second information represents the positions of several macrocells. Specifically, the first information is used as input to the first network, which outputs polynomial coefficients; the second information and the polynomial coefficients are used as input to the second network, which outputs the predicted values ​​of the evaluation metrics for the candidate layouts.

[0163] In other words, depending on the different functions implemented, the indicator prediction model may include a first network and a second network. The first network is used to learn the connection relationships between several macrounits and output polynomial coefficients. The second network is used to learn the positions of several macrounits and fit Laurent polynomials based on the polynomial coefficients to output predicted values ​​of the evaluation indicators of the candidate layouts.

[0164] In one possible implementation, the first network is a graph neural network. Specifically, based on the first information, a graph structure is obtained, which includes several nodes and several connecting edges. Nodes represent macrounits, and connecting edges represent the connection relationship between every two macrounits. The graph structure is used as the input to the graph neural network, and the node representation information of each node is output. Based on the node representation information, the polynomial coefficients are obtained.

[0165] For example, the input netlist can be represented as graph data G(V, E), where nodes V are macrocells to be placed, and edges E represent the connections between any two macrocells. The input netlist contains various types of cells (standard cells, ports, macrocells, etc.) and the connections between them. The features of edge E include the number of standard cells between two macrocells and the number of paths between different standard cells. For example, node features include length, width, area, and number of pins; edge features include a weighted average of the number of connections.

[0166] For example, node features are extracted using Graph Neural Networks (GNNs). As shown in Equation (1), G represents the graph data G(V, E); θ represents the parameters of the graph neural network; H represents the node representation generated by the graph neural network; by aggregating the features of edge E, the node representation H of a macrocell node can represent the connection relationship between the macrocell node and other macrocells. H = GNN θ (G) (1)

[0167] For example, suppose the value of the evaluation metric λ is y λ Since is a function of netlist H and layout position X, we can obtain the expression shown in formula (2). Where λ is the index of the evaluation metric being considered, and y... λ It is the numerical value of the evaluation metric, f λ It is a prediction function, which is used to predict the value of the evaluation metric λ y based on the node representation H and the layout position X. λ y λ =f λ (H,X) (2)

[0168] For example, the node representation H can be expressed in the form shown in formula (3), H 1-N H1 represents the node representation of all nodes; H1 represents the node representation of the first node, H1 = [a 11 a 12 … a 1N ]; H N H represents the node representation of the Nth node.N =[a N1 a N2 … a NN For example, a 12 Let a represent the polynomial coefficients of node 1 and node 2. 12 It can be represented as a multidimensional vector, for example, This indicates that the polynomial coefficients of node 1 and node 2 are two-dimensional data. The coefficients represent the polynomial coefficients corresponding to the k-th power of the distance between several macrocells 1 and 2 of the λ-th index.

[0169] In one possible implementation, the distances of several macrocells are determined based on the second information; a power polynomial is determined based on the distances of the several macrocells, where the power polynomial represents the k-th power of the distances of the several macrocells, and k is a natural number; a Laurent polynomial is obtained based on the power polynomial and its coefficients; and a predicted value of the evaluation index of the candidate layout is obtained based on the Laurent polynomial.

[0170] For example, the distance between macrocell i and macrocell j is denoted as r. i,j Based on the distance r of several macrocells i,j Determine the power polynomial Represents the distance r between several macrocells i,j The k-th power. Optionally, the distance r of several macrocells. i,j It can be obtained according to the distance calculation formula of the Cartesian coordinate system, such as the ||x| shown in formula (4). i -x j ||2; where x i This represents the coordinates of macrocell i, such as the coordinates of the center point of macrocell i; x j Represents the coordinate value of macrocell j; ||x i -x j ||2 represents the distance between macrocells i and j in Cartesian coordinates, denoted as r. i,j . ||x represents the distance between macrocell i and macrocell j in Cartesian coordinates. i -x j ||2 raised to the power of k. Where k is the object of the second network learning of the index prediction model; as shown in formula (4), K is the result of the second network learning, and K represents the set of values ​​of k raised to the power of k.

[0171] In formula (4), the embodiments of this application fit the numerical value y of the evaluation index λ using the form of a Laurent polynomial function as shown in formula (4). λ ; This represents the predicted value of the evaluation index λ; This represents the function after the prediction function is expanded into a Laurent polynomial.

[0172] In formula (4), ||x| represents the distance ||x| between macrocells i and j representing the evaluation metric λ. i -x j The polynomial coefficients corresponding to the k-th power of 2 can be represented by the total number of nodes H. 1-N It was obtained from the middle.

[0173] Step S330: Based on the predicted values ​​of the evaluation indicators and the alternative layouts, obtain the target layout of t macrocells.

[0174] In one possible implementation, the target layout is obtained by optimizing the positions of several macrocells in the candidate layouts with the goal of optimizing the predicted values ​​of the evaluation metrics.

[0175] For example, as shown in formula (5), Λ represents the set of evaluation indicators formed by multiple evaluation indicators λ; α λ This represents the predicted value of the evaluation index λ. The weight, α λ This is a hyperparameter that adjusts the importance percentage of each indicator; the default value is 1. This can be understood as a pre-trained metric prediction model, whose inputs are node representations H and macrocell locations X, and whose output is the predicted value of the evaluation metric λ. V represents the layout space, χ represents the range of values ​​for the macro cell position X; G0 represents other cells already placed in the layout space V; Overlap(·) represents the overlapping part, and st represents the constraint condition.

[0176] As shown in formula (5), the index prediction model based on the above polynomial form... The macrocell placement problem can be represented as a polynomial optimization problem. For example, assuming that smaller evaluation metrics result in better integrated circuit placement quality, the macrocell placement problem can be transformed into finding the optimal placement location X by minimizing the sum of the predicted values ​​of all evaluation metrics. In one example, in the placement task, the chip is discretized into an 84×84 grid, and chip macrocells are placed on the grid points. Let χ be the set of all grid points. The macrocell placement problem can be transformed into finding the optimal placement location X in the set χ by minimizing the sum of the predicted values ​​of all evaluation metrics.

[0177] For example, this optimization method is an explicit polynomial optimization method, equivalent to a white-box optimization algorithm. When using the white-box optimization algorithm, a greedy strategy can be avoided, and the optimal positions of all macrocells can be obtained by solving formula (5). Specifically, in the white-box optimization algorithm, the expression of formula (5) is known, and the relationship between the predicted value of the evaluation index and the position X is explicit, that is, the polynomial coefficients and power polynomials in the Laurent polynomial are known. Based on formula (5), combined with the gradient descent method, the optimal solution for the positions of all macrocells can be obtained without using a greedy strategy to calculate the optimal position of each macrocell one by one.

[0178] In one possible implementation, a layout optimization method based on a greedy strategy is provided. The target layout is obtained by placing a number of macrocells sequentially through several iterative steps. Specifically, in the iterative step of placing the t-th macrocell, the positions of several macrocells in the candidate layouts are optimized with the goal of optimizing the predicted value of the evaluation metric, resulting in the target layout. Here, t is an integer greater than or equal to 2. This includes: obtaining the predicted values ​​of the evaluation metrics of several candidate layouts; the candidate layouts are obtained by placing the t-th macrocell in the layout of the first t-1 macrocells; and based on the predicted values ​​of the evaluation metrics of the candidate layouts, obtaining the layout of the first t macrocells from the candidate layouts.

[0179] For example, in some scenarios, due to the large number of macrocells and the existence of no-overlap constraints, the polynomial optimization problem shown in Equation (5) is still difficult to solve. To this end, based on the explicit polynomial form of the above optimization problem, this application embodiment also provides a greedy strategy to achieve efficient layout optimization. Specifically, as shown in Equation (6), each macrocell is placed sequentially. At step t, the positions of the first t-1 macrocells have been determined. In order to place the tth macrocell, it is necessary to solve for the optimal position of the tth macrocell.

[0180] In formula (6), after fixing the layout of the first t-1 macrocells, the t-th macrocell is added, resulting in the layout of the first t macrocells; Δ t (x t Δ represents the difference between the predicted values ​​of the evaluation metrics for the layout of the first t macrocells and the predicted values ​​of the evaluation metrics for the layout of the first t-1 macrocells. Alternatively, since the layout of the first t-1 macrocells is fixed, the predicted values ​​of the evaluation metrics for the layout of the first t-1 macrocells are also fixed, Δ t (x t It can also represent the predicted value of the evaluation index of the layout of the first t macrocells.

[0181] Assuming that a smaller evaluation metric indicates better integrated circuit layout quality, then minimizing Δ... t (x tBased on the principle of finding the optimal position x of the t-th macrocell, we can determine the optimal position x of the t-th macrocell. t The solution.

[0182] In one possible implementation, based on a preset optimization algorithm, the predicted value of the optimal evaluation index is obtained from the predicted values ​​of several candidate layouts; the candidate layout corresponding to the predicted value of the optimal evaluation index is determined as the layout of the first t macrocells.

[0183] In other words, to minimize Δ t (x t Based on the principle of finding the optimal position x of the t-th macrocell, we can determine the optimal position x of the t-th macrocell. t The solution can be achieved through various pre-defined optimization algorithms. These pre-defined optimization algorithms include black-box optimization algorithms, white-box optimization algorithms, deep learning algorithms, and so on.

[0184] For example, taking a black-box optimization algorithm, we can enumerate all possible positions for the t-th macrocell and obtain the Δ for each position. t (x t ), and Δ for all positions t (x t In the input value black-box optimization module, the black-box optimization module obtains the Δ corresponding to all positions according to the black-box optimization algorithm. t (x t The sorting of macrocells is performed; based on the sorting results, the optimal macrocell layout can be obtained.

[0185] For example, taking the white-box optimization algorithm, the expression of formula (6) is known, and the relationship between the predicted value of the evaluation index and the position X is explicit, that is, the polynomial coefficients and power polynomial in the Laurent polynomial are known. Based on formula (6) and combined with the gradient descent method, the optimal position of the t-th macrocell can be found without enumerating all possible positions of the t-th macrocell.

[0186] It is understandable that, in the actual layout of macrocells, in addition to combining the above-mentioned greedy strategy and the above-mentioned black-box optimization algorithm, the above-mentioned greedy strategy can also be combined with other black-box optimization algorithms or deep learning algorithms.

[0187] In this embodiment, a polynomial fitting function is used to predict the final PPA index corresponding to the layout, thereby achieving end-to-end optimization of the PPA index across stages. Existing methods typically only target intermediate indices such as line length in the layout stage, without directly predicting and optimizing the PPA. End-to-end optimization means that the candidate layouts of macrocells are input into the index prediction model, which directly generates the predicted value of the final PPA index, without needing to simulate the entire layout process of the integrated circuit and then obtain the final PPA index based on the final circuit layout, resulting in higher computational efficiency.

[0188] One possible implementation provides a layout optimization method that does not use a greedy strategy. Based on the predicted values ​​of evaluation metrics, reward scores for candidate layouts are determined; the candidate layouts and reward scores are then used as input to a reinforcement learning model to output the target layout.

[0189] For example, the initial solution for each macrocell position can be obtained using an evolutionary algorithm. During the layout evaluation phase, the placement of the initial solution can be optimized into a legal layout using the greedy strategy described above.

[0190] In other words, when executing step S330, as shown in formula (6), a greedy strategy can be used to determine the position of each macrocell one by one based on the candidate layout and the predicted value of the evaluation index, until the target layout of several macrocells is obtained; or, as shown in formula (5), the greedy strategy can be avoided, and the candidate layout can be optimized based on the explicit relationship between the predicted value of the evaluation index and the position of the macrocells to obtain the target layout of several macrocells. The following is a further illustrative explanation with reference to Figure 5.

[0191] For example, after training a performance evaluation model for the PPA metric, it can be applied to a reinforcement learning framework to improve the optimization efficiency of macrocell placement samples, accelerate the convergence of the reinforcement learning algorithm, and thus improve the PPA metric of the final circuit. Specifically, when running the reinforcement learning algorithm, a greedy strategy can be optionally used to limit the action space of reinforcement learning, so that each step of placing macrocells greedily improves PPA performance, resulting in candidate layouts after placing all macrocells; the performance evaluation model is used to predict the evaluation metric of the candidate layouts, obtaining the predicted value of the evaluation metric; based on the predicted value of the evaluation metric output by the performance evaluation model, the reward signal for reinforcement learning is obtained; and then the layout optimization process of reinforcement learning is performed.

[0192] For example, Figure 5 illustrates two strategies for determining the target layout provided in embodiments of this application. As shown in Figure 5, the macrocell layout process may include a greedy strategy based on a black-box optimization algorithm and a process based on other strategies. For example, other strategies include reinforcement learning algorithms, white-box optimization algorithms, etc.

[0193] Furthermore, in the black-box optimization algorithm, the greedy strategy-based process includes: placing the next macrocell in the current layout of the first t-1 macrocells to obtain multiple candidate layouts for the first t macrocells; inputting the multiple candidate layouts and their netlists of the first t macrocells into the metric prediction model, which outputs the predicted values ​​of the evaluation metrics; evaluating each metric based on the predicted values ​​of the evaluation metrics for each candidate layout to obtain the optimal position of the t-th macrocell; placing the t-th macrocell in the optimal position; and further optimizing based on the current layout of the first t macrocells until the target layout is obtained.

[0194] Furthermore, in the process based on other strategies: the current layout of all macro cells and their netlists are input into the metric prediction model, and the metric prediction model outputs the predicted values ​​of the evaluation metrics; each metric is evaluated based on the predicted values ​​of the evaluation metrics of the current layout; based on the evaluation results, the current layout is optimized until the target layout is obtained.

[0195] For example, Figure 6 illustrates a schematic diagram of an example of combining the indicator prediction model with a greedy strategy provided in an embodiment of this application. As shown in Figure 6, the input information of the indicator prediction model is obtained from the netlist, and the indicator prediction model determines the polynomial based on the information in the netlist. The macrocells to be placed, as shown in the dashed box in Figure 6, are arranged to obtain multiple candidate layouts. These candidate layouts are then input into the index prediction model. Based on the position data of each macrocell in the candidate layouts, the index prediction model derives a power polynomial. The indicator prediction model is based on polynomials and power polynomial The fitted Laurent polynomial is obtained, and the predicted values ​​of each index are output. The predicted values ​​of each index are evaluated to obtain the optimal alternative layout, resulting in a layout including the macrocells to be placed, for optimizing the placement of the next macrocell.

[0196] As shown in Figure 6, in this embodiment of the application, the indicator prediction model is a learnable PPA predictor. Therefore, the macrocell layout method in this embodiment of the application is also called a learnable optimization method (Learning mask, L-mask).

[0197] For example, Figure 7 illustrates a schematic diagram of the indicator prediction model provided in this application, which outputs predicted values ​​of multiple evaluation indicators and is applied to a prediction task of a newly added indicator. As shown in Figure 7, alternative layouts are input into the indicator prediction model to output predicted values ​​of the evaluation indicators. The alternative layouts include netlist data indicating macrocell connection relationships and layouts indicating macrocell locations. The graph neural network (an example of a first network) in the indicator prediction model generates node representations of each macrocell node based on the netlist data; wherein, for different layouts with the same netlist data, the node representations are shared. The polynomial fitting network (an example of a second network) in the indicator prediction model determines the power of the power polynomial based on the polynomial coefficients corresponding to the node representations and the macrocell distances corresponding to the layouts, and fits the Laurent polynomial.

[0198] As shown in Figure 7, the indicator prediction model can predict the values ​​of multiple evaluation indicators. For example, the indicator prediction model sets Head1 to predict the indicator WNS; Head2 to predict the indicator TNS; Head3 to predict the indicator Congestion; ...; and Headn to predict indicator n. Here, Head is the network that acquires the network output content, and Head can make predictions using the extracted features.

[0199] In this embodiment, when it is necessary to use the indicator prediction model to predict new indicators or new tasks, the indicator prediction model can be fine-tuned. The fine-tuned indicator prediction model can be applied to the new task, and new indicators can be generated for the alternative layouts of macrocells. For example, a Head n can be set in the indicator prediction model, and Head n is used to predict the new indicator n. This method has low fine-tuning cost, the indicator prediction model is more efficient in applying to new tasks, and has good generalization. In contrast, reinforcement learning-based technical solutions have poor generalization and still require a lot of training and fine-tuning on new circuits.

[0200] In this embodiment of the application, when the number of indicators is large, the number of labels used for training increases, while the number of training samples remains unchanged or does not change much. Therefore, the training time does not increase linearly with the increase of the prediction task.

[0201] This application provides a solution for multi-PPA prediction optimization tasks, where training time does not increase linearly with the number of prediction tasks. A single training iteration can predict multiple different PPA metrics. The generation time of the target layout can be controlled in minute-level iterative evolution. In the method of this application, the node representation layer of the coordinate prediction model is shared, and then multiple networks are connected to predict different PPA metrics respectively.

[0202] For example, Figure 8 illustrates a schematic diagram of the training and inference phases of the indicator prediction model provided in an embodiment of this application. As shown in Figure 8, it can be understood that the indicator prediction model is a neural network model, which includes a training phase and an inference phase.

[0203] Furthermore, during the training phase, the metric prediction model is trained offline using the training dataset. During the inference phase, the trained metric prediction model is deployed, with candidate layouts used as input, and the predicted values ​​of the evaluation metrics corresponding to each candidate layout are output. Based on the predicted values ​​of the evaluation metrics, the candidate layout is optimized until the target layout is obtained. It should be noted that the above method is equivalent to the inference method of the metric prediction model, and will not be elaborated further here.

[0204] For example, Figure 9 shows a flowchart illustrating a training method for an indicator prediction model provided in an embodiment of this application. As shown in Figure 9, a training method for an indicator prediction model mainly includes the following steps:

[0205] Step S910: Construct a training dataset. The training dataset includes several layout samples and corresponding metric labels for each layout sample. The layout samples represent the connection relationships between several macrocells and the positions of several macrocells. The metric labels represent the metric values ​​of several metrics obtained from evaluating the circuit samples. The circuit samples are obtained through several steps, including the layout samples.

[0206] In one possible implementation, the process of constructing the training dataset includes: determining several mesh representation examples, which are used to characterize the connection relationships of several units to be laid out, and the units to be laid out include several macrocells; constructing several layout samples corresponding to each mesh representation example to obtain the training dataset.

[0207] In this implementation, a netlist example refers to several known netlists. For example, several netlists can be obtained from a netlist database as netlist examples. Based on the netlist examples, various macrocells are arranged to obtain layout samples, which in turn form the training dataset. Constructing the training dataset based on the netlists can train the accuracy of the metric prediction model in predicting metrics based on a single layout sample, and also train the accuracy of ranking the metric prediction results based on multiple layout samples, further reducing the error in predicting metrics from multiple layout samples.

[0208] For example, Figure 10 illustrates a schematic diagram of the construction process of the training dataset provided in an embodiment of this application. As shown in Figure 10, in one example, in a method for constructing a training dataset, the first step is to expand the layouts according to netlist 1 to obtain multiple layout samples, such as layout 1, layout 2, etc.; and to expand multiple layouts according to other netlists. The second step is to obtain the final circuit based on the multiple layouts through a subsequent physical implementation process, calculate the PPA performance of the final circuit corresponding to each layout, and obtain the indicator label corresponding to each layout; for example, the label 1 corresponding to layout 1 is the actual value of different indicators such as line length a1, area b1, congestion c1, and timing d1; the label 2 corresponding to layout 2 is the actual value of different indicators such as line length a2, area b2, congestion c2, and timing d2.

[0209] For example, as shown in Figure 10, the constructed training dataset includes multiple training sample pairs, each pair comprising a training sample and its corresponding metric label. The training samples include a netlist representing macrounit connectivity and a layout representing macrounit location. For instance, as shown in Figure 10, training sample pair 1 includes a training sample and its corresponding label 1; training sample 1 includes netlist 1 and layout 1. Multiple training sample pairs belong to the same netlist; for example, training sample pair 1, training sample pair 2, ..., training sample pair m have the same netlist 1; training sample pair m+1, ..., training sample pair n have the same netlist 2. Each netlist-corresponding training sample pair can be further divided into one or more training data subsets, each subset being called a training batch, thereby training the metric prediction model to improve the ranking accuracy of each training sample within the training data subset.

[0210] Step S920: Use the layout sample as input to the indicator prediction model and output the predicted value of the evaluation indicator of the layout sample.

[0211] Step S930: Determine the indicator loss value based on the indicator label and the predicted value of the evaluation indicator.

[0212] Optionally, the indicator loss value may include the loss value of the indicator fitting error. The indicator loss value may also include the loss value of the ranking error.

[0213] In one example, the indicator label y λ and the predicted values ​​of the evaluation indicators The loss function is shown in formula (7), and the index loss value L is then determined. MSE For example, the loss function can be the mean squared error of the indicator measurement, used to calculate the ability of the indicator prediction model to fit the PPA indicator. This application embodiment describes the loss function... The specific implementation method is not restricted.

[0214] Step S940: Adjust the parameters of the indicator prediction model based on the indicator loss value.

[0215] For example, Figure 11 illustrates a schematic diagram of an example of the training process of the metric prediction model provided in an embodiment of this application. As shown in Figure 11, in one example, firstly, the training dataset, namely the netlist and layout samples and their metric labels y, is obtained. λ During the training of the indicator prediction model, a training dataset can be constructed based on the netlist, which will not be elaborated here. Next, the netlist is input into the first network of the indicator prediction model: a graph neural network, to obtain node representations, i.e., multinomial coefficients. Next, based on the layout sample, the distance r of each macrocell is obtained. ij The distance and polynomial coefficients The second network of the input index prediction model is a multinomial fitting network. Based on the multinomial fitting function, the multinomial fitting network learns the power k of the power polynomial and fits the polynomial coefficients. and distance Obtain the predicted value of the evaluation index Finally, based on the predicted values ​​of the evaluation metrics... and indicator label y λ Calculate the loss function Then adjust the parameters of the indicator prediction model. Loss function. It is also known as index fitting error.

[0216] In one possible implementation, the training dataset includes several training data subsets and ranking labels for the layout samples in each training data subset. The training data subsets are obtained by dividing the layout samples based on the connectivity relationships between macrounits within the layout samples. For example, several layout samples corresponding to the same network representation can be divided into one or more training data subsets. This ensures that the connectivity relationships between macrounits in the layout samples of each training data subset are identical, allowing the layout samples in the training data subsets to be ranked to train metrics to predict the ranking accuracy of the model. The ranking labels are obtained based on the metric labels of the layout samples within the training data subsets, such as Rank(y) as shown in formula (8). λ This application's embodiments address the loss function. The specific implementation method is not restricted. Rank(y) λ This is also known as sorting error.

[0217] Furthermore, based on the predicted values ​​of the evaluation metrics of the layout samples in the training data subset, the predicted ranking values ​​of the layout samples in the training data subset are obtained, as shown in Formula (8). As shown in formula (8), according to the sorting label Rank(y) λ) and ranked predicted values The ranking loss value L is obtained from the layout samples in the subset of training data. Rank .

[0218] Furthermore, the parameters of the indicator prediction model can be adjusted based on the indicator loss value and the ranking loss value. For example, as shown in formula (8), the final loss function L is the indicator loss value L. MSE And sorting loss value L Rank The weighted result. Where, L MSE L represents the mean square error of the prediction. Rank β1 represents the sorting error between different layouts; β2 and β1 are weighting coefficients, β1·L MSE Used to guide the indicator prediction model to fit the PPA index, β2·L Rank The ranking results of the PPA used to guide the fitting of the indicator prediction model circuit. L=β1vL MSE +β2·L Rank (9)

[0219] In one example, an offline dataset was constructed to train the aforementioned PPA predictor. The offline dataset included eight different chip circuits (i.e., eight different netlists). Different algorithms were run on each circuit to obtain 200 different layouts. After subsequent physical implementation, the final circuit was obtained, and its PPA performance was calculated to obtain a metric label. A total of 1600 layout samples were constructed from the eight different netlists. These 1600 layout samples belonged to eight different training data subsets. Within each training data subset, a ranking loss value L could be applied. Rank Training; each layout sample can be used to calculate the index loss value L. MSE Training.

[0220] For example, when the relative differences in the predicted values ​​of evaluation metrics for samples with different layouts are large, ranking errors are less likely to occur, i.e., L Rank If the size is small, then it can be achieved by using only L. MSE Adjust the parameters of the indicator prediction model; when the relative differences in the predicted values ​​of evaluation indicators for samples with different layouts are small, ranking errors are prone to occur. In this case, L can be used. MSE and L Rank By combining loss functions and adjusting the parameters of the indicator prediction model, the prediction accuracy of the indicator prediction model can be further improved.

[0221] Understandably, the performance indicator prediction model can predict the PPA (Power Performance Area) of the final circuit based on the macrocell layout. However, there are several steps (referred to as "subsequent steps") between the macrocell layout and the final circuit. To ensure the accuracy of the predicted performance indicators output by the performance indicator prediction model, it is necessary to ensure that the subsequent steps corresponding to the training samples are the same as or similar to the subsequent steps corresponding to the inference side.

[0222] For example, for subsequent steps, the same algorithm can be used on both the training and inference sides to ensure the accuracy of the prediction results of the indicator prediction model; or, the algorithm on the training side and the algorithm on the inference side can be matched through experiments or other methods to ensure that the error of the prediction results of the indicator prediction model is within an allowable range, so that the subsequent steps corresponding to the training samples are similar to the subsequent steps corresponding to the inference side.

[0223] For example, the steps of standard cell placement can be completed automatically by a placement tool. This placement tool automatically places standard cells in a given space, guided by netlist and timing constraints. On both the training and inference sides, this placement tool is based on the same algorithm.

[0224] To further illustrate the beneficial effects of the technical solutions in the embodiments of this application, the methods proposed in the embodiments of this application have also been verified through relevant experiments. The experimental results are analyzed below with reference to a specific example to further illustrate the beneficial effects of the methods provided in the embodiments of this application.

[0225] In one example, the proposed solution outperformed other methods in a series of publicly available benchmark tests, such as the first and second datasets. Compared to other methods, the proposed solution significantly improved multiple metrics, such as a 14.5% reduction in HPWL (half-circumference line length) and effective mitigation of congestion issues. These experimental results fully demonstrate the superior performance of the proposed solution in improving the overall chip design performance. The improvements of the proposed solution in metrics such as WNS, TNS, HPWL, and congestion were evaluated. Experimental results show that the proposed solution significantly outperforms other methods in several key metrics.

[0226] Overall, the embodiments of this application, through innovative polynomial fitting techniques and optimization strategies, not only effectively address the shortcomings of macrocell placement methods in baseline methods, but also significantly improve the overall quality and efficiency of chip design, providing strong technical support for the design of modern very large-scale integrated circuits.

[0227] Tables 1 and 2, Figures 12 and 13 below show a comparison between the method of the present application embodiment and baseline method 1, baseline method 2, baseline method 3 and baseline method 4 on the first dataset and the second dataset.

[0228] Table 1 shows the layout results obtained by training the model of this embodiment on six netlists (netlist 1, netlist 3, netlist 4, netlist 5, netlist 7, and netlist 10) of the first dataset, while performing inference directly on the other netlists. In Table 1, the best results for each method are marked in bold. The average ranking of a method refers to the average ranking of all metrics for that method.

[0229] As can be seen from Table 1, on the first dataset, the method of this embodiment shows significant improvements over the baseline method in all metrics. For example, it improves by 51.4% and 32.6% on the time series metrics TNS and WNS, respectively, and by an average of 14.5% across all metrics.

[0230] As can be seen from Table 2, on the second dataset, the method of this application embodiment has significant improvements over the previous method in multiple metrics, such as WNS and TNS metrics by 3.27% and 7.24% respectively, and the number of violation paths (NVP) metric by 6.80%.

[0231] Figure 12 shows examples of layout effects and congestion diagrams for different schemes on the netlist of the first dataset. For example, as can be seen from Figure 12, on netlist 4 of the first dataset, the method of this embodiment shows significant improvements in various indicators compared to the baseline method, such as a more reasonable layout and less congestion. Taking the layout effect of this embodiment as an example, the layout has the characteristics of relatively concentrated angles and relatively dispersed distances; for example, the layout generated by this embodiment has the characteristic of macrocells being attached to edges and corners. As shown in Figure 12, the macrocell layout is shown in pink, and the resulting congestion is shown in red.

[0232] Figure 13 shows an example of the timing path display of different schemes in the netlist of the second dataset. Exemplarily, as can be seen from Figure 13, in the netlist 113 of the second dataset, the method of this embodiment has a significant improvement in timing metrics compared to previous methods, such as lower signal latency and a slack of -0.192ns. Slack represents the actual latency; when slack is negative, the larger the absolute value, the greater the actual latency of the path, and the less it meets the constraints. As shown in Figure 13, lines of different colors represent specific critical paths; different colors indicate the connection relationships between different macrounits.

[0233] The unit for half-circle length is nm, the unit for TNS and WNS is ns, the unit for power is uW, the unit for NVP is stripe, and the unit for area is nm. 2 .

[0234] Table 1 compares the baseline method of each netlist in the first dataset with the PPA results of the embodiments of this application.

[0235] Table 2 compares the baseline method and PPA results of the embodiments of this application on each netlist of the second dataset.

[0236] Next, based on the methods in the above embodiments, a macrocell layout device and a training device for an index prediction model provided in this application will be introduced.

[0237] Referring to Figure 14, Figure 14 is a schematic diagram of the composition of a macrocell layout device provided in an embodiment of this application. As shown in Figure 11, an embodiment of this application provides a macrocell layout device 1400, which mainly includes:

[0238] The acquisition module 1410 is used to acquire the connection relationship information of t macrocells and their alternative layouts. The alternative layouts include the position information of t macrocells, where t is an integer greater than or equal to 2.

[0239] Processing module 1420 is used to input connection relationship information and location information into the indicator prediction model to output predicted values ​​of evaluation indicators. The evaluation indicators represent several indicators used to evaluate at least one of the performance, power consumption, and area of ​​the circuit formed by the candidate layout; and, based on the predicted values ​​of the evaluation indicators and the candidate layouts, to obtain the target layout of t macrocells.

[0240] In one possible implementation, the above-mentioned indicator prediction model is modeled based on a preset algorithm, which represents an algorithm for fitting the connection relationship between the evaluation indicator and the connection relationship information and location information.

[0241] In one possible implementation, the preset algorithm is a polynomial algorithm, which includes a power polynomial and its coefficients. The power polynomial represents the k-th power of the distance information between t macrocells, where k is a natural number. The aforementioned processing module 1420 is specifically used to: obtain the polynomial coefficients based on the connection relationship information; obtain the power polynomial based on the position information; and combine the polynomial coefficients to obtain the predicted value of the evaluation index.

[0242] In one possible implementation, the indicator prediction model includes a graph neural network. The aforementioned processing module 1420 is specifically used for: obtaining a graph structure based on connection relationship information, the graph structure including several nodes and several connecting edges, where nodes represent macrounits and connecting edges represent the connection relationships between macrounits; inputting the graph structure into the graph neural network to output the node representation of each node; and obtaining polynomial coefficients based on the node representations.

[0243] In one possible implementation, the indicator prediction model includes a multinomial fitting network. Specifically, the processing module 1420 is used to: determine the distance information between t macrounits based on the location information; input the multinomial coefficients and distance information into the multinomial fitting network to output the predicted value of the evaluation indicator.

[0244] In one possible implementation, the polynomial algorithm is the Laurent polynomial algorithm.

[0245] In one possible implementation, multiple candidate layouts are set, and these multiple candidate layouts are obtained by adjusting the positions of t macrocells. The aforementioned processing module 1420 is specifically used to: obtain the target layout of t macrocells from the multiple candidate layouts based on the predicted values ​​of the evaluation metrics of each candidate layout.

[0246] In one possible implementation, the target layout is selected from multiple candidate layouts based on a preset optimization algorithm.

[0247] In one possible implementation, the target layout of the t macrocells is the layout of the first t macrocells obtained in the t-th step of the greedy strategy, and the alternative layouts of the t macrocells are obtained by placing the t-th macrocell in the layout of the first t-1 macrocells.

[0248] In one possible implementation, the aforementioned processing module 1420 is specifically used to: determine the reward score of the candidate layout based on the predicted value of the evaluation index; when the candidate layout is the connection relationship information of t macro units as input to the reinforcement learning network, output the prediction result of the layout of t macro units; input the reward score into the reinforcement learning network to output the target layout of t macro units.

[0249] In one possible implementation, the evaluation metrics include cross-stage metrics, which represent metrics related to multiple stages in the process of evaluating alternative layouts forming circuits.

[0250] In one possible implementation, the cross-stage metric includes a time-series metric, which includes at least one of worst-case negative time-series margin and total negative time-series margin.

[0251] In one possible implementation, the connection relationship information is obtained through the netlist data of t macrocells. The netlist data is used to characterize the connection relationship of several cells to be laid out, which include t macrocells.

[0252] In one possible implementation, the indicator prediction model is obtained by training on a training dataset. The loss function of the training process of the indicator prediction model includes the indicator fitting error, which characterizes the error between the predicted value of the evaluation indicator output by the indicator prediction model and the true value of the evaluation indicator.

[0253] In one possible implementation, the loss function of the training process of the indicator prediction model also includes the ranking error, which represents the error between the predicted values ​​of the ranking of several training samples in the training dataset and the true values ​​of the ranking. The ranking prediction values ​​are obtained by ranking several training samples according to the predicted values ​​of the evaluation indicators output by the indicator prediction model.

[0254] In one possible implementation, the training dataset includes several training samples, which are obtained by constructing different macrocell layouts for each netlist sample in several netlist samples.

[0255] In one possible implementation, the indicator prediction model is further obtained by fine-tuning the dataset, which is based on newly added indicators in addition to the existing evaluation indicators.

[0256] Referring to Figure 15, Figure 15 is a schematic diagram of the composition of a training device for an indicator prediction model provided in an embodiment of this application. As shown in Figure 15, this embodiment of the application provides a training device 1500 for an indicator prediction model, including:

[0257] The dataset construction module 1510 is used to construct the training dataset. The training dataset includes several layout samples and corresponding metric labels for each layout sample. The layout samples represent the connection relationships and positions of several macrocells, and the metric labels represent the metric values ​​of several metrics obtained from evaluating the circuit samples. The circuit samples are obtained through several steps, including the layout samples.

[0258] The training module 1520 is used to take the layout samples as input to the indicator prediction model and output the predicted values ​​of the evaluation indicators of the layout samples; and to determine the indicator loss value based on the indicator labels and the predicted values ​​of the evaluation indicators; and to adjust the parameters of the indicator prediction model based on the indicator loss value.

[0259] In one possible implementation, the training dataset includes several training data subsets and ranking labels for layout samples within each subset. The training data subsets are obtained by dividing the dataset into several layout samples based on the relationships between several macrounits within those layout samples. The ranking labels are derived from the metric labels of the layout samples within each training data subset. The training module 1520 is specifically used for: obtaining the predicted ranking values ​​of the layout samples within the training data subset based on the predicted values ​​of the evaluation metrics; obtaining the ranking loss values ​​of the layout samples within the training data subset based on the ranking labels and the predicted ranking values; and adjusting the parameters of the metric prediction model based on the metric loss values ​​and the ranking loss values.

[0260] In one possible implementation, the dataset construction module 1510 is specifically used to: determine several mesh representation examples, which are used to characterize the connection relationships of several units to be laid out, and the units to be laid out include several macro units; and construct several layout samples corresponding to each mesh representation example to obtain a training dataset.

[0261] In one possible implementation, the indicator prediction model is also used to generate predicted values ​​for new indicators, which are new evaluation indicators added in addition to the existing evaluation indicators. The training module 1520 is also used to: determine the fine-tuning dataset based on the new indicators; and fine-tune the trained indicator prediction model based on the fine-tuning dataset to obtain the fine-tuned indicator prediction model, which is used to generate predicted values ​​for the new indicators.

[0262] The software and hardware implementation of a macrocell layout device 1400 as shown in Figure 14 and / or a training device 1500 for an index prediction model as shown in Figure 15 (hereinafter referred to as: related devices of the macrocell layout method) needs further explanation.

[0263] As an example of a software functional unit, a module can include code running on a computing instance. A computing instance can include at least one of a physical host (computing device), a virtual machine, or a container. Furthermore, the aforementioned computing instance can be one or more. For example, a module can include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code can be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code can be distributed within the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region can include multiple AZs.

[0264] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0265] As an example of a hardware functional unit, a module may include at least one computing device, such as a server. Alternatively, a module may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The aforementioned PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0266] The multiple computing devices included in the module can be distributed within the same region or in different regions. Similarly, the multiple computing devices included in the module can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the module can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0267] It should be noted that, in other embodiments, the related apparatus of the macrocell layout method is additionally provided with one or more modules for performing any of the steps included in the above implementation. The steps implemented by one or more modules in the related apparatus of the macrocell layout method can be specified as needed, and more or fewer modules than in the embodiments of this application can be obtained to implement different steps in the above method, thereby realizing all the functions of the related apparatus of the macrocell layout method.

[0268] This application also provides a computing device 1600. As shown in FIG16, the computing device 1600 includes: a bus 1602, a processor 1604, a memory 1606, and a communication interface 1608. The processor 1604, the memory 1606, and the communication interface 1608 communicate with each other via the bus 1602. The computing device 1600 can be a server, such as a central server, an edge server, or a local server in a local data center, or it can be an electronic device such as a desktop computer, a laptop computer, or a smartphone. It should be understood that this application does not limit the number of processors and memories in the computing device 1600.

[0269] Bus 1602 can be a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL), a Cache Coherent Interconnect for Accelerators (CCIX), etc. The Unified Bus is also known as the Lingqu Bus. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 16 uses only one line, but this does not imply that there is only one bus or one type of bus. Bus 1604 can include pathways for transmitting information between various components of computing device 1600 (e.g., memory 1606, processor 1604, communication interface 1608).

[0270] The processor 1604 may include any one or more of the following computing devices: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP) or digital signal processor (DSP), ASIC, FPGA, CPLD, NPU, SoC, offload card, accelerator card, etc.

[0271] Memory 1606 may include volatile memory, such as random access memory (RAM). Processor 1604 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD). Furthermore, memory 1606 may also be implemented using storage class memory (SCM), phase change memory (PCM), or other types of storage media.

[0272] It is worth noting that the same type of storage medium can be configured in the same computing device to realize the function of memory 1606, or two or more types of storage media can be configured to realize the function of memory 1606. This application does not limit this.

[0273] The memory 1606 stores executable program code, and the processor 1604 executes the executable program code to implement the functions of the relevant devices of the macrocell layout method, thereby implementing the method described in the above embodiments. That is, the memory 1606 stores instructions for executing the method described in the above embodiments.

[0274] Alternatively, the memory 1606 stores executable code, which the processor 1604 executes to implement the functions of the relevant devices of the macrocell layout method, thereby implementing the method described in the above embodiments. That is, the memory 1606 stores instructions for executing the method described in the above embodiments.

[0275] The communication interface 1608 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 1600 and other devices or communication networks.

[0276] As one possible implementation, the computing device 1600 may also include a chip system, which includes a processor and a power supply circuit. The power supply circuit supplies power to the processor, and the processor executes the operation steps corresponding to the methods of the embodiments of this application. For simplicity, further details are omitted here. The processor can be implemented using a GPU, or it can be implemented using computing devices or AI chips such as a DPU, NPU, XPU, SoC, offload card, or accelerator card.

[0277] As one possible implementation, the computing device 1600 may include various types of processors 1604, meaning the computing device 1600 is a heterogeneous device. For example, the computing device 1600 may include a CPU and a GPU, and at least one of the processors 1604 may execute the operation steps corresponding to the methods of the embodiments of this application. For the sake of brevity, further details are omitted here.

[0278] This application also provides a computing device cluster. The computing device cluster includes at least one computing device. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be an electronic device such as a desktop computer, a laptop computer, or a smartphone.

[0279] As shown in Figure 17, the computing device cluster includes at least one computing device 1600. The memory 1606 of one or more computing devices 1600 in the computing device cluster may store the same instructions for performing the methods described in the above embodiments.

[0280] In some possible implementations, the memory 1606 of one or more computing devices 1600 in the computing device cluster may also store partial instructions for executing the methods described in the above embodiments. In other words, a combination of one or more computing devices 1600 can jointly execute instructions for performing the methods described in the above embodiments.

[0281] It should be noted that the memory 1606 in different computing devices 1600 within the computing device cluster can store different instructions, each used to execute a portion of the functions of the relevant apparatus of the macrocell layout method. That is, the instructions stored in the memory 1606 of different computing devices 1600 can implement the functions of one or more modules of the relevant apparatus of the macrocell layout method.

[0282] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc. Figure 18 illustrates one possible implementation. As shown in Figure 18, two computing devices 1600A and 1600B are connected via a network. Specifically, they are connected to the network through communication interfaces in each computing device. In this type of possible implementation, the memory 1606 in computing device 1600A stores instructions for the functions of one or more modules of the related apparatus of the macrocell layout method. Simultaneously, the memory 1606 in computing device 1600B stores instructions for the functions of another one or more modules of the related apparatus of the macrocell layout method.

[0283] It should be understood that the functions of computing device 1600A shown in Figure 18 can also be performed by multiple computing devices 1600. Similarly, the functions of computing device 1600B can also be performed by multiple computing devices 1600.

[0284] This application also provides another computing device cluster. The connection relationship between the computing devices in this computing device cluster can be similarly referred to the connection method of the computing device cluster described in Figures 17 and 18. The difference is that the memory 1606 in one or more computing devices 1600 in this computing device cluster can store the same instructions for executing the methods in the above embodiments.

[0285] In some possible implementations, the memory 1606 of one or more computing devices 1600 in the computing device cluster may also store partial instructions for executing the aforementioned methods. In other words, a combination of one or more computing devices 1600 can jointly execute the instructions for executing the aforementioned methods.

[0286] Based on the methods in the above embodiments, this application provides a computer-readable storage medium including computer program instructions. When executed by a cluster of computing devices including at least one computing device, the computer program instructions cause the cluster of computing devices to perform the methods in the above embodiments. Exemplarily, the computer-readable storage medium can be any available medium capable of being stored in the cluster of computing devices or a data storage device such as a data center containing one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives).

[0287] Based on the methods in the above embodiments, this application provides a computer program product containing instructions. The computer program product may be software or program products containing instructions, capable of running on a computing device or stored on any available medium. When the instructions are executed by a cluster of computing devices containing at least one computing device, at least one computing device in the cluster of computing devices performs the methods in the above embodiments.

[0288] It is understood that the processor in the embodiments of this application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0289] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0290] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0291] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0292] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this application.

Claims

1. A macrocell layout method, characterized in that, include: Obtain the connection relationship information of t macrocells and their alternative layouts, wherein the alternative layouts include the position information of the t macrocells, where t is an integer greater than or equal to 2; The connection relationship information and the location information are input into the index prediction model to output the predicted value of the evaluation index, wherein the evaluation index represents several indicators used to evaluate at least one of the performance, power consumption and area of ​​the circuit formed by the alternative layout. Based on the predicted values ​​of the evaluation metrics and the alternative layouts, the target layouts of the t macrocells are obtained.

2. The method according to claim 1, characterized in that, The indicator prediction model is obtained based on a preset algorithm, which represents an algorithm for fitting the connection relationship between the evaluation indicator and the connection relationship information and the location information.

3. The method according to claim 2, characterized in that, The preset algorithm is a polynomial algorithm, which includes a power polynomial and polynomial coefficients of the power polynomial. The power polynomial represents the k-th power of the distance information between the t macrocells, where k is a natural number. The step of inputting the connection relationship information and the location information into the indicator prediction model to output the predicted value of the evaluation indicator includes: The polynomial coefficients are obtained based on the connection relationship information; Based on the location information, the power polynomial is obtained, and combined with the polynomial coefficients, the predicted value of the evaluation index is obtained.

4. The method according to claim 3, characterized in that, The indicator prediction model includes a graph neural network; The step of obtaining the polynomial coefficients based on the connection relationship information includes: Based on the connection relationship information, a graph structure is obtained, which includes several nodes and several connecting edges. The nodes represent the macro units, and the connecting edges represent the connection relationships between the macro units. The graph structure is input into the graph neural network to output a node representation for each node; The polynomial coefficients are obtained based on the node representation.

5. The method according to claim 3 or 4, characterized in that, The index prediction model includes a multinomial fitting network; The step of obtaining the power polynomial based on the location information and combining it with the polynomial coefficients to obtain the predicted value of the evaluation index includes: Based on the location information, determine the distance information between the t macrocells; The polynomial coefficients and the distance information are input into the polynomial fitting network to output the predicted value of the evaluation index.

6. The method according to any one of claims 3-5, characterized in that, The polynomial algorithm is the Laurent polynomial algorithm.

7. The method according to any one of claims 1-6, characterized in that, The alternative layouts are set to multiple, and the multiple alternative layouts are obtained by adjusting the positions of the t macrocells; The step of obtaining the target layout of the t macrocells based on the predicted values ​​of the evaluation indicators and the alternative layouts includes: Based on the predicted values ​​of the evaluation metrics for each candidate layout, the target layout of the t macrocells is obtained from multiple candidate layouts.

8. The method according to claim 7, characterized in that, The target layout is selected from the plurality of candidate layouts according to a preset optimization algorithm.

9. The method according to any one of claims 1-6, characterized in that, The target layout of the t macrocells is the layout of the first t macrocells obtained in the t-th step of the greedy strategy, and the alternative layouts of the t macrocells are obtained by placing the t-th macrocell in the layout of the first t-1 macrocells.

10. The method according to any one of claims 1-6, characterized in that, The step of obtaining the target layout of the t macrocells based on the predicted values ​​of the evaluation indicators and the alternative layouts includes: Based on the predicted value of the evaluation index, the reward score of the candidate layout is determined. The candidate layout is the prediction result of the layout of the t macro units when the input of the reinforcement learning network is the connection relationship information of the t macro units. The reward score is input into the reinforcement learning network to output the target layout of the t macrocells.

11. The method according to any one of claims 1-10, characterized in that, The evaluation metrics include cross-stage metrics, which represent metrics related to multiple stages in the process of forming the circuit from the alternative layout.

12. The method according to claim 11, characterized in that, The cross-stage indicators include time-series indicators, which include at least one of worst-case negative time-series margin and total negative time-series margin.

13. The method according to any one of claims 1-12, characterized in that, The connection relationship information is obtained through the netlist data of the t macro cells. The netlist data is used to characterize the connection relationship of several cells to be laid out, and the cells to be laid out include the t macro cells.

14. The method according to any one of claims 1-13, characterized in that, The indicator prediction model is obtained by training the training dataset. The loss function of the training process of the indicator prediction model includes the indicator fitting error, which represents the error between the predicted value of the evaluation indicator output by the indicator prediction model and the true value of the evaluation indicator.

15. The method according to claim 14, characterized in that, The loss function of the training process of the indicator prediction model also includes a sorting error. The sorting error represents the error between the predicted value of the sorting of several training samples in the training dataset and the true value of the sorting. The predicted value of the sorting is obtained by sorting the several training samples according to the predicted value of the evaluation indicator output by the indicator prediction model.

16. The method according to claim 14 or 15, characterized in that, The training dataset includes several training samples, which are obtained by constructing different macrocell layouts for each netlist sample in several netlist samples.

17. The method according to any one of claims 14-16, characterized in that, The indicator prediction model is further obtained by fine-tuning the dataset, which is based on newly added indicators, which are new evaluation indicators in addition to the evaluation indicators.

18. A macrocell layout device, characterized in that, include: The acquisition module is used to acquire the connection relationship information of t macrocells and their alternative layouts, wherein the alternative layouts include the position information of the t macrocells, where t is an integer greater than or equal to 2; The processing module is configured to input the connection relationship information and the location information into the index prediction model to output the predicted value of the evaluation index, wherein the evaluation index represents several indicators used to evaluate at least one of the performance, power consumption and area of ​​the circuit formed by the alternative layout; and, based on the predicted value of the evaluation index and the alternative layout, obtain the target layout of the t macrocells.

19. A chip system, characterized in that, The chip system includes a processor and a power supply circuit, the power supply circuit being used to supply power to the processor, the processor being used to perform the method as described in any one of claims 1-17.

20. A computing device, characterized in that, The computing device includes a processor and memory; The processor is configured to execute instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1-17.

21. A computing device cluster, characterized in that, It includes at least one computing device, each computing device including a processor and memory; The processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the cluster of computing devices to perform the method as described in any one of claims 1-17.

22. A computer-readable storage medium, characterized in that, The method includes computer program instructions that, when executed by a cluster of computing devices, cause the cluster of computing devices to perform the method as described in any one of claims 1-17, wherein the cluster of computing devices includes at least one computing device.

23. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device cluster, the computing device cluster causes the computing device cluster to perform the method as described in any one of claims 1-17, wherein the computing device cluster includes at least one computing device.

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