Imaging device

Abstract

This imaging device accelerates the settling of the potential of a signal line for reading out a signal from a pixel while suppressing deterioration in image quality.　The imaging device comprises: a pixel array part in which pixels are disposed in a matrix in a row direction and a column direction; a vertical signal line which transmits, in the column direction, pixel signals read out from the pixels; a first transistor which can form a source follower with the pixels via the vertical signal line; a drive circuit which drives the first transistor on the basis of the potential of the vertical signal line; a boost capacitor which generates, on the basis of charging via the drive circuit, a boost voltage to be used for driving the first transistor; and a first switch which switches the connection of the output of the drive circuit between columns.

Description

Imaging device

[0001] This technology relates to an imaging device. Specifically, this technology relates to an imaging device in which signals are read from pixels based on a source follower operation.

[0002] In an imaging device, in order to read signals from pixels based on a source follower operation, setting of the potential of a signal line may be performed. For example, a current source circuit including a load element as a current source that is connected to a signal line and forms a source follower discloses a technique including a circuit that causes a current corresponding to the slew rate of the signal line to flow and causes a current corresponding to this current to flow through the current source (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2011-234243

[0004] However, in the above-described conventional technology, noise from pixels and power sources and noise of the current source circuit are also amplified, so there is a risk of deterioration in image quality.

[0005] This technology has been created in view of such a situation, and an object thereof is to speed up the setting of the potential of a signal line for reading signals from pixels while suppressing deterioration in image quality.

[0006] This technology has been made to solve the above-described problems, and a first aspect thereof is a pixel array unit in which pixels are arranged in a matrix in a row direction and a column direction, a vertical signal line that transmits pixel signals read from the pixels in the column direction, a first transistor that can form a source follower with the pixel via the vertical signal line, a drive circuit that drives the first transistor based on the potential of the vertical signal line, and a first switch that switches the connection between columns of the output of the drive circuit. The drive circuit is an imaging device including a boost capacitor that generates a boost voltage used for driving the first transistor. As a result, it has an effect that amplification of current flowing through the vertical signal line becomes possible while preventing amplification of noise from pixels based on the switching of the first switch.

[0007] Furthermore, in the first aspect, the first switch may be turned off during the settling period of the vertical signal line and turned on during the sampling period or AD conversion period of the pixel signal. This results in a shortened settling period while preventing amplification of noise from the pixels during the sampling period or AD conversion period based on the switching of the first switch.

[0008] Furthermore, in the first aspect, a second switch may be provided for disconnecting the boost capacity from the drive circuit. This results in the ability to amplify the current flowing through the vertical signal line while preventing the amplification of noise from the power supply based on the switching of the second switch.

[0009] Furthermore, in the first aspect, the second switch may be turned on during the settling period of the vertical signal line and turned off during the sampling period or AD conversion period of the pixel signal. This results in a shortened settling period while preventing amplification of noise from the power supply during the sampling period or AD conversion period based on the switching of the second switch.

[0010] Furthermore, in the first aspect, the boost capacity may comprise a first boost capacity and a second boost capacity, and the second switch may comprise a P-phase switch connected in series with the first boost capacity and a D-phase switch connected in series with the second boost capacity. This provides the effect of enabling amplification of the current flowing through the vertical signal line while preventing amplification of noise from the power supply and pixels for both the P-phase and D-phase.

[0011] Furthermore, in the first aspect, the P-phase switch may be turned on during the P-phase settling period of the vertical signal line and turned off during the P-phase sampling period or P-phase AD conversion period of the pixel signal, and the D-phase switch may be turned on during the D-phase settling period of the vertical signal line and turned off during the D-phase sampling period or D-phase AD conversion period of the pixel signal. This results in a shortening of the settling period for both the P-phase and D-phase, while preventing amplification of noise from the power supply and pixels during the sampling period or AD conversion period.

[0012] Furthermore, in the first aspect, the drive circuit may include a current source that generates a charging current for the boost capacity, a second transistor connected in series with the current source that generates a source follower output based on the potential of the vertical signal line, and a third transistor connected in series with the second transistor that forms a current mirror with the first transistor. This results in the boost capacity being charged based on the potential of the vertical signal line, and the current flowing through the vertical signal line being amplified.

[0013] Furthermore, in the first aspect, a level shift circuit may be provided that level shifts the potential of the vertical signal line and applies it to the gate of the second transistor. This has the effect of easing the constraint on the operating point of the second transistor caused by the potential of the vertical signal line.

[0014] Furthermore, in the first aspect, the current source may include a bias transistor and a sample-and-hold circuit that samples and holds the bias voltage applied to the bias transistor. This has the effect of reducing lateral noise caused by the bias voltage applied to the bias transistor.

[0015] Furthermore, in the first aspect, the current source may include a cascote transistor connected in series with the bias transistor. This has the effect of suppressing coupling between the bias transistor and the vertical signal line.

[0016] Furthermore, in the first aspect, the drive circuit may be shared by multiple columns. This has the effect of reducing the area occupied by the drive circuit and boost capacity.

[0017] This is a block diagram showing an example of the configuration of an imaging device according to the first embodiment. This is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. This is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the first embodiment. This is a block diagram showing an example of the configuration of an AD conversion unit according to the first embodiment. This is a block diagram showing another example of the configuration of an AD conversion unit according to the first embodiment. This is a diagram showing an example of the configuration of a drive circuit according to the first embodiment. This is a timing chart showing an example of the read operation of a solid-state imaging device according to the first embodiment. This is a timing chart showing another example of the read operation of a solid-state imaging device according to the first embodiment. This is a diagram showing an example of the configuration of a drive circuit according to the second embodiment. This is a diagram showing an example of the change in potential of a vertical signal line during signal readout according to the second embodiment. This is a diagram showing an example of the configuration of a drive circuit according to the third embodiment. This is a diagram showing an example of the configuration of a current source applied to a drive circuit according to the fourth embodiment. This is a timing chart showing an example of the operation of a current source applied to a drive circuit according to the fourth embodiment. This is a diagram showing an example of the configuration of a drive circuit according to the fifth embodiment. This is a timing chart showing an example of the operation of a drive circuit according to the fifth embodiment. This is a block diagram showing an example of the configuration of a solid-state imaging device according to the fifth embodiment. This is a diagram showing an example of pixel selection during signal readout according to the fifth embodiment. This figure shows an example of the configuration of a drive circuit according to the sixth embodiment. This perspective view shows an example of stacking of a solid-state imaging device according to the seventh embodiment. This block diagram shows a schematic example of the configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit.

[0018] The following describes embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will proceed in the following order: 1. First embodiment (an example of driving a vertical signal line via a drive circuit with a boost capacitance during vertical signal line settling) 2. Second embodiment (an example of making the capacitance value of the boost capacitance of the drive circuit that drives the vertical signal line different for the P phase and the D phase) 3. Third embodiment (an example of applying a level-shifted output of the drive circuit that drives the vertical signal line to the vertical signal line) 4. Fourth embodiment (an example of sampling and holding the bias voltage of the current source used in the drive circuit that drives the vertical signal line) 5. Fifth embodiment (an example of sharing a drive circuit that drives a vertical signal line with multiple vertical signal lines) 6. Sixth embodiment (an example of applying a level-shifted output of a drive circuit shared by multiple vertical signal lines to the vertical signal line) 7. Seventh embodiment (an example of stacking pixel arrays) 8. Application examples to mobile devices

[0019] <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0020] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0021] The optical system 101 directs light from the subject into the solid-state imaging device 102 and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0022] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. Single-slope AD conversion may be used for the digitization of the electrical signal. Each pixel may be equipped with a single photodiode, or it may be equipped with multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC (Lateral Overflow Integration Capacitor) type image sensor.

[0023] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0024] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0025] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0026] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0027] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0028] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0029] Figure 2 is a block diagram showing an example configuration of a solid-state imaging device according to the first embodiment.

[0030] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0031] The pixel array section 111 comprises a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX row by row when reading a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read from the pixel PX to the column signal processing unit 114 column by column.

[0032] Each pixel PX may be a single pixel, a shared pixel with two pixels, a shared pixel with four pixels, or a shared pixel with eight pixels. Furthermore, each pixel PX may include an image plane phase-difference pixel. Each pixel PX may support rolling shutter readout or global shutter readout. Each pixel PX may be an HDR (High Dynamic Range) pixel capable of switching conversion efficiency for output. Furthermore, each pixel PX may constitute a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0033] The vertical scanning circuit 112 scans the pixels PX to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HSL when reading a signal from each pixel PX.

[0034] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from each pixel PX. In this case, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0035] The column signal processing unit 114 processes the signals transmitted from each pixel PX in the column direction. For example, the column signal processing unit 114 can perform CDS (Correlated Double Sampling) processing based on the signals transmitted from each pixel PX in the column direction. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted from each pixel PX in the column direction and output an imaging signal Gout. The column signal processing unit 114 includes a column ADC unit 114A.

[0036] The column ADC unit 114A can perform AD conversion processing in parallel for each column. In this case, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion.

[0037] The horizontal scanning circuit 115 scans the pixels PX to be read out in the row direction. The horizontal scanning circuit 115 may also include a horizontal register.

[0038] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0039] Figure 3 is a block diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the first embodiment.

[0040] In the figure, the pixel PX comprises a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0041] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. Also, the floating diffusion FD is connected to the power supply voltage VDD via the reset transistor 123. Further, the power supply voltage VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0042] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG. 2.

[0043] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion FD. And the source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and is transmitted via the vertical signal line VSL. Also, when the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0044] FIG. 4 is a block diagram showing a configuration example of the AD conversion unit according to the first embodiment. In the figure, the vertical signal lines VSL1 and VSL2 for two columns are shown, but the same applies even if there are more vertical signal lines.

[0045] In the figure, pixels PX1 and PX2 are respectively connected to the vertical signal lines VSL1 and VSL2. At this time, the amplification transistors 124 of the pixels PX1 and PX2 are connected to the vertical signal lines VSL1 and VSL2 via the selection transistors 125, respectively.

[0046] The column readout circuit 113 includes current sources LM1, LM2, drive circuits DR1, DR2, and switches SW1, SW10. The current sources LM1, LM2 and the drive circuits DR1, DR2 are provided for each column.

[0047] Each of the current sources LM1, LM2 is connected to the vertical signal lines VSL1, VSL2 respectively. Each of the current sources LM1, LM2 can form a source follower with each pixel PX1, PX2 via the vertical signal lines VSL1, VSL2 respectively when reading signals. Each of the current sources LM1, LM2 may be a MOS transistor.

[0048] Each of the drive circuits DR1, DR2 drives each of the current sources LM1, LM2 based on the potentials of the vertical signal lines VSL1, VSL2. At this time, each of the drive circuits DR1, DR2 can charge the boost capacitance respectively based on the potentials of the vertical signal lines VSL1, VSL2, and generate a boost voltage for driving each of the current sources LM1, LM2. At this time, the outputs of the drive circuits DR1, DR2 for driving each of the current sources LM1, LM2 respectively can use the mirror output of the current flowing through each of the current sources LM1, LM2.

[0049] Each of the switches SW1, SW10 switches the connection between the outputs of the drive circuits DR1, DR2 among columns. For example, the switch SW1 can switch the connection between the output of the drive circuit DR1 connected to the vertical signal line VSL1 and the output of the drive circuit DR2 connected to the vertical signal line VSL2. At this time, each of the switches SW1, SW11 can be turned off during the setting period of the vertical signal lines VSL1, VSL2, and turned on during the sampling period or the AD conversion period of the pixel signal transmitted through the vertical signal lines VSL1, VSL2.

[0050] The column ADC section 114A includes comparators CM1, CM2 and counters CN1, CN2. The comparators CM1, CM2 and the counters CN1, CN2 are provided for each column.

[0051] Comparator CM1 compares the pixel signal transmitted via the vertical signal line VSL1 with the reference signal REF. Comparator CM2 compares the pixel signal transmitted via the vertical signal line VSL2 with the reference signal REF.

[0052] Furthermore, an auto-zero signal AZ is input to each of the comparators CM1 and CM2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, in comparator CM1, a DC-blocking capacitor CA1 is connected to the non-inverting input terminal, and a DC-blocking capacitor CB1 is connected to the inverting input terminal. Similarly, in comparator CM2, a DC-blocking capacitor CA2 is connected to the non-inverting input terminal, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.

[0053] In auto-zero operation, the charge stored in each DC-blocking capacitor CA1 and CB1 is controlled so that the non-inverting and inverting inputs of comparator CM1 are balanced. Similarly, in auto-zero operation, the charge stored in each DC-blocking capacitor CA2 and CB2 is controlled so that the non-inverting and inverting inputs of comparator CM2 are balanced.

[0054] Each counter CN1 and CN2 performs a counting operation column by column until the level of the pixel signal read from each pixel PX1 and PX2 matches the level of the ramp wave of the reference signal REF, and holds the digital values ​​D1 and D2 of the pixel signal read from each pixel PX1 and PX2 for each column. At this time, the digitization of the pixel signal read from each pixel PX1 and PX2 can be performed row by row in each comparator CM1 and CM2. The digital values ​​D1 and D2 held in each counter CN1 and CN2 can then be updated row by row.

[0055] During this time, in each comparator CM1 and CM2, the pixel signals read from each pixel PX1 and PX2 are compared column by column with the ramp wave included in the reference signal REF during the AD conversion period provided for each horizontal scanning period. Based on the comparison results in each comparator CM1 and CM2 during that AD conversion period, the digital values ​​D1 and D2 of the pixel signals read from each pixel PX1 and PX2 are stored in each counter CN1 and CN2.

[0056] Figure 5 is a block diagram showing other configuration examples of the AD conversion unit according to the first embodiment.

[0057] In this figure, the readout circuit has sample-and-hold circuits SHD1 and SHD2 added to the readout circuit in Figure 4. The other configurations of this readout circuit are the same as those in Figure 4.

[0058] The sample-and-hold circuit SHD1 samples and holds the potential of the vertical signal line VSL1 and applies it to the comparator CM1 via the DC-cut capacitor CB1. The sample-and-hold circuit SHD2 samples and holds the potential of the vertical signal line VSL2 and applies it to the comparator CM2 via the DC-cut capacitor CB2. Each sample-and-hold circuit SHD1 and SHD2 is equipped with sample-and-hold switches WH1 and WH2, sample-and-hold capacitors CH1 and CH2, and buffers BF1 and BF2, respectively. The sample-and-hold switches WH1 and WH2 may be MOS transistors. The vertical signal line VSL1 is connected to the DC-cut capacitor CB1 via the sample-and-hold switch WH1 and buffer BF1 in sequence. The vertical signal line VSL2 is connected to the DC-cut capacitor CB2 via the sample-and-hold switch WH2 and buffer BF2 in sequence. The sample-and-hold capacitor CH1 is connected between the connection point of the sample-and-hold switch WH1 and buffer BF1 and the ground potential. The sample-hold capacitor CH2 is connected between the connection point of the sample-hold switch WH2 and buffer BF2 and the ground potential.

[0059] At this time, when sample-and-hold switches WH1 and WH2 are turned on, the potentials of each vertical signal line VSL1 and VSL2 are sampled into each sample-and-hold capacitor CH1 and CH2, respectively. Then, when sample-and-hold switches WH1 and WH2 are turned off, the potentials of each vertical signal line VSL1 and VSL2 are applied from each sample-and-hold capacitor CH1 and CH2 to each comparator CM1 and CM2, respectively. This allows for pipelined settling of each vertical signal line VSL1 and VSL2 and AD conversion of the pixel signal, thereby accelerating the digitization of the pixel signal.

[0060] Figure 6 shows an example of the configuration of a drive circuit according to the first embodiment. In this figure, an example of the configuration of drive circuit DR1 is shown, but drive circuit DR2 can be configured in the same way.

[0061] In the figure, a load transistor 131 can be used as the current source LM1. The load transistor 131 is connected in series with the vertical signal line VSL1. At this time, by applying a bias voltage Vb to the gate of the load transistor 131, the load transistor 131 can be operated as the current source LM1. An NMOS transistor can be used as the load transistor 131.

[0062] The drive circuit DR1 includes a current source GA, a boost capacitor CB, a switch SW2, a source follower transistor 132, and a mirror transistor 133.

[0063] The current source GA generates the charging current for the boost capacitor CB. The current source GA may also be a MOS transistor.

[0064] The boost capacitor CB generates a boost voltage used to drive the load transistor 131. The boost capacitor CB is connected to the output of the current source GA via switch SW2. At this time, the boost capacitor CB can be charged based on the source potential Va of the source follower transistor 132.

[0065] Switch SW2 switches the connection between the boost capacitor CB and the current source GA. Switch SW2 can be turned on during the settling period of the vertical signal line VSL1 and turned off during the sampling period or AD conversion period of the pixel signal transmitted via the vertical signal line VSL1.

[0066] The source follower transistor 132 and the current source GA constitute a source follower circuit. The source follower transistor 132 generates a source follower output based on the potential of the vertical signal line VSL1. The source follower transistor 132 is connected in series with the current source GA. In this configuration, the source follower transistor 132 generates a source potential Va that tracks the potential of the vertical signal line VSL1 and can be applied to the boost capacitor CB via the switch SW2. A PMOS transistor can be used for the source follower transistor 132.

[0067] The mirror transistor 133 forms a current mirror with the load transistor 131 and amplifies the current flowing through the load transistor 131. At this time, the mirror ratio between the mirror transistor 133 and the load transistor 131 can be set to 1:N (where N is a real number greater than 1). The mirror transistor 133 is connected in series with the source follower transistor 132. One end of the switch SW1 is connected to the connection point between the source follower transistor 132 and the mirror transistor 133. An NMOS transistor can be used for the mirror transistor 133.

[0068] Figure 7 is a timing chart showing an example of the readout operation of a solid-state imaging device according to the first embodiment. In the figure, a shows an example of noise superimposed on the vertical signal line VSL1. In the figure, b shows the on / off timing of switches SW1 and SW2.

[0069] In the figure, the pixel signal readout operation includes a settling period TS and an AD conversion period TA. At this time, the AD conversion period TA begins after the end of the settling period TS. During the settling period TS, switch SW1 is turned off and switch SW2 is turned on, and then switch SW1 is turned on and switch SW2 is turned off. When switch SW2 is turned on, the mirror transistor 133, whose gate and drain are shorted, generates a gate voltage Vb corresponding to the amount of current charged and discharged from the boost capacitance CB. As a result, the current flowing to the load transistor 131 can be amplified based on the current mirror operation of the mirror transistor 133, and the settling of the potential of the vertical signal line VSL can be accelerated.

[0070] Next, during the AD conversion period TA, switch SW1 is turned on and switch SW2 is turned off, and the signal is sampled at sampling time TSP. By turning off switch SW2, the charging and discharging operation of the boost capacitor CB can be stopped. This prevents noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131. Also, by turning on switch SW1, the output of the drive circuit DR1 can be averaged, and the noise output from the drive circuit DR1 can be reduced. At this time, the settling time STL is set between the time switch SW2 is turned on and the sampling time TPT.

[0071] For example, during the settling period TS, noise NZ is superimposed on the vertical signal line VSL1. This noise NZ includes noise from the pixel PX1 and power supply noise. By turning switch SW1 off and switch SW2 on during the settling period TS, the settling of the potential VL1 of the vertical signal line VSL1 can be accelerated. By turning switch SW1 on and switch SW2 off before the end of the settling period TS, noise from the pixel PX1 and power supply noise can be converged before the AD conversion period TA. Furthermore, by turning switch SW1 on and switch SW2 off during the AD conversion period TA, it is possible to prevent the noise NZ from being amplified and superimposed on the potential VL1 of the vertical signal line VSL1. In addition, even when switching each of the switches SW1 and SW2, the continuity of the current flowing through the load transistor 131 can be maintained, and the switching of each of the switches SW1 and SW2 can be performed smoothly.

[0072] Figure 8 shows another example of the waveforms of each part during pixel signal readout according to the first embodiment. In this figure, an example of the waveform including P-phase readout and D-phase readout within a 1H period (1 horizontal synchronization period) is shown.

[0073] In the figure, the P-phase readout period PRD and the D-phase readout period DRD are set during the 1H period. The P-phase readout period PRD includes the P-phase settling period TSP and the P-phase AD conversion period TAD. The D-phase readout period DRD includes the D-phase settling period TSD and the D-phase AD conversion period TAD.

[0074] Here, the reset signal RST rises before the P-phase readout period PRD (t1), the reset transistor 123 turns on, and the floating diffusion FD is reset. Also, the selection signal SEL rises, and the selection transistor 125 turns on.

[0075] Next, the reset signal RST falls (t2), and the reset transistor 123 turns off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0076] Here, during the P-phase settling period TSP, switch SW1 is off and switch SW2 is on. By turning on switch SW2 at this time, the boost voltage of the boost capacitor CB can be applied to the gate of the mirror transistor 133 via the source follower transistor 132. As a result, the current flowing to the load transistor 131 can be amplified based on the current mirror operation of the mirror transistor 133, and the settling of the potential of the vertical signal line VSL can be accelerated.

[0077] Next, during the P-phase AD conversion period TAD, switch SW1 is turned ON and switch SW2 is turned OFF. By turning off switch SW2, the boost voltage of the boost capacitor CB is not applied to the gate of the mirror transistor 133. This prevents noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131. Also, by turning on switch SW1, the output of the drive circuit DR1 can be averaged, and the noise output from the drive circuit DR1 can be reduced. At this time, even when switching each of switches SW1 and SW2, the continuity of the current flowing to the load transistor 131 can be maintained, and the switching of each of switches SW1 and SW2 can be performed smoothly. In addition, a ramp wave is applied to the comparator CM1 as the reference signal REF.

[0078] Then, the potential of the vertical signal line VSL corresponding to the P-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output as the comparison result. At this time, based on the count operation until the level of the reference signal REF matches the potential of the vertical signal line VSL, the P-phase level read from the pixel PX is AD converted column by column.

[0079] Next, the transfer signal TGL rises before the D-phase readout period DRD (t3), the transfer transistor 122 turns on, and the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.

[0080] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 turns off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0081] During the D-phase settling period TSD, switch SW1 is off and switch SW2 is on. By turning on switch SW2, the boost voltage of the boost capacitor CB can be applied to the gate of the mirror transistor 133 via the source follower transistor 132. As a result, the current flowing through the load transistor 131 can be amplified based on the current mirror operation of the mirror transistor 133, and the settling of the potential of the vertical signal line VSL can be accelerated.

[0082] Next, during the D-phase AD conversion period TAD, switch SW1 is turned ON and switch SW2 is turned OFF. By turning off switch SW2, the boost voltage of the boost capacitor CB is not applied to the gate of the mirror transistor 133. This prevents noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131. Also, by turning on switch SW1, the output of the drive circuit DR1 can be averaged, and the noise output from the drive circuit DR1 can be reduced. In addition, a ramp wave is applied to the comparator CM1 as the reference signal REF.

[0083] Then, the potential of the vertical signal line VSL corresponding to the D-phase level is compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output as the comparison result. At this time, the D-phase level read from the pixel PX is AD converted column by column based on the count operation until the level of the reference signal REF matches the potential of the vertical signal line VSL.

[0084] As described above, in the first embodiment, a switch SW1 is provided to switch the connection between columns of the output of the drive circuit DR1, and a switch SW2 is provided to switch the connection between the boost capacitor CB and the current source GA. This makes it possible to prevent noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131, while speeding up the settling of the potential of the vertical signal line VSL, and also makes it possible to average the output of the drive circuit DR1 and reduce the noise output from the drive circuit DR1.

[0085] <2. Second Embodiment> In the first embodiment described above, the vertical signal line VSL1 was driven via a drive circuit DR1 equipped with a boost capacitance CB during settling of the vertical signal line VSL1. In this second embodiment, the capacitance value of the boost capacitance of the drive circuit that drives the vertical signal line VSL1 is made different for the P phase and the D phase.

[0086] Figure 9 is a block diagram showing an example configuration of a solid-state imaging device according to the second embodiment.

[0087] In the figure, the drive circuit DR2 is equipped with boost capacities CBP and CBD instead of boost capacities CB in the first embodiment described above. The other configurations of this drive circuit DR2 are the same as those of the drive circuit DR1 in the first embodiment described above.

[0088] The boost capacitor CBP generates a boost voltage used to drive the load transistor 131 during P-phase settling. The boost capacitor CBD generates a boost voltage used to drive the load transistor 131 during D-phase settling. The boost capacitor CBP is connected to the output of the current source GA via switch SWP2. The boost capacitor CBD is connected to the output of the current source GA via switch SWD2. Switch SWP2 can be turned on and off at the same timing as switch SW2 during the P-phase readout period PRD in Figure 8. Switch SWD2 can be turned on and off at the same timing as switch SW2 during the D-phase readout period DRD in Figure 8. It is desirable that the capacitance value of the boost capacitor CBD be larger than the capacitance value of the boost capacitor CBP.

[0089] Figure 10 shows an example of the change in potential of the vertical signal line during signal readout according to the second embodiment.

[0090] In point a of the figure, during P-phase readout, the potential of the vertical signal line VSL1 transitions from a high potential to a low potential. At this time, based on the boost operation of the potential of the vertical signal line VSL1 by the drive circuit DR2, the current flowing to the load transistor 131 is temporarily reduced.

[0091] Here, if the boost capacitance CBP is too small, the falling edge of the potential VP2 of the vertical signal line VSL1 becomes slow, leading to an increase in the settling time. On the other hand, if the boost capacitance CBP is too large, an undershoot occurs in the falling edge of the potential VP3 of the vertical signal line VSL1, also leading to an increase in the settling time. Therefore, by optimizing the capacitance value of the boost capacitance CBP according to the responsiveness of the potential of the vertical signal line VSL1 during P-phase readout, the time required for the falling edge of the potential VP2 of the vertical signal line VSL1 can be reduced.

[0092] In the figure, at point b, during D-phase readout, the potential of the vertical signal line VSL1 transitions from a low potential to a high potential. At this time, based on the boost operation of the vertical signal line VSL1 by the drive circuit DR2, the current flowing through the load transistor 131 is temporarily increased.

[0093] Here, if the capacitance value of the boost capacitance CBD is too small, the rise of the potential VD2 of the vertical signal line VSL1 becomes slow, leading to an increase in the settling time. On the other hand, if the capacitance value of the boost capacitance CBD is too large, an overshoot occurs in the rise of the potential VD3 of the vertical signal line VSL1, also leading to an increase in the settling time. Therefore, by optimizing the capacitance value of the boost capacitance CBD according to the responsiveness of the potential of the vertical signal line VSL1 during D-phase readout, the time required for the rise of the potential VD2 of the vertical signal line VSL1 can be reduced.

[0094] Thus, in the second embodiment described above, the capacitance values ​​of the boost capacitors CBP and CBD in the drive circuit DR2 that drives the vertical signal line VSL1 are made different for the P-phase and D-phase. This makes it possible to match the capacitance values ​​of the boost capacitors CBP and CBD to the response of the potential of the vertical signal line VSL1 during P-phase settling and the response of the potential of the vertical signal line VSL1 during D-phase settling. As a result, it is possible to accelerate the P-phase settling and D-phase settling of the potential of the vertical signal line VSL, respectively, while preventing noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131.

[0095] In the second embodiment described above, an example was given in which the boost capacitance CBP is used for P-phase reading and the boost capacitance CBD is used for D-phase reading, but the boost capacitances CBP and CBD may also be used for D-phase reading. <3. Third Embodiment> In the first embodiment described above, the vertical signal line VSL1 was driven via a drive circuit DR1 equipped with a boost capacitance CB when the vertical signal line VSL1 was settling. In this third embodiment, the output of the drive circuit DR1 that drives the vertical signal line VSL1 is level-shifted and applied to the vertical signal line VSL1.

[0096] Figure 11 shows an example of the configuration of a drive circuit according to the third embodiment.

[0097] In the figure, this readout circuit has a level shift circuit LS added to the readout circuit of the first embodiment described above. The other configurations of this readout circuit are the same as those of the readout circuit of the first embodiment described above.

[0098] The level shift circuit LS shifts the potential of the vertical signal line VSL1 and applies it to the gate of the source follower transistor 132. The level shift circuit LS includes an NMOS transistor 301 and a current source 302.

[0099] The NMOS transistor 301 and the current source 302 are connected in series with each other. The gate of the NMOS transistor 301 is connected to the vertical signal line VSL1. The connection point between the NMOS transistor 301 and the current source 302 is connected to the gate of the source follower transistor 132. At this time, the potential of the vertical signal line VSL1 is level-shifted via the NMOS transistor 301 and applied to the gate of the source follower transistor 132.

[0100] Thus, in the third embodiment described above, the output of the drive circuit DR1 that drives the vertical signal line VSL1 is level-shifted and applied to the vertical signal line VSL1. This prevents noise from the pixel PX1 and power supply noise from being amplified and applied to the load transistor 131, while also accelerating the settling of the potential of the vertical signal line VSL, and easing the constraints on the operating point of the source follower transistor 132 caused by the potential of the vertical signal line VSL1. <4. Fourth Embodiment> In the first embodiment described above, the vertical signal line VSL1 was driven via a drive circuit DR1 equipped with a boost capacitance CB during the settling of the vertical signal line VSL1. In this fourth embodiment, the bias voltage of the current source used in the drive circuit that drives the vertical signal line VSL1 is sampled and held.

[0101] Figure 12 shows an example of the configuration of a current source applied to a drive circuit according to the fourth embodiment.

[0102] In the figure, this drive circuit includes a current source GA2 instead of the current source GA of the first embodiment described above. The other configurations of this drive circuit are the same as those of the drive circuit DR1 of the first embodiment described above.

[0103] The current source GA2 includes a bias transistor T1, a cascode transistor T2, sample-and-hold capacitors C1 and C2, and sample-and-hold switches SW11 and SW12. The bias transistor T1 and the cascode transistor T2 may be PMOS transistors.

[0104] The bias transistor T1 and the cascode transistor T2 are connected in series with each other. A sample-and-hold switch SW11 is connected in series with the gate of the bias transistor T1. A sample-and-hold capacitor C1 is connected at the connection point between the gate of the bias transistor T1 and the sample-and-hold switch SW11. A sample-and-hold switch SW12 is connected in series with the gate of the cascode transistor T2. A sample-and-hold capacitor C2 is connected at the connection point between the gate of the cascode transistor T2 and the sample-and-hold switch SW12.

[0105] A bias voltage V1 is applied to the gate of bias transistor T1 via sample-and-hold switch SW11. A bias voltage V2 is applied to the gate of cascode transistor T2 via sample-and-hold switch SW12. Each bias voltage V1 and V2 can be shared by all columns. Sample-and-hold switch SW11 is turned on and off based on the sample-and-hold signal SH1. Sample-and-hold switch SW12 is turned on and off based on the sample-and-hold signal SH2.

[0106] Figure 13 is a timing chart showing an example of the operation of a current source applied to a drive circuit according to the fourth embodiment.

[0107] In the same figure, during P-phase readout and D-phase readout, switches SW1 and SW2 are turned on and off according to the same timing as in Figure 8. At this time, at the start of the P-phase settling period TSP during P-phase readout, sample-and-hold switches SW11 and SW12 are turned on based on sample-and-hold signals SH1 and SH2, and the respective bias voltages V1 and V2 are sampled and held in the respective sample-and-hold capacitors C1 and C2. Then, once the respective bias voltages V1 and V2 have been sampled and held in the respective sample-and-hold capacitors C1 and C2, the sample-and-hold switches SW11 and SW12 are turned off based on sample-and-hold signals SH1 and SH2. Then, the respective bias voltages V1 and V2 that have been sampled and held in the respective sample-and-hold capacitors C1 and C2 are applied to the gates of the bias transistor T1 and the cascode transistor T2, respectively.

[0108] Here, the potential of the bias transistor T1 fluctuates in accordance with the potential of the vertical signal line VSL1. At this time, by connecting a cascode transistor T2 in series between the bias transistor T1 and the source follower transistor 132, fluctuations in the current output from the current source GA2 can be suppressed in response to fluctuations in the potential of the vertical signal line VSL1.

[0109] Furthermore, when the source potential Va of the source follower transistor 132 of the column where the potential of the vertical signal line VSL1 transitions also transitions, the bias voltage V2 fluctuates via the gate-drain capacitance of the cascode transistor T2. At this time, by applying the bias voltage V2 to the gate of the cascode transistor T2 after sample-holding, it is possible to suppress the effect of the potential transition of the vertical signal line VSL1 on the characteristics of other columns.

[0110] Furthermore, since the noise generated during sampling of each bias voltage V1 and V2 (such as kTC noise and charge injection) is common to both the P-phase and D-phase, it can be removed based on CDS processing.

[0111] Thus, in the fourth embodiment described above, the bias voltage V1 of the current source GA2 used in the drive circuit that drives the vertical signal line VSL1 is sampled and held. This makes it possible to reduce lateral noise caused by the bias of the current source GA2. <5. Fifth Embodiment> In the first embodiment described above, the vertical signal line VSL1 was driven via a drive circuit DR1 equipped with a boost capacitance CB when the vertical signal line VSL1 was settling. In this fifth embodiment, the drive circuit DR1 that drives the vertical signal line is shared by multiple vertical signal lines.

[0112] Figure 14 shows an example of the configuration of a drive circuit according to the fifth embodiment. In this figure, an example is shown in which the drive circuit DR1 is shared by four vertical signal lines VSL1 to VSL4, but the drive circuit DR1 may be shared by M (M is an integer of 2 or more) vertical signal lines.

[0113] In the figure, this readout circuit has a gate voltage generation circuit 501 added to the readout circuit of the first embodiment described above. The other configurations of this readout circuit are the same as those of the readout circuit of the first embodiment described above.

[0114] The gate voltage generation circuit 501 generates the gate voltage Vc of the source follower transistor 132 based on the potentials of each vertical signal line VSL1 to VSL4 and applies it to the gate of the source follower transistor 132. At this time, the gate voltage generation circuit 501 can generate the gate voltage Vc of the source follower transistor 132 based on the average value of the potentials of each vertical signal line VSL1 to VSL4. The gate voltage generation circuit 501 includes capacitors C21 to C24 and switches SW21 to SW24 and SW32 to SW34.

[0115] Capacitor C21 and switch SW21 are connected in parallel to each other. The parallel circuit of capacitor C21 and switch SW21 is connected between the vertical signal line VSL1 and the gate of source follower transistor 132.

[0116] Capacitor C22 and switch SW22 are connected in parallel to each other. The parallel circuit of capacitor C22 and switch SW22 is connected in series with switch SW32. The parallel circuit of capacitor C22 and switch SW22 is connected between the vertical signal line VSL2 and the gate of source follower transistor 132 via switch SW32.

[0117] Capacitor C23 and switch SW23 are connected in parallel to each other. The parallel circuit of capacitor C23 and switch SW23 is connected in series with switch SW33. The parallel circuit of capacitor C23 and switch SW23 is connected between the vertical signal line VSL3 and the gate of source follower transistor 132 via switch SW33.

[0118] Capacitor C24 and switch SW24 are connected in parallel to each other. The parallel circuit of capacitor C24 and switch SW24 is connected in series with switch SW34. The parallel circuit of capacitor C24 and switch SW24 is connected between the vertical signal line VSL4 and the gate of source follower transistor 132 via switch SW34.

[0119] Figure 15 is a timing chart showing an example of the operation of the drive circuit according to the fifth embodiment.

[0120] In the figure, it is assumed that adjacent pixels of the same color are read from adjacent columns. In a normal imaging scene, adjacent pixels of the same color will have roughly the same signal amplitude. Switches SW1 and SW2 are turned on and off according to the same timing as in Figure 7. At the beginning of P-phase readout (and D-phase readout), switches SW21 to SW24 are turned on for a short period of time to initialize the gate voltage Vc of the source follower transistor 132 to the potential of the vertical signal line VSL1. The amount of change in the gate voltage Vc of the source follower transistor 132 after initialization is the average value of the amount of change in the potential of the vertical signal lines VSL1 to VSL4. At this time, the common bias voltage Vb across the vertical signal lines VSL1 to VSL4 is dynamically adjusted in accordance with the change in the gate voltage Vc of the source follower transistor 132. Here, the gate voltage Vc is reset when the potential of vertical signal line VSL1 is high and the potential of vertical signal lines VSL2 to VSL4 is low. Even if the potential of vertical signal lines VSL2 to VSL4 increases, the gate voltage Vc can be set to the average value of the potentials of vertical signal lines VSL1 to VSL4. This prevents difficulties in securing the operating point of the source follower transistor 132 and prevents exceeding the breakdown voltage of the source follower transistor 132.

[0121] Figure 16 is a block diagram showing an example configuration of a solid-state imaging device according to the fifth embodiment.

[0122] In the figure, the solid-state imaging device 602 includes a pixel array unit 611 and a column signal processing unit 614 instead of the pixel array unit 111 and column signal processing unit 114 of the first embodiment described above. The other configurations of the solid-state imaging device 602 are the same as those of the solid-state imaging device 102 of the first embodiment described above.

[0123] The pixel array section 611 includes vertical signal lines VSLA and VSLB instead of the vertical signal line VSL of the first embodiment described above. In this case, each pixel PX is connected to the vertical signal lines VSLA and VSLB for each column. The other configurations of this pixel array section 611 are the same as those of the pixel array section 111 of the first embodiment described above.

[0124] The column signal processing unit 614 includes a column ADC unit 614A. The column ADC unit 614A can perform AD conversion processing in parallel for each same-colored, adjacent pixel. At this time, pixel signals read from same-colored, adjacent pixels of different rows can be input to the column ADC unit 614A in parallel via vertical signal lines VSLA and VSLB.

[0125] Figure 17 shows an example of pixel selection during signal readout according to the fifth embodiment. In this figure, an example is shown in which pixels PX are arranged in a vertical × horizontal = 4 × 4 grid.

[0126] In the figure, the pixels PX may be arranged in a Bayer array. The Bayer array includes red pixels R, blue pixels B, and green pixels Gb and Gr. In addition, four AD converters AD are arranged above and below the pixel array section 611.

[0127] Here, in point a in the figure, during the first AD conversion period, the pixel signals read from the four red pixels R are distributed to the four upper AD converters AD. The pixel signals read from the four green pixels Gr are distributed to the four lower AD converters AD.

[0128] Furthermore, in point b of the same figure, during the second AD conversion period, the pixel signals read from the four blue pixels B are distributed to the four upper AD converters AD. The pixel signals read from the four green pixels Gb are distributed to the four lower AD converters AD.

[0129] Thus, in the fifth embodiment described above, the drive circuit DR1 that drives the vertical signal line is shared by multiple vertical signal lines. This eliminates the need to provide a drive circuit DR1 for each vertical signal line from VLS1 to VLS4, and makes it possible to reduce the occupied area and power consumption of the drive circuit DR1. <6. Sixth Embodiment> In the first embodiment described above, the vertical signal line VSL1 was driven via a drive circuit DR1 equipped with a boost capacity CB when the vertical signal line VSL1 was settling. In this sixth embodiment, the output of the drive circuit DR1, which is shared by multiple vertical signal lines, is level-shifted and applied to the vertical signal line.

[0130] Figure 18 shows an example of the configuration of a drive circuit according to the sixth embodiment.

[0131] In the figure, this readout circuit has a level shift circuit LS added to the readout circuit of the fifth embodiment described above. In this case, the level shift circuit LS can level shift the average value of the potentials of each vertical signal line VSL1 to VSL4 and apply it to the gate of the source follower transistor 132. The other configurations of this readout circuit are the same as those of the readout circuit of the fifth embodiment described above.

[0132] Thus, in the sixth embodiment described above, the output of the drive circuit DR1, which is shared by multiple vertical signal lines, is level-shifted and applied to the vertical signal lines. This makes it possible to share the drive circuit DR1 across multiple vertical signal lines VLS1 to VLS4 while easing the constraints on the operating point of the source follower transistor 132 caused by the potential difference between each vertical signal line VLS1 to VLS4.

[0133] <7. Seventh Embodiment> In the first embodiment described above, the pixel conversion efficiency was switched based on the determination result of the readout level of the pixel signal. In this seventh embodiment, semiconductor chips, each provided with a pixel array section in which pixels are arranged in a matrix, are stacked.

[0134] Figure 19 is a perspective view showing an example of stacking of pixel arrays according to the seventh embodiment.

[0135] In the figure, the solid-state imaging device comprises semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921.

[0136] A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922, enabling electrical connection between the semiconductor chips 921 and 922.

[0137] Peripheral circuits 924 are formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. The column readout circuit 925 may have any of the configurations of the first to sixth embodiments described above.

[0138] The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0139] Thus, in the seventh embodiment described above, the semiconductor chip 922 on which the pixel array 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0140] <7. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0141] Figure 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0142] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0143] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0144] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0145] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0146] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0147] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0148] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0149] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0150] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0151] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 20, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0152] Figure 21 shows an example of the installation position of the imaging unit 12031.

[0153] In Figure 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0154] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0155] Figure 21 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0156] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0157] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0158] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0159] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0160] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each imaging device of the above embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, the frame rate can be improved without degrading the image quality of the imaging unit 12031.

[0161] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0162] Furthermore, this technology can also take the following configurations: (1) An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; a vertical signal line for transmitting pixel signals read from the pixels in the column direction; a first transistor capable of forming a source follower with the pixels via the vertical signal line; a drive circuit for driving the first transistor based on the potential of the vertical signal line; and a first switch for switching the connection of the output of the drive circuit between columns, wherein the drive circuit includes a boost capacitor that generates a boost voltage used to drive the first transistor. (2) The imaging device according to (1), wherein the first switch is turned off during the settling period of the vertical signal line and turned on during the sampling period or AD conversion period of the pixel signal. (3) The imaging device according to (1) or (2), further comprising a second switch for disconnecting the boost capacitor from the drive circuit. (4) The imaging device according to (3), wherein the second switch is turned on during the settling period of the vertical signal line and turned off during the sampling period or AD conversion period of the pixel signal. (5) The imaging apparatus according to any one of (1) to (4), wherein the boost capacity comprises a first boost capacity and a second boost capacity, and the second switch comprises a P-phase switch connected in series with the first boost capacity and a D-phase switch connected in series with the second boost capacity. (6) The imaging apparatus according to (5), wherein the P-phase switch is turned on during the P-phase settling period of the vertical signal line and turned off during the P-phase sampling period or P-phase AD conversion period of the pixel signal, and the D-phase switch is turned on during the D-phase settling period of the vertical signal line and turned off during the D-phase sampling period or D-phase AD conversion period of the pixel signal. (7) The imaging apparatus according to any one of (1) to (6), wherein the drive circuit comprises a current source that generates a charging current for the boost capacity, a second transistor connected in series with the current source that generates a source follower output based on the potential of the vertical signal line, and a third transistor connected in series with the second transistor that constitutes a current mirror with the first transistor.(8) The imaging apparatus according to (7), further comprising a level shift circuit that level shifts the potential of the vertical signal line and applies it to the gate of the second transistor. (9) The imaging apparatus according to (7) or (8), wherein the current source comprises a bias transistor and a sample-and-hold circuit that sample-and-holds the bias voltage applied to the bias transistor. (10) The imaging apparatus according to (9), wherein the current source comprises a cascote transistor connected in series with the bias transistor. (11) The imaging apparatus according to any one of (1) to (10), wherein the drive circuit is shared by a plurality of columns.

[0163] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Storage unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column reading circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HSL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplifier transistor 125 Selection transistor DR1 Drive circuit GA Current source CB Boost capacitance SW1, SW2 Switches 131 Load transistor 132 Source follower transistor 133 Mirror transistor

Claims

1. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row direction and column direction; a vertical signal line for transmitting pixel signals read from the pixels in the column direction; a first transistor capable of forming a source follower with the pixels via the vertical signal line; a drive circuit for driving the first transistor based on the potential of the vertical signal line; and a first switch for switching the connection of the output of the drive circuit between columns, wherein the drive circuit includes a boost capacitor for generating a boost voltage used to drive the first transistor.

2. The imaging apparatus according to claim 1, wherein the first switch is turned off during the settling period of the vertical signal line and turned on during the sampling period or AD conversion period of the pixel signal.

3. The imaging apparatus according to claim 1, further comprising a second switch for disconnecting the boost capacity from the drive circuit.

4. The imaging apparatus according to claim 3, wherein the second switch is turned on during the settling period of the vertical signal line and turned off during the sampling period or AD conversion period of the pixel signal.

5. The imaging apparatus according to claim 1, wherein the boost capacity comprises a first boost capacity and a second boost capacity, and the second switch comprises a P-phase switch connected in series with the first boost capacity and a D-phase switch connected in series with the second boost capacity.

6. The imaging apparatus according to claim 5, wherein the P-phase switch is turned on during the P-phase settling period of the vertical signal line and turned off during the P-phase sampling period or P-phase AD conversion period of the pixel signal, and the D-phase switch is turned on during the D-phase settling period of the vertical signal line and turned off during the D-phase sampling period or D-phase AD conversion period of the pixel signal.

7. The imaging apparatus according to claim 1, wherein the drive circuit comprises a current source that generates a charging current of the boost capacity; a second transistor connected in series with the current source that generates a source follower output based on the potential of the vertical signal line; and a third transistor connected in series with the second transistor that constitutes a current mirror with the first transistor.

8. The imaging apparatus according to claim 7, further comprising a level shift circuit for level shifting the potential of the vertical signal line and applying it to the gate of the second transistor.

9. The imaging apparatus according to claim 7, wherein the current source comprises a bias transistor and a sample-and-hold circuit for sampling and holding the bias voltage applied to the bias transistor.

10. The imaging apparatus according to claim 9, wherein the current source comprises a cascoat transistor connected in series with the bias transistor.

11. The imaging apparatus according to claim 1, wherein the drive circuit is shared by a plurality of columns.

Images