Display device

Abstract

This display device includes: a substrate having a long shape and including a plurality of display regions provided in a longitudinal direction; a plurality of display elements provided in the plurality of display regions of the substrate; a plurality of pixel ICs provided in the plurality of display regions of the substrate and connected to the plurality of display elements to drive the plurality of display elements; a power supply line for supplying power to the plurality of pixel ICs; and a reference potential line for supplying a reference potential to the plurality of pixel ICs. The plurality of pixel ICs are connected in series in the longitudinal direction of the substrate. In the plurality of pixel ICs adjacent to each other, a clock signal output terminal and a clock signal input terminal are connected, and an image data output terminal and an image data input terminal are connected. The power supply line and the reference potential line connecting the plurality of pixel ICs adjacent to each other are wavy.

Description

Display device

[0001] The present invention relates to a display device.

[0002] Patent Documents 1 and 2 disclose a technique in which a pixel IC (represented as a pixel controller or a controller in Patent Documents 1 and 2) is connected to each of one or more pixels.

[0003] U.S. Patent No. 10832609, Japanese Patent Application Laid-Open No. 2014-63845

[0004] When a display device is used for interior, signage, etc., display devices having various shapes and sizes are required. For this reason, it is necessary to increase the degree of freedom in the shape of the display device.

[0005] An object of the present disclosure is to provide a display device capable of improving the degree of freedom in shape.

[0006] A display device according to an aspect of the present disclosure includes a substrate that is elongated and provided with a plurality of display regions along a longitudinal direction, a plurality of display elements provided in the plurality of display regions of the substrate, and a plurality of display elements provided in the plurality of display regions of the substrate. A plurality of pixel ICs connected to the plurality of display elements and driving the plurality of display elements, a power supply line for supplying power to the plurality of pixel ICs, and a reference potential line for supplying a reference potential to the plurality of pixel ICs. The plurality of pixel ICs are connected in series along the longitudinal direction of the substrate, and each of the plurality of pixel ICs has a clock signal input terminal to which a clock signal is input, an image data input terminal to which image data is input, a clock signal output terminal that outputs the clock signal, an image data output terminal that outputs the image data, and a connection terminal connected to at least one of the display elements. In the plurality of adjacent pixel ICs, the clock signal output terminal and the clock signal input terminal are connected, the image data output terminal and the image data input terminal are connected, and the power supply line and the reference potential line connecting between the plurality of adjacent pixel ICs are wavy.

[0007] Figure 1 is a schematic plan view showing a display device according to an embodiment. Figure 2 is a schematic block diagram showing an example configuration of the display device according to an embodiment. Figure 3 is a schematic plan view showing an example configuration of a substrate. Figure 4 is a circuit diagram showing a driver IC, a plurality of pixel ICs, and a plurality of light-emitting elements. Figure 5 is a block diagram showing an example configuration of a pixel IC. Figure 6 is a timing chart showing a clock signal and image data in a pixel IC. Figure 7 is a schematic plan view showing an example configuration of one substrate of the display device according to the first modified example. Figure 8 is a cross-sectional view taken along VIII-VIII' in Figure 7. Figure 9 is a plan view showing an enlarged view of the two display areas in Figure 7. Figure 10 is a schematic plan view showing one display area of ​​the display device according to the second modified example. Figure 11 is an explanatory diagram for explaining the connection configuration between a pixel IC and a plurality of pixels in the display device according to the second modified example. Figure 12 is a schematic perspective view showing an example configuration of a display device according to the third modified example. Figure 13 is a schematic plan view showing an example configuration of a plurality of substrates of the display device according to the fourth modified example. Figure 14 is a schematic perspective view showing an example of the configuration of a display device according to the fifth modified example. Figure 15 is a schematic plan view showing an example of the configuration of one substrate of the display device according to the fifth modified example.

[0008] The embodiments for implementing this disclosure will be described in detail with reference to the drawings. This disclosure is not limited to the embodiments described below. Furthermore, the components described below include those that can be easily conceived by a person skilled in the art, and those that are substantially the same. In addition, the components described below can be combined as appropriate. The disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive while maintaining the spirit of this disclosure are naturally included within the scope of this disclosure. Furthermore, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of this disclosure. Furthermore, in this disclosure and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In this disclosure, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0010] (Embodiment) Figure 1 is a schematic plan view showing a display device according to an embodiment. In Figure 1, the display areas 23 of the substrate 21 are schematically shown with hatching to facilitate understanding.

[0011] As shown in Figure 1, the display device 1 of this embodiment has a plurality of elongated substrates 21. Each of the plurality of substrates 21 is a flexible substrate. Each substrate 21 has a plurality of display areas 23 provided along its longitudinal direction. The display surface of the display device 1 is composed of a plurality of display areas 23 arranged in a matrix.

[0012] More specifically, each of the multiple substrates 21 extends in the second direction Dy and is arranged in the first direction Dx. The display areas 23 are arranged in a matrix on the multiple substrates 21. That is, on one substrate 21, the multiple display areas 23 are arranged along the second direction Dy. Also, on two substrates 21 adjacent to each other in the first direction Dx, the display areas 23 of one substrate 21 and the display areas 23 of the other substrate 21 are arranged adjacent to each other in the first direction Dx.

[0013] In the following description, the first direction Dx is one direction in a plane parallel to the surface of the display surface (multiple display areas 23) of the display device 1. The second direction Dy is one direction in a plane parallel to the display surface of the display device 1 and is perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is perpendicular to both the first direction Dx and the second direction Dy. The third direction Dz is the normal direction to the display surface of the display device 1. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the display surface of the display device 1.

[0014] Figure 1 shows an example where the display areas 23 of multiple substrates 21 are arranged in a 6x4 configuration for clarity. However, it is not limited to this, and the display surface of the display device 1 may be 5x3 or less, or 7x5 or more. The display device 1 may have different numbers of substrates 21. For example, the display device 1 may be configured with at least one substrate 21. Alternatively, the longitudinal lengths of the multiple substrates 21 may be different. In addition, although the display surface as a whole is formed by multiple substrates 21 (display areas 23), it is possible to form a display surface with an irregular shape, such as having an arc-shaped curved portion on part of the outer periphery.

[0015] Furthermore, the configuration of the multiple substrates 21 is not limited to being arranged in a planar shape, but can also be applied to a display surface having a curved surface. In this case, the display area 23 of the multiple substrates 21 is arranged along the curved surface of the display surface. When the multiple substrates 21 are arranged to have a curved surface, the first direction Dx, the second direction Dy, and the third direction Dz indicate the directions when the multiple substrates 21 are unfolded in a planar shape.

[0016] As described above, the display device 1 of this embodiment is elongated and has multiple substrates 21, each having multiple display areas 23 along its longitudinal direction. This allows the dimensions and shape of the display surface of the display device 1 to be changed by varying the length of each substrate 21 along its longitudinal direction, or by varying the number of substrates 21. As a result, the display device 1 of this embodiment can improve the degree of freedom in the shape of its display surface and can be incorporated into various products with diverse shapes, such as interiors and signage.

[0017] Next, the system configuration of the display device 1 and the detailed configuration of the display area 23 will be described. Figure 2 is a schematic block diagram showing an example of the configuration of a display device according to the embodiment. As shown in Figure 2, the display device 1 has a pixel IC 50 provided in the display area 23 of the substrate 21 and wiring 19 connecting the pixel IC 50. Furthermore, the display device 1 includes a driver IC (Integrated Circuit) 11 and a host 101. The host 101 may be a host IC, a host CPU, etc.

[0018] Multiple pixel ICs 50 are arranged along the longitudinal direction of the substrate 21 and connected in series via wiring 19. The detailed configuration of the substrate 21 and the detailed configuration of the pixel ICs 50 will be described later in Figure 3 and subsequent figures.

[0019] The driver IC 11 is a circuit that controls the display of multiple substrates 21 of the display device 1. The host 101 is a display control circuit that controls the driver IC 11. That is, the driver IC 11 supplies a clock signal CK and image data DT (see Figure 4) to each of the multiple pixel ICs 50 on the substrate 21. The driver IC 11 supplies the clock signal CK and image data DT in synchronization to the multiple pixel ICs 50 provided on each of the multiple substrates 21 arranged in a first direction Dx.

[0020] The driver IC 11 is connected to the host 101 and controls multiple pixel ICs 50 provided on multiple boards 21 based on control signals from the host 101. The display device 1 is not limited to having only one driver IC 11, but may have multiple driver ICs 11 depending on the number of boards 21. Furthermore, the driver IC 11 may be configured as a single circuit or as two or more circuits.

[0021] Figure 3 is a schematic plan view showing an example of the substrate configuration. Although Figure 3 shows the configuration of one substrate 21 out of several substrates 21, the configurations of the other substrates 21 are similar.

[0022] As shown in Figure 3, the display area 23 of the substrate 21 is arranged with pixels PX (multiple light-emitting elements 3R, 3G, 3B) and a pixel IC 50 for driving the multiple light-emitting elements 3R, 3G, 3B. The multiple light-emitting elements 3R, 3G, 3B are arranged on top of the pixel IC 50.

[0023] The light-emitting elements 3R, 3G, and 3B are display elements of the display device 1 and are self-emitting elements that emit red light, green light, and blue light, respectively. The light-emitting elements 3R, 3G, and 3B are, for example, inorganic light-emitting diodes (LEDs). The light-emitting elements 3R, 3G, and 3B may also be micro-LEDs having a size of approximately 3 μm to 300 μm in a planar view. A display device 1 equipped with micro-LEDs in each pixel PX is also called a micro-LED display device.

[0024] In the following explanation, unless it is necessary to distinguish between the light-emitting elements 3R, 3G, and 3B, they will simply be referred to as "light-emitting element 3." Note that multiple light-emitting elements 3 may emit four or more different colors of light. Also, in the example shown in Figure 3, the multiple light-emitting elements 3R, 3G, and 3B are arranged in an L-shape. However, the arrangement of the multiple light-emitting elements 3R, 3G, and 3B is merely an example and is not limited to this.

[0025] The pixel IC 50 is composed of, for example, a micro IC and is provided for each display area 23. In addition, one pixel IC 50 and one pixel PX (multiple light-emitting elements 3) connected to it are arranged in one display area 23. In the example shown in Figure 3, three light-emitting elements 3 are connected to one pixel IC 50.

[0026] On the substrate 21, the pixel IC 50 and multiple light-emitting elements 3 provided in each display area 23 are arranged along the second direction Dy. Furthermore, pixel IC 50 provided in adjacent display areas 23 are connected in series by wiring 19 provided in the non-display area 24. In other words, the non-display area 24 of the substrate 21 does not have elements such as light-emitting elements 3, and only wiring 19 connecting the display areas 23 is provided. The wiring 19 includes, for example, a power potential supply wiring 17 and a reference potential supply wiring 18. The power potential supply wiring 17 is for supplying power potential to the multiple pixel IC 50. The reference potential is, for example, the ground potential.

[0027] The power supply potential supply wiring 17 (power line) and the reference potential supply wiring 18 (reference potential line) connecting multiple adjacent pixel ICs 50 are wavy. Specifically, the power supply potential supply wiring 17 and the reference potential supply wiring 18 each extend in a wavy shape along the second direction Dy. Furthermore, the power supply potential supply wiring 17 and the reference potential supply wiring 18 are arranged adjacent to each other in the first direction Dx. In this disclosure, "wavy" refers to a shape that changes direction and meanders as it progresses in a predetermined direction. Wavy includes zigzag shapes. As a result, even when the substrate 21 is deformed, such as when the substrate 21 is expanded or contracted along the second direction Dy, or when the substrate 21 is bent along a curved support member, stress concentration in the wiring 19 can be suppressed. Therefore, in this embodiment, disconnection of the wiring 19 can be suppressed.

[0028] In Figure 3, for the sake of clarity, the wiring 19 is shown to include the power potential supply wiring 17 and the reference potential supply wiring 18. However, the wiring 19 also includes the clock signal supply wiring 12 and the image data supply wiring 13 (see Figure 4). In other words, it may be configured so that four wirings connecting adjacent pixel ICs 50 are arranged in parallel and in a wave-like pattern.

[0029] Of the multiple pixel ICs 50 connected in series, the first-stage pixel IC 50 is connected to the driver IC 11. Each pixel IC 50 controls a predetermined current to flow through each light-emitting element 3 based on control signals (clock signal CK and image data DT) from the driver IC 11, causing the light-emitting elements 3 to emit light.

[0030] Figure 3 shows a configuration in which one pixel IC 50 is connected to one pixel PX, but the configuration is not limited to this, and one pixel IC 50 may be connected to multiple pixel PXs (four or more light-emitting elements 3). Also, the configuration is not limited to multiple light-emitting elements 3 overlapping the pixel IC 50 in one display area 23, and multiple light-emitting elements 3 and the pixel IC 50 may be arranged adjacent to each other in a plan view.

[0031] As shown in Figure 3, the width Wsub of the substrate 21 (width in the first direction Dx) is, for example, about 1 mm to 15 mm. Alternatively, the width Wsub of the substrate 21 is, for example, 0.1 mm to 30 mm. The width Wsub of the substrate 21 can be appropriately set according to the respective sizes and arrangement of the pixel IC 50 and the light-emitting element 3.

[0032] Figure 4 is a circuit diagram showing a driver IC, multiple pixel ICs, and multiple light-emitting elements. As shown in Figure 4, the multiple pixel ICs 50 include a first pixel IC 50-1, a second pixel IC 50-2, and a third pixel IC 50-3 connected in series. The first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 are each provided corresponding to the display area 23.

[0033] In Figure 4, for the sake of clarity, a 3x2 pixel IC 50 (display area 23) is shown among the multiple pixel ICs 50 (display area 23). Furthermore, in the following explanation, if it is not necessary to distinguish between the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, they will simply be referred to as pixel IC 50. Similarly, if it is not necessary to distinguish between the clock signal supply lines 12-1, 12-2, 12-3, and 12-4, they will simply be referred to as clock signal supply line 12. Furthermore, if it is not necessary to distinguish between the image data supply lines 13-1, 13-2, 13-3, and 13-4, they will simply be referred to as image data supply line 13.

[0034] Each of the multiple pixel ICs 50 has a clock signal input terminal 51, an image data input terminal 52, a clock signal output terminal 53, and an image data output terminal 54. A clock signal CK is input to the clock signal input terminal 51. Image data DT is input to the image data input terminal 52. A clock signal output terminal 53 outputs a clock signal CK. An image data output terminal 54 outputs image data DT.

[0035] In the second direction Dy, for multiple adjacent pixel ICs 50, the clock signal output terminal 53 and the clock signal input terminal 51 are connected, and the image data output terminal 54 and the image data input terminal 52 are connected.

[0036] More specifically, the clock signal input terminal 51 of the first pixel IC 50-1 is connected to the driver IC 11 via the clock signal supply wiring 12-1. The image data input terminal 52 of the first pixel IC 50-1 is also connected to the driver IC 11 via the image data supply wiring 13-1. The first pixel IC 50-1 corresponds to the first-stage pixel IC 50 described above. Furthermore, the multiple clock signal supply wirings 12-1, 12-2, 12-3, and 12-4 are independently provided between two adjacent pixel ICs 50 in the second direction Dy (the longitudinal direction of the substrate 21). Similarly, the multiple image data supply wirings 13-1, 13-2, 13-3, and 13-4 are independently provided between two adjacent pixel ICs 50 in the second direction Dy (the longitudinal direction of the substrate 21).

[0037] The clock signal output terminal 53 of the first pixel IC 50-1 is connected to the clock signal input terminal 51 of the second pixel IC 50-2 via the clock signal supply wiring 12-2. The image data output terminal 54 of the first pixel IC 50-1 is connected to the image data input terminal 52 of the second pixel IC 50-2 via the image data supply wiring 13-2.

[0038] The clock signal output terminal 53 of the second pixel IC 50-2 is connected to the clock signal input terminal 51 of the third pixel IC 50-3 via the clock signal supply wiring 12-3. The image data output terminal 54 of the second pixel IC 50-2 is connected to the image data input terminal 52 of the third pixel IC 50-3 via the image data supply wiring 13-3.

[0039] In other words, the multiple clock signal supply lines 12 are provided between two adjacent pixel ICs 50 in the second direction Dy, spaced apart from each other. Similarly, the multiple image data supply lines 13 are provided between two adjacent pixel ICs 50 in the second direction Dy, spaced apart from each other. As a result, the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, which are arranged in the second direction Dy, are connected in series.

[0040] Referring to Figures 3 and 4, on a single substrate 21, the clock signal output terminal 53 of a pixel IC 50 (for example, a first pixel IC 50-1) provided in one of two adjacent display areas 23 separated by a non-display area 24 is connected to the clock signal input terminal 51 of a pixel IC 50 (for example, a second pixel IC 50-2) provided in the other display area 23 via wiring 19 (for example, clock signal supply wiring 12-2) provided in the non-display area 24.

[0041] With this configuration, the clock signal CK output from the driver IC 11 is transmitted sequentially in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the clock signal supply wiring 12. Similarly, the image data DT output from the driver IC 11 is transmitted sequentially in series to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 via the image data supply wiring 13.

[0042] As a result, the display device 1 of this embodiment can increase the bandwidth (frequency) of the transmitted clock signal CK and image data DT compared to the case where multiple pixel ICs 50 are connected in parallel to a common clock signal supply line 12 and a common image data supply line 13. In other words, the display device 1 can suppress voltage fluctuations and delays of the clock signal CK and image data DT due to the wiring resistance of the clock signal supply line 12 and the image data supply line 13. This allows the phase relationship between the clock signal CK and the image data DT to be maintained.

[0043] Therefore, the display device 1 of this embodiment can achieve good display characteristics even when the number of display areas 23 connected in series is increased. For example, the display device 1 can achieve good display characteristics even when the length of the substrate 21 is changed or the number of substrates 21 is changed to increase the degree of freedom of the shape and area of ​​the display surface.

[0044] Note that between the substrates 21 adjacent in the first direction Dx, the clock signal supply wiring 12 and the image data supply wiring 13 are not provided, and the transmission and reception of the clock signal CK and the image data DT are not performed. The driver IC 11 outputs the clock signal CK and the image data DT synchronously among the plurality of substrates 21 arranged in the first direction Dx.

[0045] The plurality of pixel ICs 50 further include a power supply terminal 55, a reference potential terminal 56, and connection terminals 57, 58, 59 (see FIG. 5). The power supply terminal 55 is connected to the driver IC 11 via the power supply potential supply wiring 17. Thereby, the driver IC 11 supplies the power supply potential to the plurality of pixel ICs 50 through the power supply terminal 55 and the power supply potential supply wiring 17. Further, the power supply potential supply wiring 17 is connected to the anodes of the light emitting elements 3 (3R, 3G, 3B). The driver IC 11 supplies the power supply potential to the anodes of the light emitting elements 3 (3R, 3G, 3B) through the power supply potential supply wiring 17.

[0046] The plurality of pixel ICs 50 and the plurality of light emitting elements 3 are connected in parallel to the power supply potential supply wiring 17. In other words, the power supply potential supply wiring 17 is commonly provided for the plurality of display regions 23 (pixel ICs 50 and the plurality of light emitting elements 3) arranged in the second direction Dy, respectively.

[0047] The reference potential terminal 56 is connected to the driver IC 11 via the reference potential supply wiring 18. Thereby, the driver IC 11 supplies the reference potential GND to the plurality of pixel ICs 50 through the reference potential terminal 56 and the reference potential supply wiring 18. The reference potential GND is, for example, a ground potential. However, it is not limited thereto, and the reference potential GND may be a predetermined fixed potential different from the ground potential.

[0048] The plurality of pixel ICs 50 are connected in parallel to the reference potential supply wiring 18. In other words, the reference potential supply wiring 18 is commonly provided for the plurality of display regions 23 (pixel ICs 50 and the plurality of light emitting elements 3) arranged in the second direction Dy, respectively.

[0049] The connection terminals 57, 58, and 59 are connected to the cathodes of the light-emitting elements 3R, 3G, and 3B, respectively. The cathodes of the light-emitting elements 3R, 3G, and 3B are connected to the reference potential GND via the drive transistor inside the light-emitting element drive circuit 68 (see Figure 5) of the pixel IC 50, as a result of the operation of the light-emitting element drive circuit 68. As a result, the light-emitting elements 3R, 3G, and 3B are driven in a forward bias and emit light.

[0050] Note that Figures 3 and 4 show an example where one pixel IC 50 is connected to one pixel PX (three light-emitting elements 3) for clarity. However, two or more pixel PXs, i.e., six or more light-emitting elements 3, may be connected to one pixel IC 50, and in this case, the number of connection terminals can be changed according to the number of light-emitting elements 3. One pixel IC 50 may be provided with six or more connection terminals.

[0051] Figure 5 is a block diagram showing an example of the configuration of a pixel IC. As shown in Figure 5, the pixel IC 50 includes buffer circuits 61 and 62, flip-flop circuits 63 and 64, control circuit 65, PWM control circuit 66, memory circuit 67, and light-emitting element driving circuit 68 (display element driving circuit).

[0052] The buffer circuit 61 is connected between the clock signal input terminal 51 and the clock signal output terminal 53. As a result, the clock signal CK input to the clock signal input terminal 51 of the pixel IC 50 is output from the clock signal output terminal 53 via the buffer circuit 61. The buffer circuit 61 corrects and outputs voltage fluctuations of the clock signal CK due to resistance in the clock signal supply wiring 12 and wiring within the pixel IC 50. As a result, even in a configuration where multiple pixel ICs 50 are connected in series, the clock signal CK is transmitted reliably to the final stage pixel IC 50 (the nth pixel IC 50-n).

[0053] The flip-flop circuit 63 is connected between the clock signal input terminal 51 and the image data input terminal 52 and the control circuit 65. The buffer circuit 62 and the flip-flop circuit 64 are connected in series between the control circuit 65 and the image data output terminal 54.

[0054] The flip-flop circuit 63 receives the clock signal CK from the clock signal input terminal 51 and the image data DT from the image data input terminal 52, and outputs the image data DT to the control circuit 65 at a timing corresponding to the clock signal CK.

[0055] The control circuit 65 controls the lighting of the light-emitting element 3 connected to the pixel IC 50 based on the image data DT input through the image data input terminal 52 and the flip-flop circuit 63. The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the buffer circuit 62.

[0056] The buffer circuit 62 corrects and outputs the voltage fluctuations and delay time of the image data DT caused by resistance in the image data supply wiring 13 and wiring within the pixel IC 50. The delay time correction is adjusted so that the delay time of the data after predetermined processing of the image data DT does not become shorter than the delay time generated by the buffer circuit 61 provided for the clock signal CK.

[0057] The flip-flop circuit 64 receives a clock signal CK supplied from the clock signal input terminal 51 through the buffer circuit 61, and image data DT from the image data input terminal 52 via the flip-flop circuit 63, control circuit 65, and buffer circuit 62. The flip-flop circuit 64 outputs the image data DT to the image data output terminal 54 at a timing corresponding to the clock signal CK.

[0058] The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the storage circuit 67, and controls the PWM control circuit 66 and the light-emitting element drive circuit 68 based on the input image data DT. The storage circuit 67 stores the image data DT input from the control circuit 65. The PWM control circuit 66 determines the illumination period of the multiple light-emitting elements 3 corresponding to the grayscale and generates a PWM control signal based on the image data DT acquired from the control circuit 65.

[0059] The light-emitting element driving circuit 68 drives a plurality of light-emitting elements 3 connected to the connection terminals 57, 58, and 59 of the pixel IC 50 based on a PWM control signal obtained from the PWM control circuit 66. Specifically, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch the connection state between the cathode of the light-emitting element 3 and the reference potential terminal 56. For example, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch between connection (on) and disconnection (off) between the cathode of the light-emitting element 3 and the reference potential GND based on a PWM control signal. Current flows to the light-emitting element 3 and it lights up during a predetermined period when the cathode of the light-emitting element 3 is connected to the reference potential GND. Also, the light-emitting element 3 turns off during the period when the cathode of the light-emitting element 3 is not connected to the reference potential GND. By making the lighting period and the off period different based on the PWM control signal, the light-emitting element 3 can express gradations according to the image data DT. As described above, the multiple light-emitting elements 3 are driven by PWM (Pulse Width Modulation) based on the image data DT acquired by the control circuit 65.

[0060] Figure 6 is a timing chart showing the clock signal and image data in a pixel IC. Figure 6 shows the clock signal CK(IN) input to the clock signal input terminal 51, the image data DT(IN) input to the image data input terminal 52, the clock signal CK(OUT) output from the clock signal output terminal 53, and the image data DT(OUT) output from the image data output terminal 54.

[0061] As shown in Figure 6, the clock signal CK(OUT) output from the clock signal output terminal 53 is slightly delayed relative to the clock signal CK(IN) due to the operation of the buffer circuit 61. For example, the delay of the clock signal CK(OUT) is the difference between time t2 and time t1 shown in Figure 6. This delay is very small and does not pose any practical problems.

[0062] The flip-flop circuits 63 and 64 output the image data DT at the timing of the rising (or falling) edge of the clock signal CK. In other words, the image data DT is output by each of the flip-flop circuits 63 and 64 with a 1-bit delay relative to the clock signal CK.

[0063] Specifically, as shown in Figure 6, the image data DT includes multiple image data DT(a), DT(b), DT(c), and DT(d). Note that image data DT(a), DT(b), DT(c), and DT(d) are shown schematically for clarity.

[0064] Focusing on image data DT(a) within the image data DT, image data DT(a) is input to the image data input terminal 52 after a predetermined time has elapsed from time t1, when the clock signal CK(IN) is input to the clock signal input terminal 51. In the first stage flip-flop circuit 63, image data DT(a) is output at the rising edge timing of the clock signal CK(IN) (time t3). In other words, image data DT(a) is delayed by 1 bit relative to the clock signal CK(IN).

[0065] In the second stage flip-flop circuit 64, the image data DT(a) is output at the rising edge timing (time t6) of the clock signal CK(OUT). As a result, when compared with the timing relationship between the input clock signal CK(IN) and the image data DT(IN), the image data DT(OUT) is output with a total delay of 2 bits relative to the clock signal CK(OUT).

[0066] As described above, in the pixel IC 50, buffer circuits 61, 62 and flip-flop circuits 63, 64 cause a predetermined bit (for example, 2 bits) delay between the image data DT(OUT) output from the image data output terminal 54 and the clock signal CK(OUT) output from the clock signal output terminal 53. However, the timing relationship (delay time) between the clock signal CK(OUT) and the image data DT(OUT) is substantially the same for each of the multiple pixel ICs 50. As a result, the display device 1 can display images well even in a configuration that does not synchronize horizontally (for example, without gate drive signals in an active matrix system).

[0067] Note that the configuration and operation of the pixel IC 50 shown in Figures 4 to 6 are merely examples and can be modified as appropriate.

[0068] (First Modified Example) Figure 7 is a schematic plan view showing an example of the configuration of one substrate of the display device according to the first modified example. Figure 8 is a cross-sectional view taken along VIII-VIII' in Figure 7. Figure 9 is a plan view showing an enlarged view of the two display areas in Figure 7. In the following description, the same reference numerals are used for components that are the same as those described in the above-described embodiment, and redundant descriptions are omitted.

[0069] As shown in Figure 7, in the display device 1A according to the first modified example, among the multiple pixel ICs 50, multiple pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to one pixel IC. That is, the display area 23 includes one pixel IC 50 and multiple pixel PXs (light-emitting elements 3R, 3G, 3B) connected to the pixel IC 50. The multiple light-emitting elements 3 connected to one pixel IC 50 are arranged in a matrix.

[0070] In the example shown in Figure 7, the pixels PX connected to one pixel IC 50 are arranged in a 4x4 grid. If one pixel PX has three light-emitting elements 3R, 3G, and 3B, then 48 light-emitting elements 3 are connected to one pixel IC 50.

[0071] In this modified configuration, multiple pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to a single pixel IC, allowing for higher resolution display compared to a configuration where one pixel PX is connected to one pixel IC 50. Furthermore, in this modified configuration, even if the number of pixel PXs increases, the number of pixel ICs 50 provided on the substrate 21 can be kept from increasing, thereby reducing the cost of the display device 1A. Note that the number and arrangement of pixel PXs (light-emitting elements 3) connected to a single pixel IC 50 are merely examples and can be changed as appropriate.

[0072] As shown in Figure 8, the multiple light-emitting elements 3 are mounted on a common substrate 21 shared with the pixel IC 50. The substrate 21 is a flexible substrate made of a resin material such as polyimide resin. A protective film 27 is provided to cover the multiple light-emitting elements 3 and the pixel IC 50. The protective film 27 is a film made of a light-transmitting resin material, such as OCA (Optically Clear Adhesive).

[0073] The substrate 21 is placed on the support member 28. The support member 28 is made of a deformable material, such as cloth or tape. This allows the support member 28 to support the substrate 21 in a deformable manner while improving its strength.

[0074] The support member 28 may be provided for each substrate 21, or multiple substrates 21 may be bonded together on a single support member 28. Alternatively, the support member 28 may be omitted.

[0075] As shown in Figure 9, the wiring 19 connecting adjacent pixel ICs 50 (clock signal supply wiring 12, image data supply wiring 13, power supply potential supply wiring 17, and reference potential supply wiring 18) is wavy. In addition, of the anode wire 17a and cathode wire 18a connecting the pixel IC 50 and the multiple light-emitting elements 3, at least the portion extending along the second direction Dy is wavy. The anode wire 17a is electrically connected to, for example, the power supply potential supply wiring 17, and the cathode wire 18a is electrically connected to, for example, the reference potential supply wiring 18.

[0076] As a result, in this modified example, disconnections of the wiring 19 (clock signal supply wiring 12, image data supply wiring 13, power supply potential supply wiring 17, and reference potential supply wiring 18), and the anode wire 17a and cathode wire 18a connecting the pixel IC 50 and the plurality of light-emitting elements 3 can be suppressed.

[0077] Note that in Figure 9, some of the wiring 19 (clock signal supply wiring 12, image data supply wiring 13, power supply potential supply wiring 17, and reference potential supply wiring 18), anode wires 17a, and cathode wires 18a are omitted for clarity. For example, one anode wire 17a connected to one pixel PX is shown, but in reality, multiple anode wires 17a (for example, three anode wires 17a) are connected to correspond to the multiple light-emitting elements 3 that one pixel PX has.

[0078] (Second Modification) Figure 10 is a schematic plan view showing one display area of ​​the display device according to the second modification. Figure 11 is an explanatory diagram for illustrating the connection configuration between the pixel IC and multiple pixels of the display device according to the second modification.

[0079] In the first modified example, a configuration was described in which multiple pixels PX (light-emitting elements 3R, 3G, 3B) are arranged in a matrix in the display area 23, but the invention is not limited thereto. As shown in Figure 10, in the display device 1B according to the second modified example, multiple pixels PX (light-emitting elements 3R, 3G, 3B) are connected to one of the multiple pixel ICs 50. The multiple pixels PX (light-emitting elements 3R, 3G, 3B) connected to one pixel IC 50 are arranged in the second direction Dy (one direction).

[0080] The pixel IC 50 is positioned adjacent to a plurality of pixels PX (light-emitting elements 3R, 3G, 3B) arranged in the second direction Dy, in the first direction Dx.

[0081] As shown in Figure 11, the display area 23 will be described by dividing it into four partial display areas 23a, 23b, 23c, and 23d, each consisting of four pixels PX. One anode line 17a is connected in parallel to one pixel PX in partial display area 23a, one pixel PX in partial display area 23b, one pixel PX in partial display area 23c, and one pixel PX in partial display area 23d. In addition, an anode line 17a is connected in parallel to each of the other pixels PX in each of the partial display areas 23a, 23b, 23c, and 23d.

[0082] Furthermore, one cathode wire 18a is connected in parallel to the four pixels PX of the partial display area 23a. Similarly, one cathode wire 18a is connected in parallel to each of the partial display areas 23b, 23c, and 23d. This enables a connection configuration in which the wiring for so-called passive matrix drive is deployed in series.

[0083] Figures 10 and 11 show a single display area 23, but multiple display areas 23 are arranged in the second direction Dy (one direction). As a result, in the display device 1B according to the second modified example, the width Wsub of the substrate 21 can be reduced, and it can be applied to a long substrate 21.

[0084] In Figure 11, the wiring is shown as a straight line for clarity, but as with the first embodiment and the first modified example described above, the wiring 19 extending in the second direction Dy is wavy. Alternatively, at least the portion of the anode wire 17a and the cathode wire 18a extending in the second direction Dy may be wavy.

[0085] (Third Modification) Figure 12 is a schematic perspective view showing an example of the configuration of a display device according to the third modification. As shown in Figure 12, the display device 1C according to the third modification has a curved display surface. Specifically, the display device 1C according to the third modification has a spherical support member 29, and the substrate 21 is arranged in a spiral shape on the surface of the spherical support member 29. One end of the substrate 21 in the longitudinal direction is located at the top of the spherical support member 29. In addition, the substrate 21 extends in a spiral shape in a plan view and is arranged to approach the peripheral edge of the spherical support member 29.

[0086] Furthermore, the spherical support member 29 is provided with an external power line 17A and an external reference potential line 18A. The external power line 17A and the external reference potential line 18A extend from the top to the periphery of the spherical support member 29 so as to intersect with the spirally arranged substrate 21. At multiple intersections with the substrate 21, the external power line 17A is electrically connected to the power potential supply wiring 17 (power line) provided on the substrate 21. Similarly, at multiple intersections with the substrate 21, the external reference potential line 18A is electrically connected to the reference potential supply wiring 18 (reference potential line) provided on the substrate 21. As a result, even if the substrate 21 is formed in a long shape, the power potential and reference potential can be supplied stably. Therefore, voltage drops due to resistive components are suppressed, and fluctuations in the power potential and reference potential along the longitudinal direction of the substrate 21 can be suppressed.

[0087] (Fourth Modification) Figure 13 is a schematic plan view showing an example of the configuration of multiple substrates in the display device according to the fourth modification. The display device 1D according to the fourth modification differs from the third modification described above in that it has multiple substrates 21, and the multiple substrates 21 are arranged in a spiral pattern on the surface of a spherical support member 29 (see Figure 12). In the example shown in Figure 13, four substrates 21 are arranged in a spiral pattern in parallel.

[0088] By increasing the number of substrates 21, the density of pixels PX per predetermined area can be increased, enabling higher resolution display. Alternatively, by increasing the number of substrates 21, the length of a single substrate 21 can be shortened, thereby increasing the frame rate.

[0089] In Figure 13, four substrates 21 are arranged in a spiral pattern, but the arrangement is not limited to this. There may be three or fewer substrates 21, or five or more. For example, 16 substrates 21 may be arranged in parallel in a spiral pattern. Furthermore, an external power line 17A and an external reference potential line 18A (see Figure 12) may be provided so as to intersect with the multiple substrates 21 arranged in a spiral pattern. In this case, the external power line 17A is electrically connected to the power supply wiring 17 (power line) of each of the multiple substrates 21. The external reference potential line 18A is electrically connected to the reference potential supply wiring 18 (reference potential line) of each of the multiple substrates 21.

[0090] (Fifth Modification) Figure 14 is a schematic perspective view showing an example of the configuration of a display device according to the fifth modification. Figure 15 is a schematic plan view showing an example of the configuration of one substrate of the display device according to the fifth modification.

[0091] As shown in Figure 14, the display device 1E according to the fifth modified example has a plurality of substrates 21A and a support substrate 22. The support substrate 22 is a plate-shaped member having a main surface that intersects the third direction Dz. One end of the plurality of substrates 21A is connected to the main surface of the support substrate 22. Each of the plurality of substrates 21A extends in the third direction Dz and is arranged in a matrix in a plan view from a direction perpendicular to the main surface of the support substrate 22.

[0092] As a result, the multiple display areas 23 (pixels PX and pixel ICs 50) provided on each of the multiple substrates 21A are arranged three-dimensionally. That is, on one substrate 21A, the multiple display areas 23 are arranged along the third direction Dz (longitudinal direction). Also, on substrates 21A adjacent to the first direction Dx, the multiple display areas 23 are adjacent to the first direction Dx. Furthermore, on substrates 21A adjacent to the second direction Dy, the multiple display areas 23 are adjacent to the second direction Dy.

[0093] In the display device 1E, the display areas 23 of multiple substrates 21A are arranged three-dimensionally so that the image is visible when viewed from, for example, a second direction Dy. Note that the display device 1E is not limited to a display visible from one direction, and the display areas 23 may be arranged so that the image is visible from multiple directions.

[0094] As shown in Figure 15, multiple pixels PX (light-emitting elements 3R, 3G, 3B) are connected to one pixel IC 50 on the substrate 21A. The multiple pixels PX (light-emitting elements 3R, 3G, 3B) connected to one pixel IC 50 are arranged in a matrix.

[0095] Furthermore, the substrate 21A has open regions OP1 and OP2 and non-open regions 21Aa, 21Ab, 21Ac, 21Ad, and 21Ae. In Figure 15, the non-open regions 21Aa, 21Ab, 21Ac, 21Ad, and 21Ae are shown with hatching for clarity.

[0096] The non-opening regions 21Aa, 21Ab, 21Ac, 21Ad, and 21Ae are arranged in a grid pattern, and the opening regions OP1 and OP2 are rectangular regions surrounded by the non-opening regions 21Aa, 21Ab, 21Ac, 21Ad, and 21Ae.

[0097] Specifically, the non-opening regions 21Ac, 21Ad, and 21Ae extend along the third direction Dz (the longitudinal direction of the substrate 21A) and are arranged with spacing in the first direction Dx. The non-opening region 21Aa extends in the first direction Dx and connects the non-opening regions 21Ac and 21Ad. In addition, multiple non-opening regions 21Aa are arranged in the third direction Dz. As a result, the opening region OP1 is formed in the region surrounded by the non-opening regions 21Aa, 21Ac, and 21Ad.

[0098] The non-opening region 21Ab extends in the first direction Dx and connects the non-opening region 21Ad and the non-opening region 21Ae. Furthermore, multiple non-opening regions 21Ab are arranged in the third direction Dz. As a result, the opening region OP2 is formed in the area enclosed by the non-opening regions 21Ab, 21Ad, and 21Ae.

[0099] Multiple light-emitting elements 3 and multiple pixel ICs 50 are provided in the non-aperture regions 21Aa and 21Ab of the substrate 21A. In addition, power supply potential supply wiring 17 (power line) and reference potential supply wiring 18 (reference potential line) are provided in the non-aperture region 21Ad, extending in the third direction Dz.

[0100] With this configuration, when multiple substrates 21A are arranged on the support substrate 22, the light-emitting elements 3 of other substrates 21A can be viewed through the aperture regions OP1 and OP2 of the substrates 21A. Furthermore, by forming the aperture regions OP1 and OP2 in areas where no wiring 19 is provided, the light transmittance of the substrates 21A can be ensured. As a result, the display device 1E according to the fifth modified example can achieve a three-dimensional display.

[0101] Note that the configuration of the substrate 21A shown in Figure 15 is merely an example and can be modified as appropriate. For example, the number, size, and arrangement of aperture regions OP1 and OP2 can be changed as appropriate depending on the number and arrangement of light-emitting elements 3 and pixel ICs 50, or the arrangement of multiple substrates 21A.

[0102] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each embodiment and each modification described above.

[0103] 1, 1A, 1B, 1C, 1D, 1E Display device 3, 3B, 3G, 3R Light-emitting element 11 Driver IC 12, 12-1, 12-2, 12-3, 12-4 Clock signal supply wiring 13, 13-1, 13-2, 13-3, 13-4 Image data supply wiring 17 Power supply potential supply wiring 18 Reference potential supply wiring 19 Wiring 21, 21A Substrate 21Aa, 21Ab, 21Ac, 21Ad, 21Ae Non-aperture area 22 Support substrate 23 Display area 24 Non-display area 27 Protective film 28, 29 Support member 50 Pixel IC 51 Clock signal input terminal 52 Image data input terminal 53 Clock signal output terminal 54 Image data output terminal 57, 58, 59 Connection terminals 101 Host OP1, OP2 opening area

Claims

1. A display device comprising: a substrate that is elongated and has a plurality of display areas along its longitudinal direction; a plurality of display elements provided in the plurality of display areas of the substrate; a plurality of pixel ICs provided in the plurality of display areas of the substrate and connected to the plurality of display elements for driving the plurality of display elements; a power line for supplying power to the plurality of pixel ICs; and a reference potential line for supplying a reference potential to the plurality of pixel ICs, wherein the plurality of pixel ICs are connected in series along the longitudinal direction of the substrate; each of the plurality of pixel ICs has a clock signal input terminal into which a clock signal is input, an image data input terminal into which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements; in adjacent plurality of pixel ICs, the clock signal output terminal and the clock signal input terminal are connected, and the image data output terminal and the image data input terminal are connected; and the power line and the reference potential line connecting adjacent plurality of pixel ICs are wavy.

2. The display device according to claim 1, wherein the plurality of display elements are connected to one of the plurality of pixel ICs, and the plurality of display elements connected to the one pixel IC are arranged in a matrix.

3. The display device according to claim 1, wherein the plurality of display elements are connected to one of the plurality of pixel ICs, and the plurality of display elements connected to the one pixel IC are arranged in one direction.

4. The display device according to claim 1, wherein the substrate is arranged in a spiral pattern on the surface of a spherical support member.

5. The display device according to claim 1, which has a plurality of substrates, wherein the plurality of substrates are arranged in a spiral pattern on the surface of a spherical support member.

6. The display device according to claim 4, wherein an external power line and an external reference potential line are connected to the power line and the reference potential line provided on the substrate.

7. The display device according to claim 1, wherein the width of the substrate is 1 mm or more and 15 mm or less.

8. The display device according to claim 1, comprising a plurality of substrates and a support substrate having a main surface intersecting the longitudinal direction of the substrates, wherein the plurality of substrates are arranged in a matrix on the main surface of the support substrate, and the plurality of display areas provided on each of the plurality of substrates are arranged three-dimensionally.

9. The display device according to claim 8, wherein the plurality of substrates have an aperture region and a non-aperture region, and the plurality of display elements, the plurality of pixel ICs, the power lines, and the reference potential lines are provided in the non-aperture region of the substrate.

10. The display device according to claim 1, wherein the display element is an inorganic LED.

11. The display device according to claim 1, wherein the width of the substrate is 0.1 mm or more and 30 mm or less.

Images