Display device

Abstract

This display device includes: a substrate; a plurality of display elements which are provided on the substrate; a plurality of pixel ICs which are provided on the substrate, and are connected to the plurality of display elements so as to drive the plurality of display elements; power supply lines; and reference potential lines. The plurality of pixel ICs are connected in series along one prescribed direction. In the adjacent pixel ICs, clock signal output terminals and clock signal input terminals are connected, and image data output terminals and image data input terminals are connected. When the plurality of pixel ICs arranged along said one direction are defined as a set of pixel ICs, a plurality of sets of pixel ICs are arranged in a direction intersecting said one direction, and the number of the pixel ICs included in a set of pixel ICs positioned on the outer edge side of the substrate in the direction intersecting said one direction is smaller than the number of the pixel ICs included in a set of pixel ICs positioned on the center side of the substrate in the direction intersecting said one direction.

Description

Display device

[0001] The present invention relates to a display device.

[0002] Patent Documents 1 and 2 disclose a technique in which a pixel IC (represented as a pixel controller or a controller in Patent Documents 1 and 2) is connected to each of one or more pixels.

[0003] U.S. Patent No. 10832609, Japanese Unexamined Patent Application Publication No. 2014 - 63845

[0004] When a display device is used for interiors, signage, etc., display devices having various shapes and sizes are required. For this reason, it is necessary to increase the degree of freedom in the shape of the display device.

[0005] An object of the present disclosure is to provide a display device capable of improving the degree of freedom in shape.

[0006] A display device according to an aspect of the present disclosure includes a substrate, a plurality of display elements provided on the substrate, a plurality of pixel ICs provided on the substrate and connected to the plurality of display elements for driving the plurality of display elements, a power supply line for supplying power to the plurality of pixel ICs, and a reference potential line for supplying a reference potential to the plurality of pixel ICs. The plurality of pixel ICs are connected in series along a predetermined one direction. Each of the plurality of pixel ICs has a clock signal input terminal to which a clock signal is input, an image data input terminal to which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements. In the plurality of adjacent pixel ICs, the clock signal output terminal and the clock signal input terminal are connected, and the image data output terminal and the image data input terminal are connected. When the plurality of pixel ICs arranged along the one direction are taken as a set of pixel ICs, the plurality of sets of pixel ICs are arranged in a direction intersecting the one direction, and the number of pixel ICs included in the set of pixel ICs located on the outer edge side of the substrate in the direction intersecting the one direction is smaller than the number of pixel ICs included in the set of pixel ICs located on the central side of the substrate in the direction intersecting the one direction.

[0007] Figure 1 is a schematic plan view showing a display device according to the first embodiment. Figure 2 is a schematic block diagram showing an example configuration of the display device according to the first embodiment. Figure 3 is a schematic plan view showing an example configuration of a plurality of pixel ICs and a plurality of light-emitting elements. Figure 4 is a circuit diagram showing a driver IC, a plurality of pixel ICs and a plurality of light-emitting elements. Figure 5 is a block diagram showing an example configuration of a pixel IC. Figure 6 is a timing chart showing a clock signal and image data in a pixel IC. Figure 7 is a schematic plan view showing an example configuration of a set of pixel ICs in a display device according to a first modification of the first embodiment. Figure 8 is a schematic diagram showing an example of equipment on a four-wheeled vehicle including a display device according to the second embodiment. Figure 9 is a schematic plan view showing a display device according to the second embodiment. Figure 10 is a schematic plan view showing a display device according to a second modification of the second embodiment. Figure 11 is a schematic perspective view showing a display device according to the third embodiment. Figure 12 is a schematic plan view showing a plurality of substrates of the display device according to the third embodiment in an unfolded state. Figure 13 is a schematic plan view showing a plurality of pixel ICs of the display device according to the third embodiment. Figure 14 is a schematic plan view showing a plurality of pixel ICs of a display device according to a third modification of the third embodiment. Figure 15 is a schematic plan view showing a plurality of pixel ICs of a display device according to a fourth modification of the third embodiment. Figure 16 is a schematic plan view showing a plurality of pixel ICs of a display device according to a fifth modification of the third embodiment.

[0008] The embodiments for implementing this disclosure will be described in detail with reference to the drawings. This disclosure is not limited to the embodiments described below. Furthermore, the components described below include those that can be easily conceived by a person skilled in the art, and those that are substantially the same. In addition, the components described below can be combined as appropriate. The disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive while maintaining the spirit of this disclosure are naturally included within the scope of this disclosure. Furthermore, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of this disclosure. Furthermore, in this disclosure and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In this disclosure, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0010] (First Embodiment) Figure 1 is a schematic plan view showing a display device according to the first embodiment. As shown in Figure 1, the display device 1 of this embodiment has a substrate 21 on which a plurality of display areas 23 are provided. The outer shape of the substrate 21 is substantially rectangular, and it has an irregular shape with arc-shaped curved portions 21a at the corners. The substrate 21 is a flexible substrate formed of a resin material such as polyimide resin.

[0011] Multiple display areas 23 are arranged in a matrix on the substrate 21. In other words, the multiple display areas 23 are arranged on the substrate 21 in a first direction Dx and a second direction Dy. The display surface of the display device 1 is composed of multiple display areas 23 arranged in a matrix. The number of multiple display areas 23 arranged in the first direction Dx and the number of multiple display areas 23 arranged in the second direction Dy vary depending on the external shape of the substrate 21.

[0012] For example, in the region where the curved portion 21a is provided (the upper side of the substrate 21 in Figure 1), the number of display areas 23 arranged in the first direction Dx is smaller than in the region where the curved portion 21a is not provided (the lower side of the substrate 21 in Figure 1). Alternatively, on the outer edge side of the substrate 21 in the first direction Dx, the number of display areas 23 arranged in the second direction Dy is smaller than on the central side of the substrate 21 in the first direction Dx.

[0013] In the following explanation, the first direction Dx is one direction in a plane parallel to the display surface of the substrate 21. The second direction Dy is one direction in a plane parallel to the display surface of the substrate 21 and is perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is perpendicular to both the first direction Dx and the second direction Dy. The third direction Dz is the normal direction to the display surface of the substrate 21. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the display surface of the substrate 21.

[0014] In Figure 1, a portion of the display area 23 of the circuit board 21 is omitted for clarity. Furthermore, an example is shown where the display area 23 of the circuit board 21 is arranged in 9 rows. However, it is not limited to this arrangement; the display area 23 of the circuit board 21 may have 8 rows or fewer, or 10 rows or more. Also, the external shape of the circuit board 21 is merely an example and can be any shape.

[0015] Furthermore, the substrate 21 is not limited to a configuration arranged in a planar shape, but can also be applied to a display surface having a curved surface. In this case, the display area 23 of the substrate 21 is arranged along the curved surface of the display surface. When the substrate 21 is arranged with a curved surface, the first direction Dx, the second direction Dy, and the third direction Dz indicate the directions when multiple substrates 21 are unfolded in a planar shape.

[0016] Next, the system configuration of the display device 1 and the detailed configuration of the display area 23 will be described. Figure 2 is a schematic block diagram showing an example of the configuration of the display device according to the first embodiment. Figure 2 is a schematic enlarged view showing the arrangement of multiple display areas 23 (pixel ICs 50) in area A of Figure 1. As shown in Figure 2, the display device 1 has pixel ICs 50 provided in the display area 23 of the substrate 21 and wiring 19 connecting the pixel ICs 50. Furthermore, the display device 1 includes a driver IC (Integrated Circuit) 11 and a host 101. The host 101 may be a host IC, a host CPU, etc.

[0017] Multiple pixel ICs 50 are arranged along the second direction Dy (a predetermined one direction) of the substrate 21 and connected in series via wiring 19. The detailed configuration of the display area 23 of the substrate 21 and the detailed configuration of the pixel ICs 50 will be described later in Figure 3 and subsequent figures.

[0018] Here, multiple pixel ICs 50 arranged along the second direction Dy are considered a pair of pixel ICs 50S. Multiple pairs of pixel ICs 50S are arranged in the first direction Dx (a direction intersecting the first direction). In Figure 2, the pairs of pixels ICs 50S-1, 50S-2, ..., 50S-n are arranged in the order of 50S-1, 50S-2, ..., 50S-n, starting from the outer edge of the substrate 21 in the first direction Dx and moving towards the center of the substrate 21.

[0019] The number of pixels IC 50 in a set of multiple pixel ICs 50S varies depending on the external shape of the substrate 21. In this embodiment, the number of pixels IC 50 in a set of pixel ICs 50S decreases as it approaches the outer edge of the substrate 21 in the first direction Dx, corresponding to the curved portion 21a of the substrate 21. That is, the number of pixels IC 50 in a set of pixel ICs 50S-1 located on the outer edge side of the substrate 21 in the first direction Dx is less than the number of pixels IC 50 in a set of pixel ICs 50S-n located on the central side of the substrate 21 in the first direction Dx.

[0020] Furthermore, in adjacent pairs of pixel ICs IC50S-1 and IC50S-2 located on the outer edge of the substrate 21, the pixel ICs IC50 located at the ends in the second direction Dy are electrically connected via connecting wiring 19a. Adjacent pairs of pixel ICs IC50S-1 and IC50S-2 are connected in series in a folded manner. As a result, even if the number of pixel ICs IC50 in a pair of pixel ICs IC50S-1 located on the outer edge of the substrate 21 is less than that of another pair of pixel ICs IC50S, variations in the number of series-connected pixel ICs IC50 and variations in the total length of wiring 19 can be suppressed.

[0021] When the number of pixels IC50 in at least one of two adjacent pairs of pixels IC50S, at least one pair of pixels IC50S, is less than a predetermined number, the adjacent pairs of pixels IC50S are electrically connected via the connecting wiring 19a. For example, when the number of pixels IC50 in a pair of pixels IC50S-1 is 1 / 2 or less of the number of pixels in a pair of pixels IC50S located in the center, the adjacent pairs of pixels IC50S-1 and 50S-2 are electrically connected.

[0022] Figure 2 illustrates an example where two adjacent pairs of pixel ICs 50S are connected, but the invention is not limited to this. For example, when the number of pixels IC50 in a pair of pixel ICs 50S-1 is 1 / 3 or less of the number of pixels in a pair of pixel ICs 50S located in the center, pairs of pixels 50S-1, 50S-2, and 50S-3 in three adjacent rows may be electrically connected.

[0023] The driver IC 11 is a circuit that controls the display of multiple display areas 23. The host 101 is a display control circuit that controls the driver IC 11. That is, the driver IC 11 supplies a clock signal CK and image data DT (see Figure 4) to each of the multiple pixel ICs 50 on the substrate 21. The driver IC 11 supplies the clock signal CK and image data DT in synchronization to each of the multiple pairs of pixel ICs 50S (multiple pixel ICs 50) arranged in the first direction Dx.

[0024] Furthermore, if an adjacent pair of pixel ICs 50S-1 and 50S-2 are connected in series via the connection wiring 19a, one of the adjacent pair of pixel ICs 50S-1 and 50S-2 (for example, one pair of pixel ICs 50S-2) is connected to the driver IC 11. The other pair of pixel ICs 50S-1 is electrically connected to the driver IC 11 via the connection wiring 19a and the pair of pixel ICs 50S-2.

[0025] The driver IC 11 is connected to the host 101 and controls multiple pixel ICs 50 provided on multiple boards 21 based on control signals from the host 101. The display device 1 is not limited to having only one driver IC 11, but may have multiple driver ICs 11 depending on the number of boards 21. Furthermore, the driver IC 11 may be configured as a single circuit or as two or more circuits.

[0026] As described above, the display device 1 of this embodiment has multiple sets of pixel ICs 50S, and the number of pixel ICs 50 in each set of pixel ICs 50S is different from one another. This allows the dimensions and shape of the display surface of the display device 1 to be changed by varying the length of each set of pixel ICs 50S along the second direction Dy, or by varying the number of sets of pixel ICs 50S. As a result, the display device 1 of this embodiment can improve the degree of freedom in the shape of the display surface and can be incorporated into various products with diverse shapes, such as interiors and signage.

[0027] Figure 3 is a schematic plan view showing an example configuration of multiple pixel ICs and multiple light-emitting elements. In Figure 3, the configuration of one set of pixel ICs 50S-1, 50S-2, and 50S-3 located on the outer edge of the substrate 21 is shown, but the configuration of other sets of pixel ICs 50S is similar.

[0028] As shown in Figure 3, the display area 23 of the substrate 21 is arranged with pixels PX (multiple light-emitting elements 3R, 3G, 3B) and a pixel IC 50 for driving the multiple light-emitting elements 3R, 3G, 3B. The multiple light-emitting elements 3R, 3G, 3B are arranged on top of the pixel IC 50.

[0029] The light-emitting elements 3R, 3G, and 3B are display elements of the display device 1 and are self-emitting elements that emit red light, green light, and blue light, respectively. The light-emitting elements 3R, 3G, and 3B are, for example, inorganic light-emitting diodes (LEDs). The light-emitting elements 3R, 3G, and 3B may also be micro-LEDs having a size of approximately 3 μm to 300 μm in a planar view. A display device 1 equipped with micro-LEDs in each pixel PX is also called a micro-LED display device.

[0030] In the following explanation, unless it is necessary to distinguish between the light-emitting elements 3R, 3G, and 3B, they will simply be referred to as "light-emitting element 3." Note that multiple light-emitting elements 3 may emit four or more different colors of light. Also, in the example shown in Figure 3, the multiple light-emitting elements 3R, 3G, and 3B are arranged in an L-shape. However, the arrangement of the multiple light-emitting elements 3R, 3G, and 3B is merely an example and is not limited to this.

[0031] The pixel IC 50 is composed of, for example, a micro IC and is provided for each display area 23. In addition, one pixel IC 50 and one pixel PX (multiple light-emitting elements 3) connected to it are arranged in one display area 23. In the example shown in Figure 3, three light-emitting elements 3 are connected to one pixel IC 50.

[0032] On the substrate 21, the pixel IC 50 and multiple light-emitting elements 3 provided in each display area 23 are arranged along the second direction Dy. Furthermore, pixel IC 50 provided in adjacent display areas 23 are connected in series by wiring 19 provided in the non-display area 24. In other words, the non-display area 24 of the substrate 21 does not have elements such as light-emitting elements 3, and only wiring 19 connecting the display areas 23 is provided. The wiring 19 includes, for example, a power potential supply wiring 17 and a reference potential supply wiring 18. The power potential supply wiring 17 is for supplying power potential to the multiple pixel IC 50. The reference potential is, for example, the ground potential.

[0033] The power supply potential supply wiring 17 (power line) and the reference potential supply wiring 18 (reference potential line) connecting multiple adjacent pixel ICs 50 are wavy. Specifically, the power supply potential supply wiring 17 and the reference potential supply wiring 18 each extend in a wavy shape along the second direction Dy. Furthermore, the power supply potential supply wiring 17 and the reference potential supply wiring 18 are arranged adjacent to each other in the first direction Dx. In this disclosure, "wavy" refers to a shape that changes direction and meanders as it progresses in a predetermined direction. Wavy includes zigzag shapes. As a result, even when the substrate 21 is deformed, such as when the substrate 21 is expanded or contracted along the second direction Dy, or when the substrate 21 is bent along a curved support member, stress concentration in the wiring 19 can be suppressed. Therefore, in this embodiment, disconnection of the wiring 19 can be suppressed.

[0034] In Figure 3, for the sake of clarity, the wiring 19 is shown to include the power potential supply wiring 17 and the reference potential supply wiring 18. However, the wiring 19 also includes the clock signal supply wiring 12 and the image data supply wiring 13 (see Figure 4). In other words, it may be configured so that four wirings connecting adjacent pixel ICs 50 are arranged in parallel and in a wave-like pattern.

[0035] Of the multiple pixel ICs 50 in a set of pixel ICs 50S, the first-stage pixel IC 50 is connected to the driver IC 11. Each pixel IC 50 controls a predetermined current to flow through each light-emitting element 3 based on control signals (clock signal CK and image data DT) from the driver IC 11, causing the light-emitting elements 3 to emit light.

[0036] Figure 3 shows a configuration in which one pixel IC 50 is connected to one pixel PX, but the configuration is not limited to this, and one pixel IC 50 may be connected to multiple pixel PXs (four or more light-emitting elements 3). Also, the configuration is not limited to multiple light-emitting elements 3 overlapping the pixel IC 50 in one display area 23, and multiple light-emitting elements 3 and the pixel IC 50 may be arranged adjacent to each other in a plan view.

[0037] Figure 4 is a circuit diagram showing a driver IC, multiple pixel ICs, and multiple light-emitting elements. As shown in Figure 4, the multiple pixel ICs 50 include a first pixel IC 50-1, a second pixel IC 50-2, and a third pixel IC 50-3 connected in series. The first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 are each provided corresponding to the display area 23.

[0038] In Figure 4, for the sake of clarity, a 3x2 pixel IC 50 (display area 23) is shown among the multiple pixel ICs 50 (display area 23). Furthermore, in the following explanation, if it is not necessary to distinguish between the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3, they will simply be referred to as pixel IC 50. Similarly, if it is not necessary to distinguish between the clock signal supply lines 12-1, 12-2, 12-3, and 12-4, they will simply be referred to as clock signal supply line 12. Furthermore, if it is not necessary to distinguish between the image data supply lines 13-1, 13-2, 13-3, and 13-4, they will simply be referred to as image data supply line 13.

[0039] Each of the multiple pixel ICs 50 has a clock signal input terminal 51, an image data input terminal 52, a clock signal output terminal 53, and an image data output terminal 54. A clock signal CK is input to the clock signal input terminal 51. Image data DT is input to the image data input terminal 52. A clock signal output terminal 53 outputs a clock signal CK. An image data output terminal 54 outputs image data DT.

[0040] In the second direction Dy, for multiple adjacent pixel ICs 50, the clock signal output terminal 53 and the clock signal input terminal 51 are connected, and the image data output terminal 54 and the image data input terminal 52 are connected.

[0041] More specifically, the clock signal input terminal 51 of the first pixel IC50-1 is connected to the driver IC11 via the clock signal supply wiring 12-1. Also, the image data input terminal 52 of the first pixel IC50-1 is connected to the driver IC11 via the image data supply wiring 13-1. The first pixel IC50-1 corresponds to the pixel IC50 of the first stage described above. Also, the plurality of clock signal supply wirings 12-1, 12-2, 12-3, 12-4 are provided independently between two pixel ICs 50 adjacent in the second direction Dy. Similarly, the plurality of image data supply wirings 13-1, 13-2, 13-3, 13-4 are provided independently between two pixel ICs 50 adjacent in the second direction Dy.

[0042] The clock signal output terminal 53 of the first pixel IC50-1 is connected to the clock signal input terminal 51 of the second pixel IC50-2 via the clock signal supply wiring 12-2. The image data output terminal 54 of the first pixel IC50-1 is connected to the image data input terminal 52 of the second pixel IC50-2 via the image data supply wiring 13-2.

[0043] The clock signal output terminal 53 of the second pixel IC50-2 is connected to the clock signal input terminal 51 of the third pixel IC50-3 via the clock signal supply wiring 12-3. The image data output terminal 54 of the second pixel IC50-2 is connected to the image data input terminal 52 of the third pixel IC50-3 via the image data supply wiring 13-3.

[0044] In other words, the plurality of clock signal supply wirings 12 are provided between two pixel ICs 50 adjacent in the second direction Dy and are provided separately for each pixel IC50. Similarly, the plurality of image data supply wirings 13 are provided between two pixel ICs 50 adjacent in the second direction Dy and are provided separately for each pixel IC50. Thereby, the first pixel IC50-1, the second pixel IC50-2, and the third pixel IC50-3 arranged in the second direction Dy are connected in series.

[0045] Referring to FIGS. 3 and 4, on one substrate 21, the clock signal output terminal 53 of a pixel IC 50 (for example, the first pixel IC 50-1) provided in one display area 23 adjacent to the non-display area 24 across the non-display area 24 is connected to the clock signal input terminal 51 of a pixel IC 50 (for example, the second pixel IC 50-2) provided in the other display area 23 through a wiring 19 (for example, the clock signal supply wiring 12-2) provided in the non-display area 24.

[0046] With such a configuration, the clock signal CK output from the driver IC 11 is sequentially transmitted in series (serially) to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 through the clock signal supply wiring 12. Also, the image data DT output from the driver IC 11 is sequentially transmitted in series (serially) to the first pixel IC 50-1, the second pixel IC 50-2, and the third pixel IC 50-3 through the image data supply wiring 13.

[0047] Thereby, the display device 1 of the present embodiment can increase the bandwidth (frequency) of the transmitted clock signal CK and image data DT compared to the case where a plurality of pixel ICs 50 are connected in parallel to the common clock signal supply wiring 12 and the common image data supply wiring 13. In other words, the display device 1 can suppress the voltage fluctuation and delay of the clock signal CK and the image data DT due to the wiring resistance of the clock signal supply wiring 12 and the image data supply wiring 13. Thereby, the phase relationship between the clock signal CK and the image data DT can be maintained.

[0048] Therefore, the display device 1 of the present embodiment can achieve good display characteristics even when the number of serially connected display areas 23 is increased. For example, the display device 1 can change the length (the number of pixel ICs 50) in the second direction Dy of a set of pixel ICs 50S, or change the number of a set of pixel ICs 50S arranged in the first direction Dx, and can achieve good display characteristics even when the degree of freedom of the shape and area of the display surface is increased.

[0049] In addition, clock signal supply wiring 12 and image data supply wiring 13 are not provided between adjacent pairs of pixel ICs 50S in the first direction Dx, and therefore no transmission or reception of clock signals CK and image data DT takes place between them. The driver IC 11 outputs the clock signals CK and image data DT in synchronization with multiple pairs of pixel ICs 50S arranged in the first direction Dx.

[0050] Each of the multiple pixel ICs 50 further has a power terminal 55, a reference potential terminal 56, and connection terminals 57, 58, and 59 (see Figure 5). The power terminal 55 is connected to the driver IC 11 via a power potential supply wiring 17. As a result, the driver IC 11 supplies power potential to the multiple pixel ICs 50 through the power terminal 55 and the power potential supply wiring 17. The power potential supply wiring 17 is also connected to the anodes of the light-emitting elements 3 (3R, 3G, 3B). The driver IC 11 supplies power potential to the anodes of the light-emitting elements 3 (3R, 3G, 3B) through the power potential supply wiring 17.

[0051] Multiple pixel ICs 50 and multiple light-emitting elements 3 are connected in parallel to the power supply wiring 17. In other words, the power supply wiring 17 is provided in common to multiple display areas 23 (pixel ICs 50 and multiple light-emitting elements 3) which are arranged in the second direction Dy.

[0052] The reference potential terminal 56 is connected to the driver IC 11 via the reference potential supply wiring 18. As a result, the driver IC 11 supplies a reference potential GND to multiple pixel ICs 50 through the reference potential terminal 56 and the reference potential supply wiring 18. The reference potential GND is, for example, the ground potential. However, it is not limited to this, and the reference potential GND may be a predetermined fixed potential different from the ground potential.

[0053] Multiple pixel ICs 50 are connected in parallel to the reference potential supply wiring 18. In other words, the reference potential supply wiring 18 is provided in common to multiple display areas 23 (pixel ICs 50 and multiple light-emitting elements 3) which are arranged in the second direction Dy.

[0054] The connection terminals 57, 58, and 59 are connected to the cathodes of the light-emitting elements 3R, 3G, and 3B, respectively. The cathodes of the light-emitting elements 3R, 3G, and 3B are connected to the reference potential GND via the drive transistor inside the light-emitting element drive circuit 68 (see Figure 5) of the pixel IC 50, as a result of the operation of the light-emitting element drive circuit 68. As a result, the light-emitting elements 3R, 3G, and 3B are driven in a forward bias and emit light.

[0055] Note that Figures 3 and 4 show an example where one pixel IC 50 is connected to one pixel PX (three light-emitting elements 3) for clarity. However, two or more pixel PXs, i.e., six or more light-emitting elements 3, may be connected to one pixel IC 50, and in this case, the number of connection terminals can be changed according to the number of light-emitting elements 3. One pixel IC 50 may be provided with six or more connection terminals.

[0056] Furthermore, although not shown in Figure 4, in a pair of pixel ICs 50S-1 and 50S-2 that are adjacent to each other and connected in series on the outer edge of the substrate 21, the arrangement of the pair of pixel ICs 50S-2 connected to the driver IC 11 is the same as in the example shown in Figure 4. However, the arrangement of the pair of pixel ICs 50S-1 that are connected in a folded manner is the same as the configuration of the multiple pixel ICs 50 shown in Figure 4 rotated by 180°.

[0057] Figure 5 is a block diagram showing an example of the configuration of a pixel IC. As shown in Figure 5, the pixel IC 50 includes buffer circuits 61 and 62, flip-flop circuits 63 and 64, control circuit 65, PWM control circuit 66, memory circuit 67, and light-emitting element driving circuit 68 (display element driving circuit).

[0058] The buffer circuit 61 is connected between the clock signal input terminal 51 and the clock signal output terminal 53. As a result, the clock signal CK input to the clock signal input terminal 51 of the pixel IC 50 is output from the clock signal output terminal 53 via the buffer circuit 61. The buffer circuit 61 corrects and outputs voltage fluctuations of the clock signal CK due to resistance in the clock signal supply wiring 12 and wiring within the pixel IC 50. As a result, even in a configuration where multiple pixel ICs 50 are connected in series, the clock signal CK is transmitted reliably to the final stage pixel IC 50 (the nth pixel IC 50-n).

[0059] The flip-flop circuit 63 is connected between the clock signal input terminal 51 and the image data input terminal 52 and the control circuit 65. The buffer circuit 62 and the flip-flop circuit 64 are connected in series between the control circuit 65 and the image data output terminal 54.

[0060] The flip-flop circuit 63 receives the clock signal CK from the clock signal input terminal 51 and the image data DT from the image data input terminal 52, and outputs the image data DT to the control circuit 65 at a timing corresponding to the clock signal CK.

[0061] The control circuit 65 controls the lighting of the light-emitting element 3 connected to the pixel IC 50 based on the image data DT input through the image data input terminal 52 and the flip-flop circuit 63. The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the buffer circuit 62.

[0062] The buffer circuit 62 corrects and outputs the voltage fluctuations and delay time of the image data DT caused by resistance in the image data supply wiring 13 and wiring within the pixel IC 50. The delay time correction is adjusted so that the delay time of the data after predetermined processing of the image data DT does not become shorter than the delay time generated by the buffer circuit 61 provided for the clock signal CK.

[0063] The flip-flop circuit 64 receives a clock signal CK supplied from the clock signal input terminal 51 through the buffer circuit 61, and image data DT from the image data input terminal 52 via the flip-flop circuit 63, control circuit 65, and buffer circuit 62. The flip-flop circuit 64 outputs the image data DT to the image data output terminal 54 at a timing corresponding to the clock signal CK.

[0064] The control circuit 65 performs predetermined processing on the input image data DT and outputs it to the storage circuit 67, and controls the PWM control circuit 66 and the light-emitting element drive circuit 68 based on the input image data DT. The storage circuit 67 stores the image data DT input from the control circuit 65. The PWM control circuit 66 determines the illumination period of the multiple light-emitting elements 3 corresponding to the grayscale and generates a PWM control signal based on the image data DT acquired from the control circuit 65.

[0065] The light-emitting element driving circuit 68 drives a plurality of light-emitting elements 3 connected to the connection terminals 57, 58, and 59 of the pixel IC 50 based on a PWM control signal obtained from the PWM control circuit 66. Specifically, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch the connection state between the cathode of the light-emitting element 3 and the reference potential terminal 56. For example, the light-emitting element driving circuit 68 may be configured to include a plurality of switch elements that switch between connection (on) and disconnection (off) between the cathode of the light-emitting element 3 and the reference potential GND based on a PWM control signal. Current flows to the light-emitting element 3 and it lights up during a predetermined period when the cathode of the light-emitting element 3 is connected to the reference potential GND. Also, the light-emitting element 3 turns off during the period when the cathode of the light-emitting element 3 is not connected to the reference potential GND. By making the lighting period and the off period different based on the PWM control signal, the light-emitting element 3 can express gradations according to the image data DT. As described above, the multiple light-emitting elements 3 are driven by PWM (Pulse Width Modulation) based on the image data DT acquired by the control circuit 65.

[0066] Figure 6 is a timing chart showing the clock signal and image data in a pixel IC. Figure 6 shows the clock signal CK(IN) input to the clock signal input terminal 51, the image data DT(IN) input to the image data input terminal 52, the clock signal CK(OUT) output from the clock signal output terminal 53, and the image data DT(OUT) output from the image data output terminal 54.

[0067] As shown in Figure 6, the clock signal CK(OUT) output from the clock signal output terminal 53 is slightly delayed relative to the clock signal CK(IN) due to the operation of the buffer circuit 61. For example, the delay of the clock signal CK(OUT) is the difference between time t2 and time t1 shown in Figure 6. This delay is very small and does not pose any practical problems.

[0068] The flip-flop circuits 63 and 64 output the image data DT at the timing of the rising (or falling) edge of the clock signal CK. In other words, the image data DT is output by each of the flip-flop circuits 63 and 64 with a 1-bit delay relative to the clock signal CK.

[0069] Specifically, as shown in Figure 6, the image data DT includes multiple image data DT(a), DT(b), DT(c), and DT(d). Note that image data DT(a), DT(b), DT(c), and DT(d) are shown schematically for clarity.

[0070] Focusing on image data DT(a) within the image data DT, image data DT(a) is input to the image data input terminal 52 after a predetermined time has elapsed from time t1, when the clock signal CK(IN) is input to the clock signal input terminal 51. In the first stage flip-flop circuit 63, image data DT(a) is output at the rising edge timing of the clock signal CK(IN) (time t3). In other words, image data DT(a) is delayed by 1 bit relative to the clock signal CK(IN).

[0071] In the second stage flip-flop circuit 64, the image data DT(a) is output at the rising edge timing (time t6) of the clock signal CK(OUT). As a result, when compared with the timing relationship between the input clock signal CK(IN) and the image data DT(IN), the image data DT(OUT) is output with a total delay of 2 bits relative to the clock signal CK(OUT).

[0072] As described above, in the pixel IC 50, buffer circuits 61, 62 and flip-flop circuits 63, 64 cause a predetermined bit (for example, 2 bits) delay between the image data DT(OUT) output from the image data output terminal 54 and the clock signal CK(OUT) output from the clock signal output terminal 53. However, the timing relationship (delay time) between the clock signal CK(OUT) and the image data DT(OUT) is substantially the same for each of the multiple pixel ICs 50. As a result, the display device 1 can display images well even in a configuration that does not synchronize horizontally (for example, without gate drive signals in an active matrix system).

[0073] Note that the configuration and operation of the pixel IC 50 shown in Figures 4 to 6 are merely examples and can be modified as appropriate.

[0074] (First Modification of the First Embodiment) Figure 7 is a schematic plan view showing an example of the configuration of a set of pixel ICs in a display device according to the first modification of the first embodiment. In the following description, the same reference numerals are used for components that are the same as those described in the above-described embodiments, and redundant descriptions are omitted.

[0075] As shown in Figure 7, in the display device 1A according to the first modified example, in a set of pixel ICs 50S, multiple pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to one pixel IC 50. That is, the display area 23 includes one pixel IC 50 and multiple pixel PXs (light-emitting elements 3R, 3G, 3B) connected to the pixel IC 50. The multiple light-emitting elements 3 connected to one pixel IC 50 are arranged in a matrix.

[0076] In the example shown in Figure 7, the pixels PX connected to one pixel IC 50 are arranged in a 4x4 grid. If one pixel PX has three light-emitting elements 3R, 3G, and 3B, then 48 light-emitting elements 3 are connected to one pixel IC 50.

[0077] In this modified configuration, multiple pixel PXs (light-emitting elements 3R, 3G, 3B) are connected to a single pixel IC, allowing for higher resolution display compared to a configuration where one pixel PX is connected to one pixel IC 50. Furthermore, in this modified configuration, even if the number of pixel PXs increases, the number of pixel ICs 50 provided on the substrate 21A can be suppressed, thereby reducing the cost of the display device 1A. Note that the number and arrangement of pixel PXs (light-emitting elements 3) connected to a single pixel IC 50 are merely examples and can be changed as appropriate.

[0078] Furthermore, in Figure 7, only one pair of pixel ICs 50S is shown for clarity. However, the diagram is not limited to this, and multiple pairs of pixel ICs 50S may be provided on the substrate 21A. Also, although the substrate 21A is rectangular, it is not limited to this, and may have a curved portion 21a, similar to the first embodiment.

[0079] (Second Embodiment) Figure 8 is a schematic diagram showing an example of equipment for a four-wheeled vehicle including the display device according to the second embodiment. Figure 9 is a schematic plan view showing the display device according to the second embodiment.

[0080] Figure 8 shows examples of equipment for a four-wheeled vehicle, including a windshield FG, side glass SG, A-pillar AP between the windshield FG and side glass SG, steering wheel HN, rearview mirror BM, dashboard DB, etc. The display device 1B according to the second embodiment is located on the interior side of the A-pillar AP.

[0081] As shown in Figure 9, the display device 1B according to the second embodiment has an irregular shape in which the four sides S1, S2, S3, and S4 of the substrate 21B are non-parallel to each other. Specifically, the distance between adjacent sides S3 and S4 in the first direction Dx decreases as the distance from the driver IC 11 in the second direction Dy increases.

[0082] In a single pair of pixel ICs 50S, multiple pixel ICs 50 are arranged along the second direction Dy. Multiple pairs of pixel ICs 50S are arranged along the first direction Dx. The number of pixel ICs 50 in a pair of pixel ICs 50S varies depending on the external shape of the substrate 21B. For example, side S4 of the substrate 21B (the left side in Figure 9) extends in a direction parallel to the arrangement direction of the pixel ICs 50 in a pair of pixel ICs 50S. Side S3 of the substrate 21B (the right side in Figure 9) extends in a direction intersecting the arrangement direction of the pixel ICs 50 in a pair of pixel ICs 50S. The number of pixel ICs 50 in a pair of pixel ICs 50S decreases as it approaches side S3 of the substrate 21B (the right side in Figure 9).

[0083] Furthermore, although not shown in the figures, similar to the first embodiment, a pair of adjacent pixels IC50S-n and a pair of pixels IC50S-(n-1) on the outer edge side of the first direction Dx of the substrate 21B may be connected in series in a folded manner.

[0084] The display device 1B according to the second embodiment can improve the degree of freedom in shape by varying the number of pixels IC50 in a set of pixel IC50S, and can therefore be applied to various equipment with diverse shapes, such as the A-pillar AP of a four-wheeled vehicle. Furthermore, the display device 1B according to the second embodiment is not limited to the A-pillar AP, but can also be applied to parts of the windshield FG, side glass SG, rearview mirror BM, or dashboard DB.

[0085] In Figure 9, multiple pixel ICs 50 on the substrate 21B are shown for clarity, but as in the first embodiment (see Figure 3), each of the display areas 23 on the substrate 21B is provided with a pixel IC 50 and multiple light-emitting elements 3. Furthermore, the display device 1B of the second embodiment can also be combined with the configuration of the first modified example of the first embodiment (see Figure 7).

[0086] (Second Modification of the Second Embodiment) Figure 10 is a schematic plan view showing a display device according to a second modification of the second embodiment. The display device 1C according to the second modification of the second embodiment has a different external shape of the substrate 21C compared to the second embodiment described above.

[0087] In the second modified example, both sides S3 (right side in Figure 10) and S4 (left side in Figure 10) of the substrate 21C extend in a direction intersecting the arrangement direction of the pixel ICs 50 of a pair of pixel ICs 50S. The number of pixel ICs 50 of a pair of pixel ICs 50S decreases as it approaches side S3 (right side in Figure 10) of the substrate 21C, compared to the center side in the first direction Dx. Also, the number of pixel ICs 50 of a pair of pixel ICs 50S decreases as it approaches side S4 (left side in Figure 10) of the substrate 21C, compared to the center side in the first direction Dx.

[0088] The display device 1C according to the second modified example can be applied to A-pillar APs having various shapes by varying the number of pixels IC 50 in a set of pixel ICs 50S. Furthermore, the display device 1C according to the second modified example can be combined with the configuration of the first embodiment (see Figure 3) or the first modified example of the first embodiment (see Figure 7), similar to the second embodiment described above.

[0089] (Third Embodiment) Figure 11 is a schematic perspective view showing a display device according to the third embodiment. Figure 12 is a plan view showing a plurality of substrates of the display device according to the third embodiment in a schematic unfolded state. Figure 13 is a plan view showing a plurality of pixel ICs of the display device according to the third embodiment.

[0090] As shown in Figures 11 and 12, the display device 1D according to the third embodiment has a plurality of substrates 21D. Each of the plurality of substrates 21D is formed based on a boat-shaped polyconic projection and is arranged on the surface of a spherical support member 29. As shown in Figure 12, when each of the plurality of substrates 21D is unfolded in a planar shape, it has a boat shape or boat bottom shape with a longitudinal direction along the second direction Dy.

[0091] As shown in Figure 13, the pixels IC 50 in a pair of pixel ICs 50S are arranged along the second direction Dy. Multiple pairs of pixel ICs 50S are arranged along the first direction Dx. The number of pixels IC 50 in a pair of pixel ICs 50S varies depending on the external shape of the substrate 21D. The number of pixels IC 50 in a pair of pixel ICs 50S decreases as you move from the center of the first direction Dx on the substrate 21D towards the outer edge of the first direction Dx. Each of the multiple pairs of pixel ICs 50S is connected to a driver IC 11 located in the second direction Dy.

[0092] With this configuration, the display device 1D according to the third embodiment has a spherical display surface. In addition, although Figure 13 shows multiple pixel ICs 50 on the substrate 21D for clarity, each of the display areas 23 of the substrate 21D is provided with a pixel IC 50 and multiple light-emitting elements 3. That is, the display device 1D according to the third embodiment can also be combined with the configuration of the first embodiment (see Figure 3) or the first modified example of the first embodiment (see Figure 7). In each of the modified examples described below, the configuration can also be combined with the configuration of the first embodiment (see Figure 3) or the first modified example of the first embodiment (see Figure 7).

[0093] (Third Modification of the Third Embodiment) Figure 14 is a schematic plan view showing a plurality of pixel ICs of a display device according to a third modification of the third embodiment. In the third embodiment described above, a configuration was described in which each of a plurality of pairs of pixel ICs 50S is connected to the driver IC 11, but the invention is not limited to this.

[0094] As shown in Figure 14, in the display device 1E according to the third modification of the third embodiment, a pair of adjacent pixel ICs 50S-1, 50S-2, and 50S-3 on the outer edge side of the first direction Dx of the substrate 21D are connected in series in a meander configuration. A pixel IC 50 located on one end side of the second direction Dy of a pair of pixel ICs 50S-1 and a pixel IC 50 located on one end side of the second direction Dy of a pair of pixel ICs 50S-2 are connected via a connection wire 19a. Furthermore, a pixel IC 50 located on the other end side of the second direction Dy of a pair of pixel ICs 50S-2 and a pixel IC 50 located on the other end side of the second direction Dy of a pair of pixel ICs 50S-3 are connected via a connection wire 19b.

[0095] In the first direction Dx, three pairs of pixel ICs 50S located on the opposite side of one pair of pixel ICs 50S-1, 50S-2, and 50S-3 are directly connected in a meander manner, similar to the pair of pixel ICs 50S-1, 50S-2, and 50S-3. Additionally, three pairs of pixel ICs 50S located towards the center of the substrate 21D in the first direction Dx are each connected to the driver IC 11.

[0096] As described above, in the display device 1E according to the third modified example, the connection configuration between pairs of pixel ICs 50S can be appropriately varied depending on the number of pixel ICs 50 that each pair of pixel ICs 50S has.

[0097] (Fourth Modification of the Third Embodiment) Figure 15 is a schematic plan view showing a plurality of pixel ICs in a display device according to the fourth modification of the third embodiment. As shown in Figure 15, in the display device 1F according to the fourth modification of the third embodiment, all pairs of pixel ICs 50S are connected in a meander manner. That is, adjacent pairs of pixel ICs 50S are electrically connected by a connection wire 19a or a connection wire 19b. The connection wires 19a and 19b are arranged alternately along the first direction Dx. In this embodiment, a pair of pixel ICs 50S located on the outer edge side (right side in Figure 15) of the substrate 21D in the first direction Dx is connected to the driver IC 11.

[0098] In this modified example, the number of terminals of the driver IC 11 can be reduced compared to the third embodiment and the third modified example described above.

[0099] (Fifth Modification of the Third Embodiment) Figure 16 is a schematic plan view showing a plurality of pixel ICs of a display device according to the fifth modification of the third embodiment. In the first to third embodiments described above, a configuration in which a plurality of pixel ICs 50 (display area 23) are arranged in a matrix on substrates 21, 21B, 21C, and 21D has been described, but the invention is not limited thereto.

[0100] As shown in Figure 16, in the display device 1G according to the fifth modification of the third embodiment, the plurality of pixel ICs 50 are arranged in a staggered pattern on the substrate 21D. In the fifth modification, the inclination direction Da is defined as one direction in a plane parallel to the display surface of the substrate 21 that intersects the first direction Dx and the second direction Dy.

[0101] In the fifth modified example, a set of pixel ICs 50S has a plurality of pixel ICs 50 arranged along the inclination direction Da. In one set of pixel ICs 50S, the plurality of pixel ICs 50 arranged along the inclination direction Da are connected in series. Furthermore, a set of three or four adjacent rows of pixel ICs 50S are connected in a meander configuration.

[0102] In the fifth modified example, the display device 1G allows for greater flexibility in the arrangement of the multiple pixel ICs 50 and the connection configuration of the multiple pixel ICs 50.

[0103] In the fifth modified example, the configuration is not limited to one in which adjacent pairs of pixel ICs 50S are connected in a meander configuration. For example, each of multiple pairs of pixel ICs 50S may be connected to a driver IC. Alternatively, all pairs of pixel ICs 50S may be connected in a meander configuration.

[0104] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each embodiment and each modification described above.

[0105] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G Display device 3, 3B, 3G, 3R Light-emitting element 11 Driver IC 12, 12-1, 12-2, 12-3, 12-4 Clock signal supply wiring 13, 13-1, 13-2, 13-3, 13-4 Image data supply wiring 17 Power supply potential supply wiring 18 Reference potential supply wiring 19 Wiring 21, 21A, 21B, 21C, 21D Substrate 23 Display area 24 Non-display area 29 Support member 50 Pixel IC 50S, 50S-1, 50S-2, 50S-3 A pair of pixel ICs 51 Clock signal input terminal 52 Image data input terminal 53 Clock signal output terminal 54 Image data output terminal 57, 58, 59 Connection terminals 101 Host

Claims

1. The device comprises a substrate, a plurality of display elements provided on the substrate, a plurality of pixel ICs provided on the substrate and connected to the plurality of display elements for driving the plurality of display elements, a power line for supplying power to the plurality of pixel ICs, and a reference potential line for supplying a reference potential to the plurality of pixel ICs, wherein the plurality of pixel ICs are connected in series along a predetermined one direction, each of the plurality of pixel ICs has a clock signal input terminal into which a clock signal is input, an image data input terminal into which image data is input, a clock signal output terminal for outputting the clock signal, an image data output terminal for outputting the image data, and a connection terminal connected to at least one of the display elements, wherein in adjacent plurality of pixel ICs, the clock signal output terminal and the clock signal input terminal are connected, and the image data output terminal and the image data input terminal are connected, and when the plurality of pixel ICs arranged along the one direction are considered as a pair of pixel ICs, the plurality of the pair of pixel ICs are arranged in a direction intersecting the one direction. A display device in which the number of pixel ICs in a pair of pixel ICs located on the outer edge side of the substrate in a direction intersecting the aforementioned one direction is less than the number of pixel ICs in a pair of pixel ICs located on the central side of the substrate in a direction intersecting the aforementioned one direction.

2. The display device according to claim 1, wherein in a pair of adjacent pixel ICs, the pixel ICs located at the ends in one direction are electrically connected to each other via connecting wiring.

3. The display device according to claim 1, wherein when at least one of the adjacent pairs of pixel ICs has fewer pixel ICs than a predetermined number, the pixel ICs located at the one-way ends of the adjacent pairs of pixel ICs are electrically connected via connecting wiring.

4. The display device according to claim 1, wherein the power lines and reference potential lines connecting adjacent pixel ICs in the set of pixel ICs are wavy.

5. The display device according to claim 1, wherein the substrate on which the plurality of display elements are provided is arranged on the interior side of the pillar of an automobile.

6. The display device according to claim 1, which has a plurality of substrates, each of which is formed based on a boat-shaped polyconic projection and arranged on the surface of a spherical support member.

7. The display device according to claim 1, wherein the display element is an inorganic LED.

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