Display device, manufacturing method therefor, and electronic device

Abstract

A display device, a manufacturing method therefor, and an electronic device are provided. According to an embodiment, the display device may comprise: a pixel electrode layer disposed on a substrate; a light-emitting element disposed on the pixel electrode layer and including a contact electrode; an organic layer having an island pattern shape and covering a portion of the side surface of the light-emitting element and a portion of the pixel electrode layer exposed by the light-emitting element; a first reflective layer disposed on the side surface of the organic layer; and a protective layer for protecting the light-emitting element, the organic layer, and the first reflective layer.

Description

Display device, method of manufacturing the same, and electronic device

[0001] The present invention relates to a display device, a method of manufacturing the same, and an electronic device.

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. For example, display devices may be flat panel displays such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays.

[0003] The light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode (OLED) as a light-emitting element, and a micro light-emitting display device comprising a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the micro light-emitting diode element is made of inorganic material, it has the advantage of having a long lifespan with fewer degradation issues compared to the organic light-emitting diode (OLED).

[0004] The problem that the present invention aims to solve is to provide a display device capable of increasing light extraction efficiency and reducing power consumption, and a method for manufacturing the same.

[0005] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0006] A display device according to one embodiment for solving the above problem may include a pixel electrode layer disposed on a substrate, a light-emitting element disposed on the pixel electrode layer and including a contact electrode, an organic layer covering a part of the side of the light-emitting element and a part of the pixel electrode layer exposed by the light-emitting element in an island pattern shape, a first reflective layer disposed on the side of the organic layer, and a protective layer protecting the light-emitting element, the organic layer, and the first reflective layer.

[0007] The above protective layer may include a first protective layer covering the upper surface and side of a light-emitting element and a pixel electrode layer where the light-emitting element is not placed, a second protective layer placed on the upper surface of the organic layer and the upper surface and side of the light-emitting element, and a third protective layer placed on the second protective layer, the light-emitting element, the organic layer, and a substrate where the organic layer is not placed.

[0008] The second protective layer has a tip protruding outward from the upper surface of the organic layer, and the first reflective layer may be disposed below the tip.

[0009] The above organic layer may have a cross-section that is dome-shaped, rectangular, or trapezoidal.

[0010] The above organic layer may have a shape that gradually narrows as it goes upward.

[0011] The side of the organic layer and the first reflective layer may have an inclination angle in the range of 55° to 85°.

[0012] The light-emitting element comprises: a conductive layer disposed on the lower surface of the first semiconductor layer; a first semiconductor layer disposed on the conductive layer and including a semiconductor material layer doped with a first conductive type dopant; an active layer disposed on the first semiconductor layer; and

[0013] The second semiconductor layer is disposed on the active layer and includes a semiconductor material layer doped with a second conductive type dopant, and the organic layer may surround the sides of the conductive layer, the first semiconductor layer, and the active layer.

[0014] The light-emitting element may further include a third semiconductor layer, which is an undoped semiconductor layer disposed on the second semiconductor layer.

[0015] The light-emitting element may further include a light extraction pattern having a concave pattern on its upper surface.

[0016] The above contact electrode comprises a first contact electrode disposed on the protective film and connected to the conductive layer exposed without being covered by the protective film, and a second contact electrode disposed on the protective film and disposed in a hole penetrating the conductive layer and a part of the semiconductor stack, and the pixel electrode layer comprises a pixel electrode and a common electrode disposed spaced apart from each other, the first contact electrode may be connected to the pixel electrode, and the second contact electrode may be connected to the common electrode.

[0017] The pixel electrode layer includes a pixel electrode, and the contact electrode is disposed on the pixel electrode and can be connected to the conductive layer exposed without being covered by the protective film.

[0018] The above display device further includes a common electrode disposed on top of the light-emitting element and the organic layer, and the protective layer includes an opening that exposes at least a portion of the upper part of the light-emitting element, and through the opening, the upper part of the light-emitting element can be connected to the common electrode.

[0019] The above display device may further include a partition wall positioned to surround the light-emitting element and a reflective layer positioned on the side of the partition wall and on the bottom of the space formed by the partition wall.

[0020] The above display device may further include a wavelength conversion layer disposed in the space formed by the partition wall.

[0021] The above display device may further include a capping layer, an overcoat layer, and a color filter layer sequentially disposed on the wavelength conversion layer and the partition wall.

[0022] A method for manufacturing a display device according to another embodiment for solving the above problem may include the steps of: forming a light-emitting element comprising a plurality of semiconductor layers, a conductive layer, a protective layer, and a contact electrode; transferring the light-emitting element onto a circuit board; forming a first protective layer by applying a full surface coating on the side of the light-emitting element and on a circuit board where the light-emitting element is not placed; forming an organic material layer covering the side of the light-emitting element, forming a protective material layer to cover the light-emitting element and the organic material layer, and patterning the protective material layer and the organic material layer to form an organic layer and a second protective layer; and forming a first reflective layer disposed on the side of the second organic layer by depositing a reflective material layer on the full surface to cover the light-emitting element and the organic layer and dry etching.

[0023] In the step of forming the organic layer and the second protective layer, by dry etching using a hard mask on the protective material layer, the organic layer is formed in an island pattern, and the second protective layer having a tip protruding outward from the upper surface of the organic layer can be formed.

[0024] The first reflective layer can be placed on the lower part of the protruding tip.

[0025] The step of forming the light-emitting element may include: forming a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer on a semiconductor substrate; etching the second semiconductor material layer, the active material layer, the first semiconductor material layer, and the conductive material layer to form light-emitting elements each comprising the second semiconductor layer, the active layer, the first semiconductor layer, and the conductive layer; forming a hole penetrating the conductive layer, the first semiconductor layer, and the active layer in each of the light-emitting elements; forming a protective material layer surrounding each of the light-emitting elements and patterning the protective material layer to form a protective film; and forming a mask pattern and forming a contact electrode on the protective film.

[0026] The above method for manufacturing a display device may further include the steps of forming a partition defining a light-emitting region, forming a wavelength conversion layer in the space formed by the partition, and forming an overcoat layer and a color filter layer sequentially disposed on the partition and the wavelength conversion layer.

[0027] In another embodiment for solving the above problem, an electronic device that provides an image, wherein the electronic device includes a display device that displays an image, and the display device may include a substrate, a pixel electrode layer disposed on the substrate, a light-emitting element disposed on the pixel electrode layer and including a contact electrode, an organic layer covering a portion of the side of the light-emitting element and a portion of the pixel electrode layer exposed by the light-emitting element in an island pattern shape, a first reflective layer disposed on the side of the organic layer, and a protective layer that protects the light-emitting element, the organic layer, and the first reflective layer.

[0028] In one embodiment, the electronic device may further include a reflective member that reflects an image displayed on the display device and a display device housing capable of housing the display device and the reflective member.

[0029] In one embodiment, the electronic device may further include a lens that provides an image reflected from the reflective member to either the user's left eye or right eye.

[0030] In one embodiment, the display device may be a glasses-type display device. Specific details of other embodiments are included in the detailed description and drawings.

[0031] According to the display device and the method of manufacturing the same according to the embodiments, the amount of light emitted and scattered in the direction of the lower side of the light-emitting element can be reduced. Accordingly, panel brightness can be increased and power consumption for the same brightness can be reduced.

[0032] Furthermore, by reducing the amount of light scattered downward from the light-emitting elements, the display device can utilize the emitted light more efficiently. This efficiency enables higher panel brightness without increasing power input. As a result, the display device can maintain enhanced brightness levels while consuming less power. These improvements not only enhance the user experience by providing a sharper and brighter screen but also extend the device's battery life.

[0033] Strategically placing the first reflective layer beneath the protruding end of the organic layer plays a crucial role in this light management. The reflective layer redirects light that would otherwise be lost, ensuring that more light is directed toward the display surface. This redirection reduces or minimizes light loss and increases or maximizes the efficiency of the light-emitting elements. As a result, the display device can provide high brightness and vivid colors with low energy consumption, making it environmentally friendly and cost-effective in the long run.

[0034] Furthermore, the use of micro light-emitting diode (LED) devices made of inorganic materials contributes to the overall durability and extended lifespan of display devices. These devices extend the life of displays because they have a lower potential for degradation compared to organic devices. This durability is particularly important for devices subjected to frequent use and exposure to various environmental conditions. The combination of high efficiency, low power consumption, and a long lifespan makes these display devices highly suitable for a wide range of applications, from consumer electronics to industrial displays.

[0035] A manufacturing method according to one embodiment also enables the production of thinner and more flexible display panels. By improving the arrangement of light-emitting elements and reflective layers, the display device can be made smaller without compromising performance. This flexibility opens up new possibilities for innovative device designs, including foldable and rollable displays, which are becoming increasingly popular in the market. This advanced display technology production capability further strengthens the competitiveness of the display device within the industry.

[0036] For example, the display device and the method for manufacturing the same according to the present invention provide improvements in terms of light extraction efficiency, power consumption, durability, and / or design flexibility. These improvements not only enhance the performance and user experience of the display device but also contribute to the development of more sustainable and versatile electronic devices.

[0037] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0038] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0039] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0040] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0041] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0042] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0043] FIG. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I-I' of FIG. 5.

[0044] Figure 7 is a cross-sectional view showing in detail an example of area A of Figure 6.

[0045] Figure 8 is a cross-sectional view showing another example of the A1 region of Figure 6 in detail.

[0046] Figure 9 is a cross-sectional view showing another example of the A1 region of Figure 6 in detail.

[0047] FIG. 10 is a layout diagram showing pixels of a display area according to one embodiment.

[0048] FIG. 11 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I1-I1' of FIG. 10.

[0049] FIG. 12 is a cross-sectional view showing in detail an example of area A2 of FIG. 11.

[0050] FIG. 13 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0051] FIGS. 14 to 26 are exemplary drawings for explaining a method of manufacturing a display device according to one embodiment.

[0052] FIG. 27 is an example drawing showing a smart watch including a display device according to one embodiment.

[0053] FIGS. 28 and FIGS. 29 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0054] FIG. 30 is an example drawing showing a virtual reality device including a display device according to another embodiment.

[0055] FIG. 31 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0056] FIG. 32 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0057] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0058] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0059] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0060] Specific embodiments will be described below with reference to the attached drawings.

[0061] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0062] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IOT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0063] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device (10) has been described with a focus on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, a micro light-emitting diode has been described as a light-emitting element below.

[0064] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0065] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0066] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0067] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of subpixels. For example, each of the pixels may include a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color, but the embodiments of the present specification are not limited thereto.

[0068] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0069] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. As an example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0070] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0071] The power supply circuit (500) can generate multiple panel driving voltages according to the power supply voltage from an external source. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0072] FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0073] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0074] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0075] A display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a minimum unit of subpixel group capable of expressing a white gradation.

[0076] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0077] The first scan drive unit (SDC1) and the second scan drive unit (SDC2) may be placed in a non-display area (NDA). The first scan drive unit (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan drive unit (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but the embodiments of the present specification are not limited thereto.

[0078] Each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to the display driver circuit (250) through scan fan out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) receives a scan control signal from the display driver circuit (250) and can generate scan signals according to the scan control signal and output them to the scan lines.

[0079] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0080] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0081] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0082] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive material such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive material such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0083] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0084] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0085] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL).

[0086] Multiple pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). Multiple scan lines (SL) include multiple write scan lines (GWL), multiple control scan lines, multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0087] Each of the plurality of subpixels (SPX) can be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines, one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of light emission control lines (EL), and one of the plurality of data lines (DL). Each of the plurality of subpixels (SPX) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from the light-emitting element according to the data voltage.

[0088] The non-display area (NDA) includes a first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250).

[0089] Each of the first scan drive unit (SDC1) and the second scan drive unit (SDC2) may include a write scan signal output unit (611), an initial scan signal output unit (612), a bias scan signal output unit (613), and a light emission signal output unit (614). Each of the write scan signal output unit (611), the initial scan signal output unit (612), the bias scan signal output unit (613), and the light emission signal output unit (614) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and output them sequentially to the write scan lines (GWL). The initial scan signal output unit (612) may generate initial scan signals according to the scan timing control signal (SCS) and output them sequentially to the initial scan lines (GIL). The bias scan signal output unit (613) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (EBL). The light emission signal output unit (614) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL). In another embodiment, the first scan driving unit (SDC1) and the second scan driving unit (SDC2) each further include a control scan signal output unit, and the control scan signal output unit can generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines.

[0090] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0091] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0092] The timing control circuit (251) can receive digital video data and timing signals from an external source. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and the data timing control signal (DCS) to the data driving circuit (252).

[0093] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from an external source. For example, the power supply circuit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), and a third driving voltage (VINT) and supply them to the display panel (100).

[0094] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0095] Referring to FIG. 4, a subpixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), a light emission control line (EL), and a data line (DL). For example, the subpixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a control scan line, a bias scan line, a light emission line (EL), and a data line (DL).

[0096] A subpixel (SPX) according to one embodiment includes a driving transistor (DT), switching elements, a capacitor (C1), and a light-emitting element (LE). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0097] The driving transistor (DT) includes a gate electrode, a conductive layer, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the conductive layer and the second electrode according to the data voltage applied to the gate electrode.

[0098] The light-emitting element (LE) can be a micro light-emitting diode.

[0099] The light-emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light-emitting element (LE) is connected to the conductive layer of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to a second power supply line (VSL) to which a second power supply voltage is applied.

[0100] A capacitor (C1) is formed between the second electrode of a driving transistor (DT) and a first power line (VDL) to which a first power supply voltage is applied. The first power supply voltage may be a voltage level higher than the second power supply voltage. One electrode of the capacitor (C1) may be connected to the second electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0101] As shown in FIG. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as P-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0102] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to the initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as P-type MOSFETs, they may be turned on when a scan signal of gate low voltage and a light emission signal are applied to the control scan line, the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the light emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) may be connected to the initialization voltage line (VIL) and the voltage line (VAIL), respectively.

[0103] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as P-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as N-type MOSFETs. The active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as N-type MOSFETs may be formed of an oxide semiconductor.

[0104] In this case, since the first transistor (ST1) and the third transistor (ST3) are formed as N-type MOSFETs, the first transistor (ST1) can be turned on when a write scan signal of gate high voltage is applied, and the third transistor (ST3) can be turned on when an initialization scan signal of gate high voltage is applied. In contrast, since the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as P-type MOSFETs, they can be turned on when a scan signal of gate low voltage and a light emission signal of gate low voltage are applied.

[0105] Alternatively, the fourth transistor (ST4) is formed as an N-type MOSFET, and thus the active layer of each of the fourth transistors (ST4) can be formed as an oxide semiconductor. When the fourth transistor (ST4) is formed as an N-type MOSFET, it can be turned on when a bias scan signal of gate high voltage is applied.

[0106] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as N-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed as an oxide semiconductor.

[0107] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0108] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three subpixels (SPX1, SPX2, SPX3), but the embodiments of the present specification are not limited thereto. For example, in one embodiment, each of the plurality of pixels (PX) of the display area (DA) may include four subpixels.

[0109] Multiple pixels (PX) can be arranged in a matrix form. In each of the multiple pixels (PX), the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0110] In the case where each of the plurality of pixels (PX) includes three subpixels (SPX1, SPX2, SPX3), the first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. Here, the first color light may be light in the blue wavelength band, the second color light may be light in the green wavelength band, and the third color light may be light in the red wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to 750 nm.

[0111] Alternatively, if each of the plurality of pixels (PX) includes four subpixels, the first subpixel may emit light of a first color, the second subpixel and the fourth subpixel may emit light of a second color, and the third subpixel may emit light of a third color. Alternatively, the first subpixel may emit light of a first color, the second subpixel may emit light of a second color, the third subpixel may emit light of a third color, and the fourth subpixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0112] The first subpixel (SPX1) includes a first pixel electrode (PXE1), a first common electrode (CE1), a plurality of light-emitting elements (LE), and a first light-converting layer (QDL1). The second subpixel (SPX2) includes a second pixel electrode (PXE2), a second common electrode (CE2), a plurality of light-emitting elements (LE), and a second light-converting layer (QDL2). The third subpixel (SPX3) includes a third pixel electrode (PXE3), a third common electrode (CE3), a plurality of light-emitting elements (LE), and a light-transmitting layer (TPL).

[0113] Pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3) may be arranged in a second direction (DR2) at each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3). Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape, but the embodiments of the present specification are not limited thereto. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiments of the present specification are not limited thereto.

[0114] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the second common electrode (CE2) may be larger than the area of ​​the first common electrode (CE1). In addition, since the light transmission layer (TPL) transmits the light of the light-emitting element (LE) as is, while the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3), and the area of ​​the first common electrode (CE1) may be larger than the area of ​​the third common electrode (CE3).

[0115] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to the second electrode of the fourth transistor (ST4 in FIG. 4) and the second electrode of the sixth transistor (ST6 in FIG. 4) of the corresponding subpixel.

[0116] The first common electrode (CE1) can be connected to a second power supply line (VSL) to which a second driving voltage (VSS) is applied through a first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power supply line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power supply line (VSL) through a third common connection hole (CT6). Thus, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, CE3). The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as the anode electrode or the first electrode, and the common electrodes (CE1, CE2, CE3) may be referred to as the cathode electrode or the second electrode.

[0117] A plurality of light-emitting elements (LEs) may be disposed on pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3). Each of the plurality of light-emitting elements (LEs) may have a rectangular planar shape, but the embodiments of this specification are not limited thereto. For example, each of the plurality of light-emitting elements (LEs) may have a circular planar shape.

[0118] The first light conversion layer (QDL1) can completely overlap with a plurality of light-emitting elements (LE) of the first subpixel (SPX1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light to light of another specific peak wavelength and emit it. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from a plurality of light-emitting elements (LE) of the first subpixel (SPX1) into first light.

[0119] The second light conversion layer (QDL2) can completely overlap with the plurality of light-emitting elements (LE) of the second subpixel (SPX2). The area of ​​the second light conversion layer (QDL2) may be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of the incident light to light of another specific peak wavelength and emit it. For example, the second light conversion layer (QDL2) can convert or shift the third light emitted from the plurality of light-emitting elements (LE) of the second subpixel (SPX2) into the second light.

[0120] The light-transmitting layer (TPL) can completely overlap with the plurality of light-emitting elements (LE) of the third subpixel (SPX3). The light-transmitting layer (TPL) can transmit incident light as is. For example, the light-transmitting layer (TPL) can transmit the third light emitted from the plurality of light-emitting elements (LE) of the third subpixel (SPX3) as is.

[0121] When the light-emitting element (LE) of the first subpixel (SPX1) emits light of the first color, the light-emitting element (LE) of the second subpixel (SPX2) emits light of the second color, and the light-emitting element (LE) of the third subpixel (SPX3) emits light of the third color, the light conversion layers (QDL1, QDL2) and the light transmission layer (TPL) may be omitted.

[0122] FIG. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I-I' of FIG. 5. FIG. 7 is a cross-sectional view showing in detail an example of area A1 of FIG. 6.

[0123] Referring to FIGS. 6 and FIGS. 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0124] A barrier film (BR) may be disposed on a substrate (SUB). The barrier film (BR) is a film intended to protect the transistors of the thin-film transistor layer (TFTL) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. The barrier film (BR) may be composed of multiple inorganic films stacked alternately.

[0125] A thin-film transistor (TFT1) may be disposed on the barrier film (BR). The thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 4. The thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0126] A first active layer (ACT1) of a thin-film transistor (TFT1) may be disposed on a barrier film (BR). The first active layer (ACT1) of the thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin-film transistor (TFT1) may be made of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0127] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions into a semiconductor material.

[0128] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1).

[0129] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) and a first capacitor electrode (CAE1) of a thin-film transistor (TFT1). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being separated from each other in FIG. 6, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0130] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin-film transistor (TFT1).

[0131] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed between them.

[0132] A first interlayer insulating film (141) may be disposed on the second capacitor electrode (CAE2).

[0133] A first data metal layer may be disposed on the first interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D1) of the first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the first interlayer insulating film (141).

[0134] A first flattening organic film (160) for flattening the step difference caused by a thin film transistor (TFT1) may be disposed on the first source connection electrode (PCE1).

[0135] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) that penetrates the first planarization organic film (160).

[0136] A second planarizing organic film (180) may be placed on the second source connection electrode (PCE2).

[0137] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0138] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0139] The first flattening organic film (160) and the second flattening organic film (180) can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0140] A light-emitting element layer may be disposed on the second planarized organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and (210).

[0141] A pixel electrode layer comprising pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) can be disposed on a second planarization organic film (180).

[0142] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) can be connected to the second source connection electrode (PCE2) through a connection hole (CT1 / CT2 / CT3 in FIG. 5) penetrating the second planarization organic film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) can be connected to the first source region (S1) or the first drain region (D1) of the thin-film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin-film transistor (TFT1) can be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0143] Common electrodes (CE1, CE2, CE3) can be connected to a second power supply line (VSL in FIG. 4) to which a second driving voltage (VSS in FIG. 3) is applied through a common connection hole (CT4 / CT5 / CT6 in FIG. 5). For example, the first common electrode (CE1) can be connected to the second power supply line (VSL) through the second common connection hole (CT4). The second common electrode (CE2) can be connected to the second power supply line (VSL) through the second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power supply line (VSL) through the third common connection hole (CT6). Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, CE3).

[0144] The pixel electrode layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any one of their alloys. For example, to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu), which has low sheet resistance.

[0145] A light-emitting element (LE) can be placed on each pixel electrode layer.

[0146] In FIGS. 6 and 7, the light-emitting element (LE) is exemplified as a flip-type micro LED. A flip-type micro LED refers to an LED having contact electrodes (CTE1, CTE2) formed on one side (e.g., the bottom side) of the light-emitting element (LE).

[0147] Each of the multiple light-emitting elements (LEs) can be formed from an inorganic material such as gallium nitride (GaN).

[0148] Each of the plurality of light-emitting elements (LE) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements (LE) can be transferred directly from the semiconductor substrate or via a relay substrate onto the pixel electrode layer of the display panel (100). Alternatively, the plurality of light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) via an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS (Polydimethylsiloane) or silicon as a transfer substrate.

[0149] Although not illustrated in the present specification, a reflective layer may be disposed on the upper surface of the pixel electrode (PXE1) and the common electrode (CE1).

[0150] The reflective layer can reflect light traveling downward from the light-emitting element (LE) and emit it to the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased.

[0151] The reflective layer can be formed as a single layer of a metal with high reflectivity, or as a multilayer layer such as titanium (Ti) / aluminum (Al) / titanium (Ti) or ITO / aluminum (Al) / ITO.

[0152] The light-emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (SEM3), a first contact electrode (CTE1), a second contact electrode (CTE2), and a protective layer (INS) (e.g., a protective film).

[0153] A conductive layer (E1) may be disposed on the lower surface of a first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0154] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0155] The active layer (MQW) can be placed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light through the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0156] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of indium gallium nitride (InGaN), and the barrier layers may be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments of this specification are not limited thereto.

[0157] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different group 3 to group 5 semiconductor materials depending on the wavelength of the emitted light.

[0158] For example, when the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts to a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts to a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of a light-emitting device (LE) that emits a third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0159] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0160] A third semiconductor layer (SEM3) may be disposed on a second semiconductor layer (SEM2). The third semiconductor layer (SEM3) is a semiconductor material layer in which the n-type dopant is lower than a predetermined threshold value and may be referred to as an un-doped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), in which the n-type dopant is lower than a predetermined threshold value.

[0161] The upper surface of the third semiconductor layer (SEM3) may have a light extraction pattern (LEP).

[0162] Light extraction patterns (LEPs) may be patterns designed to increase the efficiency of light emitted from the upper surface of a light-emitting element (LE). Light extraction patterns (LEPs) may be concave patterns formed as hemispheres or semi-ellipses. Light extraction patterns (LEPs) may be concave patterns having a semicircular or semi-elliptical cross-sectional shape.

[0163] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer may be omitted.

[0164] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN). The superlattice layer may be omitted.

[0165] The protective layer (INS) may be a film for protecting the bottom surface and sides of the light-emitting element (LE). The protective layer (INS) may be disposed on the bottom surface and sides of the conductive layer (E1) and on the sides of a plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3). The protective layer (INS) may be an inorganic film, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as follows. The protective layer (INS) is preferably placed from one end to the other end of the side of the light-emitting element (LE), but it may be placed spaced apart from one end due to process error.

[0166] A hole (LEH) may be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a rectangular planar shape, but the embodiments of this specification are not limited thereto. As an example, the hole (LEH) may have a polygonal shape such as a square, a circular shape, or an elliptical shape.

[0167] Additionally, the protective layer (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective layer (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective layer (INS).

[0168] The first contact electrode (CTE1) can be disposed on the lower surface of the conductive layer (E1). The first contact electrode (CTE1) can be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective layer (INS). Therefore, the first contact electrode (CTE1) can be electrically connected to the conductive layer (E1).

[0169] The second contact electrode (CTE2) may be disposed on at least one side and the bottom surface of the conductive layer (E1). In this case, the first contact electrode (CTE1) is disposed on the first side of the semiconductor stack (e.g., SEM1, MQW, SEM2, and SEM3) and the first side of the conductive layer (E1), whereas the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack and the second side of the conductive layer (E1).

[0170] The second contact electrode (CTE2) can be placed on a protective layer (INS) disposed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective layer (INS). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0171] The first contact electrode (CTE1) and the second contact electrode (CTE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, to increase reflectivity, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed with a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide).

[0172] A first protective layer (INS1) may be disposed to cover all pixel electrodes (PXE1, PXE2, PXE3), common electrodes (CE1, CE2, CE3), and light-emitting elements (LE) disposed thereon. The first protective layer (INS1) may cover all pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) where light-emitting elements (LE) are not disposed.

[0173] A first organic layer (211) may be disposed on a first protective layer (INS1) on which a light-emitting element (LE) is not disposed. For example, the first organic layer (211) may overlap with at least a portion of the pixel electrodes (PXE1, PXE2, PXE3) and at least a portion of the common electrodes (CE1, CE2, CE3). The first organic layer (211) may be disposed to cover a portion of the side of a plurality of light-emitting elements (LE). Thus, the first organic layer (211) may serve to fix the light-emitting element (LE). For example, the first organic layer (211) may cover the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the plurality of light-emitting elements (LE), and cover at least a portion of the second semiconductor layer (SEM2). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed without being covered by the first organic layer (211). For example, the first organic layer (211) can be arranged in an island shape around each subpixel (SPX1, SPX2, SPX3).

[0174] In one embodiment, the first organic layer (211) may be arranged in an island pattern shape on each subpixel (SPX1, SPX2, SPX3). For example, the first organic layer (211) arranged on each subpixel (SPX1, SPX2, SPX3) may be spaced apart from the first organic layer (211) arranged on adjacent subpixels (SPX1, SPX2, SPX3).

[0175] The first organic layer (211) can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0176] A first reflective layer (RF1) may be placed on the side of the first organic layer (211).

[0177] The first reflective layer (RF1) may be disposed from the bottom to the top of the first organic layer (211). For example, one end of the first reflective layer (RF1) may be disposed on the second flattening organic film (180), and the other end of the first reflective layer (RF1) may be disposed in the same plane as the top of the first organic layer (211). The first reflective layer (RF1) may include a metal material with high reflectivity, such as aluminum (Al).

[0178] The first reflective layer (RF1) surrounds the side of the first organic layer (211), thereby surrounding the active layer (MQW) of the light-emitting element (LE). Accordingly, the first reflective layer (RF1) can minimize or reduce the loss of light emitted from the side of the active layer (MQW) and scattered. Accordingly, the brightness of the display device according to one embodiment can be increased when the same current as in the conventional device is injected. In addition, the power consumption of the display device according to one embodiment can be reduced compared to the same brightness as in the conventional device.

[0179] The second protective layer (INS2) may be positioned to cover the upper portion of the first organic layer (211) and the entire light-emitting element (LE) that is exposed and not covered by the first organic layer (211). The second protective layer (INS2) may not cover the sides of the first organic layer (211). The second protective layer (INS2) may be positioned on the other end of the first reflective layer (RF1).

[0180] The third protective layer (INS3) may cover the upper part of the second protective layer (INS2) and surround the side of the first reflective layer (RF1). Additionally, the third protective layer (INS3) may be placed on the first protective layer (INS1) where the first organic layer (211) is not placed. The third protective layer (INS3) may overlap the second partition (BM1), which will be described later, in the third direction (DR3).

[0181] The first protective layer (INS1), the second protective layer (INS2), and the third protective layer (INS3) are inorganic films, for example, silicon nitride (SiN x), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0182] The upper part of the first reflective layer (RF1) is surrounded by the second protective layer (INS2), the side of the first reflective layer (RF1) is surrounded by the third protective layer (INS3), and the lower part of the first reflective layer (RF1) is covered by the first protective layer (INS1), so the first reflective layer (RF1) can be surrounded by protective layers.

[0183] On the third protective layer (INS3), partitions (BM1, BM2) that partition each subpixel (SPX1, SPX2, SPX3) may be further disposed.

[0184] The barrier (BM1, BM2) can also be called a light-blocking layer in that it includes a light-blocking material to prevent light from the light-emitting element (LE) of one subpixel from proceeding to the adjacent subpixel.

[0185] The partitions (BM1, BM2) may be formed in a grid-like pattern over the entire display area (DA in FIG. 1). The partitions (BM1, BM2) may not overlap with a plurality of light-emitting elements (LE) in the third direction (DR3). The partitions (BM1, BM2) may serve to provide a space for the formation of a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL). The partitions (BM1, BM2) may be formed from organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0186] In one embodiment, the partitions (BM1, BM2) are formed as a single layer, but are not limited thereto. For example, the partitions (BM1, BM2) may be formed as two layers. The partitions (BM1, BM2) may be formed as two layers to sufficiently secure space for forming the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmission layer (TPL).

[0187] The partitions (BM1, BM2) may include a light-blocking material as described above. For example, the partitions (BM1, BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0188] A reflective layer (RF2, RF3) may be disposed inside the space formed by partitions (BM1, BM2). The reflective layer (RF2, RF3) may be disposed on the side of the partitions (BM1, BM2), or on the bottom surface between the partitions (BM1, BM2) that does not overlap with the pixel electrodes (PXE1, PXE2, PXE3), the common electrode (CE), and the light-emitting element (LE). The reflective layer (RF2, RF3) may include an opening formed in an area that overlaps with the pixel electrodes (PXE1, PXE2, PXE3), the common electrode (CE), and the light-emitting element (LE). The reflective layer (RF2, RF3) may not come into contact with the pixel electrodes (PXE1, PXE2, PXE3) and the common electrode (CE), and may not be electrically connected.

[0189] The reflective layers (RF2, RF3) serve to reflect light traveling in the lateral direction from the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmission layer (TPL).

[0190] The reflective layer (RF2, RF3) may include a metallic material with high light reflectivity. For example, the reflective layer (RF2, RF3) may include aluminum or silver, and may also include an alloy thereof.

[0191] A first light conversion layer (QDL1) may be disposed between the partition (BM) and the partition (BM) in the first subpixel (SPX1), a second light conversion layer (QDL2) may be disposed between the partition (BM) and the partition (BM) in the second subpixel (SPX2), and a light transmission layer (TPL) may be disposed between the partition (BM) and the partition (BM) in the third subpixel (SPX3).

[0192] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into the first light (light in the red wavelength band). The first light conversion layer (QDL1) may include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) may include a transparent organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into the first light (light in the red wavelength band).

[0193] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into second light (light in the green wavelength band). It may include a second base resin (BRS2) and a second wavelength conversion particle (WCP2). The second base resin (BRS2) may include a transparent organic material. The second wavelength conversion particle (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into second light (light in the green wavelength band).

[0194] The light-transmitting layer (TPL) may include a light-transmitting organic material.

[0195] For example, the first base resin (BRS1), the second base resin (BRS2), and the light-transmitting layer (TPL) may include epoxy resin, acrylic resin, cardo resin, or imide resin, etc. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QD), quantum rods, fluorescent materials, or phosphorescent materials.

[0196] A capping layer (CAP) can be disposed on a partition wall (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light transmission layer (TPL).

[0197] The capping layer (CAP) is an inorganic film, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as follows. The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmission layer (TPL) can be encapsulated by a capping layer (CAP).

[0198] A fourth organic film (213) may be disposed on the capping layer (CAP). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0199] A first color filter (CF1) disposed in a first subpixel (SPX1) can transmit a first light (light in the red wavelength band) and absorb or block a third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and can absorb or block the third light (light in the blue wavelength band) that is not converted by the first light conversion layer (QDL1). Accordingly, the first subpixel (SPX1) can emit the first light (light in the red wavelength band).

[0200] A second color filter (CF2) placed in the second subpixel (SPX2) can transmit second light (light in the green wavelength band) and absorb or block third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit second light (light in the green wavelength band) converted by the second light conversion layer (QDL2) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and can absorb or block third light (light in the blue wavelength band) that is not converted by the second light conversion layer (QDL2). Accordingly, the second subpixel (SPX2) can emit second light (light in the green wavelength band).

[0201] A third color filter (CF3) placed in a third subpixel (SPX3) can transmit third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit third light (light in the blue wavelength band) emitted from a light-emitting element (LE) passing through a light-transmitting layer (TPL). Accordingly, the third subpixel (SPX3) can emit third light (light in the blue wavelength band).

[0202] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap with the partition walls (BM1, BM2) in the third direction (DR3).

[0203] A fifth organic film (214) for flattening can be placed on a plurality of color filters (CF1, CF2, CF3).

[0204] The fourth organic film (213) and the fifth organic film (214) can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0205] Figure 8 is a cross-sectional view showing another example of the A1 region of Figure 6 in detail.

[0206] The embodiment of FIG. 8 differs from the embodiment of FIG. 7 in that the first organic layer (211) is dome-shaped. In FIG. 8, descriptions that overlap with the embodiment of FIG. 7 are omitted, and the explanation focuses on the differences from the embodiment of FIG. 7.

[0207] The first organic layer (211) may be arranged to cover a portion of the side of a plurality of light-emitting elements (LE). Additionally, the first organic layer (211) may be arranged to cover pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) covered by the first protective layer (INS1).

[0208] The first organic layer (211) may be dome-shaped, narrowing from the side of the light-emitting element (LE) toward the top. For example, the first organic layer (211) may cover the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the plurality of light-emitting elements (LE), and cover at least a portion of the second semiconductor layer (SEM2). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the first organic layer (211).

[0209] In one embodiment, the first organic layer (211) may be arranged in an island pattern shape on each subpixel (SPX1, SPX2, SPX3). For example, the first organic layer (211) arranged on each subpixel (SPX1, SPX2, SPX3) may be spaced apart from the first organic layer (211) arranged on adjacent subpixels (SPX1, SPX2, SPX3). For example, the first organic layer (211) may be arranged in an island shape around each subpixel (SPX1, SPX2, SPX3).

[0210] The first reflective layer (RF1) can be placed on the dome-shaped side of the first organic layer (211).

[0211] In one embodiment, the first partition (BM1) does not overlap with the first organic layer (211), but is not limited thereto. The first partition (BM1) may overlap with a portion of the first organic layer (211). In this case, at least a portion of the first reflective layer (RF1) disposed on the side of the first organic layer (211) may overlap with the first partition (BM1).

[0212] Figure 9 is a cross-sectional view showing another example of the A1 region of Figure 6 in detail.

[0213] The embodiment of FIG. 9 differs from the embodiment of FIG. 7 in that the side of the first organic layer (211) has an acute angle of inclination. In FIG. 9, descriptions that overlap with the embodiment of FIG. 7 are omitted, and the explanation focuses on the differences from the embodiment of FIG. 7.

[0214] The side of the first organic layer (211) may have an angle of inclination of about 55° to 85° relative to the bottom surface of the first organic layer (211). Accordingly, the first reflective layer (RF1) may also have an angle of inclination of about 55° to 85°.

[0215] The first organic layer (211) may have a regular tapered shape that gradually narrows as it goes upward in the thickness direction of the display device. If the side of the first organic layer (211) is formed in a regular tapered shape, the light emission efficiency may be increased.

[0216] In another embodiment, to achieve the effect of widening the viewing angle, the side of the first organic layer (211) can be formed in an inverse taper shape that becomes wider as it goes upward.

[0217] Unless otherwise defined in this specification, “gradually” means that the shape of the first organic layer (211) changes smoothly and continuously as it extends upward. Specifically, the layer forms a tapered shape that gradually narrows as its thickness increases. Alternatively, the layer may form an inverse tapered shape as it widens smoothly and continuously as it extends upward. Such gradual shape changes are intended to improve the luminous efficiency of the display device or to widen the viewing angle. For example, “gradually” means that the change occurs in small and consistent increments over a certain period. That is, there is no sudden change in shape; instead, the change occurs smoothly and gradually.

[0218] FIG. 10 is a layout diagram showing pixels of a display area according to one embodiment.

[0219] The embodiment of FIG. 10 differs from the embodiment of FIG. 5 in that the light-emitting element (LE) in each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) overlaps with the pixel electrodes (PXE1 / PXE2 / PXE3). In the embodiment of FIG. 10, descriptions that overlap with the embodiment of FIG. 5 are omitted.

[0220] Referring to FIG. 10, the first subpixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LE), and a first light conversion layer (QDL1). The second subpixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LE), and a second light conversion layer (QDL2). The third subpixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LE), and a light-transmitting layer (or third light conversion layer) (TPL).

[0221] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the area of ​​the subpixel may be larger as the light conversion efficiency decreases.

[0222] For example, as shown in FIG. 10, if the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). Also, since the light transmission layer (TPL) transmits the light of the light-emitting element (LE) as is, whereas the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0223] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to the second electrode of the fourth transistor (ST4 in FIG. 4) and the second electrode of the sixth transistor (ST6 in FIG. 4) of the corresponding subpixel.

[0224] A plurality of light-emitting elements (LEs) may be placed on each of the pixel electrodes (PXE1, PXE2, PXE3). An equal number of light-emitting elements (LEs) may be placed on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light-emitting elements (LEs) may be placed on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0225] The first light conversion layer (QDL1) can completely overlap with the plurality of light-emitting elements (LE) of the first pixel electrode (PXE1) and the first subpixel (SPX1). The area of ​​the first light conversion layer (QDL1) may be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light to light of another specific peak wavelength and emit it. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light-emitting elements (LE) of the first subpixel (SPX1) into first light.

[0226] The second light conversion layer (QDL2) can completely overlap with the plurality of light-emitting elements (LE) of the second pixel electrode (PXE2) and the second subpixel (SPX2). The area of ​​the second light conversion layer (QDL2) may be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of the incident light to light of another specific peak wavelength and emit it. For example, the second light conversion layer (QDL2) can convert or shift the third light emitted from the plurality of light-emitting elements (LE) of the second subpixel (SPX2) into the second light.

[0227] The light-transmitting layer (TPL) can completely overlap with the plurality of light-emitting elements (LE) of the third pixel electrode (PXE3) and the third subpixel (SPX3). The light-transmitting layer (TPL) can transmit incident light as is. For example, the light-transmitting layer (TPL) can transmit the third light emitted from the plurality of light-emitting elements (LE) of the third subpixel (SPX3) as is.

[0228] FIG. 11 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I1-I1' of FIG. 10. FIG. 12 is a cross-sectional view showing in detail an example of area A2 of FIG. 11.

[0229] The embodiments of FIG. 11 and FIG. 12 differ from the embodiment of FIG. 6 in that the light-emitting element (LE) is a vertical type micro LED in which each of the plurality of light-emitting elements (LE) extends in a third direction (DR3). A vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3) are sequentially arranged in a third direction (DR3) which is a vertical direction.

[0230] In the embodiments of FIGS. 11 and 12, descriptions that overlap with the embodiments of FIGS. 6 and 7 are not repeated.

[0231] Referring to FIGS. 11 and 12, a pixel electrode layer may be disposed on the second planarized organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3).

[0232] Although not illustrated in the present specification, a reflective layer may be disposed on the upper surface of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0233] The reflective layer can reflect light traveling downward from the light-emitting element (LE) and emit it to the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased.

[0234] A light-emitting element (LE) is disposed on the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0235] Each of the plurality of light-emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3), each ranging from several to several hundred μm. For example, each of the plurality of light-emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3), each ranging from approximately 100 μm or less.

[0236] The light-emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (SEM3), a contact electrode (CTE), and a protective layer (INS).

[0237] A protective layer (INS) may be disposed on one side of the conductive layer (E1), the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), the side of the second semiconductor layer (SEM2), and the side of the third semiconductor layer (SEM3). The protective layer (INS) may be a film for protecting the side of the light-emitting element (LE). The protective layer (INS) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0238] A contact electrode (CTE) can be placed on a protective layer (INS). Each of the plurality of contact electrodes (CTE) can be placed between the pixel electrodes (PXE1, PXE2, PXE3) and the protective layer (INS).

[0239] The protective layer (INS) has one or more openings that expose the conductive layer (E1). In one embodiment, the protective layer (INS) includes one opening.

[0240] The contact electrode (CTE) can be connected to the exposed conductive layer (E1) without being covered by the protective layer (INS).

[0241] A plurality of contact electrodes (CTEs) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, to increase reflectivity, the plurality of contact electrodes (CTEs) may be formed into a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide).

[0242] A first protective layer (INS1) may be disposed to cover all pixel electrodes (PXE1, PXE2, PXE3) and light-emitting elements (LE) disposed on the pixel electrodes (PXE1, PXE2, PXE3). The first protective layer (INS1) may cover all pixel electrodes (PXE1, PXE2, PXE3) on which light-emitting elements (LE) are not disposed.

[0243] A first organic layer (211) may be disposed on a first protective layer (INS1) on which a light-emitting element (LE) is not disposed. For example, the first organic layer (211) may overlap with at least a portion of the pixel electrodes (PXE1, PXE2, PXE3). The first organic layer (211) may be disposed to cover a portion of the side of a plurality of light-emitting elements (LE). For example, the first organic layer (211) may cover the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the plurality of light-emitting elements (LE), and cover at least a portion of the second semiconductor layer (SEM2). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the first organic layer (211).

[0244] In one embodiment, the first organic layer (211) may be arranged in an island pattern shape on each subpixel (SPX1, SPX2, SPX3). For example, the first organic layer (211) arranged on each subpixel (SPX1, SPX2, SPX3) may be spaced apart from the first organic layer (211) arranged on adjacent subpixels (SPX1, SPX2, SPX3).

[0245] A first reflective layer (RF1) may be disposed on the side of the first organic layer (211). By surrounding the side of the first organic layer (211), the first reflective layer (RF1) surrounds the active layer (MQW) of the light-emitting element (LE). Accordingly, the first reflective layer (RF1) can minimize the loss of light emitted from the active layer (MQW) to the side and scattered.

[0246] The second protective layer (INS2) may be positioned to cover the upper portion of the first organic layer (211) and the entire light-emitting element (LE) that is exposed and not covered by the first organic layer (211). The second protective layer (INS2) may not cover the sides of the first organic layer (211). The second protective layer (INS2) may be positioned on the other end of the first reflective layer (RF1) (e.g., the end from the first protective layer (INS1)).

[0247] The third protective layer (INS3) may cover the top of the second protective layer (INS2) and surround the side of the first reflective layer (RF1). Additionally, the third protective layer (INS3) may be placed on the first protective layer (INS1) where the first organic layer (211) is not placed. The third protective layer (INS3) may overlap the first partition (BM1) described later and the third direction (DR3). For example, the first organic layer (211) may be placed in an island shape around each subpixel (SPX1, SPX2, and SPX3). For example, the first organic layer (211) forms a separated island around each subpixel (SPX1, SPX2, and SPX3) so that there is no direct connection between the organic layers of adjacent subpixels.

[0248] The first reflective layer (RF1) is positioned on the side of the first organic layer (211) and is protected by a protective layer (INS1, INS2, INS3), so there is no risk of contact with the common electrode (CE) or pixel electrode (PXE1, PXE2, PXE3).

[0249] The third protective layer (INS3) and the second protective layer (INS2) have an opening that exposes at least a portion of the upper part of the light-emitting element (LE).

[0250] The common electrode (CE) may be arranged to overlap the first organic layer (211) on the upper surface of each of the plurality of light-emitting elements (LE) and on the third protective layer (INS3). The common electrode (CE) may be a common layer formed commonly on the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3).

[0251] The common electrode (CE) can be made of transparent conductive materials (TCO) such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO) that can transmit light.

[0252] The pixel electrodes (PXE1, PXE2, PXE3) are referred to as the anode electrode or the first electrode, and the common electrode (CE) may be referred to as the cathode electrode or the second electrode.

[0253] FIG. 13 is a flowchart showing a method for manufacturing a display device according to one embodiment. FIG. 14 to 26 are exemplary drawings for explaining a method for manufacturing a display device according to one embodiment.

[0254] Hereinafter, a method for manufacturing a display device according to one embodiment will be described in detail by combining FIG. 13 with FIG. 14 to 26. The method for manufacturing a display device described with reference to FIG. 14 to 26 may be a display device comprising a light-emitting element and a display panel described with reference to FIG. 5 to 7.

[0255] First, a plurality of semiconductor material layers (SEML3, SEML2, MQWL, SEML1) and a conductive layer (EL1) are formed on a semiconductor substrate (SSUB). (S110 of FIG. 13)

[0256] The semiconductor substrate (SSUB) may be a silicon wafer substrate or a sapphire substrate. A light extraction pattern layer (LEPL) is formed on one side of the semiconductor substrate (SSUB). The light extraction pattern layer (LEPL) may include convex patterns formed as hemispheres or semi-ellipses. The light extraction pattern layer (LEPL) may include convex patterns having a cross-sectional shape of a semicircle or semi-ellipse. The light extraction pattern layer (LEPL) may be formed of a semiconductor material layer, an organic film, or an inorganic film.

[0257] Then, a third semiconductor material layer (SEML3) is formed on the light extraction pattern layer (LEPL). Due to the light extraction pattern layer (LEPL), light extraction patterns (LEPs of FIG. 7) can be formed on one side of the third semiconductor material layer (SEML3). The third semiconductor material layer (SEML3) may be a semiconductor material layer doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), tin (Sn), etc.

[0258] Then, a second semiconductor material layer (SEML2) is formed on the third semiconductor material layer (SEML3), an active material layer (MQWL) is formed on the second semiconductor material layer (SEML2), and a first semiconductor material layer (SEML1) is formed on the active material layer (MQWL). The active material layer (MQWL) may include the same semiconductor material layer as the first semiconductor material layer (SEML1), the second semiconductor material layer (SEML2), and the third semiconductor material layer (SEML3). For example, if the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2) include gallium nitride (GaN), the active material layer (MQWL) may also include gallium nitride (GaN). For example, the active material layer (MQWL) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The first semiconductor material layer (SEML1) may be a semiconductor material layer doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc.

[0259] The light extraction pattern layer (LEPL), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) can be formed on a semiconductor substrate (SSUB) through an epitaxial growth process. As an epitaxial growth process, methods for forming the light extraction pattern layer (LEPL), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) may include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc. Preferably, metal-organic chemical vapor deposition (MOCVD) may be used, but the embodiments of this specification are not limited thereto.

[0260] Then, a conductive material layer (EL1) is formed on the third semiconductor material layer (SEML3) and the first semiconductor material layer (SEML1). The conductive material layer (EL1) can be formed from any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0261] Secondly, light-emitting elements (LEs) are formed. (S120 in FIG. 13)

[0262] The third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) are etched.

[0263] Referring to FIG. 15, after forming a mask pattern on a conductive material layer (EL1), a third semiconductor material layer (SEML3), a second semiconductor material layer (SEML2), an active material layer (MQWL), a first semiconductor material layer (SEML1), and a conductive material layer (EL1) are etched according to the mask pattern. The mask pattern can be removed after forming light-emitting elements (LE).

[0264] The third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) can be etched by dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible, so it may be suitable for vertical etching. When using dry etching, the etching gas may be chlorine (Cl2) or oxygen (O2) gas, but is not limited thereto.

[0265] Then, a hole (LEH) is formed in each of the light-emitting elements (LE) to penetrate the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) to expose the second semiconductor layer (SEM2).

[0266] Afterwards, as shown in Fig. 16, a protective layer (INS) and electrodes (CTE1, CTE2) are formed.

[0267] A protective material layer is formed to surround light-emitting elements (LEs), and a mask pattern is formed on the protective material layer.

[0268] A protective material layer can be deposited over the entire surface of one side of a semiconductor substrate (SSUB). The protective material layer can be formed to cover one side and the sides of light-emitting elements (LEs). The protective material layer can be formed on one side of the semiconductor substrate (SSUB) exposed between the light-emitting elements (LEs).

[0269] The mask pattern can be formed to expose a portion of the hole (LEH) of each of the light-emitting elements (LE). For example, the mask pattern can be formed so as not to cover a protective material layer placed on the bottom surface of the hole (LEH) of each of the light-emitting elements (LE). Additionally, the mask pattern can be positioned to expose a portion of the protective material layer placed on one side of each of the light-emitting elements (LE).

[0270] The protective material layer not covered by the mask pattern is etched. Then, the mask pattern can be removed by an ashing process.

[0271] Subsequently, a contact electrode layer is deposited on one side of a semiconductor substrate (SSUB), and a portion of the contact electrode layer is etched using a mask pattern to form contact electrodes.

[0272] Then, the mask pattern can be removed by an ashing process.

[0273] Third, the light-emitting elements (LEs) are transferred onto a circuit board (S130 in FIG. 13).

[0274] As shown in FIG. 17, light-emitting elements (LEs) can be transferred onto a pixel electrode (PXE1) and a common electrode (CE1). The first contact electrode (CTE1) of each light-emitting element (LE) is exemplified as being placed on the pixel electrode (PXE1, PXE2, PXE3) and the second contact electrode (CTE2) is placed on the common electrode (CE1, CE2, CE3).

[0275] Fourth, a first protective layer (INS1), a first organic layer (211), and a second protective layer (INS2) are formed. (S140 of FIG. 13)

[0276] As shown in Fig. 18, a protective material layer is formed to cover the light-emitting elements (LE).

[0277] The protective material layer is deposited on one side of the circuit board and can cover a portion of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3).

[0278] A protective material layer can be formed on one side of a circuit board exposed between pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3).

[0279] Afterward, as shown in FIG. 19, an organic material layer (211L) is formed to fix the light-emitting elements (LE) and flatten the step difference caused by the light-emitting elements (LE). The organic material layer (211L) can fill all the spaces between the light-emitting elements (LE), but the height of the organic material layer (211L) is formed lower than the height of the light-emitting elements (LE) so that the top of the light-emitting elements (LE) can be exposed.

[0280] Subsequently, a protective material layer (INSL) is deposited on the circuit board to cover the light-emitting element (LE) and the organic material layer (211L), and a hard mask is formed. For example, as shown in FIGS. 20 to 22, a photoresist (PR) is applied to the entire surface to cover the protective material layer (INSL), and the photoresist (PR) is patterned using a mask pattern. The protective material layer (INSL) and the organic material layer (211L) are patterned using the photoresist pattern and dry-etched to form a second protective layer (INS2) and a first organic layer (211). Due to the patterning, an island pattern shape can be formed at each subpixel of the first organic layer (211). Since the etching rate of the first organic layer (211) is higher than that of the second protective layer (INS2), one end of the second protective layer (INS2) can protrude outside the first organic layer (211) to form a tip.

[0281] The first protective layer (INS1) can protect the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) during dry etching.

[0282] Fifth, a first reflective layer (RF1) and a third protective layer (INS3) are formed. (S150 of FIG. 13)

[0283] As shown in FIG. 23, a reflective material layer (RF1L) is deposited on the entire surface of a circuit board to cover a light-emitting element (LE) and a first organic layer (211).

[0284] Subsequently, as shown in FIG. 24, dry etching can be performed to form a first reflective layer (RF1) by leaving only the reflective material layer disposed on the side of the first organic layer (211). Anisotropic etching may be possible through dry etching. Additionally, a tip protruding outward from the second protective layer (INS2) prevents the etching of the reflective material layer below the tip, thereby allowing the first reflective layer (RF1) to be formed on the side of the first organic layer (211). The reflective material on the upper part of the other light-emitting element (LE), the upper part of the first organic layer (211), and the upper part of the first protective layer (INS1) between the first organic layers (211) can be removed.

[0285] As shown in FIG. 25, a protective material layer (INSL) is deposited on the entire surface of a circuit board on which a first reflective layer (RF1) is formed to form a third protective layer (INS3).

[0286] Sixth, as shown in FIG. 26, a light-blocking layer, a wavelength conversion layer, a light-transmitting layer, and a color filter layer are formed sequentially. (S160 of FIG. 13)

[0287] A first capping layer (CPL1) is formed on the third organic film (213) and the light-emitting elements (LE), and a first barrier (BM1) and a second barrier (BM2) are formed on the first capping layer (CPL1) so as not to overlap with the light-emitting elements (LE) in the third direction (DR). Then, a second capping layer (CPL2) covering the first barrier (BM1), the second barrier (BM2), and the first capping layer (CPL1) is formed. Then, a reflective layer (RF2) covering the second capping layer (CPL2) disposed on the first barrier (BM1) and the second barrier (BM2) is formed.

[0288] Then, a first light conversion layer (QDL1) is formed on each of the first subpixels (SPX1), a second light conversion layer (QDL2) is formed on each of the second subpixels (SPX2), and a light transmission layer (TPL) is formed on each of the third subpixels (SPX3). Then, a capping layer (CAP in FIG. 6) is formed covering the first light conversion layers (QDL1), the second light conversion layers (QDL2), and the light transmission layers (TPL). Then, a fourth organic film (213) is formed on the capping layer (CAP).

[0289] Then, a first color filter (CF1) is formed overlapping the first light conversion layer (QDL1) in the third direction (DR3) on the fourth organic film (213), a second color filter (CF2) is formed overlapping the second light conversion layer (QDL2) in the third direction (DR3), and a third color filter (CF3) is formed overlapping the light transmission layer (TPL) in the third direction (DR3). In the region overlapping the first partition (BM1) and the second partition (BM2) in the third direction (DR3), the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can all be formed.

[0290] Then, a fifth organic film (214) is formed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3).

[0291] FIG. 27 is an example drawing showing a smart watch including a display device according to one embodiment.

[0292] Referring to FIG. 27, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0293] FIGS. 28 and FIGS. 29 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0294] Referring to FIGS. 28 and 29, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece (1210), a second eyepiece (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0295] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIG. 1 and FIG. 2, the description of the first display device (10_2) and the second display device (10_3) is omitted.

[0296] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0297] The middle frame (1400) is positioned between the first display device (10_2) and the control circuit board (1600), and may be positioned between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0298] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) through a connector. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) through the connector.

[0299] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0300] The display device housing (1100) serves to house the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The housing cover (1200) is positioned to cover an open side of the display device housing (1100). The housing cover (1200) may include a first eyepiece (1210) in which the user's left eye is positioned and a second eyepiece (1220) in which the user's right eye is positioned. Although FIGS. 28 and 29 illustrate the first eyepiece (1210) and the second eyepiece (1220) being positioned separately, the embodiments of this specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0301] The first eyepiece (1210) is aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view an image of the first display device (10_2) magnified into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view an image of the second display device (10_3) magnified into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0302] The head mounting band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be maintained in a state where they are positioned on the user's left and right eyes, respectively. When the display device storage unit (1200) is implemented as a lightweight and compact unit, the head-mounted display device (1000) may be equipped with an eyeglass frame as shown in FIG. 30 instead of the head mounting band (1300).

[0303] In addition, the head-mounted display device (1000_2) may further be equipped with a battery for supplying power, an external memory slot for storing external memory, an external connection port for receiving video sources, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0304] FIG. 30 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. FIG. 30 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0305] Referring to FIG. 30, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. A virtual reality device (1000_3) according to one embodiment may have a display device (10_4), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device housing (50).

[0306] FIG. 30 illustrates a virtual reality device (1000_3) that is an eyeglass-type display device including eyeglass frame temples (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that shown in FIG. 30 and can be applied in various forms in various other electronic devices.

[0307] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view the virtual reality image displayed on the display device (10_4) through their right eye.

[0308] FIG. 31 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0309] FIG. 31 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. FIG. 32 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0310] Referring to FIG. 31, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0311] FIG. 32 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0312] Referring to FIG. 32, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light simultaneously. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_5) but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) may include a light-transmitting portion capable of transmitting light or be formed of a material capable of transmitting light.

[0313] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. Substrate; A pixel electrode layer disposed on the above substrate; A light-emitting element disposed on the pixel electrode layer and including a contact electrode; An organic layer having an island pattern shape, covering a portion of the side of the light-emitting element and a portion of the pixel electrode layer exposed by the light-emitting element; A first reflective layer disposed on the side of the above organic layer; and A protective layer protecting the light-emitting element, the organic layer, and the first reflective layer. A display device including 2. In Paragraph 1, The above protective layer is, A first protective layer covering the upper and side surfaces of a light-emitting element and a pixel electrode layer where the light-emitting element is not placed; A second protective layer disposed on the upper surface of the organic layer and on the upper surface and side of the light-emitting element; and A display device comprising, on the second protective layer, the light-emitting element, the organic layer, and a third protective layer disposed on a substrate on which the organic layer is not disposed.

3. In Paragraph 2, The second protective layer has a tip protruding outward from the upper surface of the organic layer, and The first reflective layer is a display device positioned at the bottom of the tip.

4. In Paragraph 1, The above organic layer is a display device having a cross-section that is dome-shaped, rectangular, or trapezoidal.

5. In Paragraph 1, The above organic layer is a display device having a shape that gradually narrows as it rises in the thickness direction.

6. In Paragraph 5, A display device having a side of the organic layer and a first reflective layer with an inclination angle in the range of 55° to 85°.

7. In Paragraph 1, The above light-emitting element is, A conductive layer disposed on the lower surface of the first semiconductor layer, A first semiconductor layer disposed on the conductive layer and comprising a semiconductor material layer doped with a first conductive type dopant; An active layer disposed on the first semiconductor layer; and A second semiconductor layer disposed on the above active layer and comprising a semiconductor material layer doped with a second conductivity type dopant, and The above organic layer is a display device that surrounds the sides of the conductive layer, the first semiconductor layer, and the active layer.

8. In Paragraph 7, The above light-emitting element is, A display device further comprising a third semiconductor layer, which is an undoped semiconductor layer disposed on the second semiconductor layer.

9. In Paragraph 8, The above light-emitting element is, A display device further comprising a light extraction pattern having a concave pattern on the upper side.

10. In Paragraph 7, The above contact electrode is A first contact electrode disposed on the protective layer and connected to the conductive layer exposed without being covered by the protective layer, and It includes a second contact electrode disposed on the protective layer and disposed in a hole penetrating the conductive layer and a part of the semiconductor stack, and The pixel electrode layer includes pixel electrodes and a common electrode arranged spaced apart from each other. The above semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer, and A display device in which the first contact electrode is connected to the pixel electrode and the second contact electrode is connected to the common electrode.

11. In Paragraph 7, The pixel electrode layer above includes a pixel electrode, and A display device in which the above contact electrode is disposed on the pixel electrode and connected to the conductive layer exposed without being covered by the protective layer.

12. In Paragraph 11, It further includes a common electrode disposed on top of the light-emitting element and the organic layer, and A display device in which the protective layer includes an opening that exposes at least a portion of the upper part of the light-emitting element, and the upper part of the light-emitting element is connected to the common electrode through the opening.

13. In Paragraph 1, A partition wall positioned to surround the light-emitting element; and A display device further comprising a reflective layer disposed on the side of the above partition and on the bottom of the space formed by the above partition.

14. In Paragraph 13, A display device further comprising a wavelength conversion layer disposed in the space formed by the above partition.

15. A step of forming a light-emitting device comprising a plurality of semiconductor layers, a conductive layer, a protective layer, and a contact electrode; A step of transferring the above light-emitting element onto a circuit board; A step of forming a first protective layer by applying a full coating on the side of the light-emitting element and on a circuit board where the light-emitting element is not placed; A step of forming an organic material layer covering the side of the light-emitting element, forming a protective material layer to cover the light-emitting element and the organic material layer, and patterning the protective material layer and the organic material layer to form an organic layer and a second protective layer; A step of forming a first reflective layer disposed on the side of a second organic layer by depositing a reflective material layer on the entire surface to cover the light-emitting element and the organic layer and dry etching; and Step of forming the above organic layer and a third protective layer surrounding the light-emitting elements A method for manufacturing a display device including 16. In Paragraph 15, In the step of forming the above organic layer and the second protective layer, A method for manufacturing a display device, wherein an organic layer is formed in an island pattern by dry etching on the above-mentioned protective material layer using a hard mask, and a second protective layer having a tip protruding outward from the upper surface of the organic layer is formed.

17. In Paragraph 16, A method for manufacturing a display device in which the first reflective layer is disposed on the lower part of the protruding tip.

18. In Paragraph 15, The step of forming the light-emitting element is, A step of forming a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer on a semiconductor substrate; A step of forming light-emitting devices each comprising a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer by etching a second semiconductor material layer, an active layer, a first semiconductor layer, and a conductive layer; A step of forming a hole penetrating the conductive layer, the first semiconductor layer, and the active layer in each of the above light-emitting elements; A step of forming a protective material layer surrounding each of the above-mentioned light-emitting elements, and patterning the protective material layer to form a protective layer; and A method for manufacturing a display device comprising the steps of forming a mask pattern and forming a contact electrode on the protective layer.

19. In Paragraph 15, A step of forming a partition that defines a light-emitting region; A wavelength conversion layer on the space formed by the above partition; and A method for manufacturing a display device further comprising the step of forming an overcoat layer and a color filter layer sequentially disposed on the above partition and the above wavelength conversion layer.

20. Includes a display device for displaying images, The above display device is, Substrate; A pixel electrode layer disposed on the above substrate; A light-emitting element disposed on the pixel electrode layer and including a contact electrode; An organic layer having an island pattern shape, covering a portion of the side of the light-emitting element and a portion of the pixel electrode layer exposed by the light-emitting element; A first reflective layer disposed on the side of the above organic layer; and A protective layer protecting the light-emitting element, the organic layer, and the first reflective layer. An electronic device including

Images