Automatic switching between two types of interface devices on parallel data buses

Abstract

Automatic Switching Between Two Types of Interface Devices on Parallel Data Buses Various aspects of the disclosed technology relate to automatic switching between two types of interface devices on a data streaming network. The first type of interface devices can enter a sleep mode in response to a unique command data packet and sleep for a number of clock cycles specified in the unique command data packet (1230). The second type of interfaces devices can be activated by a sentinel signal and then process data transmitted in the data streaming network while the first type of interfaces is in the sleep mode (1240, 1250). After completing processing the data, the second type of interfaces devices become deactivated, and the first type of interfaces exits the sleep mode to process data transmitted in the data streaming network (1260). The process can be repeated.

Description

[0001] 202419433

[0002] Automatic Switching Between Two Types of Interface Devices on Parallel Data Buses

[0003] RELATED APPLICATIONS

[0004]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 715,003, filed on November 01, 2024, and naming Jean-Francois Cote et al. as inventors, which application is incorporated entirely herein by reference.

[0005] FIELD OF THE DISCLOSED TECHNOLOGY

[0006]

[0002] The presently disclosed technology relates to the field of integrated circuit design, verification, manufacture and test. Various implementations of the disclosed technology may be particularly useful for increasing bandwidth of serial networks in a circuit.

[0007] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0008]

[0003] The increasing integration of functionality into single semiconductor devices continues to drive a significant rise in the number of functional units. These units can range from sensors (e.g., for temperature or voltage) and clock control circuitry (e.g., Phase-Locked Loops or PLLs) to scan configuration controllers or entire Built-In Self-Test (BIST) engines for memory or logic testing. Effectively operating a large number of these functional units — which includes accessing, controlling, and observing them — presents a considerable challenge to designers.

[0009]

[0004] Traditionally, functional units are daisy-chained within a single, serial access network. This approach necessitates numerous scan operations to shift data bits into and out of these functional blocks. To reduce access time, reconfigurable scan networks can be employed as an alternative. Through specific programming operations of special elements within the access network, parts of a reconfigurable scan network can be dynamically included in or excluded from the scan path. A typical reconfigurable scan 202419433 network, conforming to IEEE 1687-2014 and IEEE 1149.1-2013, is referred to as an IJTAG network.

[0010]

[0005] By being dynamically reconfigurable, an IJTAG network can minimize the number of shift operations required for operating desired functional units, such as configuring various aspects of a circuit's test modes. However, as device complexity and the volume of diagnostic data to be extracted increase, the inherent low speed and serial nature of the IJTAG scan network are becoming a bottleneck, leading to extended test times.

[0011]

[0006] Attempts have been made to increase the speed of shift by introducing clock gaps around the transition of the controls (clock stretching) or by adding pipeline stages on the control signals with matching stages on the scan path. Unfortunately, those two techniques are mutually exclusive. While such solutions may help achieve shift speeds in the low 100 MHz range, the resulting bandwidth is still orders of magnitude lower than required. This limitation stems from the serial nature of these solutions and the two-edge timing employed when crossing clock domains.

[0012]

[0007] The IEEE1687-2014 standard supports the use of multi-chain scan interfaces. However, routing many scan chains across physical block boundaries is costly, complex, and incompatible with modern core-based design flows.

[0013]

[0008] Parallel data streaming networks have been utilized to provide fast and parallel access to a circuit’s cores (circuit blocks), significantly enhancing test data throughput. This parallel access allows cores to be accessed concurrently. For example, test data can be readily broadcast to identical cores. Parallel data streaming networks can also support infield testing, enabling efficient monitoring of a device’s state throughout its life cycle.

[0014]

[0009] Recently, a method has been developed for utilizing parallel data streaming networks to apply IJTAG configuration data. This approach, known as high-bandwidth IJTAG (HB- IJTAG) over a parallel data streaming network (e.g., Siemens EDA's Streaming Scan Network (SSN)), significantly improves IJTAG configuration time. In this method, IJTAG can operate in two modes: a global IJTAG mode and an HB-IJTAG mode. 202419433

[0015] Although serial and inherently slow, the global IJTAG mode is necessary to initialize the HB-IJTAG mode. Conventional HB-IJTAG approaches require a fallback to the global IJTAG mode after each test pattern delivery and execution by the parallel data streaming network, but before the configuration and setup data for the next test pattern can be delivered. This necessity arises because the two types of interface devices on the parallel data streaming network — one for delivering test data to the circuit under test's cores and the other for delivering test configuration and setup data to local IJTAG networks — cannot actively listen to the network simultaneously. These two interface device types implement distinct and incompatible packet protocols.

[0016] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0017]

[0010] Various aspects of the disclosed technology relate to automatic switching between two types of interface devices, enabling continuous utilization of a data streaming network to deliver data to local serial networks in a circuit. In one aspect, there is a circuit, comprising: a first network comprising multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks, each of the plurality of second networks comprising a local serial network configured to transmit data serially in one of the circuit blocks in the circuit; a third network configured to transmit data serially in the circuit; and a plurality of network switching interface devices, each of the plurality of network switching interface devices being associated with one of the circuit blocks and configured to couple either the first network or the third network to one of the plurality of second networks based on a control signal stored in a register in the each of the plurality of network switching interface devices, wherein when the first network is coupled to the one of the plurality of second networks based on the control signal, the each of the plurality of network switching interface devices is configured to: enter, based on a unique command data packet received from the first network, a sleep mode in which the each of the plurality of network switching interface devices is configured to not process data transmitted in the first network and to block a communication path between the one of the plurality of second 202419433 networks and the first network, remain in the sleep mode for a number of clock cycles specified in the unique command data packet, and exit the sleep mode, and wherein during the sleep mode, one or more circuit block interface devices that are activated among the circuit block interface devices are configured to allow corresponding circuit blocks to communicate with the first network, the activation of the one or more circuit block interface devices being based on configuration data received from a combination of the first network and corresponding second networks and subsequently on a further activation signal received from the first network. The control signal stored in the register in the each of the plurality of network switching interface devices may be received from the third network.

[0018]

[0011] The third network and the plurality of second networks may conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group). The unique command data packet may comprise a unique sequence of TMS (test mode select) bits causing a TAP (test access port) finite-state machine to enter a sequence not used for normal packets and bits specifying the number of clock cycles for the sleep mode. During the sleep mode, the each of the plurality of network switching interface devices may be configured to prevent, a locally generated clock signal from reaching the one of the plurality of second networks, a TMS signal from reaching a TAP finite-state machine, or both.

[0019]

[0012] In another aspect, there is a method, comprising: A: transmitting, via a third network in a circuit, configuration data to a plurality of network switching interface devices, wherein the third network is configured to transmit data serially in the circuit, and wherein each of the plurality of network switching interface devices is associated with one of circuit blocks in the circuit, the configuration data comprising a control signal causing a plurality of second networks to change from being coupled to the third network to being coupled to a first network, wherein each of the plurality of second networks comprises a local serial network configured to transmit data serially in one of the circuit blocks, and wherein the first network comprises multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of the circuit blocks; B: transmitting, via 202419433 the first network, setup data to the plurality of second networks, the setup data comprising test setup data for one or more of the circuit blocks and configuration data for configuring and enabling one or more of the circuit block interface devices; C: transmitting, via the first network, a unique command data packet to cause the plurality of network switching interface devices to enter a sleep mode in which the plurality of network switching interface devices are configured to not process data transmitted in the first network and to block communication paths between the plurality of second networks and the first network; D: transmitting, via the first network, a further activation signal to cause the one or more of the circuit block interface devices to be ready for communication between the first network and the one or more of the circuit blocks; E: transmitting, via the first network, test data to the one or more of the circuit blocks; F: exiting the sleep mode by the plurality of network switching interface devices after sleeping for a number of clock cycles specified in the unique command data packet; and G: repeating operations B, C, D, E and F..

[0020]

[0013] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0021]

[0014] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclose technology. Thus, for example, those skilled in the art will recognize that the disclose technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023]

[0015] Figure 1 illustrates an example of an IJTAG network. 202419433

[0024]

[0016] Figure 2 illustrates an example of a data streaming system in a circuit, in which a serial network is used for setting up core interfaces for communications with a parallel data streaming network.

[0025]

[0017] Figure 3 illustrates an example of bit assignment for data channels of the parallel data streaming network in Fig. 2.

[0026]

[0018] Figure 4A illustrates an example of a circuit block interface device such as the first interface device in Fig. 2 that may be implemented according to various embodiments of the disclosed technology.

[0027]

[0019] Figure 4B illustrates an example of a modified circuit block interface device such as the first interface device in Fig. 2 that may be implemented according to various embodiments of the disclosed technology.

[0028]

[0020] Figure 5 illustrates an example of a pipeline device that may be implemented according to various embodiments of the disclosed technology.

[0029]

[0021] Figure 6 illustrates an example of a multiplexing device that may be implemented according to various embodiments of the disclosed technology.

[0030]

[0022] Figure 7 illustrates an example of a circuit utilizing a data streaming network to increase serial network bandwidth that may be implemented according to various embodiments of the disclosed technology.

[0031]

[0023] Figure 8 illustrates an example of a network switching interface device that may be implemented according to various embodiments of the disclosed technology.

[0032]

[0024] Figure 9 illustrates an example of a detailed block diagram of a network switching interface device that may be implemented according to various embodiments of the disclosed technology. 202419433

[0033]

[0025] Figure 10 illustrates an example of a command message decoder that may be inserted into network switching interface devices according to various embodiments of the disclosed technology.

[0034]

[0026] Figure 11 illustrates an example of a TAP finite-state machine conforming to the IEEE 1149.1-2013 standard.

[0035]

[0027] Figure 12 illustrates a flowchart 1700 showing a flow of automatic switching between two types of interface devices that may be implemented according to various examples of the disclosed technology.

[0036]

[0028] Figure 13 illustrates an example of bus values for ATPG pattern delivery via a data streaming network with persistent HB(high-bandwidth) — IJTAG utilization that may be implemented according to various embodiments of the disclosed technology.

[0037] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0038] General Considerations

[0039]

[0029] Various aspects of the disclosed technology relate to automatic switching between two types of interface devices, enabling continuous utilization of a data streaming network to deliver data to local serial networks in a circuit. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the presently disclosed technology.

[0040]

[0030] The detailed description of a method or a device sometimes uses terms like “transmit” and “enable” to describe the disclosed method or the device function / structure. Such terms are high-level abstractions. The actual operations or functions / structures that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art. It should also be appreciated by one 202419433 of ordinary skill in the art that the term “coupled” means “connected directly or indirectly.”

[0041]

[0031] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods.

[0042] Reconfigurable Scan Networks

[0043]

[0032] A reconfigurable scan network conforming to IEEE 1687-2014 (IJTAG) provides, among other things, access to embedded test and test setup for manufacturing test. Fig. 1 illustrates an example of an IJTAG network 100. In the IJTAG network 100, a SIB (Segment Insertion Bit) 123 switches between two different access paths between a TDI (Test Data In) port 115 and a TDO (Test Data Out) port 117, which both belong to a TAP (Test Access Port) 110. The shorter access path directly connects the SIB 123 to a SIB 121 while the longer access path connects the SIB 123 to the SIB 121 through two TDRs (Test Data Registers) 135 and 136. A ScanMux (multiplexer) 140 selects one of two scan segments of the access network 100 (one through TDR 133 and the other through TDR 134) based on control data received. For these two scan segments to be accessed, SIBs 121 and 122 need to be programmed accordingly. A scan path can also bypass TDRs 132, 133 and 134 and reach the SIB 122 directly from TDR 131.

[0044]

[0033] As Fig. 1 shows, programmable components of a reconfigurable scan network such as the SIBs 121, 122 and 123 and the ScanMux 140 in the scan network 100 allow dynamic configuration of the access network to bring a specific functional block into the scope of the access network. These programmable components can be programmed by shifting configuration data into the shift flip-flops of the control register and latching the shifted 202419433 bits into the parallel latches in them. The functional blocks of the circuit are controlled by the TDRs 131-136. This dynamic access network configuration minimizes the number of shift operations needed for operating the desired functional block(s).

[0045]

[0034] Additional advantages of such reconfigurable scan networks are derived from the ability to configure the access network according to power and clock domains. For example, placing a SIB in front of a power domain allows the part of the access network outside of this power domain remains operational when the power domain is switched off. In a similar way, hierarchical design entities can be taken in and out of the scope of the access network, enabling the bypass of every functional object within the respective design hierarchy entity.

[0046] Data Streaming Networks

[0047]

[0035] With integrated circuits growing to include billions of transistors in some instances, it is virtually impossible to design them flat with no partitioning. Electronic Design Automation (EDA) tools would not be able to process them efficiently. Additionally, there is significant reuse of Intellectual Property (IP) from one design to another. Large designs, known as Systems-On-A-Chip (SOCs), include a large number of “cores” that are used as building blocks (also referred to circuit blocks). Each core is usually designed and validated individually first, then integrated with other cores to form the entire SOC. This is known as hierarchical design. Ideally, as much of the design and validation work is done at the core level, which is smaller and more manageable, leaving the integration and chip-level validation to be done at the top level. All work done at the core level can also be done earlier when working on the core, and moved out of the critical path when the SOC comes together closer to the tape-out deadline.

[0048]

[0036] As designs have grown, the number of levels of core hierarchy has grown as well. Hierarchical design started with two levels of hierarchy: The core level and the chip / top level. Increasingly, cores are first integrated into larger sized cores or sub-systems, then 202419433 integrated into the chip. This represents three levels of core hierarchy. Some large designs can have even more levels of core hierarchy.

[0049]

[0037] Just as designs adopt hierarchical design to manage complexity, so has scan test. In hierarchical test methodologies, the scan chains and compression logic are inserted into every core. The test patterns are generated and validated at the core level to test most of the logic in the core. Subsequently, the patterns from multiple cores are retargeted or mapped to the top level. They are also merged with retargeted patterns for other cores to be tested at the same time. In addition to retargeting patterns generated for testing most of the content of each core, test pattern generation is also run at the next level up to test peripheral logic between the cores as well as logic at that level that is involved in integrating the cores. If this higher level is not the chip level, then those patterns will also have to be retargeted to the chip level.

[0050]

[0038] The same test pattern generation and retargeting methodology is applied recursively regardless of the levels of hierarchy, but the planning and design of design for test (DFT) gets more complex with additional levels of hierarchy when using conventional scan access methods.

[0051]

[0039] Planning and implementing hierarchical scan test in SOCs has several challenges, most related to providing access to scan channels in the cores. A scan channel is a channel connecting to inputs / outputs of scan chains, inputs / outputs of test controllers for test compression, or a combination thereof. When retargeting and merging core-level patterns to the top level, usually a subset of cores are tested at any given time due to two reasons: First, the power dissipation may not allow all cores to be tested concurrently; and second, the limited number of chip-level Inputs / Outputs (I / Os, or ports) does not allow all corelevel channels to be accessed simultaneously.

[0052]

[0040] For any group of cores that are to be tested concurrently, their channel inputs and outputs need to be connected to different chip-level I / Os when employing the conventional point- to-point scan access methods (sometimes referred to as star or switch topologies). Since 202419433 there are usually more core-level channels that chip-level I / Os available for scan, the pin availability limits the number of cores that can be tested concurrently, and increases the number of groups (test sessions). Each top-level I / O can connect to a different core-level pin in each group. With the number of cores growing and the number of chip-level I / Os available for scan test diminishing, fewer and fewer cores can be accessed directly from chip-level I / Os and tested concurrently.

[0053]

[0041] A relatively recent trend in SOC design, referred to as tile-based layout, is adding further complexity and constraints to DFT architectures. In tile-based designs, virtually all logic and routing is done within the cores and not at the top level. The cores abut one another when integrated into the chip with connections flowing from one core to the next. Any connectivity between cores has to flow through cores that are between them. Logic that is logically at the top level has to be pushed into the cores and designed as part of the cores.

[0054]

[0042] A general packet-based core access architecture has been proposed to overcome the test access challenges. In this architecture, each parallel word includes the address of the core (or core group) the information is destined for, an opcode indicating what to do with that data, and the actual payload. This architecture can work for both heterogeneous and identical cores. For identical cores, it supports efficient broadcast of stimuli and expected values (good-machine responses), on-chip comparison, and accumulation of pass / fail data such that multiple identical cores could be tested in near constant time. This architecture, however, is not efficient due to its significant overhead in every parallel word. Information that is not the payload, namely the address and opcode, occupies certain number of bits. A very narrow bus would not be able to support this architecture.

[0055]

[0043] Another packet-based core access architecture reserves streamed packets all for the actual payload, and employs a separate serial network for setting up core interfaces for communications with the data streaming network. Fig. 2 illustrates an example of such a data streaming system 200 in a circuit. The data streaming system 200 comprises a first network 220 and a second network 230. The first network 220 comprises first data 202419433 channels 227 (first data bus) and first interface devices 225 (also referred to as circuit block interface devices). The second network 230 comprises one or more second data channels 237 (second data bus) and second interface devices 235. The first interface devices 225 comprises registers and clock signal generation logic. Each of the first interface devices 225 is coupled to ports of one of circuit blocks 210 in the circuit 200. Each of the first interface devices 225 is also coupled to one of the second interface devices 235. Inputs and outputs of the first data channels 227 can be connected to some chip-level I / Os (the GPIO pads). Inputs and outputs of the one or more second data channels 237 can also be connected to some other chip-level I / Os (the GPIO pads). While only one first network 220 and one second network 230 are shown in Fig. 2, a circuit can have multiple first networks 220 and one or more second networks 230.

[0056]

[0044] The first data channels in the first network 220 can be formed by chains of flip-flops, acting as pipeline stages. Some of these flip-flops are in the first interface devices 225. The first network 220 is configurable to transmit a plurality of data packets consecutively. Each of the plurality of data packets has m bits, and each of the m bits is assigned to one of the circuit blocks 210 preconfigured in an active mode. The second network 230 is configurable to transmit configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device in the first interface devices 230 is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by each of the first interface devices activated. The second network 230 may conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

[0057]

[0045] The active mode of a circuity block may be a mode for testing or a mode for loading / unloading data. Here m is equal to or greater than a number of the first data channels 225 used for the transporting the plurality of data packets. While the total number of the first data channels for a manufactured circuit is typically fixed, the number of the first data channels used for the transporting the plurality of data packets may be less than the total number. For example, a setup for wafer testing may not need all of the 202419433 first data channels 225 while a setup for testing the same circuit in a system may take advantage of all of the first data channels 225.

[0058]

[0046] Assume that the number of first data channels used for the transporting data packets is n. The first network 220 transports the data packets at a rate of one / 7-bit word per clock cycle, and if m is greater than n, the bit assignment to the circuit blocks 210 in the active mode for a particular / 7-bit word (bus word) repeats every LCM( / ?7, / 7) / / 7 clock cycles according to various embodiments of the disclosed technology. Here, LCM( / ?7, / 7) is the least common multiple of m and n. In some bit assignments, bits in each of the plurality of data packets are divided into bit blocks, bits in each of the bit blocks are next to each other except bits at two ends of the block, and each of the bit blocks is assigned to one of the circuit blocks preconfigured in the active mode. Each of the first interface devices activated can be configured to keep track of the location of its data bits in each of the bus words.

[0059]

[0047] Fig. 3 illustrates an example of bit assignment for the first data channels 225 used for transporting data packets. In this example, two circuit blocks (core A and core B) are being driven through the first network - exchanging data with the first network. One of them loads / unloads four bits per shift cycle of the circuit block, while the other loads / unloads five bits. The size of each data packet is therefore nine bits. In the figure, “Al” means data bits for the core A and “BI” means data bits for the core B. For the two circuit blocks to shift once, nine bits (in = 9) have to be delivered. The number of the first data channels used for data streaming is eight, i.e., the bus for delivering the data is eight bits wide (n = 8). The locations of the 9-bit packets within each 8-bit bus word thus rotate with each packet to use every bit of every bus word without using wasteful padding. As a result, the packet starts at the same bus bit position every nine clock cycles, i.e., repeating the same bit assignment every nine clock cycles. Further, each data packet is divided into two bit blocks. A data packet 310 in Fig. 3, for example, is divided into a bit block consisting of AI64-AI60 and a bit block consisting of BI60-BI63. 202419433

[0060]

[0048] A data packet can be as wide as needed, and can occupy as many bus words as needed. The internal channel requirements (9 bits in the example shown in Fig. 3) are decoupled from the available scan pins at the chip level (8 x 2 I / O for scan in this case). If the packet is wider than the bus and occupies multiple bus words, the circuit block can shift less often than once every bus shift cycle but it will be possible to drive all the circuit blocks needed. Because the scan bus can usually shift data at a higher rate than the circuit blocks can shift internally, it can be possible to keep the circuit blocks shifting at their maximum rates even if they do not shift every bus clock cycle. The bus (the first data channels) can be re-programmed to reduce its active width such that it does not exceed the number of bits in a packet when the packet size (in) is less than the physical bus width (n).

[0061]

[0049] A system for streaming data in a circuit that is implemented according to various embodiments of the disclosed technology may be used to deliver different types of data in the circuit such as data to be stored in memory circuitry and data for circuit testing. As noted previously, hierarchical design is used extensively nowadays. Packet-based streaming based on the disclosed technology can greatly improve test efficiency and flexibility for SOC designs. For testing one or more of the circuit blocks, each data packet comprises one or more bits of a test pattern or a compressed test pattern. Bits of multiple test patterns for testing different circuit blocks can be contained in each data packet as illustrated in Fig. 3.

[0062]

[0050] Fig. 4A illustrates an example of a first interface device (circuit block interface device) 400. The first interface device 400 has multiple static registers 410, labelled as IJT AG static registers. The multiple static registers 410 are programmed (configured) prior to the start of the streaming. IJTAG or other access mechanism may be used for delivering data for programing. If the interface device 400 is activated, bits in the bus word received from bus_in 420 will be selected and delivered to scan_in ports 430 while bits received from scan out ports 440 will be added to the bus word before the bus word is transported out through bus out 450 of the interface device 400. Because the data bits within a word that belong to a given core can rotate when the packet width is not a multiple of the bus width, the interface device 400 may use shifters to access the right bits. Additionally, 202419433 since the bits within a packet that go to a core can be spread across multiple bus words, the data may have to be collected across multiple bus clock cycles before one shift cycle within the core can occur. The same can happen for the unloaded data. The data unloaded from one cycle of the core is to be inserted into a packet. That data can occupy part of a bus word, a whole bus word, or bits spread across multiple bus words. The interface device 400 have clock generation circuitry 470 for generating edt_clock 475 and shift_cap_clock 480. A finite state machine 490 (FSM) is used to generate signals of scan en 492 and edt update 495. These clock and control signals are locally generated for scan testing. If the interface device 400 is not activated, the original bus word will bypass the internal logic and selected by a multiplexer 460 for output. As such, the interface device 400 acts as a pipeline stage within the first network.

[0063]

[0051] The first interface device 400 may be modified to allow automatic switching between two types of interface devices, circuit block interface devices like the first interface device 400 and network switching interface devices. The detailed description of allow automatic switching between two types of interface devices will be presented later. Fig. 4B illustrates an example of a modified first interface device (circuit block interface device) 405 that may be implemented according to various embodiments of the disclosed technology. For simplicity, Fig. 4B does not show some common components shared with the first interface device 400. In the figure, the modified first interface device 405 comprises a sentinel signal monitoring circuit 406. A sentinel signal is also referred to as a further activation signal since it is a signal needed for full activation after the first interface device 400 is configured and enabled by configuration data. The configuration data may be delivered by a different network such as a local IJTAG network. In Fig. 4B, the sentinel signal is represented by “11” on data channels 1 and 0 (or bus bits 1 and 0). Once the sentinel signal is detected by the sentinel signal monitoring circuit 406, the first interface device 405 will immediately start a relative offset counter 407. Once the counter 407 reaches zero, the first interface device 405 will start to process the payload data. There is an additional IJTAG configuration register in the IJTAG registers 408 that allows to selectively enable the relative offset move (relative_initial_offset_enable 409). 202419433

[0064]

[0052] In a conventional setup, a circuit block interface device may use an absolute initial offset - the number of bus clock cycles for which the circuit block interface device must wait before processing data designated for itself. To implement automatic switching between two types of interface devices, a relative initial offset may be employed since the data for one type of interface devices is transmitted immediately following the data for the other type of interface devices. Using a relative initial offset means initializing the counter only to count to the relative position within the packet. This is combined with a sentinel value that is transmitted just before the payload data. Having been configured and enabled, the first interface device 405 will wait for the sentinel value to arrive. When the sentinel value is read from the bus (the first data channels 403), the first interface device 405 will start counting down the relative offset value that determines the start position, before start processing the bus data. The sentinel signal (or the further activation signal) thus provides a mechanism for one of the two types of interface devices - the circuit block interface devices - to be fully activated at desired bus clock cycles according to various embodiments of the disclosed technology. It should be noted that “11” on data channels 1 and 0 is just an example and that different forms of the sentinel signal can be used.

[0065]

[0053] Referring to Fig. 2, the first network 220 may further comprise multiplexing devices, pipeline devices or both. Fig. 5 illustrates an example of a pipeline device 500 that may be implemented according to various embodiments of the disclosed technology. The pipeline device 500 can be used to meet timing requirements. If there is a long route between two cores, or between cores and chip-level I / Os, the propagation delay through that route may impede the ability to operate the bus at a high frequency. To reducing the length of the route that the data propagates through within one cycle, one or more pipeline devices may be inserted. Once data starts propagating through the first network 220 and nodes in the network are filled with data, there is no loss of throughput due to the presence of additional nodes such as those pipeline stages. Their presence may slightly increase latency at the start of test application.

[0066]

[0054] Fig. 6 illustrates an example of a multiplexing device 600 that may be implemented according to various embodiments of the disclosed technology. The multiplexing device 202419433

[0067] 600 can select which of two preceding nodes to connect to its output. It can serve the same purpose as a Segment Insertion Bit (SIB) node does in the IJTAG standard. Such a node allows a portion of the network to be included in the network, or bypassed when inactive. This enables among others: 1) improving efficiency by bypassing a portion of the network when not being used; 2) improving operational flexibility by allowing, for example, cores including the inactive part of the network to be powered down without breaking the operation of the active portion of the network; 3) bypassing, without disabling the entire network, a portion of the network when there is a manufacturing defect in that portion of the network; and 4) linking different width sections of the network, allowing the use of the full wider width when the smaller width section is bypassed.

[0068] Architecture For Utilizing Data StreamingNetwork To Increase Serial Network Bandwidth

[0069]

[0055] Fig. 7 illustrates an example of a circuit 700 utilizing a data streaming network to increase serial network bandwidth that may be implemented according to various embodiments of the disclosed technology. The circuit 700 comprises three circuit blocks 750, 755, 757 and a first network 710 comprising a data streaming network configured to transmit data in parallel in the circuit 700. The first network 710 comprises circuit block interface devices 760, 765, 767. Each of the circuit block interface devices 760, 765, 767 is coupled to ports of one of circuit blocks 750, 755, 757. Figs. 4A-B show examples of the circuit block interface devices 760, 765, 767. The first network 710 can be configured to transmit test data into and transmit test response data out of the circuit blocks 750, 755, 757 via the corresponding circuit block interface devices 760, 765, 767.

[0070]

[0056] The first network 710 may be implemented using the two packet-based core access systems discussed previously. The data streaming system 200 shown in Fig. 2 is one of them. Like the data streaming system 200, the first network 710 may be reconfigurable - capable of bypassing one or more circuit blocks for data streaming. To achieve configurability, devices like the multiplexing device 600 shown in Fig. 6 may be employed. 202419433

[0071]

[0057] The circuit 700 also comprises second networks 720, 725, 727 and a third network 730. Each of the second networks 720, 725, 727 is configured to transmit data in serial in one of the circuit blocks 750, 755, 757. As Fig. 7 shows, the second networks 720, 725 and 727 are located in the circuit blocks 750, 755 and 757, respectively. The third network 730 is configured to transmit data in serial in the circuit 700. The third network 730 can be coupled to one or more of the second networks 720, 725, 727 via corresponding network switching interface devices 740, 745 and 747. The second networks 720, 725, 727 and the third network 730 may be reconfigurable. Conventionally, the second networks 720, 725 and 727 are coupled to the third network 730 to form a single serial network which can be used for, for example, test setup. An example of such a network is an IJTAG network.

[0072]

[0058] Each of the network switching interface devices 740, 745 and 747 is configured to couple either the first network 710 or the third network 730 to the respective second network in the second networks 720, 725, 727 based on a control signal stored in a register in each of the network switching interface devices 740, 745 and 747. For example, the network switching interface device 740 can allow the second network 720 to be coupled to either the first network 710 or the third network 730. The first network 710 is parallel in nature and may be able to operate at a much higher frequency than the serial network formed by a combination of the third network 730 and the plurality of second networks. Thus, the ability to couple the first network 710 to the second networks 720, 725 and 727 can significantly increase the bandwidth for transmitting data into and out of the circuit blocks 750, 755 and 757 for devices served by the second networks 720, 725 and 727. This high-bandwidth mode can be used to deliver setup data that may comprise test setup data for the circuit blocks 750, 755, 757 and configuration data to configure and activate one or more of the circuit block interface devices 760, 765, 767. The circuit block interface devices are shown as the first interface devices 225 in Fig. 2, which are configured and activated by data transmitted via the second network 230 and the second interface devices 235. The second interface devices 235 may not be needed here since the configuration and activation data may be transferred via the first network 710, the 202419433 network switching interface devices 740, 745, 747, and the second networks 720, 725 and 727. Here the second networks 720, 725 and 727 are shown to be coupled to the corresponding circuit block interface devices 760, 765, 767.

[0073]

[0059] Fig. 8 illustrates an example of a network switching interface device 800 that may be implemented according to various embodiments of the disclosed technology. The network switching interface device 800 is configured to couple a local network 820 (the second network 720 / 725 / 727 in Fig. 7) to either a serial network 830 (the third network 730 in Fig. 7) or a parallel network 810 (the first network 710 in Fig. 7) based on a control signal stored in a register 840. The control signal stored in the register 840 can be updated using either the serial network 830 when the serial network 830 is coupled to the local network 820 or the parallel network 810 when the parallel network 810 is coupled to the local network 820. As such, the access to the local network 820 via either the parallel network 810 or the serial network 830 can be changed dynamically.

[0074]

[0060] Fig. 9 illustrates an example of a detailed block diagram of a network switching interface device 900 that may be implemented according to various embodiments of the disclosed technology. The network switching interface device 900 is configured to couple a local IJTAG network 920 (second network) to either a third network 930 (serial network) or a first network 910 (parallel network) depending on a control bit stored in an SIH enable register 950. The control bit stored in the SIH enable register 950 can be updated via either the first network 910 or the third network 930 depending on the stored bit before the update operation. The first network 910 has eight data channels SiN - SoN (N = 0- 7). Here, the data channel SiO - SoO is used to transmit a TMS (Test Mode Select) signal 911 when the local IJTAG network 920 is coupled to the first network 910. The TMS signal 911 is a control signal supplied by a TAP (Test Access Port) controller conforming to JTAG (Joint Test Action Group, IEEE 1149.1). The network switching interface device 900 can use the TMS signal 911 to drive a finite-state machine (FSM) 949 which controls shift, capture and update operations of data registers. The other seven data channels SiN - SoN (N = 1-7) can be used to transmit data into and out of the local 202419433

[0075] IJTAG network 920 when the local IJTAG network 920 is coupled to the first network 910.

[0076]

[0061] The network switching interface device 900 comprises two registers 940 and 945 for the first network 910. Each of the registers 940 and 945 may comprise eight flip-flops, one for each data channel of the first network 910. The two flip-flops in the registers 940 and 945 for each channel are connected in serial, serving as two pipeline stages of the first network 910.

[0077]

[0062] The network switching interface device 900 also comprises a multiplexer device 947, a host SIB 960, a configuration SIB 970, a broadcast control unit 980, and a configuration unit 990. The multiplexer device 947 is configured to select one of the seven data channels SiN - SoN (N = 1-7) to be coupled to the local IJTAG network 920. The host SIB 960 and the configuration SIB 970 are typical IJTAG segment insertion bit devices like those shown in Fig. 1. The host SIB 960 determines whether the local IJTAG network 920 is to be bypassed or not. The configuration SIB 970 determines whether the configuration unit 990 is to be bypassed or not. The configuration unit 990 is configured to store control bits including ones determining at which clock cycle (stored in a register 991) and from which data channel of the first network 910 the local IJTAG network 920 receives data (stored in a register 992) and ones representing the ratio between the global clock frequency and the local clock frequency (stored in a register 993). The broadcast control unit 980 is configured to stored control bits for output from the local IJTAG network 920 in the broadcast mode. The first network 910 can be coupled to the local IJTAG network 920 in at least three modes: a daisy chain mode, a broadcast mode, and a parallel mode. A description of these modes can be found in US Patent No. 12,314,207.

[0078]

[0063] If the SIH enable register 950 is set to ‘ 1 ’ for delivering test patterns to circuit cores via the first network 910 and circuit block interface devices like the modified first interface device 405 in Fig. 4B while keeping the network switching interface device 900 not deactivated, there would be a high risk of changing the value of any of the internal registers in the network switching interface device 900 or the registers in the local IJTAG 202419433 network 920. This is because the test pattern’s value on bit 0 of the first network 910 would be interpreted by the FSM 949 as the TMS signal 911, causing its state to change and corrupting the IJTAG network. To solve this problem without being deactivated, the network switching interface device 900 may be configured to enter a sleep mode when the first network 910 is transmitting test data to the circuit blocks via the circuit block interface devices according to various embodiments of the disclosed technology.

[0079]

[0064] The sleep mode can be initiated by a unique command data packet transmitted via the first network 910. The sleep mode is a mode in which the network switching interface devices are configured to block communication paths between and the second networks (e.g., the local IJTAG network 920) and the first network and to not process data transmitted in the first network. After sleeping for a number of clock cycles specified in the unique command data packet, the network switching interface devices can automatically wake up and exit the sleep mode to process the data designated to them on the data bus (the first network). While the network switching interface devices are in the sleep mode, the circuit block interface devices that are that are activated are configured to allow corresponding circuit blocks to communicate with the first network, After the communication is completed, the circuit block interface devices are deactivated. A circuit block interface device can be activated based on two steps. First, the circuit block interface device is enabled for monitoring data transmitted in the first network based on configuration data received from a combination of the first network and a corresponding second network. Second, the circuit block interface device is fully activated for processing data designated to it in the first network based on a further activation signal received from the first network. Alternative transmission of the further activation signal (the sentinel signal) and the unique command data packet can enable automatic switching between the two types of interface devices.

[0080]

[0065] To implement the sleep mode operation, the network switching interface device 900 may be modified by adding a command message decoder configured to decode the unique command data packet. The modification may include two more changes: circuit for suppression of the TMS signal, the locally generated clock signal, or both. Fig. 10 202419433 illustrates an example of a command message decoder 1000 that may be inserted into network switching interface devices according to various embodiments of the disclosed technology. The command message decoder 1000 is configured to decode the unique command data packet transmitted through a parallel network 1010 (the first network 910 in Fig. 9) and to generate a sleep mode signal 1020. The command message decoder 1000 comprises a special sequence detection finite-state machine (FSM) 1030 and a command message decoder 1040. The detection of the unique command data packet by the special sequence detection FSM 1030 can activate the command message decoder 1040. The command message decoder 1040 reads bits 7 down to 1 of the parallel network 1010 during the Update-DR FSM state as the command opcode. To activate the sleep mode, the opcode may be set as “000 0000”. If this opcode is received, the sleep counter loading mechanism is triggered. Four 7-bit words representing the number of clock cycles for the sleep mode are loaded into a counter 1050. Then, after receiving the sentinel signal which is used to activate the other type of interface devices like the circuit block interface devices 740, 745, 747 in Fig. 7, the counter 1050 starts to count down the value. The sleep mode signal 1020 is set high until the counter 1050 reaches 0.

[0081]

[0066] In Fig. 10, the inversion version of the sleep mode signal 1020 is shown to control two AND gates 1070, 1080. When the network switching interface device is in the sleep mode, the sleep mode signal 1020 is asserted. As such, the AND gate 1070 blocks a clock signal 1060 generated in the network switching interface device from reaching the hosted IJTAG network 1095 (the local IJTAG network 920 in Fig. 9), and the AND gate 1080 blocks bit 0 of the parallel bus 1010 from reaching the TAP FSM 1090 (the FSM 949 in Fig. 9) in the network switching interface device. The suppressing of the clock signal 1060 to the internal and hosted IJTAG network 1095 can save power. The suppression of bit 0 of the parallel bus 1010 to the TAP FSM 1090 can prevent the latter from changing and corrupting the hosted IJTAG network 1095. Bit 0 of the parallel bus 1010 is treated by the network switching interface device as the TMS (test mode select) signal according to some embodiments of the disclosed technology. The TMS signal is used to control a local TAP FSM 1090, which is responsible for generating the IJTAG control 202419433 signals. By keeping the TMS signal at ‘0’ during the sleeping mode, the local TAP FSM 1090 will remain in the RunTestldle state, and the value of any of the registers in the network switching interface device or registers in the hosted IJTAG network 1095 will not change. The suppression, along with closing the host SIB 960 and the configuration SIB 970 allows the state of both the local IJTAG network and the network switching interface device to be maintained.

[0082]

[0067] The unique command data packet may include a unique sequence of TMS bits causing a TAP FSM to enter a sequence not used for normal packets. Fig. 11 illustrates an example of a TAP finite-state machine 1100 conforming to the IEEE 1149.1-2013 standard. The TAP finite-state machine 1100 progresses on the test clock (TCK) edge, with the value of the test mode select (TMS) pin controlling the behavior. Assuming the TAP finite- state machine 1100 begins at Test-Logic-Reset, the test clock moves, when TMS = 0, the TAP finite-state machine 1100 into the Run-Test / Idle state, and then moves, when TMS = 1, the TAP finite-state machine 1100 into the state of selecting a path, either entering a data register path 1110 or the Select-IR state which can enter an instruction register path 1120. The data register path 1110 includes three important states: Capture-DR, Shift-DR and Update-DR. In the Capture-DR state, the shift element of the data register loads data bits present at their parallel inputs. In the Shift-DR state, the shift element of the data register shifts data bits along the scan path from TDI to TDO. In the Update-DR state, the data bits in the shift element of the data register are latched into the storage element of the data register. The unique sequence of TMS bits for activating the sleep mode that starts from the Run-Test / Idle state may be “ 10110”. This sequence corresponds to a specific TAP finite-state machine sequence: Idle Select-DR — - Capture-DR — -

[0083] Exitl-DR — - Update-DR — - Idle. The sequence skips the Shift-DR state and after Exitl- DR, goes directly to Update-DR. This sequence is never used during HB-IJTAG pattern delivery. Thus, it is safe to use this sequence for the unique command data packet.

[0084] Methods for Automatic Switching Between Two Types of Interface Devices 202419433

[0085]

[0068] Fig. 12 illustrates a flowchart 1700 showing a flow of automatic switching between two types of interface devices that may be implemented according to various examples of the disclosed technology. For ease of understanding, methods for automatic switching between two types of interface devices that may be employed according to various embodiments of the disclosed technology will be described with reference to the circuit 700 in Fig. 7 and the flow chart 1200 illustrated in Fig. 12. It should be appreciated, however, that alternate implementations of a circuit that utilizes a data streaming network to increase serial network bandwidth may be used to perform the methods for automatic switching between two types of interface devices illustrated by the flow chart 1200 according to various embodiments of the disclosed technology. Likewise, the circuit 700 may be employed to perform other methods for automatic switching between two types of interface devices according to various embodiments of the disclosed technology.

[0086]

[0069] In operation 1210 of the flow chart 1200, configuration data is transmitted, via the third network 730, to the network switching interface devices 740, 745, 747. The third network 730 is configured to transmit data serially in the circuit 700. The circuit 700 comprises three circuit blocks 750, 755, 757, of which each is associated with one of the second networks 720, 725, 727 and with one of the network switching interface devices 740, 745, 747. Each of the second networks 720, 725, 727 comprises a local serial network configured to transmit data serially in the circuit block it is associated with. The third network 730 can be coupled to one or more of the second networks 720, 725, 727 through the corresponding network switching interface devices to form one serial network, which may be referred to as a global serial network.

[0087]

[0070] The configuration data includes a control signal causing the second networks 720, 725, 727 to change from being coupled to the third network 730 to being coupled to the first network 710. The first network 710 comprises multiple data channels configured to transmit data in parallel in the circuit 700. The first network 710 further comprises the circuit block interface devices 760, 765, 767. Each of the circuit block interface devices 760, 765, 767 is coupled to ports of one of the circuit blocks 750, 755, 757. 202419433

[0088]

[0071] In operation 1220 of the flow chart 1200, setup data is transmitted, via the first network 710, to the second networks 720, 725, 727. The setup data can include test setup data for one or more of the circuit blocks 750, 755, 757, which may be used to initialize the corresponding circuit blocks (e.g., to enable the on-chip oscillators or to unlock a security module). The setup data can also include configuration data for configuring and enabling one or more of the circuit block interface devices 760, 765, 767. Once a circuit block interface is configured and enabled (or turned on), it can start to monitor whether a further activation signal arrives via the first network 710.

[0089]

[0072] In operation 1230 of the flow chart 1200, a unique command data packet is transmitted, via the first network 710, to cause the network switching interface devices 740, 745, 747 to enter a sleep mode. The sleep mode is a mode in which the network switching interface devices 740, 745, 747 are configured to not process data transmitted in the first network 710 and to block communication paths between the second networks 720, 725, 727 and the first network 710. Even though the network switching interface devices 740, 745, 747 are not deactivated, they act like pipeline stages of the first network 710, ignoring data transmitted in the first network 710 for one or more of the circuit block interface devices 760, 765, 767. As discussed previously, some control and clock signals (e.g., the TMS and locally generated clock signals) may be suppressed during the sleep mode.

[0090]

[0073] In operation 1240 of the flow chart 1200, a further activation signal (sentinel signal) is transmitted, via the first network 710, to cause the one or more of the circuit block interface devices 760, 765, 767 to be ready for communication between the first network 710 and the one or more of the circuit blocks 750, 755, 757. After this operation, the one or more of the circuit block interface devices 760, 765, 767 are fully activated and are able to process the data in the first network 710.

[0091]

[0074] In operation 1250 of the flow chart 1200, test data is transmitted, via the first network 710, to the one or more of the circuit blocks 750, 755, 757. During this operation, the network switching interface devices 740, 745, 747 are in the sleep mode. After the 202419433 transmission is completed, the one or more of the circuit block interface devices 760, 765, 767 become deactivated, stopping interacting with the first network 710.

[0092]

[0075] In operation 1260 of the flow chart 1200, the network switching interface devices 740, 745, 747 exit the sleep mode after sleeping for a number of clock cycles specified in the unique command data packet.

[0093]

[0076] The operations 1220-1260 may be repeated for different circuit blocks and / or different test sets until the test is completed.

[0094]

[0077] The third network and the second networks may conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group). Fig. 13 illustrates an example of bus values for ATPG pattern delivery via a data streaming network with persistent HB(high- bandwidth) — IJTAG utilization that may be implemented according to various embodiments of the disclosed technology. The figure shows the full sequence of bus values that are necessary for the hand-off of the data streaming network before and after the ATPG pattern payload.

[0095]

[0078] After the last normal HB-IJTAG operation 1310, the network switching interface device receives a unique command data packet 1320 that puts it into the sleep mode for a number of clock cycles specified in the unique command data packet. To distinguish unique command data packet 1320 from a normal IJTAG payload packet, it utilizes a specific TAP state machine sequence that is typically not used for normal packets: Idle — - Select DR Capture DR Exitl DR Update DR Idle.

[0096]

[0079] Following this TAP sequence, the network switching interface device reads 7 bits of the bus (the data streaming network) from bit 7 down to bit 1 (the LSB bit is reserved for TMS). These 7 bits are the operation code (opcode) of the command packet. Then, depending on the opcode, a number of command payload bits 1330 are transmitted. To place the network switching interface device into the sleep mode, the opcode is “000 0000”. It is followed by four more 7-bit words that specify the number of bus clock cycles that the network switching interface device should sleep for. For both the opcode and the 202419433 payload, bit 0 is always ‘O’. This ensures that the circuit block interface devices do not see their sentinel signal during HB-IJT AG programming. The command packet ends with AT padding idle cycles 1340 to allow all the counters along the data streaming network to return to 0 before the data streaming network payload begins. This may be necessary since the data streaming network ATPG payload assumes initial counter values of 0.

[0097]

[0080] Next, ATPG patterns 1350 for the circuit block interface devices are delivered. These patterns begin with a sentinel signal ("11" on bus bits 1 and 0) that activate the circuit block interface devices. During this stage, the network switching interface devices are in the sleep mode and count the number of bus clock cycles until they have to wake up again. The payload sequence ends with a different set of N padding idle cycles 1360 to return all the counters along the data streaming network to 0 for the handoff between the patterns.

[0098] 202419433

[0099] Conclusion

[0100]

[0081] While the disclosed technology has been described with respect to specific examples including presently preferred modes of carrying out the disclosed technology, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and technology that fall within the spirit and scope of the disclosed technology as set forth in the appended claims. For example, while the data streaming network shown in Fig. 2 has been employed to describe the disclosed technology, it should be appreciated that other parallel network may be utilized to increase the serial network bandwidth.

Claims

202419433What is claimed is:

1. A circuit, comprising: a first network comprising multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks, each of the plurality of second networks comprising a local serial network configured to transmit data serially in one of the circuit blocks in the circuit; a third network configured to transmit data serially in the circuit; and a plurality of network switching interface devices, each of the plurality of network switching interface devices being associated with one of the circuit blocks and configured_to couple either the first network or the third network to one of the plurality of second networks based on a control signal stored in a register in the each of the plurality of network switching interface devices, wherein when the first network is coupled to the one of the plurality of second networks based on the control signal, the each of the plurality of network switching interface devices is configured to: enter, based on a unique command data packet received from the first network, a sleep mode in which the each of the plurality of network switching interface devices is configured to not process data transmitted in the first network and to block a communication path between the one of the plurality of second networks and the first network, remain in the sleep mode for a number of clock cycles specified in the unique command data packet, and202419433 exit the sleep mode, and wherein during the sleep mode, one or more circuit block interface devices that are activated among the circuit block interface devices are configured to allow corresponding circuit blocks to communicate with the first network, the activation of the one or more circuit block interface devices being based on configuration data received from a combination of the first network and corresponding second networks and subsequently on a further activation signal received from the first network.

2. The circuit recited in claim 1, wherein the control signal stored in the each of the plurality of network switching interface devices is received from the third network.

3. The circuit recited in claim 1, wherein the third network and the plurality of second networks conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

4. The circuit recited in claim 3, wherein the unique command data packet comprises a unique sequence of TMS (test mode select) bits causing a TAP (test access port) finite-state machine to enter a sequence not used for normal packets and bits specifying the number of clock cycles for the sleep mode.

5. The circuit recited in claim 3, wherein during the sleep mode, the each of the plurality of network switching interface devices is configured to prevent, a locally generated clock signal202419433 from reaching the one of the plurality of second networks, a TMS signal from reaching a TAP finite-state machine, or both.

6. A method, comprising:A: transmitting, via a third network in a circuit, configuration data to a plurality of network switching interface devices, wherein the third network is configured to transmit data serially in the circuit, and wherein each of the plurality of network switching interface devices is associated with one of circuit blocks in the circuit, the configuration data comprising a control signal causing a plurality of second networks to change from being coupled to the third network to being coupled to a first network, wherein each of the plurality of second networks comprises a local serial network configured to transmit data serially in one of the circuit blocks, and wherein the first network comprises multiple data channels configured to transmit data in parallel in the circuit and circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of the circuit blocks;B: transmitting, via the first network, setup data to the plurality of second networks, the setup data comprising test setup data for one or more of the circuit blocks and configuration data for configuring and enabling one or more of the circuit block interface devices;C: transmitting, via the first network, a unique command data packet to cause the plurality of network switching interface devices to enter a sleep mode in which the plurality of network switching interface devices are configured to not process data transmitted in the first network and to block communication paths between the plurality of second networks and the first network;202419433D: transmitting, via the first network, a further activation signal to cause the one or more of the circuit block interface devices to be ready for communication between the first network and the one or more of the circuit blocks;E: transmitting, via the first network, test data to the one or more of the circuit blocks;F: exiting the sleep mode by the plurality of network switching interface devices after sleeping for a number of clock cycles specified in the unique command data packet; andG: repeating operations B, C, D, E and F.

7. The method recited in claim 6, wherein the third network and the plurality of second networks conform to the IEEE 1687 standard (IJTAG, Internal Joint Test Action Group).

8. The method recited in claim 7, wherein the unique command data packet comprises a unique sequence of TMS (test mode select) bits causing a TAP (test access port) finite-state machine to enter a sequence not used for normal packets and bits specifying the number of clock cycles for the sleep mode.

9. The method recited in claim 7, wherein during the sleep mode, the each of the plurality of network switching interface devices is configured to prevent, a locally generated clock signal from reaching the one of the plurality of second networks, a TMS signal from reaching a TAP finite-state machine, or both.

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