Chip stack structure and preparation method therefor, and electronic device
By decoupling the through-silicon via (TSV) bridging chip from the active chip, arranging them side-by-side, and connecting them with redistribution layers, the problems of low chip area utilization and high manufacturing cost in existing 3D stacking structures are solved, achieving efficient chip stacking and heat dissipation.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-06-05
- Publication Date
- 2026-05-15
AI Technical Summary
In existing 3D stacking structures, it is difficult to achieve more layers of chip stacking using wire bonding, and TSV structures occupy active area and prolong the manufacturing process, resulting in low chip area utilization and high cost.
By decoupling the through-silicon via (TSV) bridging chip from the active chip and using side-by-side layout and redistribution layer connection, vertical interconnection is achieved, avoiding the need for TSVs in the active chip, simplifying the process flow and improving area utilization.
It improves the area utilization of active chips, simplifies the manufacturing process, reduces manufacturing costs, and enhances the number of chip stacking layers and heat dissipation.
Smart Images
Figure CN2025099372_15052026_PF_FP_ABST
Abstract
Description
Chip stacking structure and its fabrication method, electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202411606899.1, filed on November 11, 2024, entitled "Chip Stacking Structure and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a chip stacking structure, an electronic device including the chip stacking structure, and a method for fabricating the chip stacking structure. Background Technology
[0003] As Moore's Law gradually reaches its limits, various chips, such as memory chips or logic chips, will inevitably move towards 3D stacking to form a three-dimensional integrated circuit (3D-IC) structure.
[0004] In related 3D stacked structures, wire bonding can be used to bring out each chip layer, but this makes it difficult to stack more layers of chips. In addition, some multi-chip stacked structures use through-silicon via (TSV) structures, which occupy the active area of the chip and lengthen and complicate the manufacturing process. Summary of the Invention
[0005] This application provides a chip stacking structure, an electronic device including the chip stacking structure, and a method for fabricating the chip stacking structure. The main objective is to optimize the chip stacking structure by separating the manufacturing processes of TSVs and active chips into parallel processes, thereby improving the area utilization and yield of active chips.
[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0007] In one aspect, this application provides a chip stacking structure, for example, the chips in the chip stacking structure may include memory circuits, logic circuits or digital circuits, etc.
[0008] The chip stacking structure includes a substrate and a multilayer structure stacked three-dimensionally on the substrate. The multilayer structure may include a first layer and a second layer. Either the first layer or the second layer may include a first chip and a first through-silicon via (TSV) bridging chip, as well as a redistribution layer. The first TSV bridging chip is arranged side by side with the first chip, such as the first TSV bridging chip and the first chip being arranged in a direction parallel to the surface of the substrate. The redistribution layer is arranged parallel to the surface of the substrate and connects the first TSV bridging chip and the first chip.
[0009] In the three-dimensional stacked chip structure provided in this application, any layer includes a first chip and a first through-silicon via (TSV) bridging chip arranged side by side, and a redistribution layer is provided on one side of the first TSV bridging chip and the first chip. For example, a second layer is stacked on the first layer, and electrical signals or voltages in the second layer can be transmitted to the substrate through the redistribution layer, the first TSV bridging chip in the second layer, and the first TSV bridging chip in the first layer, thereby achieving vertical interconnection. The TSV bridging chip and the active chip in the layer structure do not overlap in their orthographic projections.
[0010] In addition, this application uses through-silicon via (TSV) bridging chips as the electrical connection structure for vertical interconnection. That is, the TSV is not placed in the active chip (such as the first chip), but is decoupled from the active chip, which can improve the area utilization of the active chip. This structure can realize the stacking of multi-layer structures, such as more than four layers.
[0011] This application decouples through-silicon vias (TSVs) from active chips. Compared with placing TSVs in active chips, this not only simplifies the active chip process and reduces manufacturing difficulty, but also decouples and improves yield and reduces the manufacturing cost of TSV-based stacked chips.
[0012] In one possible implementation, a first through-silicon via (TSV) bridging chip of a first-layer structure and a second through-silicon via (TSV) bridging chip of a second-layer structure are disposed opposite each other in a direction perpendicular to the substrate surface; the first TSV bridging chip of the first-layer structure and the second through-silicon via (TSV) bridging chip of the second-layer structure are electrically connected.
[0013] This application utilizes three-dimensionally stacked through-silicon via (TSV) bridging chips to achieve vertical interconnection between active chips and a substrate. As independent chips used for vertical electrical connections, the TSV bridging chips are easily stacked in three dimensions during manufacturing, thus posing no challenges to the process and correspondingly reducing production costs.
[0014] In one possible implementation, the chip stack structure also includes a top layer structure; the top layer structure includes a top chip, but does not include a through-silicon via (TSV) bridging chip; the substrate of the top chip is located on the side of the active layer away from the substrate.
[0015] In this example, the substrate of the top chip is further away from the substrate than the active layer, meaning that the substrate of the top chip is exposed with its face upwards. This enhances heat dissipation and further improves the heat dissipation effect of the stacked structure.
[0016] In one possible implementation, the chip stack structure also includes a heat dissipation structure disposed on the substrate of the top chip.
[0017] Since the substrate of the top chip faces upwards, a heat dissipation structure can be placed over the substrate, which can quickly conduct heat to the stacked structure and improve the heat dissipation effect.
[0018] In one possible approach, a redistribution layer is disposed on the side of the active layer of the top-layer chip that is away from the substrate.
[0019] In this way, the top-level chip can be vertically interconnected with the substrate through the redistribution layer located below it and the vertically stacked through-silicon vias bridging the chips.
[0020] In one possible implementation, the chip stack structure also includes a molding compound layer, with the multilayer structure located within the molding compound layer and the substrate of the top chip exposed outside the molding compound layer.
[0021] In other words, the molding layer does not cover the substrate of the top chip, and the substrate of the top chip is exposed, which can improve heat dissipation.
[0022] In one possible implementation, the top-level structure includes a silicon structure. For example, the silicon structure is disposed on the outer periphery of the top-level chip.
[0023] Setting up a silicon structure in the top layer can improve the thermal conductivity, balance stress, improve heat dissipation of the entire chip stack structure, and reduce the warpage of the stack structure.
[0024] In one possible implementation, a first layer is stacked on a substrate, and a second layer is stacked on the first layer; in either the first or second layer, a redistribution layer is disposed on the side of the first through-silicon via (TSV) bridging chip and the first chip away from the substrate; the first chip and the first TSV bridging chip in the second layer are connected to the redistribution layer in the first layer via an electrical connection structure.
[0025] For example, the electrical connection structure can be fabricated using a microbump bonding process or a hybrid bonding process. Electrical connection structures fabricated using these processes have a higher thermal conductivity, which is beneficial for heat dissipation of the stacked structure.
[0026] In one feasible manner, in either the first or second layer structure, the substrate of the first chip is located on the side of the active layer away from the substrate.
[0027] This can be understood as follows: the substrate of the first chip faces upward and the active layer faces downward. This can further improve the heat dissipation effect of the chip. While ensuring effective heat dissipation, it can also increase the number of chip stacking layers.
[0028] In feasible fabrication processes, after obtaining the redistribution layer of the first layer structure, a hybrid bonding process or a microbump bonding process can be used to place the first chip of the second layer structure and the first through-silicon via bridging chip above the redistribution layer of the first layer structure.
[0029] In one possible implementation, the first chip and the first through-silicon via (TSV) bridging chip in the second layer structure are electrically connected through a redistribution layer in the first layer structure, and / or; the first chip and the TSV bridging chip in the second layer structure are electrically connected through a redistribution layer in the first layer structure.
[0030] In this way, the electrical signal or voltage of the first chip in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip in the second layer structure through the redistribution layer in the first layer structure. The first TSV bridge chip in the second layer structure is connected to the first TSV bridge chip in the first layer structure. The first TSV bridge chip in the first layer structure is connected to the substrate, thereby realizing the vertical interconnection between the first chip in the second layer structure and the substrate.
[0031] Alternatively, the electrical signal or voltage of the first chip in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip in the first layer structure through the redistribution layer in the first layer structure. The first TSV bridging chip in the first layer structure is connected to the substrate, thereby achieving vertical interconnection between the first chip in the second layer structure and the substrate.
[0032] In one feasible approach, the active layer of the first chip in the first layer structure can be vertically interconnected with the substrate via an electrical connection structure.
[0033] In one possible implementation, in either the first or second layer structure, the active layer of the first chip is located on the side of the substrate away from the substrate.
[0034] That is, the substrate of the first chip faces down and the active layer faces up.
[0035] In one possible implementation, the first chip and the first through-silicon via (TSV) bridging chip in the second layer structure are electrically connected through a redistribution layer in the second layer structure.
[0036] For example, the first chip in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip in the second layer structure through a redistribution layer. The first TSV bridging chip in the second layer structure is connected to the first TSV bridging chip in the first layer structure. The first TSV bridging chip in the first layer structure is connected to the substrate, thereby achieving vertical interconnection between the first chip in the second layer structure and the substrate.
[0037] In one feasible approach, the first chip in the first layer structure can be connected to the first through-silicon via (TSV) bridging chip in the first layer structure via a redistribution layer, and the first TSV bridging chip in the first layer structure is connected to the substrate, thereby achieving vertical interconnection between the first chip in the first layer structure and the substrate.
[0038] In one possible implementation, a first layer is stacked on a substrate, and a second layer is stacked on the first layer; in the first layer, the active layer of the first chip is located on the side of the substrate away from the substrate; in the second layer, the substrate of the first chip is located on the side of the active layer away from the substrate; a redistribution layer is disposed between the first layer and the second layer, and the first layer and the second layer share the same redistribution layer.
[0039] In other words, in the adjacent first and second layer structures, the active chips are arranged face to face, and the two layers share the same redistribution layer. This reduces the number of redistribution layers in the entire chip stack structure and simplifies the process flow.
[0040] In one possible implementation, the redistribution layer located between the first layer structure and the second layer structure is a shared redistribution layer; the first chip and the first through-silicon via (TSV) bridging chip in the first layer structure are connected through the shared redistribution layer; the first chip and the first TSV bridging chip in the second layer structure are connected through the shared redistribution layer.
[0041] In one possible implementation, the first layer structure also includes a second chip stacked on top of the first chip, with the substrates of the first chip and the substrates of the second chip disposed opposite to each other.
[0042] This can be understood as a three-dimensional stacking of the first and second chips to increase the number of chips integrated and the integration density. In this example, the two chips are set back to back, which can reduce the number of chips bridged by through-silicon vias in the chip stacking structure, and can also reduce the number of molding processes, simplifying the structure and simplifying the process.
[0043] In one possible implementation, the first layer structure also includes a third chip, which is arranged in a direction parallel to the surface of the substrate.
[0044] More chips can be integrated into the chip layer structure to increase the chip integration density.
[0045] In one possible implementation, the first layer structure further includes a second chip and a third chip, which are arranged side by side, with the second chip stacked on top of the first and third chips; the substrates of the first chip and the second chip are arranged opposite each other, and the substrates of the third chip and the second chip are arranged opposite each other, with the first layer structure located at the bottom layer of the multilayer structure.
[0046] In one possible implementation, the first layer structure further includes a second through-silicon via (TSV) bridging chip; the first TSV bridging chip, the second TSV bridging chip, and the first chip are arranged in a direction parallel to the substrate surface. For example, the chip stack structure includes a chip integration region for integrating chips, with the first chip disposed in the chip integration region, and the first and second TSV bridging chips disposed around the periphery of the chip integration region. The TSV bridging chips and the active chips do not overlap in orthographic projection.
[0047] This arrangement of chips and active chips via silicon vias is relatively simple, simplifying the manufacturing process and reducing manufacturing costs.
[0048] In one feasible approach, a multi-layered structure must include at least three layers. For example, it could have four layers, or more.
[0049] In one possible implementation, the chip stacking structure also includes an interposer; the multilayer structure is disposed on the interposer, which is disposed on a substrate.
[0050] Secondly, this application also provides an electronic device, which includes a circuit board and a chip stacking structure as described in any of the above implementations, the chip stacking structure being disposed on the circuit board.
[0051] The electronic device provided in this application includes a chip stacking structure as described in any of the above implementations. In this chip stacking structure, the through-silicon via (TSV) bridging chip and the active chip are disposed in the same layer, rather than stacked. This increases the number of chip stacking layers. Furthermore, the TSV bridging chip and the active chip are decoupled, and the TSV is not disposed in the active chip. This improves the heat dissipation of the active chip, increases the area utilization of the active chip, avoids the impact of TSV stress on the chip, reduces manufacturing costs, and is easy to implement in terms of process.
[0052] Thirdly, this application also provides a method for fabricating a chip stacked structure, the method comprising:
[0053] The first chip and the first through-silicon via (TSV) bridging chip are arranged side by side on the carrier board, with the arrangement direction of the first chip and the first TSV bridging chip parallel to the surface of the carrier board.
[0054] A redistribution layer is disposed on the first chip and the first through-silicon via (TSV) bridging chip to obtain the first layer structure;
[0055] A first chip and a first through-silicon via (TSV) bridging chip, as well as a redistribution layer, are disposed on the redistribution layer of the first layer structure to obtain the second layer structure.
[0056] Remove the carrier board;
[0057] A structure comprising a stacked first layer and a second layer is disposed on a substrate.
[0058] In the chip stacking structure obtained by this application, the first chip and the first through-silicon via (TSV) bridging chip are two independent chips, and these two chips are arranged side by side. This can increase the number of chip stacking layers. The TSV bridging chip and the active chip are decoupled, which can improve the area utilization of the active chip.
[0059] In one possible implementation, the first chip and the first through-silicon via (TSV) bridging chip are disposed side-by-side on a carrier board, including: the substrate of the first chip is located on the side of the active layer away from the carrier board.
[0060] With the substrate of the first chip facing upwards, the heat dissipation of the stacked structure can be optimized, thus improving the heat dissipation effect.
[0061] In one possible implementation, the first chip and the first through-silicon via (TSV) bridging chip are disposed side-by-side on a carrier board, comprising: stacking the first chip and the second chip, with the substrates of the first chip and the second chip disposed opposite to each other; and placing the stacked first chip and second chip, along with the first TSV bridging chip, side-by-side on the carrier board.
[0062] In some chip layer structures, active chips are stacked in three dimensions, which can increase chip stacking density, reduce the number of molding processes, and simplify the manufacturing process.
[0063] In one possible approach, the first chip and the first through-silicon via (TSV) bridging chip are arranged side-by-side on a carrier board, including: arranging the first chip, the third chip, and the first TSV bridging chip side-by-side on the carrier board.
[0064] In some chip layer structures, multiple active chips are arranged side by side, which can increase the chip stacking density.
[0065] In one possible implementation, the first chip and the first through-silicon via (TSV) bridging chip are disposed side-by-side on a carrier board, including: the active layer of the first chip is located on the side of the substrate away from the carrier board; the first chip is disposed on the redistribution layer of the first chip, including: the active layer of the first chip faces the redistribution layer of the first chip.
[0066] In the fabrication method of this example, the two first chips in adjacent layers are arranged face to face, so that they can share the same redistribution layer, simplifying the process steps and enabling multi-layer structure stacking.
[0067] In one feasible manner, after obtaining the second layer structure, the fabrication method further includes: obtaining a top layer structure, the top layer structure including a top chip, the substrate of the top chip being located on the side of the active layer away from the carrier.
[0068] The substrate of the top chip is further away from the substrate than the active layer, meaning that the substrate of the top chip is exposed with its face upwards. This enhances heat dissipation and further improves the heat dissipation effect of the stacked structure. Attached Figure Description
[0069] Figure 1 is a partial structural diagram of an electronic device according to an example of this application;
[0070] Figure 2 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0071] Figure 3 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0072] Figure 4 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0073] Figure 5 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0074] Figure 6 is a top view of a chip stacking structure provided in an embodiment of this application;
[0075] Figure 7 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0076] Figure 8 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0077] Figure 9 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0078] Figure 10 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0079] Figure 11 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;
[0080] Figure 12 is a flowchart of a method for fabricating a chip stacking structure according to an embodiment of this application;
[0081] Figures 13 to 19 are schematic diagrams of the process structure after each step is completed in a chip stacking structure fabrication method provided in the embodiments of this application.
[0082] Reference numerals: 100-Circuit board; 200-Electrical connection structure; 300-Semiconductor device packaging structure; 301-Substrate; 302-Multilayer structure; 11-First chip; 12-Second chip; 13-Third chip; 21-First through-silicon via (TSV) bridging chip; 22-Second TSV bridging chip; 3-Redistribution layer; 4-Electrical connection structure; 5-Molding layer; 6-Heat dissipation structure; 7-Thermal interface material layer; 8-Structural component; 9-Carrier board; 10-Adhesive layer; 14-Electrical connection structure. Detailed Implementation
[0083] The following embodiments of this application will be described in conjunction with the accompanying drawings.
[0084] The technical solutions of this application can be applied to various electronic devices employing semiconductor devices. For example, the electronic devices in the embodiments of this application can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application are not limited in this regard.
[0085] As shown in Figure 1, the aforementioned electronic device may include a circuit board 100, such as a printed circuit board (PCB), on which a semiconductor device package structure 300 is disposed. The semiconductor device package structure 300 can be electrically connected to the circuit board 100 through an electrical connection structure 200, thereby enabling the semiconductor device package structure 300 to achieve signal interconnection with other chips or other electronic modules on the circuit board 100.
[0086] In alternative implementations, the electrical connection structure 200 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.
[0087] In some examples, as shown in Figure 1, the semiconductor device package structure 300 can be a chip stack structure. The chip stack structure can include a substrate 301 and a multilayer structure 302, with the multilayer structure 302 stacked on the substrate 301 in a direction perpendicular to the surface of the substrate 301. That is, the chips are stacked three-dimensionally on the substrate 301, forming a three-dimensional integrated circuit (3D-IC) structure.
[0088] In some implementation structures, the chip in the semiconductor device package structure 300 may include memory, logic circuits, system-on-chip (SOC), or analog chips, digital chips, etc. Alternatively, it may include active or passive devices, such as transistors, resistors, inductors, and other electronic devices.
[0089] The substrate 301 in the chip stacking structure may include at least one of a packaging substrate or other electrical connection board.
[0090] Alternatively, in some examples, the multilayer structure 302 may be disposed on an interposer or a chip, which is disposed on a substrate 301.
[0091] In order to increase the number of chip stacking layers in Figure 1, increase the stacking density, and realize multi-layer high-capacity, high-bandwidth stacking technology, this application provides some achievable structures, as detailed below.
[0092] Figure 2 is a schematic diagram of a chip stacking structure according to an embodiment of this application. In this example, two layers are shown stacked on a substrate 301: a first layer and a second layer. The first and second layers are arranged along a direction perpendicular to the surface of the substrate 301. For example, along the Z-direction of Figure 2, away from the substrate 301, the first and second layers are stacked sequentially on the substrate 301.
[0093] For example, the first layer structure or the second layer structure may include a first chip 11, a first through-silicon via (TSV) bridging chip 21, and a redistribution layer (RDL) 3.
[0094] In this application example, the through-silicon via (TSV) bridge chip can be understood as: a through-silicon via (TSV) is formed in the silicon substrate along the thickness direction of the silicon substrate.
[0095] In the example of Figure 2, the first through-silicon via (TSV) bridging chip 21 and the first chip 11 are arranged side by side. This can be understood as the first TSV bridging chip 21 and the first chip 11 being arranged side by side along a direction parallel to the surface of the substrate 301, such as along the X direction shown in Figure 2. Alternatively, the first chip 11 and the first TSV bridging chip 21 can be considered to be on the same layer.
[0096] As shown in Figure 2, the redistribution layer 3 is disposed parallel to the surface of the substrate 301, and is located on the same side of the first through-silicon via (TSV) bridging chip 21 and the first chip 11. The first TSV bridging chip 21 and the first chip 11, which are arranged side by side, have a first side and a second side. The first side is away from the substrate 301, and the second side is close to the substrate 301. In some examples, as shown in Figure 2, the redistribution layer 3 may be disposed on the first side; in other examples, the redistribution layer 3 may be disposed on the second side.
[0097] In some circuits, as shown in Figure 2, in the first or second layer structure, the redistribution layer 3 can electrically connect the first through-silicon via (TSV) bridge chip 21 and the first chip 11.
[0098] For example, in Figure 2, the first chip 11 in the first layer structure can be vertically interconnected with the substrate 301 through the electrical connection structure 14.
[0099] For example, in Figure 2, the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip 21 in the second layer structure through the redistribution layer 32 in the second layer structure. The first TSV bridge chip 21 in the second layer structure is electrically connected to the first TSV bridge chip 21 in the first layer structure. The first TSV bridge chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0100] For example, in Figure 2, the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip 21 in the first layer structure through the redistribution layer 31 in the first layer structure. The first TSV bridge chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0101] In the chip stacking structure of this application example, chip signals of each layer can be transmitted to the substrate through redistribution layers (RDL) and through-silicon vias (TSVs), achieving vertical interconnection.
[0102] In this application example, the through-silicon via (TSV) is decoupled from the active chip (such as the first chip 11). That is, the TSV is not integrated into the active chip, but a separate TSV bridge chip is used. This avoids the phenomenon that the TSV occupies a large area in the active chip, which would increase the cost of the active chip. In addition, it also avoids the phenomenon that the thermal process and stress field would affect the chip performance during the fabrication of the TSV in the active chip, and would prolong the manufacturing cycle of the active chip. Furthermore, decoupling the TSV from the active chip (such as the first chip 11) can also improve the heat dissipation effect of the active chip, weaken the impact of heat dissipation on the number of chip layers, and thus increase the number of chip stacking layers.
[0103] Continuing with Figure 2, this application arranges the through-silicon via (TSV) bridging chip and the active chip side by side, and uses a redistribution layer to connect the TSV bridging chip and the active chip. Compared with stacking the TSV bridging chip and the active chip, this application can increase the number of chip stacking layers and increase the stacking density while effectively dissipating heat. For example, the number of stacking layers can be greater than or equal to 4 layers.
[0104] In addition, in the example of this application, the arrangement of active chips and through-silicon via (TSV) bridging chips in each layer structure is relatively simple, which is easy to implement in terms of process technology and will not pose a significant challenge to the process, thus reducing manufacturing costs.
[0105] In a multi-layered stacked chip, adjacent layers can be connected by an electrical connection structure 4, such as a bump structure. For example, micro-bump bonding can be used to connect the two layers. Alternatively, a hybrid bonding process can be used. For instance, in Figure 2, the first through-silicon via (TSV) bridging chip 21 and the first chip 11 in the second layer can be electrically connected using hybrid bonding technology.
[0106] By using the example of bump bonding or hybrid bonding to connect the two layers, thermal resistance can be reduced and heat dissipation of the chip stack structure can be improved.
[0107] In some feasible structures, the electrical connection structure 14 in Figure 2 can be fabricated using a bump bonding process or a hybrid bonding process.
[0108] To improve the strength of this multi-layer stacked structure, as shown in Figure 2, a molding layer 5 can be used to encapsulate the multi-layer structure 302.
[0109] Continuing with Figure 2, in this example, each layer structure may include a chip, such as a first chip 11. The first chip 11 may be an active chip. As shown in Figure 3, Figure 3 is a schematic diagram of another chip stacking structure given in the embodiment of this application. In this example, four layers stacked on the substrate 301 are shown, namely the first layer structure, the second layer structure, the third layer structure and the top layer structure. These layers are arranged along a direction perpendicular to the surface of the substrate 301.
[0110] In some circuits, as shown in Figure 3, in the first layer structure, the second layer structure, or the third layer structure, the redistribution layer 3 can electrically connect the first through-silicon via bridge chip 21 and the first chip 11.
[0111] For example, in Figure 3, the first chip 11 in the first layer structure can be vertically interconnected with the substrate 301 through the electrical connection structure 14.
[0112] For example, in Figure 3, the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip 21 in the second layer structure through the redistribution layer 32 in the first layer structure. The first TSV bridge chip 21 in the second layer structure is electrically connected to the first TSV bridge chip 21 in the first layer structure. The first TSV bridge chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0113] For example, in Figure 3, the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip 21 in the first layer structure through the redistribution layer 31 in the first layer structure. The first TSV bridge chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0114] In some examples, the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridge chip 21 in the second layer structure through the redistribution layer 31 in the first layer structure, and the electrical signal or voltage of the first chip 11 in the second layer structure can be connected to the first TSV bridge chip 21 in the first layer structure through the redistribution layer 31 in the first layer structure.
[0115] The transmission method of electrical signals or voltage of the first chip 11 in the third layer structure can be similar to that of the first chip in the second layer structure.
[0116] As shown in Figure 3, the first chip 11 may include a substrate (also referred to as a passive layer) and an active layer, with the active layer stacked on the substrate. The active layer in the chip of this application example can be understood to include transistors or integrated circuits, etc.
[0117] In Figure 3, the substrate of the first chip 11 is further away from the substrate 301 than the active layer; that is, the substrate of the first chip 11 faces upwards, and the active layer faces downwards. This improves the heat dissipation efficiency of each chip and optimizes the heat dissipation effect of the entire chip stack structure. If the heat dissipation effect is optimized, more layers can be integrated, increasing the chip integration density.
[0118] In other examples, as shown in Figure 4, which is a schematic diagram of another chip stacking structure given in an embodiment of this application, the substrate of the first chip 11 can face downwards and the active layer can face upwards.
[0119] In some other examples, the substrate of the first chip 11 in some chip layer structures may face upwards and the active layer downwards, while in other chip layer structures the substrate of the first chip 11 may face downwards and the active layer upwards. For example, in a first layer structure, the substrate of the first chip 11 faces upwards and the active layer downwards, while in a second layer structure, the substrate of the first chip 11 faces downwards and the active layer upwards.
[0120] In the example of Figure 4, the first chip 11 in the first layer structure can be connected to the first through-silicon via (TSV) bridging chip 21 in the first layer structure through the redistribution layer 31. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 and the substrate 301 in the first layer structure.
[0121] For example, the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip 21 in the second layer structure through the redistribution layer 32. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0122] The transmission method of electrical signals or voltage of the first chip 11 in the third layer structure can be similar to that of the first chip in the second layer structure.
[0123] As shown in Figures 3 and 4, the through-silicon via (TSV) bridging chips in adjacent layers are arranged opposite each other in the stacking direction. For example, the first TSV bridging chip 21 in the second layer is arranged vertically opposite to the first TSV bridging chip 21 in the first layer. In this way, vertical interconnection between chips and substrates in different layers can be achieved.
[0124] Referring to Figures 3 and 4, the multilayer structure includes a top layer structure located at the top, which may include a top chip N1 and may not include a through-silicon via (TSV) bridge chip.
[0125] To improve the heat dissipation of the chip stack structure, as shown in Figures 3 and 4, the substrate of the top chip N1 is further away from the substrate 301 than the active layer, that is, the substrate of the top chip N1 faces upward and the active layer faces downward.
[0126] As shown in Figure 5, the chip stack structure may also include a heat dissipation structure 6, which is disposed above the multilayer structure 302. Since the substrate of the top chip N1 faces upward, the heat dissipation structure 6 can cover the substrate of the top chip N1, thereby shortening the heat dissipation path and improving the heat dissipation effect.
[0127] In some examples, to further improve the heat dissipation effect, as shown in Figure 5, a thermal interface material (TIM) layer 7 with a large thermal conductivity can be provided at the substrate interface between the heat dissipation structure 6 and the top chip N1.
[0128] In the examples of Figures 3, 4 and 5, a redistribution layer may not be placed above the top layer structure, thus exposing the substrate of the top chip N1 to enhance heat dissipation.
[0129] As shown in Figures 3 to 5, the substrate of the top chip N1 is not covered by the molding layer 5, but is exposed. The heat dissipation structure 6 covers the substrate of the top chip N1, optimizing the heat dissipation effect of the chip stacking structure.
[0130] To achieve vertical interconnection between the top chip N1 and the substrate 301, as shown in Figure 5, a redistribution layer 33 can be provided on the side of the top chip N1 closest to the substrate 301. The top chip N1 is electrically connected to the redistribution layer 33. The electrical signal or voltage of the top chip N1 can be connected through the redistribution layer 33 to the first through-silicon via (TSV) bridge chip 21 in the next layer structure (such as the first TSV bridge chip 21 in the third layer structure), as well as multiple vertically stacked TSV bridge chips, to achieve vertical interconnection with the substrate 301.
[0131] Continuing with Figure 5, in some examples, other structural components 8 can be placed in the top layer structure. For example, structural component 8 may include passive devices or structural silicon, etc. Structural component 8 is arranged side by side with the top chip N1 in this layer. For example, structural component 8 may be placed on the outer periphery of the top chip N1.
[0132] Compared to directly wrapping the top chip N1 with a molding compound 5 without structural silicon, this application uses structural silicon, which can improve the thermal conductivity and heat dissipation. It can also avoid the phenomenon that the molding compound generates large stress, affecting the device performance. Furthermore, using structural silicon can also improve the reliability and stability of the chip stack.
[0133] In the example shown in Figure 5, structure 8 is placed in the topmost structure. In other examples, structure 8 can also be placed in other chip layer structures.
[0134] As shown in Figures 3 to 5, any one of the first, second, or third layers may include a second through-silicon via (TSV) bridging chip 22. The first TSV bridging chip 21, the first chip 11, and the second TSV bridging chip 22 are arranged side by side, that is, arranged in a direction parallel to the surface of the substrate 301.
[0135] This can be understood as follows: In this application example, in addition to the top-level structure, a first through-silicon via (TSV) bridge chip 21 and a second TSV bridge chip 22 can be set in other chip layer structures. Multiple TSV bridge chips are used to achieve vertical interconnection between the active chip and the substrate 301.
[0136] Figure 6 is a top view of the chip stacking structure given in an embodiment of this application. In the chip stacking structure, the through-silicon via (TSV) bridging chip is disposed at the outer edge of the active chip.
[0137] For example, in Figure 6, the chip stacking structure includes a chip integration area for integrating chips, and the active chips (such as the first chip 11) in each chip layer structure are all disposed in the chip integration area; the first through-silicon via (TSV) bridging chip 21 and the second TSV bridging chip 22 are disposed along the periphery of the chip integration area. This arrangement of the TSV bridging chips and active chips is relatively simple, simplifies the process, and reduces manufacturing costs.
[0138] In the example shown in Figure 6, two through-silicon via (TSV) bridging chips are illustrated. In some examples, more TSV bridging chips may be included, with multiple TSV bridging chips spaced apart along the outer periphery of the chip integration area.
[0139] See Figure 7, which is a schematic diagram of another chip stacking structure provided in an embodiment of this application. In this example, multiple chips can be arranged in some chip layer structures to improve chip integration density. For example, in the first layer structure of Figure 7, a first chip 11 and a third chip 13 are included. The first chip 11 and the third chip 13 are arranged side by side, that is, the first chip 11 and the third chip 13 are arranged side by side along a direction parallel to the surface of the substrate 301.
[0140] In the example of Figure 7, the first chip 11 in the first layer structure can be connected to the substrate 301 through the electrical connection structure 14 to achieve vertical interconnection; the third chip 13 can be connected to the substrate 301 through the electrical connection structure 14 to achieve vertical interconnection.
[0141] The first chip 11 and the third chip 13 in the first layer structure can be horizontally interconnected through a substrate (such as a packaging substrate).
[0142] In some examples, multiple chips can also be arranged side by side in other chip layer structures. For example, multiple chips can be arranged in at least one of the second, third, and fourth layer structures.
[0143] As shown in Figure 7, multiple chips are arranged side by side in the first layer structure. Multiple chips can be placed near the substrate 301, which can improve the stability of the entire stacked structure.
[0144] Referring to Figure 7, in the first layer structure, the substrate of the first chip 11 can face upwards and the active layer can face downwards, while the substrate of the third chip 13 can face upwards and the active layer can face downwards. In some examples, the substrate of the first chip 11 can face upwards and the active layer can face downwards, while the substrate of the third chip 13 can face downwards and the active layer can face upwards.
[0145] In some chip stacking structures, as shown in Figure 7, other structural components 8 may also be included. For example, the structural component 8 may include at least one of passive devices or structural silicon. As shown in Figure 7, passive devices or structural silicon can be placed between the first chip 11 and the third chip 13. Placing passive devices can increase the device integration density of the stacking structure, while placing structural silicon can improve the stability of the entire stacking structure.
[0146] In some examples, the structural component 8 can be positioned on the outer periphery of the first chip 11 and the third chip 13.
[0147] In Figure 7, passive devices or structural silicon structures are placed in the first layer structure close to the substrate 301. Of course, passive devices or structural silicon structures can also be placed in other chip layer structures.
[0148] See Figure 8, which is a schematic diagram of another chip stacking structure according to an embodiment of this application. In this example, the first layer structure includes a first chip 11 and a third chip 13, which are arranged side by side along a direction parallel to the surface of the substrate 301.
[0149] The active layer of the first chip 11 faces upwards, and the active layer of the third chip 13 faces upwards. The first chip 11 and the third chip 13 can be horizontally interconnected through the redistribution layer 31 in the first layer structure. The redistribution layer 31 acts as an interconnection bridge to connect two horizontally adjacent chips on the same layer, achieving electrical signal and mechanical interconnection.
[0150] See Figure 9, which is a schematic diagram of another chip stacking structure according to an embodiment of this application. In this example, multiple chips can be arranged in some chip layer structures, and these multiple chips are stacked in three dimensions. For example, in Figure 9, a second chip 12 is also included. The first chip 11 and the second chip 12 are stacked along a direction perpendicular to the surface of the substrate 301.
[0151] In the example shown in Figure 9, a second chip 12 is included in the first, second, and third layer structures. In the first layer structure, the first chip 11 and the third chip 13 are arranged side by side, and the second chip 12 is stacked on top of the first chip 11 and the third chip 13; in the second and third layer structures, the second chip 12 is stacked on top of the first chip 11. This further improves the chip integration density.
[0152] The stacked first chip 11 and third chip 13 can be stacked in the manner shown in Figure 8, with the substrate of the first chip 11 and the substrate of the third chip 13 facing each other, that is, the two chips are set back to back.
[0153] In some connection methods, as shown in Figure 9, the substrates of the first chip 11 and the second chip 12 can be connected by an adhesive layer, for example, a die-attach film (DAF) can be used for connection.
[0154] When using the structure shown in Figure 9 to achieve chip stacking, the number of layers of chips connected by through-silicon vias can be reduced, the number of molding processes can be reduced, the process can be simplified, the device fabrication cycle can be shortened, and the manufacturing cost can be reduced.
[0155] In the example of Figure 9, the second chip 12 in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip 21 in the second layer structure through the redistribution layer 32. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the second chip 12 in the second layer structure and the substrate 301.
[0156] In the example of Figure 9, the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip 21 in the second layer structure through the redistribution layer 31. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0157] Alternatively, the first chip 11 in the second layer structure can be connected to the first through-silicon via (TSV) bridging chip 21 in the first layer structure via the redistribution layer 31. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby achieving vertical interconnection between the first chip 11 in the second layer structure and the substrate 301.
[0158] See Figure 10, which is a schematic diagram of another chip stacking structure according to an embodiment of this application. In this example, in two adjacent layers, the active layer of the active chip in one layer is further away from the substrate 301 than the substrate, while the active layer of the active chip in the other layer is closer to the substrate 301 than the substrate. This can be understood as the active chips in two adjacent layers being arranged face-to-face.
[0159] For example, in Figure 10, the first layer structure and the second layer structure are adjacent. In the first layer structure, the active layer of the first chip 11 faces upward and the substrate faces downward. In the second layer structure, the active layer of the first chip 11 faces downward and the substrate faces upward. That is, the first chip 11 in the first layer structure and the first chip 11 in the second layer structure are arranged face to face.
[0160] As shown in Figure 10, a redistribution layer 31 can be provided between the first chip 11 in the first layer structure and the first chip 11 in the second layer structure, and the first layer structure and the second layer structure share the same redistribution layer 31.
[0161] Continuing with Figure 10, the third and fourth layer structures are adjacent. In the third layer structure, the active layer of the first chip 11 faces upward and the substrate faces downward. In the fourth layer structure, the active layer of the first chip 11 faces downward and the substrate faces upward. That is, the first chip 11 in the third layer structure and the first chip 11 in the fourth layer structure are arranged face to face.
[0162] As shown in Figure 10, a redistribution layer 32 can be provided between the first chip 11 in the third layer structure and the first chip 11 in the fourth layer structure, and the third layer structure and the fourth layer structure share the same redistribution layer 32.
[0163] Continuing with Figure 10, the fifth layer structure and the top layer structure are adjacent. In the fifth layer structure, the active layer of the first chip 11 faces upward and the substrate faces downward. In the top layer structure, the active layer of the first chip 11 faces downward and the substrate faces upward. That is, the first chip 11 in the fifth layer structure and the first chip 11 in the top layer structure are arranged face to face.
[0164] As shown in Figure 10, a redistribution layer 33 can be set between the first chip 11 in the top layer structure and the first chip 11 in the fifth layer structure, and the top layer structure and the fifth layer structure share the same redistribution layer 33.
[0165] The two adjacent layers can be connected using either bump bonding or hybrid bonding processes.
[0166] When two adjacent active chip layers are arranged using the example shown in Figure 10, the number of redistribution layers can be reduced, thereby increasing the number of active chip stacking layers and increasing the stacking density; in addition, the number of molding processes can be reduced, simplifying the process and reducing costs.
[0167] In the example of Figure 10, in the first layer structure, the first chip 11 can be connected to the first through-silicon via (TSV) bridging chip 21 in the first layer structure through the redistribution layer 31. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 and the substrate 301 in the first layer structure.
[0168] In the second layer structure, the first chip 11 can be connected to the first through-silicon via (TSV) bridging chip 21 in the second layer structure through the redistribution layer 31. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 and the substrate 301 in the second layer structure.
[0169] In the third layer structure, the first chip 11 can be connected to the first through-silicon via (TSV) bridging chip 21 in the third layer structure through the redistribution layer 32. The first TSV bridging chip 21 in the third layer structure is connected to the first TSV bridging chip 21 in the second layer structure. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the first chip 11 and the substrate 301 in the third layer structure.
[0170] See Figure 11, which is a schematic diagram of another chip stacking structure according to an embodiment of this application. In this example, in two adjacent layers, the active layer of the active chip in one layer is further away from the substrate 301 than the substrate, while the active layer of the active chip in the other layer is closer to the substrate 301 than the substrate. This can be understood as the active chips in two adjacent layers being arranged face-to-face.
[0171] In some layer structures illustrated in Figure 11, multiple chips may be included. These chips may be arranged side by side, or they may be arranged in a three-dimensional stack as shown in Figure 11. For example, in the second layer structure of Figure 11, a first chip 11 and a second chip 12 are included. The first chip 11 and the second chip 12 are stacked, and the substrates of the first chip 11 and the second chip 12 are arranged face to face. A redistribution layer 32 may be provided between the second layer structure and the third layer structure.
[0172] In the example of Figure 11, in the second layer structure, the second chip 12 can be connected to the first through-silicon via (TSV) bridging chip 21 in the second layer structure through the redistribution layer 32. The first TSV bridging chip 21 in the second layer structure is connected to the first TSV bridging chip 21 in the first layer structure. The first TSV bridging chip 21 in the first layer structure is connected to the substrate 301, thereby realizing the vertical interconnection between the second chip 12 and the substrate 301 in the second layer structure.
[0173] When two adjacent active chip layers are arranged using the example shown in Figure 11, the number of redistribution layers and the number of chips bridged by through-silicon vias can be reduced, thereby increasing the number of active chip stacking layers and stacking density; and the number of molding cycles can also be reduced, simplifying the process and reducing costs.
[0174] In other examples, chips can be placed side by side with the first chip 11 in the first layer structure or other layers to further improve chip integration density.
[0175] In the different chip stacking structures exemplified in this application, the active chip and the through-silicon via (TSV) bridging chip are placed on the same layer, rather than in a three-dimensional stack. This allows for the stacking of more layers and decouples the TSV from the active chip, avoiding the area overhead and process time costs associated with the active chip. Furthermore, the stress and related thermal processes of the TSV do not affect the active device. In multi-layer stacking, the TSV bridging chip can integrate an integrated passive device (IPD), enabling customized voltage control for different stacking layers and optimizing device energy efficiency. Additionally, the substrate of the top layer faces upwards, allowing for exposed heat dissipation. For example, it can be directly bonded to a heat dissipation structure without being covered by a molding layer, improving the heat dissipation effect of the stacked structure.
[0176] Based on the different chip stacking structures in the above examples, they can be fabricated according to the process flow diagram shown in Figure 12. The process flow shown in Figure 12 can be referred to the process structure diagrams shown in Figures 13 to 19.
[0177] Step S1: The first chip and the first through-silicon via (TSV) bridging chip are arranged side by side on the carrier board, with the arrangement direction of the first chip and the first TSV bridging chip parallel to the surface of the carrier board.
[0178] For example, in Figure 13, the first chip 11 and the first through-silicon via (TSV) bridging chip 21 can be arranged side by side on a carrier 9, which can be a silicon carrier or a glass carrier.
[0179] In some feasible processes, bonding or welding processes can be used to place the first chip 11 and the first through-silicon via (TSV) bridging chip 21 on the carrier board 9, as shown in Figure 13. A temporary bonding layer 10 is used to connect the first chip 11, the first TSV bridging chip 21, and the carrier board 9.
[0180] In some fabrication processes, in order to improve the chip integration density of the resulting chip stack structure, as shown in Figure 13, the third chip 13 can also be integrated on the carrier board 9, or other structural components 8 can be integrated on the carrier board 9.
[0181] In some feasible fabrication processes, as shown in Figure 13, the first chip 11 and the third chip 13 are arranged side by side. In other methods, a second chip may also be included, which can be stacked on top of the first chip 11 and the third chip 13 to achieve three-dimensional stacking.
[0182] For example, the first chip and the second chip can be arranged back to back, that is, the substrate of the first chip 11 and the substrate of the second chip are arranged opposite each other. The first chip and the third chip can be arranged back to back. By setting multiple chips, the chip integration density can be further improved.
[0183] Continuing with Figure 13, the second through-silicon via (TSV) bridging chip 22 can also be placed on the carrier board 9, while the first TSV bridging chip 21 and the second TSV bridging chip 22 are placed around the periphery of the multiple active chips, that is, at the outer edge of the stacked structure.
[0184] Step S2: A redistribution layer is formed on the first chip and the first through-silicon via (TSV) bridging chip to obtain the first layer structure.
[0185] As shown in Figure 14, a redistribution layer 3 is provided on the first chip 11, the third chip 13, the structural component 8, the first through-silicon via (TSV) bridging chip 21, and the second TSV bridging chip 22.
[0186] In addition, molding can be performed to obtain molding layer 5, which improves the strength of the chip layer structure.
[0187] For example, the first chip 11, the third chip 13, the structural component 8, the first through-silicon via (TSV) bridging chip 21, and the second TSV bridging chip 22 are placed on the carrier board 9, then encapsulated to form the encapsulation layer 5, and then the redistribution layer 3 is prepared.
[0188] Step S3: Deposit the first chip and the first through-silicon via (TSV) bridging chip, as well as the redistribution layer, on the redistribution layer of the first layer structure to obtain the second layer structure.
[0189] As shown in Figure 15, the first chip 11, the first through-silicon via (TSV) bridging chip 21, and the second TSV bridging chip 22 can be placed on the redistribution layer 3 of the first layer structure using a mass reflow soldering process, a thermocompression bonding (TCB) process, or a hybrid bonding process, and then encapsulated to form a plastic encapsulation layer.
[0190] As shown in Figure 16, a redistribution layer 3 is then formed to obtain the second layer structure.
[0191] In some examples, even more layers can be fabricated. For instance, in Figure 17, more layers can be stacked following the process steps shown in Figures 15 and 16, resulting in a 5-layer structure as shown in Figure 17.
[0192] In other possible ways, multiple structures can be fabricated based on Figure 14 and then sealed again, or a molded underfill (MUF) can be used.
[0193] Step S4: As shown in Figures 17 and 18, remove the carrier plate 9. For example, remove the temporary bonding layer 10 and the carrier plate 9.
[0194] Step S5: As shown in Figure 19, a structure containing a stacked first layer structure and a second layer structure is disposed on the substrate 301.
[0195] Alternatively, in some examples, a structure containing a stacked first layer and a second layer can be placed on an intermediary plate, which is then placed on a substrate 301.
[0196] In the chip stacking structure fabricated using the method of the example in this application, the through-silicon via (TSV) bridging chip and the active chip are located in the same layer, rather than being stacked, which can increase the number of stacking layers in the stacking structure.
[0197] In the method described in the example above, the substrate of each active chip faces upwards and the active layer faces downwards.
[0198] In other fabrication methods, the active layer of the active chip can face upwards and the substrate downwards. Furthermore, when performing the process shown in FIG14, the active layer of the first chip 11 in the second layer structure can face downwards and the substrate upwards, sharing the same redistribution layer 3, which simplifies the process steps and can also increase the number of stacked layers.
[0199] In some processes, passive devices or structural silicon can be placed in certain chip layer structures.
[0200] As shown in Figure 17, when fabricating a multi-layered structure at the top, the substrate of the first chip 11 faces upwards, and the active layer faces downwards. This improves heat dissipation of the entire chip stack structure and increases the number of stacked layers.
[0201] In this application example, the first chip, the second chip, and the third chip can be bare die chips without packaging.
[0202] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0203] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip stacking structure, characterized in that, include: substrate; and A multilayer structure, including a first layer structure and a second layer structure, wherein the first layer structure and the second layer structure are stacked on the substrate in a direction perpendicular to the surface of the substrate; Either the first layer structure or the second layer structure includes: A first chip and a first through-silicon via (TSV) bridging chip, wherein the first TSV bridging chip and the first chip are arranged in a direction parallel to the surface of the substrate; A redistribution layer is disposed parallel to the surface of the substrate and electrically connects the first through-silicon via (TSV) bridge chip and the first chip.
2. The chip stacking structure according to claim 1, characterized in that, The first through-silicon via (TSV) bridging chip of the first layer structure and the first TSV bridging chip of the second layer structure are disposed opposite each other in a direction perpendicular to the surface of the substrate; The first through-silicon via (TSV) bridge chip of the first layer structure is electrically connected to the first TSV bridge chip of the second layer structure.
3. The chip stacking structure according to claim 1 or 2, characterized in that, The chip stacking structure also includes: a top layer structure; The top-level structure includes a top-level chip; The substrate of the top-layer chip is located on the side of the active layer away from the substrate.
4. The chip stacking structure according to claim 3, characterized in that, The chip stacking structure also includes a heat dissipation structure; The heat dissipation structure is disposed on the substrate of the top-layer chip.
5. The chip stacking structure according to claim 3 or 4, characterized in that, The top-level structure includes a silicon structure disposed on the outer periphery of the top-level chip.
6. The chip stacking structure according to any one of claims 1-5, characterized in that, The first layer is stacked on the substrate, and the second layer is stacked on the first layer. In either the first layer structure or the second layer structure, the redistribution layer is disposed on the side of the first through-silicon via bridging chip and the first chip away from the substrate; The first chip and the first through-silicon via (TSV) bridge chip in the second layer structure are connected to the redistribution layer in the first layer structure through an electrical connection structure.
7. The chip stacking structure according to claim 6, characterized in that, In either the first layer structure or the second layer structure, the substrate of the first chip is located on the side of the active layer away from the substrate.
8. The chip stacking structure according to claim 7, characterized in that, The first chip and the first through-silicon via (TSV) bridge chip in the second layer structure are electrically connected through the redistribution layer in the first layer structure, and / or; The first chip in the second layer structure and the first through-silicon via (TSV) bridge chip in the first layer structure are electrically connected through the redistribution layer in the first layer structure.
9. The chip stacking structure according to claim 7 or 8, characterized in that, The active layer of the first chip in the first layer structure is electrically connected to the substrate through an electrical connection structure.
10. The chip stacking structure according to claim 6, characterized in that, In either the first layer structure or the second layer structure, the active layer of the first chip is located on the side of the substrate away from the substrate. The first chip and the first through-silicon via (TSV) bridge chip in the second layer structure are electrically connected through the redistribution layer in the second layer structure, or; The first chip and the first through-silicon via (TSV) bridge chip in the first layer structure are electrically connected through the redistribution layer in the first layer structure.
11. The chip stacking structure according to any one of claims 1-5, characterized in that, The first layer is stacked on the substrate, and the second layer is stacked on the first layer. In the first layer structure, the active layer of the first chip is located on the side of the substrate away from the substrate; In the second layer structure, the substrate of the first chip is located on the side of the active layer away from the substrate; The redistribution layer is provided between the first layer structure and the second layer structure, and the redistribution layer located between the first layer structure and the second layer structure is a shared redistribution layer; The first chip and the first through-silicon via (TSV) bridging chip in the first layer structure are connected through the shared redistribution layer. The first chip and the first through-silicon via (TSV) bridge chip in the second layer structure are connected through the shared redistribution layer.
12. The chip stacking structure according to any one of claims 1-7, characterized in that, The first layer structure also includes: The second chip is stacked on top of the first chip; The substrates of the first chip and the second chip are arranged opposite to each other.
13. The chip stacking structure according to any one of claims 1-12, characterized in that, The first layer structure also includes: The third chip is arranged in a direction parallel to the surface of the substrate, along with the first chip.
14. The chip stacking structure according to any one of claims 1-13, characterized in that, The first layer structure also includes: a second through-silicon via (TSV) bridging chip; The first through-silicon via (TSV) bridging chip, the second TSV bridging chip, and the first chip are arranged in a direction parallel to the surface of the substrate; The chip stacking structure includes a chip integration area for integrating chips, with the first chip disposed in the chip integration area, and the first through-silicon via (TSV) bridging chip and the second TSV bridging chip disposed around the chip integration area.
15. An electronic device, characterized in that, include: Circuit board; The chip stacking structure as described in any one of claims 1-14; The chip stack structure is disposed on the circuit board.
16. A method for fabricating a chip stacking structure, characterized in that, The preparation method includes: The first chip and the first through-silicon via (TSV) bridging chip are arranged side by side on the carrier board, with the arrangement direction of the first chip and the first TSV bridging chip parallel to the surface of the carrier board. A redistribution layer is provided on the first chip and the first through-silicon via (TSV) bridging chip to obtain a first layer structure; A first chip and a first through-silicon via (TSV) bridging chip, as well as a redistribution layer, are disposed on the redistribution layer of the first layer structure to obtain a second layer structure. Remove the carrier plate; A structure comprising a stacked first layer and a second layer is disposed on a substrate.
17. The method for fabricating a chip stacked structure according to claim 16, characterized in that, The first chip and the first through-silicon via (TSV) bridging chip are arranged side-by-side on the carrier board, including: The substrate of the first chip is located on the side of the active layer away from the carrier.
18. The method for fabricating a chip stacked structure according to claim 16, characterized in that, The first chip and the first through-silicon via (TSV) bridging chip are arranged side-by-side on the carrier board, including: The first chip and the second chip are stacked, with the substrates of the first chip and the second chip positioned opposite each other; The first through-silicon via (TSV) bridging chip, the stacked first chip, and the second chip are arranged side by side on the carrier board.
19. The method for fabricating a chip stacking structure according to claim 16, characterized in that, The first chip and the first through-silicon via (TSV) bridging chip are arranged side-by-side on the carrier board, including: The active layer of the first chip is located on the side of the substrate away from the carrier plate; Depositing a first chip on the redistribution layer of the first-layer chip includes: The active layer of the first chip faces the redistribution layer of the first chip.
20. The method for fabricating a chip stacked structure according to any one of claims 16-19, characterized in that, After obtaining the second layer structure, the preparation method further includes: A top-level structure is obtained, the top-level structure including a top chip, the substrate of which is located on the side of the active layer away from the carrier.