Power field-effect transistor comprising a fin

Abstract

The invention relates to a Power Field-effect transistor comprising a fin (FinFET) (100), wherein the power FinFET (100) comprises a drain contact (1), a substrate region (2) of a first dope type aligned to the drain contact (1), a drift region (3) of the first dope type comprising a base (31) with a lateral surface (32) and a mesa region forming the fin (33), a first passivation layer (5) aligned partially to the fin (33) and partially extending parallel to the lateral surface (32), a gate contact (7) aligned at least partially to the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) aligned at a top of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material.

Description

[0001] R.415308 - 1 -

[0002] Description

[0003] Power field-effect transistor comprising a fin

[0004] FIELD

[0005] The invention relates to a power field-effect transistor comprising a fin.

[0006] BACKGROUND

[0007] Junction-less field-effect transistors (FET) have become favored for applications that transfer at a comparable high power, especially in the mid-voltage range of 1200 V to 3300 V targeting automotive and industrial applications. FETs are vertical unipolar devices encompassing one or more conductivity layers of one dope type with low activation energy, offering numerous free charge carriers without compromising blocking capability or dynamic response associated with deep levels. The conductivity layer comprises a mesa region forming a fin. This type of FET is called FinFET. The fin allows for significantly faster switching times and higher current density compared to planar FETs.

[0008] Beyond the conductivity layer power FinFETs incorporate a passivation layer, preferable an oxide layer, for the gate. The passivation layer introduces energy barriers, preferably against both conduction and valence bands, and enables gate control within the fin. This passivation layer must have minimal interfacial traps at the semiconductor interface to facilitate effective gate control. In order to reduce leakage currents it is known to use a material of a different dope type.

[0009] Due to their remarkable material properties, such as a low intrinsic carrier concentration and high electric field strength, ultra-wide bandgap semiconductor materials have emerged as a compelling option for the conductivity layers within the realm of power electronics. The exceptional impact ionization coefficients exhibited by these materials facilitate the reduction in size of the conductivity layers e.g. the drift region. Consequently, this downsizing contributes to enhanced benefits in relation to the specific on-state resistance compared to Silicon and other wide bandgap semiconductors such as 4H-Silicon Carbide (4H- R.415308 - 2 -

[0010] SiC) and Gallium nitride (GaN), all while maintaining equivalent blocking capabilities.

[0011] Nonetheless, challenges tied to insufficient doping control and early breakdown failure have constrained the potential enhancement of electrical performance in device structures. Further, power FinFETs made from ultra-wide bandgap materials encounter several challenges and reliability issues, like premature breakdowns due to high gate leakage currents or oxide failures, the gate control's efficacy relying on interface quality, impacting the on / off performance and mobility, particularly influenced by the interface between the passivation layer and the conductivity layer, inadequate operation in the III quadrant due to the lack of an intrinsic body diode and limited short-circuit performance if the conductivity layer consists of a material with poor thermal conductivity.

[0012] Alternative approaches to tackle premature breakdowns introduce a layer of the second type, shifting the peak electric field away from the passivation layer's interface. However, this technique might not be as effective in ultra-wide bandgap power FinFETs, because of a poor controllability of second type’s doping and high activation energy.

[0013] To tackle the inadequate operation in the III quadrant, an alternative layout featuring a trench metal-oxide-semiconductor barrier Schottky diode and a junctionless FET has been introduced. However, this approach's drawback lies in the limited availability of active device area. Furthermore, techniques that make use of a p-shield typically specify that the potential of this layer should be coupled with the source terminal and thus grounded throughout the operation of the device. This approach presents certain limitations as it can limit the on state current due to the presence of a non-negligible depletion region.

[0014] Therefore, there is a great demand for a power FinFET using an ultra-wide bandgap semiconductor material for conductivity layers in order to make use of the advantages thereof while overcoming aforementioned drawbacks. This invention has the object to overcome these problems.

[0015] DISCLOSSURE OF THE INVENTION

[0016] This object is attained in a surprisingly simple but effective manner by a power field-effect transistor comprising a fin (FinFET), wherein the power FinFET comprises a drain contact, a substrate region of a first dope type aligned to the R.415308 - 3 - drain contact, a drift region of the first dope type comprising a base with a lateral surface and a mesa region forming the fin, a first passivation layer aligned partially to the fin and partially extending parallel to the lateral surface, a gate contact aligned at least partially to the first passivation layer, a second passivation layer separating the gate contact and a source contact aligned at a top of the fin, wherein a material of the substrate region and the drift region is an ultra-wide bandgap semiconductor material. The power FinFET is characterized in that the power FinFET comprises a metal layer aligned to the second passivation layer and extending form base, wherein the metal layer forms a Schottky barrier with the drift region.

[0017] The main idea of the invention is rooted in empirical evidence of minimal leakage current in ultra-wide bandgap Schottky diodes. This reduced leakage current is attributed to the low intrinsic carrier concentration and / or tunneling current experimentally demonstrated in several ultra-wide bandgap Schottky diodes. Consequently, the integration a metal layer forming a Schottky barrier between the metal layer and the drift region, as detailed in this application, allows for the attenuation of the electric field present in the first passivation layer while introducing only a minor drawback in the form of additional leakage current induced by the metal layer through the Schottky barrier. While that such integration in conventional semiconductor devices like Silicon would lead to increased leakage current at low voltages and early failure, in the context of power FinFETS using an ultra-wide bandgap semiconductor material, the presence of a Schottky barrier does not significantly affect the power FinFET’s maximum breakdown voltage.

[0018] Furthermore, the metal layer can be linked with the source contact, a connection that can be established in a three-dimensional manner orthogonal to the illustrated cross-sectional plane.

[0019] The power FinFET according to the invention comprises drain contact, which is formed by a suitable material ensuring a low-resistance pathway connectable to a control circuit operating the power FinFET.

[0020] A substrate region of a first dope type is aligned to a drain contact. Thus, electrical current can flow between the substrate region and the drain contact. The first dope type can be either n-type doped or p-type doped. The substrate region material is an ultra-wide bandgap semiconductor material. An ultra-wide bandgap semiconductor material is a semiconductor material with a bandgap R.415308 - 4 - significant larger than the bandgaps of wide bandgap semiconductor materials. A semiconductor material with a bandgap of more than 3.4 eV is usually referred to as an ultra-wide bandgap semiconductor material. Examples for ultra-wide bandgap semiconductor materials are given elsewhere in this application.

[0021] A drift region of the first dope type is aligned to the substrate region. The first dope type of the drift region can be either an n-type doped or p-type doped, as long as the doped type is identical to the dope type of the substrate region. The substrate region material is an ultra-wide bandgap semiconductor material, preferably the same material as the substrate region. The drift region has preferable a lower doping concentration than the substrate region. The purpose of the drift region is providing intrinsic charge carriers in an on-state of the power FinFET and suppress the intrinsic charge carriers in an off-state of the power FinFET. The drift region and the substrate region are conductivity layers.

[0022] The drift region comprises a base with a lateral surface and a mesa region forming the fin. The lateral surface extends on the top of the base from the fin to the edge of the base. The fin preferable comprises a high doping concentration region at the top of the fin.

[0023] A first passivation layer is aligned partially to the fin and partially extending parallel to the lateral surface. The passivation layer has preferably an L-shaped cross section with one leg of the L aligned to the fin and the other leg of the L aligned to the lateral surface. Preferably, the passivation layer material is an oxide. The passivation layer serves a galvanic isolation between the drift region and a gate contact. The gate contact is aligned at least partially to the first passivation layer. The passivation layer may extend further than the gate contact. The potential difference between the gate contact and a source contact is controlling the on / off-state of the power FinFET via the electric field built up between the gate contact and the source contact in the fin. The gate contact ensures a low-resistance pathway connectable to the control circuit operating the power FinFET.

[0024] A second passivation layer is separating the gate contact and the source contact aligned at the top of the fin. The potential difference between the source contact and the drain contact causes a flow of charge carriers if present. The source contact ensures a low-resistance pathway connectable to the control circuit operating the power FinFET. Thus, electrical current can flow between the drift region and the source contact. R.415308 - 5 -

[0025] Preferably, the source contact, the drain contact and / or the gate contact are metal contacts that exhibit an ohmic characteristic.

[0026] A metal layer is aligned to the second passivation layer and extending form base, wherein the metal layer forms a Schottky barrier with the drift region. Preferably, the metal layer extends up to the same high as the fin. The source contact may transition into the metal layer and / or the chosen metal for the source contact and the metal layer may be the same or distinct, dependent on the process and materials employed. The chosen type of metal for the metal layer in combination with the chosen type of ultra-wide bandgap material used for the drift region are main influences on the work function of the Schottky barrier. A higher work function results in a rise of leakage currents in the off-state of the power FinFET compared to a lower work function, but results in a higher current density in the on-state.

[0027] The Schottky barrier formed by the metal layer and the drift region enables the protection of the passivation layers and thus enhances the overall reliability of the power FinFET. The power FinFET according to the invention further ensures robust operation in the III quadrant, rendering the power FinFET surge-resistant, while not affecting the power FinFET’s usual on / off behavior and the properties of the interface between the drift region and the first passivation layer. Further, the metal layer establishes an additional thermal dissipation path that further contributes to the power FinFET’s reliability and performance.

[0028] Advantageous embodiments of the invention, which can be realized on their own or in combination, are described in the dependent claims.

[0029] In an advantageous embodiment of the invention, it is conceivable that the ultrawide bandgap semiconductor material is monoclinic Gallium(lll)-oxide (|3-Ga2O3), Aluminum nitride (AIN) or diamond. In [3-Ga2O3, n-type doping is attainable through silicon implantation or tin incorporation during epitaxial growth. Both dopant types create shallow donor levels within the bandgap. P-type doping can be attained through nickel oxide or iridium gallium oxide (a-QrGahOs) in conjunction with corundum gallium oxide (a-Ga2O3). Nickel oxide exhibits p-type conductivity tied to defects like Lithium vacancies that are adjustable through radio frequency sputtering argon or oxygen flow control. Similarly, a-QrGahOs, in conjunction with the a-Ga2Os polymorph has been effective to provide p-type conductivity. In AIN, n-type doping is attainable through silicon as well, p-type R.415308 - 6 - doping seams possible through Beryllium. In diamond, n-type doping is attainable through phosphorous or nitrogen and p-type through Boron. When AIN or diamond is used, the first, the second and / or the third passivation layer is preferably made of aluminum oxide (AI2O3) or silicon dioxide (SiCh).

[0030] Notably, while creating a Schottky barrier on an n-type layer, the selection of a metal with a higher work function than the semiconductor electron affinity is crucial. This choice prevents the formation of an ohmic contact, ensuring superior blocking capability. This ensures an effective operation and an extended lifespan of the power FinFET.

[0031] In an advantageous embodiment of the invention, it is conceivable that the power FinFET comprises a third passivation layer disposed between the lateral surface and the first passivation layer. This reduces premature breakdowns by mitigating the electric field's intensity at the conjunction of the base and the fin. Such structures can be achieved with slight process flow adjustments involving spacer deposition followed by planarization. The first passivation layer and the third passivation layer may consist of identical or different materials based on the preferred process and the desired quality or type of the interface between the third passivation layer and lateral surface.

[0032] In an advantageous embodiment of the invention, it is conceivable that the metal layer extends between the lateral surface and the first passivation layer towards the fin. This layout reduces the electric field intensity at the conjunction of the base and the fin, which improves the power FinFET’s lifespan. Preferably, the metal layer extends to the fin or the metal layer does not extend to the fin, while a third passivation layer is disposed between the lateral surface, the first passivation layer, the metal layer and the fin.

[0033] In an advantageous embodiment of the invention, it is conceivable that the base comprises at least one groove, wherein the metal layer extends into the groove. This layout reduces the electric field intensity at the conjunction between the base and thus improving the power FinFET’s lifespan. Preferably, the groove is disposed at the edge of the base.

[0034] In an advantageous embodiment of the invention, it is conceivable that the metal layer is grounded, floating or connected to the control circuit operating the power FinFET. If grounded or connected to the control circuit the metal layer can serve as an additional current path in the III quadrant operation reducing the electric R.415308 - 7 - field's intensity at the conjunction between the base and the fin. The connection to the circuitry operating the power FinFET allows for additional control and thus reduction of the draw backs of implicating the metal layer. A floating metal layer is easy to obtain.

[0035] In an advantageous embodiment of the invention, it is conceivable that in that the first passivation layer, the gate contact, the second passivation and the metal layer form a loop surrounding the fin. If the power FinFET comprises a third passivation layer, it is preferable that the third passivation layer forms a loop surrounding the fin as well. This layout allows for a higher control and more efficient usage of the fin. Preferably, the loop is square or hexagonal. These are forms which can be arranged in a gapless way and thus raising the efficiency in production.

[0036] Alternatively, the first passivation layer, the gate contact, the second passivation and the metal layer as well as the third passivation layer if present are at least two-parted and the two parts are disposed on opposite sides of the fin.

[0037] In an advantageous embodiment of the invention, it is conceivable that in that the metal layer is more-parted. More-parted layer refers to a discontinuous layer. Preferably, all parts of the more-parted layer are arranged on the same plane. This mitigates the rise in leakage currents, as this rise is attributed to thermionic field emissions. Preferably, the metal layer is arranged in a regular pattern and / or is formed as stripes. The second passivation layer preferably fills in the gabs between the parts of the more-parted metal layer.

[0038] It is understood that the definitions and / or embodiments of the above terms apply to all aspects described below in this description, unless otherwise indicated.

[0039] A power FinFET arrangement according to the invention comprises at least two power FinFETs descripted above and is characterized in that the at least two power FinFETs share a metal layer. The shared metal layer enables field relaxation and robust surge operation within the III quadrant for the adjacent power FinFETs. Preferably, the arrangement comprises between three and 20 power FinFETs arranged circular around the shared metal layer. R.415308 - 8 -

[0040] BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Fig. 1 shows a cross section side view and a cross section top view of a first embodiment of a power FinFET according to the invention;

[0042] Fig. 2 shows a cross section side view of the first embodiment of the power FinFET according to the invention in different operation states;

[0043] Fig. 3 shows a cross section side view of a second embodiment of a power FinFET according to the invention;

[0044] Fig. 4 shows a cross section side view of a third embodiment of a power FinFET according to the invention;

[0045] Fig. 5 shows a cross section top view of a forth embodiment of a power FinFET according to the invention;

[0046] Fig. 6 shows a top view of a first embodiment of a power FinFET arrangement according to the invention;

[0047] Fig. 7 shows a top view of a second embodiment of a power FinFET arrangement according to the invention;

[0048] Fig. 8 shows a top view of a third embodiment of a power FinFET arrangement according to the invention; and

[0049] Fig. 9 shows a top view of a forth embodiment of a power FinFET arrangement according to the invention.

[0050] DETAILED DESCRIBTION OF THE DRAWINGS

[0051] Further details, features and advantages of the invention are apparent from the following description of preferred exemplary embodiments in connection with the dependent claims. The respective features can be realized on their own or as a combination of several features together. The invention is not limited to the described embodiments. The embodiments are shown schematically in the figures. Identical reference numbers in the individual figures refer to identical or functionally identical elements or elements which correspond to each other regarding their function.

[0052] Fig. 1 shows a cross section side view (a) and a cross section top view (b) of a first embodiment of a power FinFET 100 according to the invention. The power FinFET 100 comprises a drain contact 1 , which is formed by a metal plate and aligned in direct contact to a substrate region 2. A drift region 3 is adjoined to the substrate region 2. The substrate region 2 and the drift region 3 are made of an ultra-wide bandgap semiconductor material which is n-type doped. The drift region 3 is divided into a base 31 with a lateral surface 32 and a fin 33. A two- R.415308 - 9 - parted L-shaped first passivation layer 5 is arranged next to the fin 33 with one leg of the L aligned to the fin 33 and the other leg extending parallel to the lateral surface 32. A two-parted L-shaped gate contact 7 is arranged next to first passivation layer 5. On top of the gate contact 7, there is a two-parted second passivation layer 8 encapsulating the gate contact 7. A two-parted metal layer 11 is disposed on the lateral surface 32 next to the first passivation layer 5 and the second passivation layer 8. The fin 33 comprises a doped high doping concentration region 4 at the top. A source contact 6 is aligned to the top of the fin 33. A two-parted third passivation layer 9 is disposed between the lateral surface 32, the first passivation layer 5, the metal layer 11 and the fin 33.

[0053] Fig. 2 shows a cross section side view of the first embodiment of the power FinFET 100 according to the invention in different operations states. The first depiction (a) shows an on-state, with a potential difference between the gate contact 7 and the source contact 6 being greater than 0V. Charge carriers 14 drift from the towards the source contact 6 to the drain contact 1 in an electric field caused by a potential difference between the drain contact 1 and the source contact 6 being greater than 0V. This operation is called I quadrant operation. During the on-state the metal layer 11 slightly constrains the available path for the charge carriers 14. To counteract the increase in resistance, one approach is to enhance the conductivity of the power FinFET 100 near the metal layer 11. This can be achieved by widening the fin 33, locally increasing the doping concentration or adjusting the metal layer’s 11 metal work function appropriately. Alternatively, the gate contact 7 can be made from polysilicon and its doping concentration can be tailored to render the power FinFET 100 more inherently conductive and move the threshold voltage accordingly.

[0054] The second depiction (b) shows a state where the potential difference between the gate contact 7 and the source contact 6 is 0V while the potential difference between the drain contact 1 and the source contact 6 being smaller than 0V. In this so called III quadrant operation, the metal layer 11 introduces an added pathway for the current flow, which effectively addresses concerns tied to surge current and freewheeling operation. This behavior remains irrespective of the device's inherent on / off characteristics, the latter of which only applies to devices that are naturally on or weakly normally off, with the potential difference between the gate contact 7 and the source contact 6 being 0V. The supplemental metal layer 11 outlined in this embodiment can be linked to a heatsink or more generally provide an extra route for dissipating heat. This connection is tied into the usual thermal interface located at the substrate region’s 2 bottom. This R.415308 - 10 - flexibility enhances cooling efficiency, particularly at the point of maximum junction temperature.

[0055] The third depiction (c) shows a state where the potential difference between the gate contact 7 and the source contact 6 smaller than 0V while the potential difference between the drain contact 1 and the source contact 6 being greater than 0V. In this off-state charge carriers 14 are not available. An additional depletion effect is introduced due to the reverse bias Schottky barrier, which acts as a safeguard for the first passivation layer 5 and the third passivation layer 9. The depletion is marked with a dashed line. This additional depletion can combine with the primary depletion originating from the fin 33, leading to a reduction in the electric field across the first passivation layer 5 and the third passivation layer 9.

[0056] Fig. 3 shows a cross section side view of a second embodiment of a power FinFET 100 according to the invention. The second embodiment is similar to the first embodiment, but missing the third passivation layer. The metal layer 11 extends between the lateral surface 32 and the first passivation layer 5 to the fin 33 by the distance t. Varying the distance t can be used to tune FinFET’s 100 performance.

[0057] Fig. 4 shows a cross section side view of a third embodiment of a power FinFET 100 according to the invention. The third embodiment is similar to the first embodiment, but the base 32 having grooves 15 at the edge with the metal layer 11 extending into the grooves 15. The grooves 15 have the depth la.

[0058] Fig. 5 shows a cross section top view of a forth embodiment of a power FinFET 100 according to the invention. The third embodiment is similar to the first embodiment, but the metal layer 11 being divided into six stripe-formed parts equally distributed along the fin 33. The parts of the metal layer 11 have the length of a1 and are spaced apart by the length of a2. The length of a1 and a2 may be tuned to attain a desired thermal performance of the FinFET 100.

[0059] Fig. 6 shows a top view of a first embodiment of a power FinFET 100 arrangement according to the invention. The power FinFETs’ 100 metal layers 11 , first passivation layers 5, second passivation layers 8 and the gate contacts 7 are formed as a square loop surrounding the fins 33 under the source contacts 6. The power FinFETs 100 are arranged as a 3x3 square. R.415308 - 11 -

[0060] Fig. 7 shows a top view of a second embodiment of a power FinFET 100 arrangement according to the invention. The power FinFETs’ 100 metal layers 11 , first passivation layers 5, second passivation layers 8 and the gate contacts 7 are formed as a hexagonal loop surrounding the fins 33 under the source contacts 6. The power FinFETs 100 are arranged like honeycombs.

[0061] Fig. 8 shows a top view of a third embodiment of a power FinFET 100 arrangement according to the invention. The power FinFETs’ 100 first passivation layers 5, second passivation layers 8 and the gate contacts 7 are formed as a square loop surrounding the fins 33 under the source contacts 6. The power FinFETs 100 are arranged circular around a shared metal layer 11 .

[0062] Fig. 9 shows a top view of a third embodiment of a power FinFET 100 arrangement according to the invention. The power FinFETs’ 100 first passivation layers 5, second passivation layers 8 and the gate contacts 7 are formed as a square hexagonal surrounding the fins 33 under the source contacts 6. The power FinFETs 100 are arranged circular around a shared metal layer 11 .

Claims

R.415308 - 12 -CLAIMS1 . Power Field-effect transistor comprising a fin (FinFET) (100), wherein the power FinFET (100) comprises a drain contact (1), a substrate region (2) of a first dope type aligned to the drain contact (1), a drift region (3) of the first dope type comprising a base (31) with a lateral surface (32) and a mesa region forming the fin (33), a first passivation layer (5) aligned partially to the fin (33) and partially extending parallel to the lateral surface (32), a gate contact (7) aligned at least partially to the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) aligned at a top of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material, characterized in that the power FinFET (100) comprises a metal layer (11) aligned to the second passivation layer (8) and extending form base (31), wherein the metal layer (11) forms a Schottky barrier with the drift region (3).

2. Power FinFET (100) according to claim 1 , characterized in that the ultrawide bandgap semiconductor material is monoclinic Gallium(lll)-oxide ([3- Ga2O3), Aluminum nitride (AIN) or diamond.

3. Power FinFET (100) according to claim 1 or 2, characterized in that the FinFET (100) comprises a third passivation layer (9) disposed between the lateral surface (32) and the first passivation layer (5).

4. Power FinFET (100) according to any of the previous claims, characterized in that the metal layer (11) extends between the lateral surface (32) and the first passivation layer (5) towards the fin (33).

5. Power FinFET (100) according to any of the previous claims, characterized in that the base (31) comprises at least one groove (15), wherein the metal layer (11) extends into the groove (15).

6. Power FinFET (100) according to any of the previous claims, characterized in that the metal layer (11) is grounded, floating or connected to a circuitry operating the power FinFET (100).R.415308 - 13 -7. Power FinFET (100) according to any of the previous claims, characterized in that the first passivation layer, the gate contact (7), the second passivation and the metal layer (11) form a loop surrounding the fin (33).

8. Power FinFET (100) according to claim 7, characterized in that the loop is square or hexagonal.

9. Power FinFET (100) according to any of the previous claims, characterized in that the metal layer (11) is multi-parted.

10. Power FinFET (100) arrangement comprising at least two power FinFETs according to claim 1 to 9, characterized in that the at least two power FinFETs share a metal layer (11).

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