Power field-effect transistor comprising a fin

Abstract

The invention relates to a Power Field-effect transistor comprising a fin (FinFET) (100), wherein the power FinFET (100) comprises a drain contact (1), a substrate region (2) of a first dope type aligned to the drain contact (1), a drift region (3) of the first dope type comprising a base (31) with a lateral surface (32) and a mesa region forming the fin (33), a first passivation layer (5) aligned partially to the fin (33) and partially extending parallel to the lateral surface (32), a gate contact (7) aligned at least partially to the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) aligned at a top of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material.

Description

[0001] R.415284 - 1 -

[0002] Description

[0003] Power field-effect transistor comprising a fin

[0004] FIELD

[0005] The invention relates to a Power field-effect transistor comprising a fin.

[0006] BACKGROUND

[0007] Junction-less field-effect transistors (FET) have become favored for applications that transfer at a comparable high power, especially in the mid-voltage range of 1200 V to 3300 V targeting automotive and industrial applications. FETs are vertical unipolar devices encompassing one or more conductivity layer of one dope type, with low activation energy, offering numerous free charge carriers without compromising blocking capability or dynamic response associated with deep levels. The conductivity layer comprises a mesa region forming a fin. This type of FET is called FinFET. The fin allows for significantly faster switching times and higher current density compared to planar FETs.

[0008] Beyond the conductivity layer power FinFETs incorporate a passivation layer, preferable an oxide layer, for the gate. The passivation layer introduces energy barriers, preferably against both conduction and valence bands, and enables gate control within the fin. This passivation layer must have minimal interfacial traps at the semiconductor interface to facilitate effective gate control. In order to reduce leakage currents it is known to use a material of a different dope type.

[0009] Due to their remarkable material properties, such as a low intrinsic carrier concentration and high electric field strength, ultra-wide bandgap semiconductors materials have emerged as a compelling option for the conductivity layers within the realm of power electronics. The exceptional impact ionization coefficients exhibited by these materials facilitate the reduction in size of the conductivity layers e.g. the drift region. Consequently, this downsizing contributes to R.415284 - 2 - enhanced benefits in relation to the specific on-state resistance compared to Silicon and other wide bandgap semiconductors such as 4H-Silicon Carbide (4H- SiC) and Gallium nitride (GaN), all while maintaining equivalent blocking capabilities.

[0010] Nonetheless, challenges tied to insufficient doping control and early breakdown failure have constrained the potential enhancement of electrical performance in device structures. Further, power FinFETs made from ultra-wide bandgap materials encounter several challenges and reliability issues, like premature breakdowns due to high gate leakage currents or oxide failures, the gate control's efficacy relying on interface quality, impacting the on / off performance and mobility, particularly influenced by the interface between the passivation layer and the conductivity layer, inadequate operation in the III quadrant due to the lack of an intrinsic body diode and limited short-circuit performance if the conductivity layer consists of a material with poor thermal conductivity.

[0011] Alternative approaches to tackle premature breakdowns introduce a layer of the second type, shifting the peak electric field away from the passivation layer's interface. However, this technique might not be as effective in ultra-wide bandgap power FinFETs, because of a poor controllability of second type’s doping and high activation energy.

[0012] To tackle the inadequate operation in the III quadrant, an alternative layout featuring a trench metal-oxide-semiconductor barrier Schottky diode and a junctionless FET has been introduced. However, this approach's drawback lies in the limited availability of active device area. Furthermore, techniques that make use of a p-shield typically specify that the potential of this layer should be coupled with the source terminal and thus grounded throughout the operation of the device. This approach presents certain limitations as it can limit the on state current due to the presence of a non-negligible depletion region.

[0013] Therefore, there is a great demand for a power FinFET using an ultra-wide bandgap semiconductor material for conductivity layers in order to make use of the advantages thereof while overcoming aforementioned drawbacks. This invention has the object to overcome these problems. R.415284 - 3 -

[0014] DISCLOSURE OF THE INVENTION

[0015] This object is attained in a surprisingly simple but effective manner by a power Field-effect transistor comprising a fin (FinFET), wherein the power FinFET comprises a drain contact, a substrate region of a first dope type aligned to the drain contact, a drift region of the first dope type comprising a base with a lateral surface and a mesa region forming the fin, a first passivation layer aligned partially to the fin and partially extending parallel to the lateral surface, a gate contact aligned at least partially to the first passivation layer, a second passivation layer separating the gate contact and a source contact aligned at a top of the fin, wherein a material of the substrate region and the drift region is an ultra-wide bandgap semiconductor material. The power FinFET is characterized in that the power FinFET comprises a barrier layer aligned to the lateral surface, wherein the barrier layer is of a second dope type.

[0016] The main idea of the invention is to reduce the electric field at the conjunction between the base and the fin in the on-state of the power FinFET. This reduces premature breakdowns of the power FinFET. Notably, this protection mechanism plays a vital role in mitigating issues such as Time-Dependent Dielectric Breakdown (TDDB) and hot carrier injection.

[0017] The power FinFET according to the invention comprises drain contact which is formed by a suitable material ensuring a low-resistance pathway connectable to a control circuit operating the power FinFET.

[0018] A substrate region of a first dope type is aligned to the drain contact. Thus electrical current can be transferred between the substrate region and the drain contact. The first dope type can be either an n-type doped or p-type doped. The substrate region material is an ultra-wide bandgap semiconductor material. An ultra-wide bandgap semiconductor material is a semiconductor material with a bandgap significant larger than the bandgaps of wide bandgap semiconductor materials. A semiconductor material with a bandgap of more than 3.4 eV is usually referred to as an ultra-wide bandgap semiconductor material. Examples for ultra-wide

[0019] A drift region of the first dope type is aligned to the substrate region. The first dope type of the drift region can be either an n-type doped or p-type doped, as long as the doped type is identical to the dope type of the substrate region. The R.415284 - 4 - substrate region material is an ultra-wide bandgap semiconductor material, preferably the same material as the substrate region. The drift region has preferable a lower doping concentration than the substrate region. The purpose of the drift region is providing intrinsic charge carriers in an on-state of the power FinFET and suppress the intrinsic charge carriers in an off-state of the power FinFET. The drift region and the substrate region are conductivity layers.

[0020] The ultra-wide bandgap semiconductor material may be monoclinic Gallium(lll)- oxide (|3-Ga2O3), Aluminum nitride (AIN) or diamond. In [3-Ga2O3, n-type doping is attainable through silicon implantation or tin incorporation during epitaxial growth. Both dopant types create shallow donor levels within the bandgap. P-type doping can be attained through nickel oxide or iridium gallium oxide (a-QrGahOs) in conjunction with corundum gallium oxide (a-Ga2O3). Nickel oxide exhibits p- type conductivity tied to defects like Lithium vacancies that are adjustable through radio frequency sputtering argon or oxygen flow control. Similarly, a-QrGahOs, in conjunction with the a-Ga2Os polymorph has been effective to provide p-type conductivity. In AIN, n-type doping is attainable through silicon as well, p-type doping is seams possible through Beryllium. In diamond, n-type doping is attainable through phosphorous or nitrogen and p-type through Boron. When AIN or diamond is used, a first, a second and / or a third passivation layer is preferably made of aluminum oxide (AI2O3) or silicon dioxide (SiCh).

[0021] The drift region comprises a base with a lateral surface and a mesa region forming the fin. The lateral surface extends on the top of the base from the fin to the edge of the base. The fin preferably comprises a high doping concentration region at the top of the fin.

[0022] A first passivation layer is aligned partially to the fin and partially extending parallel to the lateral surface. The passivation layer has preferably an L-shaped cross section with one leg of the L aligned to the fin and the other leg of the L aligned to the lateral surface. Preferably, the passivation layer material is an oxide. The passivation layer serves a galvanic isolation between the drift region and a gate contact. The gate contact is aligned at least partially to the first passivation layer. The passivation layer may extend further than the gate contact. The potential difference between the gate contact and a source contact is controlling the on / off-state of the power FinFET via the electric field built up between the gate contact and the source contact in the fin. The gate contact R.415284 - 5 - ensures a low-resistance pathway connectable to the control circuit operating the power FinFET.

[0023] A second passivation layer is separating the gate contact and the source contact aligned at a top of the fin. The potential difference between the source contact and the drain contact causes a flow of charge carriers if present. The source contact ensures a low-resistance pathway connectable to the control circuit operating the power FinFET. Thus, electrical current can flow between the drift region and the source contact.

[0024] Preferably, the source contact, the drain contact and / or the gate contact are metal contacts that exhibit an ohmic characteristic.

[0025] Preferably, the power FinFET comprises a third passivation layer disposed between the lateral surface and the first passivation layer. The first passivation layer and the third passivation layer may consist of identical or different materials based on the preferred process and the desired quality or type of the interface between the third passivation layer and lateral surface. The third passivation layer may extend next to the barrier layer or at least partially on top of the barrier layer. If the third passivation layer is arranged next to the barrier layer, the lengths of the third passivation layer and the barrier layer can be varied for tuning state performance and state conduction.

[0026] A barrier layer is aligned to the lateral surface, wherein the barrier layer is of a second dope type. The second dope type is different from the first dope type. The second dope type can be n-type doped if the first dope type is p-type doped or p- type doped if the first dope type is n-type doped. Thus, a power FinFET with a long term reliability is obtained.

[0027] Advantageous embodiments of the invention, which can be realized on their own or in combination, are described in the dependent claims.

[0028] In an advantageous embodiment of the invention, it is conceivable that the barrier layer is at least partly made of a first material, wherein the first material is the same material of the substrate region. This enables an effective protection of the first passivation layer. The drawback of a lower switching speed caused by the dynamic of incomplete ionization may be compensated by the poor thermal conductivity of most ultra-wide bandgap materials, especially of [3-Ga2O3. The R.415284 - 6 - continuous operation of the power FinFET will raise the temperature at the conjunction between the base and the fin to levels, which are sufficient to enable good activation of dopant species in the barrier layer.

[0029] In an advantageous embodiment of the invention, it is conceivable that the barrier layer is at least partly made of a second material, wherein the second material is different to the material of the substrate region. This ensures a correct function of the power FinFET at low temperatures with fast switching speed. The barrier layer provides a higher number of charge carriers and allow for more robust III quadrant operation. Preferably, the material is an oxide, especially NiO. The barrier layer may be partly made of the first material and partly made of the second material, with the materials being arranged on top of each other or next to each other.

[0030] In an advantageous embodiment of the invention, it is conceivable that the barrier layer extends from an edge of the base to fin. This allows for the best protection of the first passivation layer. However, in order to enhance state performance and state conduction, it is conceivable to shorten the barrier layer on the fin side and / or on the edge side.

[0031] In an advantageous embodiment of the invention, it is conceivable that the barrier layer is more-parted. More-parted layer refers to a discontinuous layer. Preferably, all parts of the more-parted layer are arranged on the same plane. The barrier layer as well as the first passivation layer, the gate contact, the second passivation, the third passivation layer a conductive layer and / or a metal layer are preferably least two-parted and the two parts are disposed on opposite sides of the fin. Alternatively, the barrier layer, the first passivation layer, the gate contact, the second passivation, the third passivation layer, the conductive layer and / or the metal layer form a loop surrounding the fin. Further, the barrier layer may be more-parted and arranged in a regular or irregular pattern along the lateral surface. The barrier layer may have 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 , 12, 13, 14, 15, 16, 17, 18, 19, 20 or more parts. This allows for a tuning of desired performances like the degree of transparency.

[0032] In an advantageous embodiment of the invention, it is conceivable that the power FinFET comprises a metal layer and / or a conductive layer aligned to the second passivation layer and extending form base and / or the barrier layer. The metal layer reduces the leakage current as it forms a Schottky barrier between the R.415284 - 7 - metal layer and the drift region. The conductive layer is connected to the barrier layer enabling a connection of the barrier layer to the control circuit. This leads to an additional attenuation of the electric field present in the first passivation layer. Preferably, the metal layer and / or the conductive layer can extend up to the same high as the fin. More preferably, the metal layer and / or the conductive layer is grounded, floating or connected to the control circuit operating the power FinFET. If grounded or connected to the control circuit, the metal layer and / or the conductive layer can serve as an additional current path in the III quadrant operation reducing the electric field's intensity at the conjunction between the base and the fin. The connection to the control circuit allows for additional control and thus reduction of the draw backs of implicating the metal layer and / or the conductive layer. A floating metal layer and / or the conductive layer is easy to obtain.

[0033] In an advantageous embodiment of the invention, it is conceivable that the metal layer and / or the conductive layer extends between the lateral surface and the first passivation layer towards the fin. This layout reduces the electric field intensity at the conjunction between the base and the fin, thus improving the power FinFET’s lifespan. Preferably, the metal layer and / or the conductive layer extends to the fin.

[0034] In an advantageous embodiment of the invention, it is conceivable that the metal layer and / or the conductive layer extends next to the barrier layer. This layout reduces the electric field intensity at the conjunction between the base and the fin, thus improving the power FinFET’s lifespan.

[0035] In an advantageous embodiment of the invention, it is conceivable that the power FinFET comprises a circuit comprising a first connection point, a first resistor, a second connection point, a second resistor and a third connection point connected in series, wherein the first connection point is connected to the gate contact, the second connection point is connected to the metal layer and / or the conductive layer and the third connection point is grounded. The barrier layer has the drawback of potentially reducing the power FinFET’s breakdown voltage, increasing the electric field in the during the-off state and raising the power FinFET’s gate-drain capacitance. A circuit as described above mitigates the risk of parasitic diode turn-on. The first resistor and / or the second resistor are preferably ten times larger than a gate resistor connected with the gate contact. Further preferably, the first resistor and / or the second resistor are larger than R.415284 - 8 -

[0036] 1 kQ. More preferably, the second resistor is 20 % of the first resistor. Most preferably, the first resistor has a positive temperature coefficient and / or the second resistor has a negative temperature coefficient.

[0037] In an advantageous embodiment of the invention, it is conceivable that the circuit comprises a diode connected parallel to the first resistor, wherein a forward direction of the diode is leading from the second connection point to the first connection point and / or the circuit comprises a capacitor connected parallel to the second resistor. This enables the negative biasing of the metal layer and / or the conductive layer, thus providing a complete protection to the first passivation layer and / or the third passivation layer and improving the power FinFET’s live span and reliability. Thecapacitiy of the capacitor is preferably in a range from 0,1 pF to 20 pF, more preferable in a range from 1 pF to 10 pF, most preferably 5 pF.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Fig. 1 shows a cross section side view of a first embodiment of a power FinFET according to the invention;

[0040] Fig. 2 shows a cross section side view of a second embodiment of a power FinFET according to the invention;

[0041] Fig. 3 shows a top view of a third embodiment of a power FinFET according to the invention;

[0042] Fig. 4 shows a cross section side view of a forth embodiment of a power FinFET according to the invention;

[0043] Fig. 5 shows a cross section side view of a fifth embodiment of a power FinFET according to the invention;

[0044] Fig. 6 shows a cross section side view of a sixth embodiment of a power FinFET according to the invention;

[0045] Fig. 7 shows a scheme of a first embodiment of a circuit connected to a power FinFET arrangement according to the invention; and

[0046] Fig. 8 shows a scheme of a second embodiment of a circuit connected to a power FinFET arrangement according to the invention.

[0047] DETAILED DESCRIBTION OF THE DRAWINGS

[0048] Further details, features and advantages of the invention are apparent from the following description of preferred exemplary embodiments in connection with the R.415284 - 9 - dependent claims. The respective features can be realized on their own or as a combination of several features together. The invention is not limited to the described embodiments. The embodiments are shown schematically in the figures. Identical reference numbers in the individual figures refer to identical or functionally identical elements or elements which correspond to each other regarding their function.

[0049] Fig. 1 shows a cross section side view of a first embodiment of a power FinFET 100 according to the invention. The power FinFET 100 comprises a drain contact

[0050] 1 , which is formed by a metal plate aligned in direct contact to a substrate region

[0051] 2. A drift region 3 is adjoined to the substrate region 2. The substrate region 2 and the drift region 3 are made of an ultra-wide bandgap semiconductor material which is n-type doped. The drift region 3 is divided into a base 31 with a lateral surface 32 and a fin 33. A two-parted L-shaped first passivation layer 5 is arranged next to the fin 33 with one leg of the L aligned to the fin 33 and the second leg arranged parallel to the lateral surface 32. A two-parted L-shaped gate contact 7 is arranged next to first passivation layer 5. On top of the gate contact 7, there is a two-parted second passivation layer 8 encapsulating the gate contact 7. A two-parted conductive layer 13 is disposed on the lateral surface 32 next to the first passivation layer 5 and the second passivation layer 8. The conductive layer 13 is preferably made from metal. At the top of the fin 33, there is a high doping concentration region 4. A source contact 6 is aligned to the top of the fin 33. A two-parted third passivation layer 9 is disposed between the lateral surface 32, the first passivation layer 5, the metal layer 13 and the fin 33. A barrier layer 10 is located at the top of the base 31 , beginning form the edge of the base 31 and extending towards the fin 33. The barrier layer 10 is shortened by the distance d on the fin side in order in to enhance state performance and state conduction. The barrier layer 10 is made from the same ultra-wide bandgap semiconductor material as the substrate region 2 and the drift region 3, but p-type doped.

[0052] Fig. 2 shows a cross section side view of a second embodiment of a power FinFET 100 according to the invention. The second embodiment is similar to the first embodiment, but the barrier layer 12 and the third passivation layer 9 are arranged next to each other. The third passivation layer 9 has the length of distance d2, by which the barrier layer 10 is shortened. The length of distance d2 can be varied in order in to tune state performance and state conduction. A metal R.415284 - 10 - layer 11 extends from the barrier layer 12. The barrier layer 12 is made from a p- typed doped oxide.

[0053] Fig. 3 shows a top view of a third embodiment of a power FinFET 100 according to the invention. The third embodiment is similar to the first embodiment and the second embodiment, but the conductive layer 13 and the barrier layer (not shown) being more parted. A more-parted metal layer 11 forming a Schottky barrier with the base (not shown) is arranged between the parts of the metal layer 11 in a regular alternating pattern on both sides if the fin 33. The parts of the metal layer 11 has the length of a1 and the parts of the conductive layer 13 have the length of a2. The length of a1 and a2 may be tuned to attain desired performances. The parts of the barrier layer are arranged beneath the parts of the conductive layer 13.

[0054] Fig. 4 shows a cross section side view of a forth embodiment of a power FinFET 100 according to the invention. The forth embodiment is similar to the first embodiment, but the conductive layer is replaced by a L-shaped metal layer 11 , the first leg extending parallel to the fin 33 and the second leg extends from the edge of the base 31 to the fin 33. The second leg of the metal layer 11 is arranged between the barrier layer 10 and the first passivation layer 5 replacing the third passivation layer 9 of the first embodiment. The barrier layer 10 is shortened by the distance d on the fin 33 side in order in to enhance state performance and state conduction.

[0055] Fig. 5 shows a cross section side view of a fifth embodiment of a power FinFET 100 according to the invention. The fifth embodiment is similar to the second embodiment, but the metal layer 11 is L-shaped, the first leg extends upwards parallel to the fin 33 and the second leg extends from the edge of the base 31 to the fin 33. The second leg of the metal layer 11 is arranged between the barrier layer 12 and the first passivation layer 5 replacing the third passivation layer 9 of the second embodiment. At the end of the second leg, the metal layer 11 extends downwards towards the lateral surface 32 next to the barrier layer 12.

[0056] Fig. 6 shows a cross section side view of a sixth embodiment of a power FinFET 100 according to the invention. The sixth embodiment is similar to the forth embodiment, but barrier layer 10 being more-parted with the parts being arranged on both sides of the fin 33 on the lateral surface 32 at the fin 33 and at the edge of the base 31. The parts of the barrier layer 10 on each side of the fin R.415284 - 11 -

[0057] 33 have the length of d1 , while being spaced apart by distance d2. Varying d1 and d2 has influence on the degree of transparency.

[0058] Fig. 7 shows a scheme of a first embodiment of a circuit 14 connected to a power FinFET arrangement according to the invention. The circuit 14 comprises a first connection point connected to the gate contact 7, a second connection point connected to the conductive layer 13 and a third connection point, which is grounded. A first resistor 15 is connected to the first connection point and the second connection point. A second resistor 16 is connected to the second connection point and the third connection point. The first resistor is 10 kQ and the second resistor is 2 kQ. A gate resistor 19 is connected to the first connection point.

[0059] Fig. 8 shows a scheme of a second embodiment of a circuit 14 connected to a power FinFET arrangement according to the invention. The second embodiment is similar to the first, but a diode 17 is connected parallel to the first resistor 15 and a capacitor 18 is connected parallel to the second resistor 16.

Claims

R.415284 - 12 -CLAIMS1 . Power Field-effect transistor comprising a fin (FinFET) (100), wherein the power FinFET (100) comprises a drain contact (1), a substrate region (2) of a first dope type aligned to the drain contact (1), a drift region (3) of the first dope type comprising a base (31) with a lateral surface (32) and a mesa region forming the fin (33), a first passivation layer (5) aligned partially to the fin (33) and partially extending parallel to the lateral surface (32), a gate contact (7) aligned at least partially to the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) aligned at a top of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material, characterized in that the power FinFET (100) comprises a barrier layer (10, 12) aligned to the lateral surface (32), wherein the barrier layer (10, 12) is of a second dope type.

2. Power FinFET (100) according to claim 1 , characterized in that the barrier layer (10, 12) is at least partly made of a first material, wherein the first material is the same material of the substrate region (2).

3. Power FinFET (100) according to claim 1 or 2, characterized in that the in that the barrier layer (10, 12) is at least partly made of a second material, wherein the second material is different to the material of the substrate region.

4. Power FinFET (100) according to any of the previous claims, characterized in that the barrier layer (10, 12) extends from an edge of the base (31 ) to fin (33).

5. Power FinFET (100) according to any of the previous claims, characterized in that the barrier layer (10, 12) is more-parted.

6. Power FinFET (100) according to any of the previous claims, characterized in that the FinFET (100) comprises a metal layer (11) and / or an conductive layer (13) aligned to the second passivation layer (8) and extending form base (31) and / or the barrier layer (10, 12).R.415284 - 13 -7. Power FinFET (100) according to claim 6, characterized in that the metal layer (11) and / or the conductive layer (13) extends between the lateral surface (32) and the first passivation layer (5) towards the fin (33).

8. Power FinFET (100) according to claim 6 or 7, characterized in that the metal layer (11) and / or the conductive layer (13) extends next to the barrier layer (10, 12).

9. Power FinFET (100) according to any of claims 6 to 8, characterized in that the FinFET (100) comprises a circuit (14) comprising a first connection point, a first resistor (15), a second connection point, a second resistor (16) and a third connection point connected in series, wherein the first connection point is connected to the gate contact (7), the second connection point is connected to the metal layer (11) and / or the conductive layer (13) and the third connection point is grounded.

10. Power FinFET (100) according to claim 9, characterized in that the circuit (14) comprises a diode (17) connected parallel to the first resistor (15), wherein a forward direction of the diode (17) is leading from the second connection point to the first connection point and / or the circuit (14) comprises a capacitor (18) connected parallel to the second resistor (16).

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