Semiconductor device

Abstract

Provided is a semiconductor device with favorable electrical characteristics. This semiconductor device has first to third conductive layers, a semiconductor layer, and first and second insulating layers. The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first insulating layer has an opening that reaches the first conductive layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with a lateral surface of the first insulating layer in the opening, and a region in contact with the first conductive layer. In the opening, one of a pair of opposing portions of the lateral surfaces of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. An upper end portion of the lateral surface of the first insulating layer has a region overlapping a lower end portion of the second conductive layer in plan view. The third conductive layer faces the semiconductor layer through the second insulating layer in the opening.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a transistor and a semiconductor device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Furthermore, examples of the technical fields of one aspect of the present invention disclosed more specifically in this specification include LSI (Large Scale Integration) chips, CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), Application Specific Integrated Circuit (ASIC), AI (Artificial Intelligence) chips, memory (storage device), input device, input / output device, sensor, imaging device, display device, light-emitting device, energy storage device, electronic equipment, methods for driving them, or methods for manufacturing them.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product or method; or to a method (process), machine, manufacture, or composition of matter.

[0004] The technology of constructing transistors using semiconductor thin films formed on insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of this low leakage current characteristic. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time.

[0006] Also, In２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1).

[0007] Examples of oxide semiconductors applicable to the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-patent document 2 discloses a thin-film transistor using polycrystalline indium hydrogenate formed by low-temperature solid-phase crystallization as the active layer.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Dhananjay & Chu, C. W. Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, it aims to provide a semiconductor device with reduced wiring load. Alternatively, it aims to provide a semiconductor device capable of carrying large currents. Alternatively, it aims to provide a semiconductor device with high reliability. Alternatively, it aims to provide a semiconductor device that can be miniaturized. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device that can be arranged at high density. Alternatively, it aims to provide a semiconductor device with reduced parasitic capacitance. Alternatively, it aims to provide a semiconductor device with low power consumption.

[0011] One aspect of the present invention aims to provide a storage device with a high operating speed. Another aspect of the present invention aims to provide a display device with high resolution or a high aperture ratio.

[0012] One aspect of the present invention aims to provide a display device with a wide display area. Alternatively, one aspect of the present invention aims to provide a display device with a narrow non-display area. Alternatively, one aspect of the present invention aims to provide a display device with a narrow bezel area. Alternatively, one aspect of the present invention aims to provide a highly reliable display device.

[0013] One aspect of the present invention aims to provide a semiconductor device having a novel configuration. Another aspect of the present invention aims to improve at least one of the problems of the prior art.

[0014] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0015] One aspect of the present invention is a semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer has an opening that reaches the first conductive layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer at the opening, and a region in contact with the first conductive layer. At the opening, the second insulating layer has a portion in contact with the semiconductor layer and a portion in contact with the side surface of the first insulating layer. At the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in a plan view. The third conductive layer faces the semiconductor layer at the opening, via the second insulating layer. The first conductive layer has a fourth conductive layer. The fourth conductive layer has a first region that overlaps with the first insulating layer and a second region that is in contact with the semiconductor layer.

[0016] Another aspect of the present invention is a semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer has an opening that reaches the first conductive layer. In plan view, the opening is located inside the first conductive layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer at the opening, and a region in contact with the first conductive layer. At the opening, the second insulating layer has a portion in contact with the semiconductor layer and a portion in contact with the side surface of the first insulating layer. At the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in plan view. The third conductive layer faces the semiconductor layer at the opening, via the second insulating layer. The first conductive layer has a fourth conductive layer. The fourth conductive layer has a first region that overlaps with the first insulating layer and a second region that is in contact with the semiconductor layer.

[0017] In the semiconductor device described above, the first conductive layer preferably has two or more conductive layers, including a fourth conductive layer. The second conductive layer preferably has two or more conductive layers, including a fifth conductive layer. The fourth and fifth conductive layers preferably are conductive oxides. The upper surfaces of the fourth conductive layer and the fifth conductive layer preferably come into contact with the semiconductor layer.

[0018] In the above-described semiconductor device, it is preferable that the thickness of the second region is thinner than the thickness of the first region.

[0019] Another aspect of the present invention is a semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first conductive layer is located on the third conductive layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer has an opening that reaches the third insulating layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer at the opening, and a region in contact with the side surface of the first conductive layer at the opening. The second insulating layer has a portion in contact with the semiconductor layer at the opening, a portion in contact with the side surface of the first insulating layer, and a portion in contact with the third insulating layer. At the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in a plan view. The third conductive layer faces the semiconductor layer through the second insulating layer at the opening.

[0020] In the semiconductor device described above, it is preferable that the third conductive layer faces the side surface of the first conductive layer at the opening, via the second insulating layer.

[0021] In the semiconductor device described above, it is preferable that the first conductive layer is in contact with the opening and located outside the opening.

[0022] In the semiconductor device described above, it is preferable that the side surface of the first insulating layer and the side surface of the first conductive layer at the opening overlap in a plan view.

[0023] In the above-described semiconductor device, the opening is preferably rectangular in plan view.

[0024] In the above-described semiconductor device, the semiconductor layer is preferably a crystalline oxide semiconductor containing indium and oxygen.

[0025] One aspect of the present invention can provide a semiconductor device with good electrical characteristics, or a semiconductor device with reduced wiring load, or a semiconductor device capable of carrying large currents, or a semiconductor device with high reliability, or a semiconductor device that can be miniaturized, or a semiconductor device with a small footprint, or a semiconductor device that can be arranged at high density, or a semiconductor device with reduced parasitic capacitance, or a semiconductor device with low power consumption.

[0026] One aspect of the present invention can provide a storage device with a high operating speed. Another aspect of the present invention can provide a display device with high resolution or a high aperture ratio.

[0027] One aspect of the present invention can provide a display device with a wide display area. Alternatively, one aspect of the present invention can provide a display device with a narrow non-display area. Alternatively, one aspect of the present invention can provide a display device with a narrow bezel area. Alternatively, one aspect of the present invention can provide a highly reliable display device.

[0028] One aspect of the present invention can provide a semiconductor device having a novel configuration. One aspect of the present invention can improve upon at least one of the problems of the prior art.

[0029] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not need to address all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0030] Figures 1A, 1B, 1C, and 1D illustrate examples of semiconductor device configurations. Figures 2A, 2B, 2C, and 2D illustrate examples of semiconductor device configurations. Figures 3A and 3B illustrate examples of semiconductor device configurations. Figures 4A, 4B, and 4C illustrate examples of semiconductor device configurations. Figures 5A, 5B, 5C, and 5D illustrate methods for manufacturing semiconductor devices. Figures 6A, 6B, 6C, and 6D illustrate methods for manufacturing semiconductor devices. Figures 7A, 7B, 7C, and 7D illustrate methods for manufacturing semiconductor devices. Figures 8A, 8B, 8C, and 8D illustrate examples of semiconductor device configurations. Figures 9A, 9B, 9C, and 9D illustrate examples of semiconductor device configurations. Figures 10A, 10B, 10C, and 10D illustrate examples of semiconductor device configurations. Figures 11A, 11B, 11C, and 11D illustrate examples of semiconductor device configurations. Figures 12A, 12B, 12C, and 12D illustrate examples of semiconductor device configurations. Figures 13A, 13B, 13C, and 13D illustrate examples of semiconductor device configurations. Figures 14A, 14B, 14C, and 14D illustrate examples of semiconductor device configurations. Figures 15A, 15B, 15C, and 15D illustrate examples of semiconductor device configurations. Figures 16A and 16B illustrate examples of semiconductor device configurations. Figures 17A, 17B, 17C, and 17D illustrate examples of semiconductor device configurations. Figures 18A and 18B illustrate examples of semiconductor device configurations. Figures 19A and 19B illustrate examples of semiconductor device configurations. Figures 20A, 20B, 20C, 20D, and 20E illustrate examples of semiconductor device configurations. Figures 21A and 21B illustrate examples of semiconductor device configurations. Figures 22A and 22B illustrate the carrier concentration dependence of Hall mobility. Figure 22C is a cross-sectional view illustrating an indium oxide film. Figures 23A, 23B, and 23C illustrate examples of memory device configurations. Figure 24 illustrates an example of memory device configuration. Figures 25A, 25B, and 25C illustrate examples of memory device configurations. Figure 26 illustrates an example of memory device configuration. Figure 27 illustrates an example of memory device configuration.Figure 28 is a diagram illustrating an example of a memory device configuration. Figure 29 is a diagram illustrating an example of a memory device configuration. Figure 30 is a block diagram illustrating an example of a semiconductor device configuration. Figures 31A, 31B, 31C, 31D, 31E, 31F, 31G, and 31H are diagrams illustrating an example of a memory cell circuit configuration. Figures 32A, 32B, and 32C are perspective views illustrating an example of a semiconductor device configuration. Figures 33A and 33B are perspective views of a semiconductor device. Figure 34 is a perspective view of a semiconductor device. Figures 35A and 35B are diagrams illustrating an example of a display device configuration. Figure 36 is a diagram illustrating an example of a display device configuration. Figure 37 is a diagram illustrating an example of a display device configuration. Figure 38 is a diagram illustrating an example of a display device configuration. Figure 39 is a diagram illustrating an example of a display device configuration. Figures 40A, 40B, and 40C are diagrams illustrating an example of a display device configuration. Figures 41A and 41B are diagrams illustrating an example of a display device configuration. Figures 42A and 42B are diagrams illustrating an example of an electronic component. Figures 43A, 43B, and 43C show an example of a large-scale computer. Figure 43D shows an example of space equipment. Figure 43E shows an example of a storage system applicable to a data center. Figures 44A, 44B, 44C, and 44D show examples of electronic equipment configurations. Figures 45A, 45B, 45C, 45D, 45E, and 45F show examples of electronic equipment configurations. Figures 46A, 46B, 46C, 46D, 46E, 46F, and 46G show examples of electronic equipment configurations.

[0031] Embodiments will be described with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the contents of the embodiments shown below.

[0032] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0033] In the figures described herein, the size of each component, the thickness of the layers, the positional relationships, or the areas may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0034] In addition, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction".

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or layering order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0036] In this specification, when describing matters common to components distinguished by letters or numbers attached to their reference numerals (e.g., conductive layer 12a_1, conductive layer 12a_2), the reference numerals without letters or numbers (e.g., conductive layer 12) may be used for the description.

[0037] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0038] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing transistors, devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties.

[0039] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0040] In this specification, transistors using a metal oxide (oxide semiconductor) in the semiconductor layer, and transistors having a metal oxide (oxide semiconductor) in the channel formation region, may be referred to as OS transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0041] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region (also called a channel-forming region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel-forming region. In addition to the three terminals described above, a back gate may be present. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as the first gate, and the other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable.

[0042] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0043] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conductive state or interrupted state).

[0044] Furthermore, unless otherwise specified in this specification, on-current refers to the drain current when the transistor is in the on state (also called the "conducting state").

[0045] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to describe the connection relationships of circuit elements as physical objects. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; however, wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0046] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0047] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0048] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0049] In this specification, "plan view" means viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0050] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the side to be formed may be described as "down," and the direction opposite to the surface to be formed may be described as "up."

[0051] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0052] In this specification, "matching heights" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process, a planarization process (typically CMP (Chemical Mechanical Polishing) process) may be performed to expose the surfaces of one or more layers. In this case, the surfaces subjected to CMP processing will have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ due to differences in the processing equipment, processing method, materials of the surfaces subjected to CMP processing, or differences in polishing rate and etching rate. In this specification, this case will also be treated as "matching heights."

[0053] In this specification, "ends coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. This includes, for example, cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern.

[0054] In general, it is difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" includes both exact matches and approximate matches.

[0055] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0056] In this specification and the like, the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ 、A Ｙ 、A Ｚ respectively, the content rate of metal element X can be expressed as A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ , the content rate of metal element X can be expressed as B Ｘ / (B Ｘ + B Ｙ + B Ｚ ).

[0057] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method thereof according to one aspect of the present invention will be described.

[0058] FIGS. 1A to 1D are diagrams showing an example of a semiconductor device. FIG. 1A is a plan view of a semiconductor device having a transistor 10. FIG. 1B is a cross-sectional view taken along the dashed line A1 - A2 shown in FIG. 1A. FIG. 1C is a cross-sectional view taken along the dashed line B1 - B2 shown in FIG. 1A. FIG. 1D is a horizontal cross-sectional view taken along the dashed line C1 - C2 shown in FIG. 1B.

[0059] The transistor 10 has at least a conductive layer 12, a conductive layer 17, a conductive layer 20, a semiconductor layer 18, and an insulating layer 19. Part or all of the conductive layer 12 functions as one of the source electrode or the drain electrode. Part or all of the conductive layer 17 functions as the other of the source electrode or the drain electrode. Part or all of the conductive layer 20 functions as a gate electrode. Part or all of the insulating layer 19 functions as a gate insulating film.

[0060] The insulating layer 11 is provided on a substrate (not shown). The conductive layer 12 is provided on the insulating layer 11. The insulating layer 16 is provided on the conductive layer 12. The conductive layer 17 is provided on the insulating layer 16. The opening 90 is provided in the insulating layer 16 and reaches the conductive layer 12. The opening 90 also reaches the insulating layer 11. The upper end of the side surface of the insulating layer 16 in the opening 90 has a region that overlaps with the lower end of the conductive layer 17 in a plan view. At least a portion of the components of the transistor 10 are located within the opening 90. Specifically, at least a portion of each of the semiconductor layer 18, insulating layer 19, and conductive layer 20 is located within the opening 90. The semiconductor layer 18 is provided on the conductive layer 17 and is provided in contact with the side surface of the insulating layer 16 in the opening 90. The semiconductor layer 18 has a region that is in contact with the conductive layer 17 and the conductive layer 12. Furthermore, as shown in Figures 1B to 1D, the semiconductor layer 18 is provided on only one of a pair of opposing portions of the side surface of the insulating layer 16 at the opening 90, and the semiconductor layer 18 is not provided on the other of the pair of opposing portions of the side surface of the insulating layer 16. The insulating layer 19 is provided on the semiconductor layer 18 so as to cover the semiconductor layer 18. At the opening 90, the insulating layer 19 has a region in contact with the semiconductor layer 18 and a region in contact with the insulating layer 16. The conductive layer 20 is provided on the insulating layer 19. At least a part of the conductive layer 20 is located at the opening 90 and has a region between it and the semiconductor layer 18 with the insulating layer 19 sandwiched in between. The insulating layer 22 is provided on the conductive layer 20 and is provided so as to cover the conductive layer 20. Preferably, the upper surface of the insulating layer 22 is flat.

[0061] As shown in Figures 1A to 1C, the transistor 10 has a configuration in which current flows in the vertical direction, with one of the source electrode and drain electrode (here, the conductive layer 12) located below and the other source electrode and drain electrode (here, the conductive layer 17) located above. The source electrode and drain electrode are located at different heights (for example, heights perpendicular to the substrate surface or insulating plane on which the transistor is mounted), and the current flowing through the semiconductor layer flows in the height direction. That is, the channel length direction has a component in the height direction (vertical direction), and can therefore be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape. Therefore, semiconductor devices can be highly integrated. Furthermore, when a semiconductor device according to one embodiment of the present invention is used as a memory device, the storage capacity per unit area can be increased.

[0062] Below, we will explain more specific configuration examples and manufacturing method examples with reference to the drawings.

[0063] [Example of Semiconductor Device Configuration 1] Figures 2A to 2D show an example of a semiconductor device. Figure 2A is a plan view of a semiconductor device having a transistor 10A. Figure 2B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 2A. Figure 2C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 2A. Figure 2D is a horizontal cross-sectional view between the dashed lines C1 and C2 shown in Figure 2B.

[0064] Figures 3A and 3B are schematic perspective views of the semiconductor device shown in Figures 2A to 2D. In Figure 3B, some layers are omitted to make the structure easier to understand.

[0065] The transistor 10A has at least a conductive layer 12, a conductive layer 17, a conductive layer 20, a semiconductor layer 18, and an insulating layer 19. Part or all of the conductive layer 12 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 17 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 20 functions as a gate electrode. Part or all of the insulating layer 19 functions as a gate insulating film.

[0066] When transistor 10A is used as a memory cell, part or all of the conductive layer 17 functions as a bit line. Also, part or all of the conductive layer 20 functions as a word line.

[0067] The insulating layer 11 is provided on a substrate (not shown). The insulating layer 11 functions as an underlay insulating film, an etching stop film, and the like.

[0068] The conductive layer 12 (conductive layer 12_1, conductive layer 12_2 on conductive layer 12_1, and conductive layer 12_3 on conductive layer 12_2) is provided on the insulating layer 11. The conductive layer 12 may be in an island shape, or it may extend in the X direction, the Y direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions). In the example shown, the conductive layer 12 consists of three layers: conductive layer 12_1, conductive layer 12_2 provided on conductive layer 12_1, and conductive layer 12_3 provided on conductive layer 12_2. However, it can also be formed as a single layer, two layers, or a laminate of four or more layers.

[0069] The insulating layer 13 is provided on the conductive layer 12, covering the conductive layer 12. The insulating layer 14 is provided on the insulating layer 13, and it is desirable that its upper surface is flat. Alternatively, the insulating layer 14 may be provided without the insulating layer 13.

[0070] The insulating layer 15 is provided on the insulating layer 14. The insulating layer 16 is provided on the insulating layer 15.

[0071] The conductive layer 17 (conductive layer 17_1, conductive layer 17_2 on conductive layer 17_1) is provided on the insulating layer 16. The conductive layer 17 may extend in the X direction, the Y direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions). In the example shown, the conductive layer 17 consists of two layers: conductive layer 17_1 and conductive layer 17_2 provided on conductive layer 17_1, but it can also be formed as a single layer or as a laminate of three or more layers.

[0072] The opening 90 is provided in the insulating layer 13, insulating layer 14, insulating layer 15, and insulating layer 16, and reaches the conductive layer 12. The opening 90 also reaches the insulating layer 11.

[0073] As shown in Figure 2B, the thickness of the region of the conductive layer 12 that overlaps with the opening 90 is thinner than the thickness of the region of the conductive layer 12 that does not overlap with the opening 90. In other words, the conductive layer 12 has a stepped portion on its upper surface.

[0074] The upper end of the side surface of the insulating layer 16 in the opening 90 has a region that overlaps with the lower end of the conductive layer 17 in a plan view.

[0075] Although the illustration shows the opening 90 as rectangular in plan view, it may also be circular, elliptical, or polygonal. Furthermore, the shape and size in plan view may differ for each of the insulating layers 13, 14, 15, and 16. For example, the diameter of the opening 90 in insulating layer 13 may be smaller than the diameter of the opening 90 in insulating layer 16. Also, at least a portion of the side surface of the insulating layer in the opening 90 may be tapered.

[0076] The semiconductor layer 18 is provided on the conductive layer 17 and has a region in contact with the conductive layer 17 and a region in contact with the conductive layer 12. Figure 3B shows an extract of the conductive layer 12, conductive layer 17, and semiconductor layer 18 of the transistor 10A. More specifically, the semiconductor layer 18 has a region outside the opening 90 that is in contact with the upper surface of the conductive layer 17, and a region at the opening 90 that is in contact with the upper surface of the conductive layer 12.

[0077] The semiconductor layer 18 has regions in contact with the side surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 15, regions in contact with the side surface of the insulating layer 14, and regions in contact with the side surface of the insulating layer 13 at the opening 90.

[0078] The semiconductor layer 18 is provided on only one of a pair of opposing portions of the side surface of the insulating layer 16 at the opening 90. The semiconductor layer 18 is not provided on the other of the pair of opposing portions of the side surface of the insulating layer 16 at the opening 90.

[0079] Furthermore, as shown in Figure 2A, in a plan view of the transistor 10A, the edge of the semiconductor layer 18 that overlaps with the opening 90 is located inside the contour of the conductive layer 12. Also, the area of ​​the region of the semiconductor layer 18 that is in contact with the conductive layer 12 is smaller than the area of ​​the upper surface of the conductive layer 12 that overlaps with the opening 90.

[0080] Furthermore, the semiconductor layer 18 is in contact with the upper surface of the conductive layer 17 and the side surface of the conductive layer 17 on the side of the opening 90.

[0081] Although Figures 2B to 3B show an example where the semiconductor layer 18 is a single layer, it may also be formed by stacking two or more layers.

[0082] The insulating layer 19 is provided on the semiconductor layer 18 so as to cover the semiconductor layer 18. At the opening 90, the insulating layer 19 has a region in contact with the upper surface of the semiconductor layer 18 (the surface parallel to the surface to be formed), a region in contact with the side surface of the semiconductor layer 18, and a region in contact with the insulating layer 16. Although the example shown is a single layer of insulating layer 19, it can also be made up of two or more layers stacked together.

[0083] At the opening 90, the insulating layer 19 is in contact with the portion of the insulating layer 16's side surface that is in contact with the semiconductor layer 18. At the opening, one of a pair of opposing portions of the insulating layer 16's side surface is in contact with the semiconductor layer 18, and the other is in contact with the insulating layer 19.

[0084] Similarly, at the opening 90, the insulating layer 19 is in contact with the portion of the insulating layer (insulating layer 13, insulating layer 14, and insulating layer 15) opposite to the portion of the insulating layer (insulating layer 13, insulating layer 14, and insulating layer 15) that is in contact with the semiconductor layer 18. At the opening, one of a pair of opposing portions of the insulating layer (insulating layer 13, insulating layer 14, and insulating layer 15) is in contact with the semiconductor layer 18, and the other is in contact with the insulating layer 19.

[0085] The insulating layer 19 has a region in contact with the side surface of the conductive layer 12 at the opening 90. Furthermore, the insulating layer 19 has a region in contact with the insulating layer 11 at the opening 90.

[0086] The conductive layer 20 (conductive layer 20_1, conductive layer 20_2 on conductive layer 20_1) is provided on the insulating layer 19. The conductive layer 20 has a region between it and the semiconductor layer 18, with the insulating layer 19 in between. The conductive layer 20 may extend in the X direction, the Y direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions). In the example shown, the conductive layer 20 consists of two layers: conductive layer 20_1 and conductive layer 20_2 provided on conductive layer 20_1, but it can also be formed as a single layer or as a stack of three or more layers.

[0087] The conductive layer 20 has a region in the opening 90 in which the insulating layer 19 is sandwiched between it and the side surface of the conductive layer 12.

[0088] The insulating layer 21 is provided on the conductive layer 20 and is provided so as to cover the conductive layer 20.

[0089] The insulating layer 22 is provided on the insulating layer 21. Preferably, the upper surface of the insulating layer 22 is flat.

[0090] As shown in Figures 2A to 3B, the transistor 10A has a configuration in which current flows in the vertical direction, with one of the source electrode and drain electrode (here, the conductive layer 12) located downwards and the other source electrode and drain electrode (here, the conductive layer 17) located upwards. A channel is formed along the side surface of the insulating layer 15 in the opening 90. Therefore, the occupied area of ​​the transistor 10A can be reduced. Consequently, the semiconductor device can be highly integrated. Furthermore, when a semiconductor device according to one aspect of the present invention is used as a memory device, the storage capacity per unit area can be increased.

[0091] As shown in Figures 2A to 3B, the transistor 10A is arranged such that the conductive layer 17 is located on only one side of the opening 90. Alternatively, if the opening 90 is rectangular in plan view, the conductive layer 17 is arranged so that it lies along one side of a pair of opposite sides of the opening 90. Alternatively, in the plan view shown in Figure 2A, the side edge of the conductive layer 17 has a recess, and a part of the opening 90 is in contact with this recess. Furthermore, in the opening 90, the side surface of the insulating layer 16 on which the semiconductor layer 18 is formed, the side surface of the insulating layer 15, and the side surface of the insulating layer 14 are positioned to overlap with the conductive layer 12. With this arrangement, the channel length of the transistor 10 can be determined, for example, by the total film thickness of the insulating layers 13, 14, 15, and 16, and the channel length does not affect the area occupied by the transistor 10, for example, the area of ​​the transistor 10 in plan view. In addition, the channel length of the transistor 10 can be controlled regardless of the performance of the exposure machine. Therefore, it is possible to achieve extremely fine channel lengths that are below the exposure limit of photolithography.

[0092] Furthermore, by reducing the total thickness of insulating layers 13, 14, 15, and 16, transistors with extremely short channel lengths can also be fabricated. Transistors with channel lengths of, for example, 5 nm to 500 nm, preferably 7 nm to 300 nm, preferably 10 nm to 200 nm, preferably 10 nm to 200 nm, preferably 10 nm to 100 nm, preferably 10 nm to 50 nm, and preferably 10 nm to 30 nm can be fabricated. Therefore, transistors with channel lengths of less than 10 nm can be realized without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0093] As shown in Figures 2B, 3A, and 3B, the presence of a stepped portion in the conductive layer 12 increases the contact area between the conductive layer 12 and the semiconductor layer 18 compared to the case without the stepped portion, thereby reducing the contact resistance between the conductive layer 12 and the semiconductor layer 18. Furthermore, it is preferable that the height of the step is equal to or greater than the total film thickness of the semiconductor layer 18 and the insulating layer 19. It is preferable that the height of the bottom surface of the conductive layer 20 located on the conductive layer 12 within the opening is the same as or lower than the height of the upper surface of the higher step of the conductive layer 12. With this configuration, compared to the case without the stepped portion, the controllability of carriers (electrons) in the semiconductor layer 18 near one of the source electrode and drain electrode (in this case, the conductive layer 12) can be improved by the gate electric field from the gate electrode (conductive layer 20).

[0094] Furthermore, the stepped portion of the conductive layer 12 may have a curved portion, as shown in Figures 2B, 3A, and 3B. Because the stepped portion has a curved portion, the regions of the semiconductor layer 18, insulating layer 19, and conductive layer 20 provided on the stepped portion near the stepped portion may also have a curved portion. In other words, these regions may have a curved surface in cross-sectional view. Also, these regions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 19 near the stepped portion, improves the dielectric breakdown voltage of the transistor 10A, and suppresses electrostatic discharge breakdown of the transistor 10A. Therefore, the reliability of the semiconductor device can be improved.

[0095] Figures 4A to 4C illustrate an example of arrangement when multiple transistors 10A, as described in Figures 2A to 3B, are arranged. Figure 4A is a diagram showing an example of semiconductor device arrangement in a plan view. Figure 4B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 4C is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0096] As shown in Figures 4A to 4C, in a plan view, the transistor 10A is not configured such that the opening 90 is located inside the conductive layer 17, but rather the conductive layer 17 is positioned on only one side of the opening 90. Alternatively, in a plan view, if the opening 90 is rectangular, the conductive layer 17 is positioned so that it lies along one side of a pair of opposing sides of the opening 90. Alternatively, in the plan view shown in Figure 4A, the side edge of the conductive layer 17 has a recess, and a portion of the opening 90 is positioned to be in contact with this recess.

[0097] By using this arrangement, the reduction in the wiring width of the conductive layer 17 near the opening 90 (W1) is kept small compared to the width of the conductive layer 17 (W2), and the thickness of the conductive layer 17 near the opening 90 (W1) can be maintained. Therefore, the increase in the wiring resistance of the conductive layer 17 due to the reduction in the width of the conductive layer 17 near the opening 90 (W1) is suppressed, and in Figure 4A, the wiring resistance of the conductive layer 17 extending in the Y direction can be kept low. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a semiconductor device capable of carrying a large current can be provided.

[0098] Furthermore, this arrangement allows for a shorter distance between adjacent transistors 10A. As shown in Figures 4A to 4C, the pitch (W3) between the nth row conductive layer 17 and the (n+1)th row conductive layer 17 can be shortened. This also allows for a higher density arrangement of transistors.

[0099] As shown in Figure 4A, the area of ​​the region where the conductive layer 12 and the conductive layer 20 overlap is smaller than the area of ​​the opening 90. Therefore, parasitic capacitance generated between the conductive layer 12 and the conductive layer 20 can be reduced. In addition, the distance from the upper end of the side surface of the insulating layer 16 in the opening 90 to the lower end of the conductive layer 17 of the adjacent transistor can be increased, thus reducing concerns about short circuits between adjacent transistors.

[0100] [Materials for the semiconductor device] The following describes the materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may be a single-layer structure or a multilayer structure.

[0101] [Substrate] For the substrate used to form the transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on the substrate include capacitive elements, resistive elements, switching elements (including transistors), light-emitting elements, and memory elements.

[0102] [Semiconductor layer] The semiconductor layer 18 preferably has a metal oxide (oxide semiconductor) that exhibits semiconductor properties.

[0103] The crystallinity of the semiconductor material used in the semiconductor layer 18 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) may be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0104] OS transistors have oxygen vacancies (V) in the channel formation region of the metal oxide. Ｏ ) and impurities can cause electrical properties to fluctuate easily, potentially leading to poor reliability. In addition, defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) Ｏ This can form an oxygen vacancy (sometimes called H) and generate electrons that act as carriers. Therefore, if the channel-forming region in the metal oxide contains oxygen vacancies, the OS transistor is likely to become a normally-ion transistor. Consequently, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel-forming region of the metal oxide. In other words, it is preferable that the carrier concentration in the channel-forming region of the metal oxide is reduced and that it is i-type (intrinsic) or substantially i-type.

[0105] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that the region has a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or metallic elements, which increases the carrier concentration and lowers the resistance. In other words, it is preferable that the source region and drain region of an OS transistor are n-type regions with a higher carrier concentration and lower resistance compared to the channel formation region.

[0106] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or higher, and more preferably 2.5 eV or higher. By using a metal oxide with a large band gap in the oxide semiconductor layer, the off-current of the transistor can be reduced. Because OS transistors have a small off-current, the power consumption of semiconductor devices can be significantly reduced. Furthermore, because OS transistors have high frequency characteristics, semiconductor devices can be operated at high speeds.

[0107] It is preferable to use indium oxide as the metal oxide that can be used in the semiconductor layer 18. Regarding the indium oxide used in the semiconductor layer 18, refer to the description in Embodiment 2.

[0108] Furthermore, the metal oxide that can be used in the semiconductor layer 18 preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from In, element M, and Zn. Element M is a metal or metalloid element with a high bond energy to oxygen; for example, a metal or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M in the metal oxide preferably consists of one or more of the above elements, and is particularly preferably one or more selected from aluminum, gallium, tin, and yttrium, with gallium being more preferred. In this specification, metal oxides containing In, M, and Zn may be referred to as In-M-Zn oxides. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the term "metal elements" used in this specification may include metalloid elements.

[0109] The metal oxides in question include zinc oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), and indium aluminum zinc oxide. Lead oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc. can be used. Alternatively, indium tungsten oxide (In-W oxide, also written as IWO), etc. can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0110] By increasing the indium content in the metal oxide, transistors can achieve high on-current and high frequency characteristics.

[0111] The composition of the In-Zn oxide can be, specifically, In:Zn = 1:1 [atomic ratio] or a composition close to that, In:Zn = 2:1 [atomic ratio] or a composition close to that, or In:Zn = 4:1 [atomic ratio] or a composition close to that. Note that a composition close to the desired atomic ratio includes a range of ±30%.

[0112] Furthermore, the In-Zn oxide may contain trace amounts of element M. For example, compositions such as In:M:Zn = 2:0.1:1 [atomic ratio], In:M:Zn = 4:0.1:1 [atomic ratio], and compositions close to these can be used. Here, for example, gallium, tin, etc. can be suitably used as element M.

[0113] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M. For example, possible atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or compositions near these. Note that compositions near these include a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0114] Furthermore, the atomic ratio of In in an In-M-Zn oxide may be less than the atomic ratio of M. For example, possible atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions close to these. Increasing the atomic ratio of M in a metal oxide can suppress the formation of oxygen vacancies.

[0115] Examples of high-mobility materials include indium oxide, In:Zn=1:1, In:Zn=2:1, In:Zn=4:1, In:Ga:Zn=4:2:3, In:Sn:Zn=4:0.1:1, or materials with compositions close to these. On the other hand, materials with lower mobility or conductivity compared to the above-mentioned materials include In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, or materials with compositions close to these.

[0116] The semiconductor layer 18 may be a single layer or a stacked structure of two or more layers. For example, when the semiconductor layer 18 has a three-layer structure, it is preferable to use a material with higher mobility in the second layer than in the first and third layers. As a result, the second layer mainly becomes the current path, which suppresses interfacial scattering between the gate insulating layer and the semiconductor layer 18, enabling the realization of a highly reliable transistor.

[0117] The semiconductor layer 18 preferably uses a crystalline metal oxide layer. For example, a metal oxide layer having a single crystal structure, a CAAC (c-axis aligned crystalline) structure, a polycrystalline structure, a microcrystalline structure, a nanocrystalline (nc: nano-crystalline) structure, etc., can be used. By using a crystalline metal oxide layer for the semiconductor layer 18, the defect level density in the semiconductor layer 18 can be reduced, and a highly reliable semiconductor device can be realized.

[0118] Here, we will explain the effects of various impurities in metal oxides (oxide semiconductors).

[0119] As mentioned above, in a transistor using an oxide semiconductor for the semiconductor layer, oxygen vacancies (V) are present in the channel formation region of the oxide semiconductor. Ｏ The presence of impurities can easily cause fluctuations in electrical properties and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of OS transistors. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to elements other than the main components that make up the oxide semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0120] In oxide semiconductors, the presence of silicon or carbon, which are both Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of carbon in the channel-forming region of an oxide semiconductor obtained by secondary ion mass spectrometry (SIMS) is 1 × 10⁻⁶. ２０atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ More preferably, 3 x 10 １９ atoms / cm ３ More specifically, 1 x 10 １９ atoms / cm ３ More preferably, 3 x 10 １８ atoms / cm ３ More preferably, 1 x 10 １８ atoms / cm ３ The following applies. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 × 10⁻⁶. ２０ atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ More preferably, 3 x 10 １９ atoms / cm ３ More specifically, 1 x 10 １９ atoms / cm ３ More preferably, 3 x 10 １８ atoms / cm ３ More preferably, 1 x 10 １８ atoms / cm ３ The following applies:

[0121] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen in their semiconductor layers tend to be normally-ion. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. This can result in unstable electrical properties of the transistor. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be 1 × 10⁻⁶. ２０ atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ More specifically, 1 x 10 １９ atoms / cm ３ More preferably 5 x 10 １８ atoms / cm３ More specifically, 1 x 10 １８ atoms / cm ３ More preferably 5 × 10 １７ atoms / cm ３ The following applies:

[0122] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to produce normally-ion transistors. For this reason, it is preferable to minimize the hydrogen content in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS should be 1 × 10⁻⁶. ２０ atoms / cm ３ Less than 5 × 10 １９ atoms / cm ３ Less than, more preferably 1 × 10 １９ atoms / cm ３ Less than, more preferably 5 × 10 １８ atoms / cm ３ Less than 1 × 10 １８ atoms / cm ３ Less than 1 × 10 １７ atoms / cm ３ Less than.

[0123] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to be normal-ion. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. １８ atoms / cm ３ The following is preferably 2 × 10 １６ atoms / cm ３ Do the following:

[0124] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0125] Examples of semiconductor materials that can be used for the semiconductor layer 18 include semiconductors composed of elemental materials or compound semiconductors. Examples of semiconductors composed of elemental materials include silicon (including single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) or germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0126] Alternatively, the semiconductor layer 18 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0127] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a semiconductor layer in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0128] [Conductive Layers] It is preferable to use highly conductive materials for conductive layers such as conductive layer 12, conductive layer 17, and conductive layer 20. As conductive materials for conductive layers such as conductive layer 12, conductive layer 17, and conductive layer 20, it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or alloys containing such metal elements. Alternatively, nitrides of the above metal elements or alloys containing the above metal elements, or oxides of the above metal elements or alloys containing the above metal elements may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain conductivity even after oxidation. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used. Furthermore, tantalum and tantalum nitride are preferred as conductive layers because they have barrier properties against hydrogen.

[0129] Conductive layers such as conductive layer 12, conductive layer 17, and conductive layer 20 may have regions that are in contact with the semiconductor layer 18. When an oxide semiconductor is used as the semiconductor layer 18, if an easily oxidizable metal such as aluminum is used in the region of the conductive layer that is in contact with the semiconductor layer 18, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer and the semiconductor layer 18, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide in at least the region of the conductive layer that is in contact with the semiconductor layer 18. For example, in the case of the transistor 10A shown in Figure 2B, it is preferable to use a conductive oxide for both conductive layer 12_3 and conductive layer 17_2. Examples of conductive oxides that can be used include indium oxide, indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (In-Sn-Si oxide, also called ITSO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, and In-Ti-Sn oxide. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide semiconductors applicable to the semiconductor layer 18 can also be used as conductive layers by increasing the carrier concentration.

[0130] Furthermore, the conductive layer may be a single-layer structure or a multi-layer structure of the conductive material described above. For example, a laminated structure combining the aforementioned metal element material with a conductive oxide may be used. For example, a single-layer structure of the conductive oxide film, a two-layer structure in which a ruthenium film or ruthenium oxide film is laminated on a tungsten film, a two-layer structure in which the conductive oxide film is laminated on a ruthenium film or ruthenium oxide film, a two-layer structure in which a conductive oxide film is laminated on a tungsten film, and so on can be used. Alternatively, a three-layer structure in which tungsten is laminated on titanium nitride and a conductive oxide is laminated on the tungsten can be used. Or, a four-layer structure can be used in which tantalum nitride is laminated from the bottom, titanium nitride is laminated on the tantalum nitride, tungsten is laminated on the titanium nitride, and a conductive oxide is laminated on the tungsten in that order.

[0131] [Insulating Layers] It is preferable to use inorganic insulating films for the insulating layers (insulating layer 11, insulating layer 13, insulating layer 14, insulating layer 15, insulating layer 16, insulating layer 19, insulating layer 21, insulating layer 22, etc.) of a semiconductor device. As transistors become smaller and more integrated, thinning of the gate insulating layer can cause problems such as leakage current. By using a material with a high dielectric constant (high-k) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. It is also possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, parasitic capacitance between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer.

[0132] Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, zinc gallium oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxide nitride films, aluminum oxide nitride films, gallium oxide nitride films, yttrium oxide nitride films, and hafnium oxide nitride films. Examples of nitride oxide insulating films include silicon oxide nitride films and aluminum oxide nitride films. In addition, organic insulating films may be used for the insulating layer of semiconductor devices.

[0133] Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium. In addition, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.

[0134] Examples of insulating materials with a lower dielectric constant compared to high-k materials include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0135] Furthermore, examples of insulating materials that have high dielectric strength or insulating materials that suppress leakage current include at least one or both, silicon oxide, silicon oxide nitride, silicon nitride, and silicon nitride.

[0136] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities, hydrogen, and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a multilayer structure.

[0137] Specifically, as materials for the insulating layer that have the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and nitride oxides such as silicon nitride can be used.

[0138] Specifically, examples of insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also, examples of nitrides include aluminum nitride and silicon nitride. Furthermore, examples of nitride oxides include silicon nitride.

[0139] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that have regions containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). For example, by having an insulating layer having regions containing excess oxygen in contact with the oxide semiconductor layer or located near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layer materials that easily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with vacancies.

[0140] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer.

[0141] Examples of insulating layer materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium-containing oxides, magnesium-containing oxides, aluminum-containing oxides, aluminum and hafnium-containing oxides (hafnium aluminate), and hafnium and silicon-containing oxides (hafnium silicate). Furthermore, these metal oxides may also contain zirconium, for example, an oxide containing hafnium and zirconium.

[0142] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0143] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0144] Furthermore, the above insulating layer may have, in part, a crystalline region and / or a grain boundary.

[0145] Furthermore, the function of capturing or fixing the corresponding substance can also be described as having the property of making the corresponding substance difficult to diffuse. Therefore, the function of capturing or fixing the corresponding substance can be rephrased as barrier property. In this specification, a barrier insulating layer refers to an insulating layer that has barrier properties. Barrier property is defined as the property of making the corresponding substance difficult to diffuse (also called the property of making the corresponding substance difficult to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as the corresponding substance, for example, it refers to hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, and NO ２ This refers to at least one of the following: (etc.), and copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: for example, an oxygen atom and an oxygen molecule, etc.

[0146] Examples of insulating layer materials that have hydrogen barrier properties include silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide, gallium oxide, or silicon nitride oxide.

[0147] Examples of insulating layer materials that have barrier properties against oxygen include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0148] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Another example of a ferroelectric material is a material obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to it. Another example of a ferroelectric material is a material obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium, etc.) to zirconium oxide. Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. In addition, as a material that can have ferroelectric properties, lead titanate (PbTiO) Ｘ ), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0149] Furthermore, metal nitrides containing element Q1, element Q2, and nitrogen are examples of materials that may possess ferroelectric properties. Here, element Q1 is one or more selected from aluminum, gallium, and indium, etc. Element Q2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium, etc. The ratio of the number of atoms of element Q1 to the number of atoms of element Q2 can be set as appropriate. In addition, metal oxides containing element Q1 and nitrogen may possess ferroelectric properties even without containing element Q2. Furthermore, materials in which element Q3 is added to the above metal nitride are examples of materials that may possess ferroelectric properties. Element Q3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium, etc. Here, the ratio of the number of atoms of element Q1, the number of atoms of element Q2, and the number of atoms of element Q3 can be set as appropriate.

[0150] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ These are some examples.

[0151] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, may be used.

[0152] Furthermore, as materials that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0153] The insulating layer of a capacitive element having a pair of opposing conductive layers and an insulating layer located between them can be a single-layer structure made of a material selected from the materials listed above, or a laminated structure made of multiple materials selected from the materials listed above.

[0154] Furthermore, at least a portion of the gate insulating layer of the transistor may be a single-layer structure made of a material selected from the materials listed above, or a multilayer structure made of multiple materials selected from the materials listed above. A transistor having such gate insulating can be made to function as an FeFET (Ferroelectric Field Effect Transistor).

[0155] The insulating materials used in insulating layers such as insulating layer 11, insulating layer 13, insulating layer 14, insulating layer 16, and insulating layer 21 are preferably insulating layer materials that have the function of suppressing the permeation of impurities and oxygen, insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, insulating layer materials that have barrier properties against hydrogen, and insulating layer materials that have barrier properties against oxygen. By using these insulating layers, the diffusion of hydrogen into the semiconductor layer 18 can be suppressed. In addition, oxidation of conductive layers such as conductive layer 12, conductive layer 17, and conductive layer 20 can be suppressed.

[0156] For example, the transistor 10A may be surrounded by insulating layers such as insulating layer 11, insulating layer 13, insulating layer 14, insulating layer 16, and insulating layer 21, using either or both silicon nitride and silicon nitride oxide. This suppresses the diffusion of hydrogen into the transistor 10A, resulting in a highly reliable transistor.

[0157] The insulating materials used for insulating layers such as insulating layer 15 and insulating layer 22 preferably have a low relative permittivity because they function as interlayer insulating layers. Also, it is preferable that they are insulating materials with high dielectric breakdown strength or that suppress leakage current. By using an insulating material with a lower relative permittivity than high-k materials as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. By using an insulating material with high dielectric breakdown strength or that suppresses leakage current as the interlayer insulating film, the leakage current generated between wirings can be reduced. As insulating layer 15 and insulating layer 22, for example, silicon oxide or silicon oxynitride can be used.

[0158] Also, for insulating layer 15 and insulating layer 22 etc., it is preferable that the impurity concentration of hydrogen or water etc. is reduced. For example, also, by using a sputtering method in which a molecule containing hydrogen is not used in the film-forming gas, the hydrogen concentration in the insulating layer can be reduced. Thereby, the mixing of impurities such as hydrogen or water into the channel formation region of semiconductor layer 18 can be suppressed. Also, it is preferable to use an insulating layer for insulating layer 15 that has a region containing excess oxygen. For example, an insulating layer having a region containing excess oxygen can be formed by film-forming in an oxygen-containing atmosphere by a sputtering method. Thus, by forming at least a part of insulating layer 15 and insulating layer 22 using a sputtering method, oxygen is supplied from insulating layer 15 and insulating layer 22 to the channel formation region of semiconductor layer 18, and oxygen deficiency and V Ｏ H reduction can be achieved.

[0159] In addition, in this specification etc., oxynitride refers to a material whose oxygen atom content is more than its nitrogen atom content in terms of its composition, and oxynitride refers to a material whose nitrogen atom content is more than its oxygen atom content in terms of its composition. For example, when silicon oxynitride is described, it refers to a material whose oxygen atom content is more than its nitrogen atom content in terms of its composition, and when silicon oxynitride is described, it indicates a material whose nitrogen atom content is more than its oxygen atom content in terms of its composition.

[0160] [Gate Insulation Layer] The insulating layer 19 functions as the gate insulation layer of the transistor. The insulating layer 19 can be an oxide insulating film, a nitride insulating film, an oxidoxide-nitride insulating film, or an oxide-nitride insulating film. The insulating layer 19 may also have a laminated structure, for example, a laminated structure having one or more oxide insulating films and one or more nitride insulating films.

[0161] Furthermore, the insulating layer 19 can be made by laminating insulating materials made of high-k material. Alternatively, the insulating layer 19 can be made by laminating insulating materials with high dielectric strength or that suppress leakage current. Additionally, a material capable of ferroelectricity can be used as the insulating layer 19. Furthermore, the insulating layer 19 can be made by laminating these materials.

[0162] The insulating layer 19 preferably uses an insulating layer material that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, an insulating layer material that has the function of capturing or fixing hydrogen, or an insulating layer material that has barrier properties against hydrogen. This can suppress the diffusion of hydrogen contained in the conductive layer 20, etc., into the semiconductor layer 18. For example, the insulating layer 19 can be made of, for example, a silicon nitride film.

[0163] Furthermore, since the insulating layer 19 is in contact with the semiconductor layer 18, it is preferable to use an insulating layer that has the function of capturing or fixing hydrogen. This allows for more effective capture or fixing of hydrogen contained in the semiconductor layer 18. Therefore, the hydrogen concentration in the semiconductor layer 18 (especially the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V in the channel formation region Ｏ By reducing H, the channel formation region can be made i-type or substantially i-type.

[0164] Furthermore, it is preferable to use an insulating layer 19 that has a region containing excess oxygen. This allows oxygen to be supplied from the insulating layer 19 to the semiconductor layer 18, thereby reducing oxygen deficiencies in the semiconductor layer 18. Silicon oxide films or silicon oxynitride films are suitable as insulating layers 19 because they have a thermally stable structure.

[0165] Furthermore, it is preferable to use an insulating layer material that has barrier properties against oxygen for the insulating layer 19. By having an insulating layer 19 that is in contact with the semiconductor layer 18 have barrier properties against oxygen, the detachment of oxygen from the semiconductor layer 18 can be suppressed. An aluminum oxide film can be used as the insulating layer 19.

[0166] The insulating layer 19 can be a single layer or a laminated structure of two or more layers. When the insulating layer 19 is a laminated structure of two or more layers, it is preferable to form it with two or more types of films. By using two or more types of films for the insulating layer 19, multiple functions can be imparted to the insulating layer 19. Examples of functions that the insulating layer 19 may have include the function of extracting hydrogen from the semiconductor layer 18 and the function of suppressing the diffusion of hydrogen into the semiconductor layer 18. In addition, an insulating layer having a region containing excess oxygen in a part of the insulating layer 19 can be used. Oxygen can be supplied from the insulating layer 19 to the semiconductor layer 18, reducing oxygen deficiency in the semiconductor layer 18.

[0167] For example, the insulating layer 19 can have a two-layer structure having a first insulating layer and a second insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 18. For example, the first insulating layer can be made of an insulating layer material having the function of capturing or fixing hydrogen, and the second insulating layer can be made of an insulating layer material having hydrogen barrier properties, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material having oxygen barrier properties. With such a configuration, the hydrogen concentration in the semiconductor layer 18 can be reduced, and the diffusion of hydrogen into the semiconductor layer 18 can be suppressed. This makes it possible to realize a highly reliable transistor. When the insulating layer 19 has a two-layer structure having a first insulating layer and a second insulating layer, for example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0168] Alternatively, for example, an insulating layer having a region containing excess oxygen can be used as the first insulating layer, and an insulating layer material having barrier properties against hydrogen or an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, can be used as the second insulating layer. Alternatively, for example, an insulating layer having a region containing excess oxygen can be used as the first insulating layer, and an insulating layer material having the function of capturing or fixing hydrogen can be used as the second insulating layer. By adopting such a configuration, the amount of oxygen vacancy and hydrogen concentration in the semiconductor layer 18 can be reduced, and the diffusion of hydrogen into the semiconductor layer 18 can be suppressed. Therefore, a highly reliable transistor can be realized. When the insulating layer 19 has a two-layer structure having a first insulating layer and a second insulating layer, for example, a silicon oxide film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0169] For example, the insulating layer 19 can have a three-layer structure comprising a first insulating layer, a second insulating layer, and a third insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 18, and the first insulating layer, the second insulating layer, and the third insulating layer are positioned from the semiconductor layer 18 side. For example, the first insulating layer can be made of an insulating material with high dielectric strength, an insulating material that suppresses leakage current, or an insulating layer having a region containing excess oxygen; the second insulating layer can be made of an insulating layer material that has the function of capturing or fixing hydrogen; and the third insulating layer can be made of an insulating layer material that has barrier properties against hydrogen, an insulating layer material that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material that has barrier properties against oxygen. With such a configuration, the amount of oxygen deficiency and hydrogen concentration in the semiconductor layer 18 can be reduced, and the diffusion of hydrogen into the semiconductor layer 18 can be suppressed. In addition, the diffusion of oxygen to the conductive layer 20 side can be prevented, and the oxidation of the conductive layer 20 can be suppressed. Therefore, a highly reliable transistor can be realized. When the insulating layer 19 has a three-layer structure consisting of a first insulating layer, a second insulating layer, and a third insulating layer, for example, a silicon oxide film can be used as the first insulating layer, a hafnium oxide film or a hafnium silicate film as the second insulating layer, and a silicon nitride film as the third insulating layer.

[0170] For example, the insulating layer 19 can have a four-layer structure comprising a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 18, and the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer are located from the semiconductor layer 18 side. For example, the first insulating layer can be made of an insulating layer material having barrier properties against oxygen or an insulating layer material having the function of suppressing the permeation of impurities and oxygen; the second insulating layer can be made of an insulating layer material with high dielectric strength or an insulating layer material that suppresses leakage current or an insulating layer having a region containing excess oxygen; the third insulating layer can be made of an insulating layer material having the function of capturing or fixing hydrogen; and the fourth insulating layer can be made of an insulating layer material having barrier properties against hydrogen, an insulating layer material having the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, or an insulating layer material having barrier properties against oxygen. With such a configuration, the detachment of oxygen from the semiconductor layer 18 can be suppressed. The amount of oxygen vacancies and hydrogen concentration in the semiconductor layer 18 can be reduced, and the diffusion of hydrogen into the semiconductor layer 18 can be suppressed. Furthermore, the diffusion of oxygen to the conductive layer 20 can be prevented, and the oxidation of the conductive layer 20 can be suppressed. Therefore, a highly reliable transistor can be realized. When the insulating layer 19 has a four-layer structure consisting of a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, for example, an aluminum oxide film can be used as the first insulating layer, a silicon oxide film as the second insulating layer, a hafnium oxide film or a hafnium silicate film as the third insulating layer, and a silicon nitride film as the fourth insulating layer.

[0171] The insulating layer 19 is preferably a thin film. For example, by setting the thickness of the insulating layer 19 to 1 nm to 50 nm, 1 nm to 20 nm, and preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0172] Furthermore, the film thickness of each layer constituting the insulating layer 19 is preferably 0.1 nm to 40 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 19 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0173] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 18 side, with thicknesses of 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 18 side. Furthermore, if a high gate breakdown voltage is required, it is preferable to increase the thickness of the silicon oxide, which is an insulating material with high dielectric strength or an insulating material that suppresses leakage current. For example, it is preferable to set the thicknesses of each layer to 1 nm, 30 nm, 1.5 nm, and 1 nm from the semiconductor layer 18 side. Furthermore, if it is required to further enhance the barrier properties against hydrogen or oxygen, it is preferable to increase the thickness of the silicon nitride, for example, with thicknesses of each layer to 1 nm, 30 nm, 1.5 nm, and 5 nm from the semiconductor layer 18 side.

[0174] Another specific example is to use a four-layer structure in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 18 side, and it is preferable that the thicknesses of these layers be 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 18 side.

[0175] Another specific example is a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in that order from the semiconductor layer 18 side, and it is preferable that the thicknesses of these layers be 1 nm and 1.5 nm from the semiconductor layer 18 side.

[0176] Furthermore, as a specific example, it is preferable to use a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 18 side, with the thicknesses of these layers being 30 nm, 1.5 nm, and 5 nm from the semiconductor layer 18 side.

[0177] [Example of Semiconductor Device Manufacturing Method] An example of a semiconductor device manufacturing method according to one embodiment of the present invention, illustrated in Figures 4A to 4C, will be explained using Figures 5A to 7D. In the drawings showing an example of a semiconductor device manufacturing method, A and C in each figure are cross-sectional views between the dashed-dotted line A1 and A2 shown in Figure 4A. Also, B and D in each figure are cross-sectional views between the dashed-dotted line B1 and B2 shown in Figure 4A.

[0178] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. ALD methods include thermal ALD, which uses only thermal energy to carry out the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, and photo-CVD. Other methods include metal-organic CVD (MOCVD) and metal CVD.

[0179] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film deposition methods such as spin coating, dip coating, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0180] Furthermore, lithography or the like can be used when processing the thin films that constitute the semiconductor device. Alternatively, the thin films may be processed by nanoimprint lithography, sandblasting, lift-off lithography, or the like. In addition, island-shaped thin films may be directly formed by a film deposition method using a shielding mask such as a metal mask.

[0181] There are two main lithography methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0182] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of the light source for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0183] Thin film etching can be performed using methods such as dry etching, wet etching, ashing, plasma treatment, and reverse sputtering. Sandblasting may also be used for etching thin films.

[0184] First, an insulating layer 11 is formed on a substrate (not shown) (Figures 5A and 5B). For the insulating layer 11, an inorganic insulating film such as silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be used. For forming the insulating layer 11, a film formation method such as sputtering, ALD, or CVD can be used. If the upper surface of the insulating layer 11 is not flat, a planarization treatment may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat. For the planarization treatment, for example, a CMP method can be used.

[0185] Subsequently, films that will become conductive layers 12 (conductive layer 12_1, conductive layer 12_2, conductive layer 12_3) are formed on the insulating layer 11. The films that will become conductive layers 12 include a film that will become conductive layer 12_1, a film that will become conductive layer 12_2 provided on the film that will become conductive layer 12_1, and a film that will become conductive layer 12_3 provided on the film that will become conductive layer 12_2. The conductive layers 12 are formed by processing the films that will become conductive layers 12. Sputtering, metal CVD, MOCVD, ALD, etc. can be used to form the conductive layers 12. For example, as conductive layers 12, titanium nitride formed by metal CVD can be used as conductive layer 12_1, tungsten formed by metal CVD can be used as conductive layer 12_2, and a conductive oxide formed by sputtering can be used as conductive layer 12_3. Alternatively, as the conductive layer 12, for example, titanium nitride deposited by sputtering as conductive layer 12_1, tungsten deposited by sputtering as conductive layer 12_2, and a conductive oxide deposited by sputtering as conductive layer 12_3 can be used. ITO, ITSO, etc., can be used as the conductive oxide. Dry etching is preferred for processing the conductive layer 12. For example, a mask (not shown) is formed on the film that will become the conductive layer 12 in the region that will become the conductive layer 12, and the film that will become the conductive layer 12 in the regions where the mask is not formed is removed by etching. Anisotropic dry etching is preferred for this etching process. The mask is removed after the etching process. Figures 5A and 5B show an example where the side surface of the conductive layer 12 is perpendicular to the surface to be formed, but depending on the etching conditions, the side surface of the conductive layer 12 may have a tapered shape that is inclined with respect to the surface to be formed.

[0186] Subsequently, an insulating layer 13 is formed on the conductive layer 12, covering the conductive layer 12 (Figures 5C and 5D). The insulating layer 13 can be formed by a film deposition method such as ALD, sputtering, or CVD. For example, silicon nitride or silicon nitride oxide, which are deposited by the ALD method, can be used for the insulating layer 13.

[0187] Subsequently, an insulating layer 14 is formed on the insulating layer 13. The insulating layer 14 can be formed by a film formation method such as sputtering, ALD, or CVD. For example, silicon nitride or silicon oxide nitride, which are formed by sputtering, can be used for the insulating layer 14. Furthermore, it is preferable to perform a planarization treatment on the insulating layer 14. For example, the CMP method can be used for the planarization treatment. Note that the insulating layer 14 may be provided without the insulating layer 13.

[0188] Subsequently, an insulating layer 15 is formed on the insulating layer 14. The insulating layer 15 can be formed by a film formation method such as sputtering, CVD, or ALD. For example, the insulating layer 15 can be made of silicon oxide, silicon oxynitride, etc., formed by sputtering. It is preferable to use a film formed by sputtering that does not contain hydrogen in the film formation gas for the insulating layer 15. After the insulating layer 15 is formed, a planarization treatment may be performed by CMP or the like. It is also preferable to perform a heat treatment after the insulating layer 15 is formed to reduce the amount of hydrogen in the insulating layer 15.

[0189] The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to use an oxygen gas concentration of about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulating layer 15, etc., can be reduced before the deposition of the oxide semiconductor film that will become the semiconductor layer.

[0190] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is 1 ppb (1 × 10⁻¹⁶). −３ppm) or less, preferably 0.1 ppb (1 × 10⁻¹⁰ −４ ppm) or less, more preferably 0.05 ppb (5 × 10⁻¹⁰ −５ It is preferable to keep the concentration below ppm. By performing heat treatment using highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the insulating layer 15 as much as possible.

[0191] There are no special limitations on the equipment used for heat treatment; it may be an equipment that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) equipment such as an LRTA (Lamp Rapid Thermal Anneal) or GRTA (Gas Rapid Thermal Anneal) equipment can be used. An LRTA equipment is an equipment that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA equipment is an equipment that performs heat treatment using high-temperature gas.

[0192] Preferably, the insulating layer 15 has the function of releasing oxygen. Alternatively, a process can be performed to supply oxygen to the insulating layer 15. Oxygen is supplied to the insulating layer 15, and then, due to heat applied after the formation of the semiconductor layer 18, oxygen can be supplied from the insulating layer 15 to the semiconductor layer 18.

[0193] Examples of oxygen supply processes include heating in an oxygen-containing atmosphere, or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Another example is a method for forming the insulating layer 16 in an oxygen-containing atmosphere.

[0194] Alternatively, as a means for supplying oxygen, an oxide (preferably a metal oxide film) may be formed on the insulating layer 15 by sputtering in an atmosphere containing oxygen to supply oxygen to the insulating layer 15. The formed oxide film is preferably removed thereafter. For example, an oxide film such as aluminum oxide or an oxide semiconductor may be formed by sputtering and removed by the CMP method. When removing the oxide film by the CMP method, if the film thickness of the insulating layer 15 decreases, the insulating layer may be formed again. Note that as the atmosphere containing oxygen, not only oxygen gas (O ２ ), but also an atmosphere containing a gas of a compound containing oxygen such as ozone (O ３ ) or nitrous oxide (N ２ O) is included. Also, the substrate temperature during plasma treatment is set to be 25°C or higher and 450°C or lower. Also, the above-described process of supplying oxygen may be carried out a plurality of times with the same process, or may be carried out a plurality of times by combining different processes.

[0195] Thereafter, an insulating layer 16 is formed on the insulating layer 15. The insulating layer 16 can be formed by a film formation method such as the ALD method, sputtering method, CVD method, or the like. For the insulating layer 16, for example, silicon nitride, silicon oxynitride, or the like formed by the ALD method can be used.

[0196] Thereafter, a film to be the conductive layer 17 (conductive layer 17_1, conductive layer 17_2) is formed on the insulating layer 16. The film to be the conductive layer 17 has a film to be the conductive layer 17_1 and a film to be the conductive layer 17_2 on the film to be the conductive layer 17_1. For the film to be the conductive layer 17, a sputtering method, a metal CVD method, a MOCVD method, an ALD method, or the like can be used. As the conductive layer 17, for example, tungsten formed by sputtering can be used as the conductive layer 17_1, and a conductive oxide formed by sputtering can be used as the conductive layer 17_2. Note that as the conductive oxide, ITO, ITSO, or the like can be used.

[0197] Subsequently, the film that will become the conductive layer 17 is etched. It is preferable to use a dry etching method for etching the film that will become the conductive layer 17. For example, a mask (not shown) is formed on the film that will become the conductive layer 17 in the region that will become the conductive layer 17, and the film that will become the conductive layer 17 in the region where the mask is not formed is removed by etching. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed. Figures 5C and 5D show an example where the side surface of the conductive layer 17 is perpendicular to the surface to be formed, but depending on the etching conditions, the side surface of the conductive layer 17 may have a tapered shape that is inclined with respect to the surface to be formed.

[0198] Subsequently, an opening 90 is formed (Figures 6A and 6B). The opening 90 is formed by forming a mask (not shown) on the insulating layer 16 and the conductive layer 17, and removing the insulating layer 16, insulating layer 15, insulating layer 14, and insulating layer 13 in the areas where the mask is not formed by etching. At this time, a part of the conductive layer 17 is removed by etching. It is also preferable to etch at least a part of the area of ​​the conductive layer 12 that overlaps with the opening 90. The thickness of the area of ​​the conductive layer 12 that overlaps with the opening 90 is made thinner than the thickness of the area of ​​the conductive layer 12 that does not overlap with the opening 90 by removing a part of the conductive layer 12. In other words, the conductive layer 12 has a stepped portion on its upper surface. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed. It is preferable that the opening 90 is processed to be perpendicular or approximately perpendicular to the surface of the conductive layer 17 to be formed. Depending on the processing conditions, the sides of the insulating layers (insulating layer 16, insulating layer 15, insulating layer 14, and insulating layer 13) at the opening 90 may be processed to have a gradient with respect to the direction perpendicular to the surface on which the conductive layer 17 is formed.

[0199] Subsequently, a film to become the semiconductor layer 18 is formed and etched (Figures 6C and 6D).

[0200] A mask (not shown) is formed on the film that will become the semiconductor layer 18 in the region that will become the semiconductor layer 18, and the film that will become the semiconductor layer 18 in the region where the mask is not formed is removed by etching. It is preferable to use anisotropic dry etching for this etching process. After the etching process, the mask is removed.

[0201] The semiconductor layer 18 can be made of a metal oxide (oxide semiconductor) exhibiting semiconductor properties. The metal oxide can be formed by sputtering or atomic layer deposition (ALD) methods. The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, it is preferable to use a crystalline metal oxide film. Although the semiconductor layer 18 is shown as a single layer in the drawing, it may be a stacked structure of two or more layers.

[0202] For example, when the semiconductor layer 18 is a stacked structure, different film deposition methods can be used for each layer. Sputtering and ALD can be combined as methods for forming the metal oxide. Furthermore, metal oxides of different compositions can be used for each layer. For example, a two-layer structure formed by the ALD method, or a three-layer structure formed by the ALD method, can be used. Alternatively, a two-layer structure can be formed by forming the first layer by the ALD method and the second layer by the sputtering method, or a three-layer structure can be formed by forming the first layer by the ALD method, the second layer by the sputtering method, and the third layer by either the ALD method or the sputtering method. A three-layer structure can also be formed by forming the first and second layers by the ALD method and the third layer by the sputtering method. Forming the first layer by the ALD method is preferable because it suppresses mixing, but it can also be formed by the sputtering method. For example, a two-layer structure can be formed by sputtering for the first layer and ALD for the second layer, or a three-layer structure can be formed by sputtering for the first layer, ALD for the second layer, and either ALD or sputtering for the third layer. The semiconductor layer 18 may also be a stacked structure of four or more layers.

[0203] When forming metal oxides by sputtering, for example, a metal oxide target can be used. The composition of the metal oxide after deposition may differ from the composition of the target. In particular, the zinc content in the metal oxide after deposition may decrease to about 50% compared to the target.

[0204] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (for example, helium gas, argon gas, xenon gas, etc.). Note that the higher the proportion of oxygen gas in the total deposition gas used to form the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be, leading to the realization of a highly reliable transistor.

[0205] When forming a metal oxide film, higher substrate temperatures result in a more crystalline and dense metal oxide film. Conversely, lower substrate temperatures result in a less crystalline and more electrically conductive metal oxide film.

[0206] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or PEALD. The thermal ALD method is preferred because it exhibits extremely high step coverage. The PEALD method is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0207] In the ALD method, films of any composition can be deposited by using multiple different types of precursors. When multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor. When depositing metal oxides using the ALD method, the film can be deposited using a precursor containing the constituent metal elements and an oxidizing agent.

[0208] For example, when forming an In-Ga-Zn oxide film, three precursors—one containing indium, one containing gallium, and one containing zinc—can be used, along with ozone, oxygen, water, or other oxidizing agents. Alternatively, two precursors—one containing indium, and two containing gallium and zinc—can be used, along with ozone, oxygen, water, or other oxidizing agents.

[0209] For example, when forming an indium oxide film, an indium-containing precursor and oxidizing agents such as ozone, oxygen, or water can be used.

[0210] Examples of indium-containing precursors that can be used include trimethylindium, triethylindium (TEI), tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0211] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride can be used.

[0212] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0213] For example, ozone, oxygen, and water can be used as oxidizing agents.

[0214] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit two or more films with different compositions in succession.

[0215] When the semiconductor layer 18 has a laminated structure having two or more metal oxide layers, the compositions may be the same or approximately the same. Alternatively, it may be a laminated structure in which two or more oxide semiconductor layers with different compositions are stacked. Furthermore, by using the ALD method, it is possible to form metal oxide layers with continuously different compositions in the thickness direction. This not only broadens the range of design choices compared to using a film with a fixed composition, but also prevents the formation of interface states between two layers with different compositions, thereby improving electrical properties and reliability. In addition, metal oxide layers having a laminated structure may be formed using both the sputtering method and the ALD method.

[0216] It is preferable to perform an impurity removal treatment on the metal oxide film. The impurity removal treatment is preferably performed intermittently during the metal oxide film formation. Alternatively, it is preferable to perform the impurity removal treatment after the metal oxide film formation. By performing the impurity removal treatment during and / or after the metal oxide film formation, impurities in the film can be removed. This suppresses the retention of impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors in the metal oxide. It also suppresses the retention of impurities (hydrogen, carbon, nitrogen, etc.) that are incorporated during film formation. Therefore, the impurity concentration in the metal oxide can be reduced. Furthermore, the treatment to remove impurities from the metal oxide film can also serve to improve the crystallinity of the metal oxide film. Improving the crystallinity of the metal oxide film makes it possible to realize transistors with good reliability.

[0217] Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0218] When performing plasma treatment or microwave treatment, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher and 500°C or lower, 100°C or higher and 500°C or lower, 200°C or higher and 500°C or lower, 300°C or higher and 500°C or lower, 400°C or higher and 500°C or lower, or 400°C or higher and 450°C or lower, respectively. The temperature for the heat treatment is preferably, for example, 100°C or higher and 950°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 450°C or lower.

[0219] The temperature during the impurity removal process should be set to a temperature below the maximum temperature in the transistor or semiconductor device manufacturing process, which is preferable as it reduces the impurity content in the metal oxide without decreasing productivity. For example, by setting the maximum temperature in the manufacturing of a semiconductor device according to one embodiment of the present invention to 500°C or less, preferably 450°C or less, the productivity of the semiconductor device can be increased.

[0220] Here, microwave processing refers to processing using, for example, a device that has a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0221] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. The power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Applying RF to the substrate side allows oxygen ions generated by the high-density plasma to be efficiently guided into the film.

[0222] Microwave treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and even more preferably 350°C to 450°C.

[0223] Microwave processing can be performed, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２The oxygen flow rate ratio (O) is greater than 0% and less than or equal to 100%. Preferably, the oxygen flow rate ratio (O) ２ / ( O ２ The oxygen flow rate ratio (O) is greater than 0% and 50% or less. ２ / ( O ２ The amount of +Ar) is 10% or more and 40% or less. More preferably, the oxygen flow rate ratio (O ２ / ( O ２ The amount of +Ar)) should be between 10% and 30%.

[0224] Furthermore, after microwave or plasma treatment, continuous heating treatment may be performed without exposure to the outside air.

[0225] Furthermore, the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. The heat treatment may also be carried out in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and even more preferably 10 ppb or less).

[0226] By performing this heat treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be removed by CO ２ And release as CO, and hydrogen in metal oxides H ２ It can be released as oxygen. Furthermore, simultaneously with the removal of the above-mentioned impurities, the rearrangement of metal atoms and oxygen atoms occurs, thereby improving crystallinity.

[0227] Subsequently, an insulating layer 19 is formed to cover the semiconductor layer 18. Then, a film that will become the conductive layer 20 is formed on the insulating layer 19 to form the conductive layer 20 (Figures 7A and 7B).

[0228] The insulating layer 19 can be formed by film deposition methods such as ALD, sputtering, and CVD. It is preferable to use the ALD method, which provides higher step coverage than other film deposition methods, for forming the insulating layer 19.

[0229] A film that will become the conductive layer 20 is formed on the insulating layer 19. The film that will become the conductive layer 20 has a film that will become the conductive layer 20_1 and a film that will become the conductive layer 20_2 provided on the film that will become the conductive layer 20_1. The film that will become the conductive layer 20 is preferably formed using, for example, a metal CVD method, a MOCVD method, an ALD method, or a sputtering method. As the film that will become the conductive layer 20, for example, titanium nitride formed by the metal CVD method can be used as the conductive layer 20_1, and tungsten formed by the metal CVD method can be used as the conductive layer 20_2. Dry etching is preferably used for processing the film that will become the conductive layer 20. A mask (not shown) is formed in the region that will become the conductive layer 20, and the conductive layer in the region where the mask is not formed is removed by etching to form the conductive layer 20. Anisotropic dry etching is preferably used for this etching process. The mask is removed after the etching process.

[0230] An insulating layer 21 is formed on the insulating layer 19 and the conductive layer 20 (Figures 7C and 7D). The insulating layer 21 can be formed by a film deposition method such as ALD, sputtering, or CVD. For example, silicon nitride or silicon oxide nitride, which are deposited by the ALD method, can be used for the insulating layer 21.

[0231] An insulating layer 22 is formed on the insulating layer 21. The insulating layer 22 can be formed by a film deposition method such as sputtering, CVD, or ALD. For example, silicon oxide or silicon oxynitride deposited by sputtering can be used for the insulating layer 22. It is preferable to use a film deposited by sputtering that does not contain hydrogen in the deposition gas for the insulating layer 22. It is also preferable to perform a heat treatment after the deposition of the insulating layer 22 to reduce the hydrogen content in the insulating layer 22. After the deposition of the insulating layer 22, the insulating layer 22 is planarized by a planarization treatment. For example, the CMP method can be used for the planarization treatment.

[0232] By following the above steps, the semiconductor device illustrated in Figures 4A to 4C can be manufactured. Using this manufacturing method, it is possible to provide transistors that can be miniaturized, or transistors with a small footprint, or transistors with high reliability, or transistors that can be arranged at high density.

[0233] In the following section, using Figures 8A to 21B, we will describe examples of transistor configurations that differ in some aspects from transistor 10A. Note that we will omit explanations of parts that overlap with the above and will only explain the differences. Furthermore, even if components differ in position or shape, if their function is the same, they may be given the same reference numeral and their explanation may be omitted. Note that the semiconductor devices shown in Figures 8A to 21B can be manufactured using the methods described in the previously mentioned [Examples of Semiconductor Device Manufacturing Methods]. Additionally, the materials and configurations described in [Semiconductor Device Material Compositions] can be used.

[0234] [Example of Semiconductor Device Configuration 2] Figures 8A and 8B show an example of a semiconductor device having a transistor 10B. Figure 8A is a cross-sectional view of the transistor 10B corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 8B is a cross-sectional view of the transistor 10B corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0235] The semiconductor device having transistor 10B shown in Figures 8A and 8B is an example in which the semiconductor layer 18 is formed to cover the conductive layer 12 located at the opening 90. The semiconductor layer 18 also has a region in contact with the side surface of the conductive layer 12 at the opening 90. Furthermore, the semiconductor layer 18 has a region in contact with the upper surface of the insulating layer 16 outside the opening 90, and a region in contact with the upper surface of the insulating layer 11 at the opening 90. The conductive layer 20 has a region in the opening 90 that sandwiches the insulating layer 19 and the semiconductor layer 18 between itself and the side surface of the conductive layer 12. In addition, the semiconductor layer 18 of transistor 10B is an example in which it is formed to cover the side surface of the conductive layer 17 in the cross section between A1 and A2, as shown in Figure 8A. In this way, by increasing the contact area between the conductive layer 12 and the semiconductor layer 18, and the contact area between the conductive layer 17 and the semiconductor layer 18, the contact resistance between the semiconductor layer 18 and the conductive layer 17 and conductive layer 12 can be reduced, and a semiconductor device capable of carrying a large current can be obtained. Furthermore, semiconductor devices with good electrical characteristics can be obtained.

[0236] [Example of Semiconductor Device Configuration 3] Figures 8C and 8D show an example of a semiconductor device having a transistor 10C. Figure 8C is a cross-sectional view of the transistor 10C corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 8D is a cross-sectional view of the transistor 10C corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0237] The semiconductor device having a transistor 10C shown in Figures 8C and 8D is an example in which the opening 90 is formed inside the conductive layer 12 in a plan view. As shown in Figure 8C, the conductive layer 12 of the transistor 10C has a recess in the region that overlaps with the opening 90. The semiconductor layer 18 has a region that is in contact with the recess of the conductive layer 12. Furthermore, the area of ​​the region of the conductive layer 12 that is in contact with the semiconductor layer 18 is smaller than the area of ​​the recess of the conductive layer 12. Also, by having a recess in the region that overlaps with the opening 90 of the conductive layer 12, the contact area between the conductive layer 12 and the semiconductor layer 18 can be increased compared to the case where there is no recess. Therefore, the contact resistance between the conductive layer 12 and the semiconductor layer 18 can be reduced. It is preferable that the depth of the recess of the conductive layer 12 be the same as or deeper than the total film thickness of the semiconductor layer 18 and the insulating layer 19. It is preferable that the height of the bottom surface of the conductive layer 20 of the opening 90 be the same as or lower than the height of the top surface of the conductive layer 12 other than the recess. This configuration allows for improved control of carriers (electrons) in the semiconductor layer 18 near one of the source and drain electrodes (in this case, the conductive layer 12) by the gate electric field from the gate electrode (conductive layer 20), compared to a configuration without a recess. The regions of the semiconductor layer 18, insulating layer 19, and conductive layer 20 provided on the recess near the recess may have curved portions. In other words, these regions may have curved or concave surfaces in cross-sectional view. Furthermore, these regions may not have corners (right angles or acute angles) in cross-sectional view. This reduces electric field concentration on the insulating layer 19 near the recess, improves the dielectric breakdown voltage of the transistor 10C, and suppresses electrostatic discharge breakdown of the transistor 10C. Therefore, the reliability of the semiconductor device can be improved.

[0238] [Example of Semiconductor Device Configuration 4] Figures 9A and 9B show an example of a semiconductor device having a transistor 10D. Figure 9A is a cross-sectional view of the transistor 10D corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 9B is a cross-sectional view of the transistor 10D corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0239] In the semiconductor device having the transistor 10D shown in Figures 9A and 9B, a portion of the conductive layer 12_1, a portion of the conductive layer 12_2, and a portion of the conductive layer 12_3 are removed when the opening 90 is formed. As shown in Figure 9A, the semiconductor layer 18 of the transistor 10D has a region in contact with the side surface of the conductive layer 12_1, a region in contact with the side surface of the conductive layer 12_2, and a region in contact with the side surface of the conductive layer 12_3 at the opening 90. The semiconductor layer 18 also has a region in contact with the upper surface of the insulating layer 11 at the opening 90. In the transistor 10D, the contact surface between the semiconductor layer 18 and the conductive layer 12 can be formed in a plane parallel to the Z direction. Therefore, a semiconductor device with a small occupied area can be obtained. Furthermore, a semiconductor device that can arrange semiconductor devices at a higher density can be obtained. Also, as shown in Figure 9A, the area of ​​the region where the conductive layer 12 and the conductive layer 20 overlap can be in the direction of the thickness of the conductive layer 12 (Z direction). Therefore, the parasitic capacitance generated between the conductive layer 12 and the conductive layer 20 can be reduced.

[0240] [Example of Semiconductor Device Configuration 5] Figures 9C and 9D show an example of a semiconductor device having a transistor 10E. Figure 9C is a cross-sectional view of the transistor 10E corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 9D is a cross-sectional view of the transistor 10E corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0241] The semiconductor device having transistor 10E shown in Figures 9C and 9D is an example in which an insulating layer 23 is added below the insulating layer 11 to the transistor 10D shown in Figures 9A and 9B. Similar to the semiconductor device having transistor 10D shown in Figures 9A and 9B, a portion of conductive layer 12_1, a portion of conductive layer 12_2, and a portion of conductive layer 12_3 are removed when the opening 90 is formed. Furthermore, in the semiconductor device having transistor 10E, the insulating layer 11 in the region overlapping with the opening 90 is removed. As shown in Figure 9C, the semiconductor layer 18 of transistor 10E has regions in contact with the side surface of conductive layer 12_1, regions in contact with the side surface of conductive layer 12_2, and regions in contact with the side surface of conductive layer 12_3 at the opening 90. The semiconductor layer 18 also has regions in contact with the side surface of insulating layer 11 at the opening 90. The semiconductor layer 18 also has regions in contact with the upper surface of insulating layer 23 at the opening 90. When forming the opening 90, the insulating layer 11 may also be opened, increasing the margin for setting the conditions for opening formation. The insulating layer 23 can use the materials and configurations described in the [Insulating Layer] section of the [Constituent Materials of Semiconductor Devices] section above.

[0242] [Example of Semiconductor Device Configuration 6] Figures 10A and 10B show an example of a semiconductor device having a transistor 10F. Figure 10A is a cross-sectional view of the transistor 10F corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 10B is a cross-sectional view of the transistor 10F corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0243] In the semiconductor device having transistor 10F shown in Figures 10A and 10B, a semiconductor layer 18 is provided on one of a pair of opposing portions of the side surface of the insulating layer 16 at the opening 90, and a conductive layer 12 is provided in a position that overlaps with the other of the pair of opposing portions of the side surface of the insulating layer 16. The lower end of the conductive layer 17 overlaps with the upper end of one of the pair of opposing portions of the side surface of the insulating layer 16, and the conductive layer 12 overlaps with the lower end of the other of the pair of opposing portions of the side surface of the insulating layer 16. In other words, the conductive layer 12 is located on the conductive layer 17 side of the transistor adjacent to it in the X direction. Note that the conductive layer 12 may be made larger, or adjacent transistors may be placed closer together, so that the conductive layer 12 and the conductive layer 17 of the adjacent transistor overlap. The semiconductor layer 18 has regions in contact with the side surface of the insulating layer 16, the side surface of the insulating layer 15, the side surface of the insulating layer 14, the side surface of the insulating layer 13, and the upper surface of the insulating layer 11, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer (total thickness of each insulating layer) exposed at the opening 90, the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 11 exposed at the bottom of the opening 90 can be used as the channel length of the transistor 10F. Therefore, the channel length of the transistor 10F can be increased without excessively increasing the occupied area. This reduces the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less likely to change. For example, it is suitable for use as part of the pixel transistors of a display device or in an analog circuit. Furthermore, since the conductive layer 12 and the conductive layer 17 of an adjacent transistor can be stacked, transistors can be arranged at a higher density.

[0244] [Semiconductor Device Configuration Example 7] Figures 10C and 10D show an example of a semiconductor device having a transistor 10G. Figure 10C is a cross-sectional view of the transistor 10G corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 10D is a cross-sectional view of the transistor 10G corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0245] The semiconductor device having the transistor 10G shown in Figures 10C and 10D has a separation between the lower end of the conductive layer 17 and the upper end of the insulating layer 16 at the opening 90. The semiconductor layer 18 has regions in contact with the upper surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 15, regions in contact with the side surface of the insulating layer 14, and regions in contact with the side surface of the insulating layer 13, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer at the opening 90 (total thickness of each insulating layer), the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 16 outside the opening 90 can be used as the channel length of the transistor 10G. Therefore, the channel length of the transistor 10G can be increased without excessively increasing the occupied area. This reduces the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less likely to change. For example, it is suitable for use as part of the pixel transistors of a display device or in an analog circuit.

[0246] [Semiconductor Device Configuration Example 8] Figures 11A and 11B show an example of a semiconductor device having a transistor 10H. Figure 11A is a cross-sectional view of the transistor 10H corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 11B is a cross-sectional view of the transistor 10H corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0247] The semiconductor device having transistor 10H shown in Figures 11A and 11B is a modified example of the semiconductor device having transistor 10F shown in Figure 10A. In the semiconductor device having transistor 10H, the lower end of the conductive layer 17 and the upper end of the insulating layer 16 in the opening 90 are separated. In the opening 90, the semiconductor layer 18 is provided on one of a pair of opposing portions of the side surface of the insulating layer 16, and the conductive layer 12 is provided in a position that overlaps with the other of the pair of opposing portions of the side surface of the insulating layer 16. The conductive layer 12 is located on the conductive layer 17 side of the transistor adjacent to it in the X direction. The conductive layer 12 may be made larger, or adjacent transistors may be placed closer together, so that the conductive layer 12 and the conductive layer 17 of the adjacent transistor overlap. The semiconductor layer 18 has regions in contact with the upper surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 15, regions in contact with the side surface of the insulating layer 14, regions in contact with the side surface of the insulating layer 13, and regions in contact with the upper surface of the insulating layer 11, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer (total thickness of each insulating layer) at the opening 90, the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 11 exposed at the bottom of the opening 90 and the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 16 can be used as the channel length of the transistor 10H. Therefore, the channel length of the transistor 10H can be increased without excessively increasing the occupied area. This makes it possible to reduce the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less likely to change. For example, it is suitable for use as part of the pixel transistors of a display device or in an analog circuit. Furthermore, since the conductive layer 12 and the conductive layer 17 of the adjacent transistor can be placed on top of each other, transistors can be arranged at a higher density.

[0248] [Example of Semiconductor Device Configuration 9] Figures 11C and 11D show an example of a semiconductor device having a transistor 10I. Figure 11C is a cross-sectional view of the transistor 10I corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 11D is a cross-sectional view of the transistor 10I corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0249] The semiconductor device having transistor 10I shown in Figures 11C and 11D is a modified example of the semiconductor device having transistor 10H shown in Figure 11A. In the semiconductor device having transistor 10I, the lower end of the conductive layer 17 and the upper end of the insulating layer 16 in the opening 90 are separated. In the opening 90, the semiconductor layer 18 is provided on one of a pair of opposing portions of the side surface of the insulating layer 16, and the conductive layer 12 is provided in a position that overlaps with the other of the pair of opposing portions of the side surface of the insulating layer 16. Furthermore, with the formation of the opening 90, a recess is formed in a part of the insulating layer 11. The semiconductor layer 18 has a region that is positioned to traverse the recess. The semiconductor layer 18 has a region in contact with the upper surface of the insulating layer 16, a region in contact with the side surface of the insulating layer 16, a region in contact with the side surface of the insulating layer 15, a region in contact with the side surface of the insulating layer 14, a region in contact with the side surface of the insulating layer 13, and a region in contact with the recess of the insulating layer 11, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer at the opening 90 (total thickness of each insulating layer), the region of the semiconductor layer 18 in contact with the recess of the insulating layer 11 exposed at the bottom of the opening 90 and the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 16 can be used as the channel length of the transistor 10I. Therefore, the channel length of the transistor 10I can be increased without excessively increasing the occupied area. This reduces the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less likely to change. For example, it is suitable for use as part of the pixel transistors of a display device or in an analog circuit. Furthermore, when forming the opening 90, a recess may be formed in the insulating layer 11, increasing the margin for setting the conditions for opening formation.

[0250] [Example of semiconductor device configuration 10] Figures 12A and 12B show an example of a semiconductor device having a transistor 10J. Figure 12A is a cross-sectional view of the transistor 10J corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 12B is a cross-sectional view of the transistor 10J corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0251] The semiconductor device having transistor 10J shown in Figures 12A and 12B has a region where the upper end of the side surface of the insulating layer 16 in the opening 90 overlaps with the lower end of the conductive layer 17, and a region where it overlaps with the lower end of the conductive layer 17 of the adjacent transistor. In the cross-section shown in Figure 12A, the width (J1) of the conductive layer 17 and the width (J1) of the insulating layer 16 are the same. With this configuration, the wiring width of the conductive layer 17 can be increased without excessively increasing the occupied area. As a result, the wiring resistance of the conductive layer 17 can be reduced, and a semiconductor device capable of carrying a large current can be obtained. Furthermore, a semiconductor device with good electrical characteristics can be obtained.

[0252] [Semiconductor Device Configuration Example 11] Figures 12C and 12D show an example of a semiconductor device having a transistor 10K. Figure 12C is a cross-sectional view of the transistor 10K corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 12D is a cross-sectional view of the transistor 10K corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0253] The semiconductor device having transistor 10K shown in Figures 12C and 12D has an upper end of the side surface of the insulating layer 16 in the opening 90 that overlaps with the lower end of the conductive layer 17, and an upper end of the conductive layer 17 of an adjacent transistor. In addition, a recess is formed in a part of the insulating layer 11 when the opening 90 is formed. In the cross-section shown in Figure 12C, the width (K1) of the conductive layer 17 and the width (K1) of the insulating layer 16 are the same. With this configuration, the wiring width of the conductive layer 17 can be increased without excessively increasing the occupied area. As a result, the wiring resistance of the conductive layer 17 can be reduced, and a semiconductor device capable of carrying a large current can be obtained. In addition, a semiconductor device with good electrical characteristics can be obtained. Furthermore, when forming the opening 90, a recess may be formed in the insulating layer 11, increasing the margin for setting the conditions for opening formation.

[0254] [Example of semiconductor device configuration 12] Figures 13A and 13B show an example of a semiconductor device having a transistor 10L. Figure 13A is a cross-sectional view of the transistor 10L corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 13B is a cross-sectional view of the transistor 10L corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0255] The semiconductor device having the transistor 10L shown in Figures 13A and 13B has a configuration in which the upper surface of the semiconductor layer 18 is in contact with the bottom surface of the conductive layer 17, and the lower end of the conductive layer 17 is separated from the upper end of the side surface of the insulating layer 16 at the opening 90. The semiconductor layer 18 has a region in contact with the upper surface of the insulating layer 16, a region in contact with the side surface of the insulating layer 16, a region in contact with the side surface of the insulating layer 15, a region in contact with the side surface of the insulating layer 14, and a region in contact with the side surface of the insulating layer 13, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer at the opening 90 (total thickness of each insulating layer), the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 16 outside the opening 90 can be used as the channel length of the transistor 10L. Therefore, the channel length of the transistor 10L can be increased without excessively increasing the occupied area. This makes it possible to reduce the short channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less prone to change. For example, it is suitable for use in some pixel transistors of a display device or in analog circuits.

[0256] [Example of Semiconductor Device Configuration 13] Figures 13C and 13D show an example of a semiconductor device having a transistor 10M. Figure 13C is a cross-sectional view of the transistor 10M corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 13D is a cross-sectional view of the transistor 10M corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0257] The semiconductor device having transistors 10M, as shown in Figures 13C and 13D, has a region where the upper surface of the semiconductor layer 18 is in contact with the bottom surface of the conductive layer 17. Furthermore, the lower end of the conductive layer 17 and the upper end of the side surface of the insulating layer 16 at the opening 90 are separated. At the opening 90, the semiconductor layer 18 is provided on one of a pair of opposing portions of the side surface of the insulating layer 16, and the conductive layer 12 is provided in a position overlapping with the other of the pair of opposing portions of the side surface of the insulating layer 16. The conductive layer 12 is located on the conductive layer 17 side of the adjacent transistor. Note that the conductive layer 12 may be made larger, or adjacent transistors may be placed closer together, so that the conductive layer 12 and the conductive layer 17 of the adjacent transistor overlap. The semiconductor layer 18 has regions in contact with the upper surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 16, regions in contact with the side surface of the insulating layer 15, regions in contact with the side surface of the insulating layer 14, regions in contact with the side surface of the insulating layer 13, and regions in contact with the upper surface of the insulating layer 11, extending from the conductive layer 17 toward the conductive layer 12. In addition to the region of the semiconductor layer 18 in contact with the side surface of the insulating layer (total thickness of each insulating layer) at the opening 90, the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 11 exposed at the bottom of the opening 90 and the region of the semiconductor layer 18 in contact with the upper surface of the insulating layer 16 can be used as the channel length of the transistor 10M. Therefore, the channel length of the transistor 10M can be increased without excessively increasing the occupied area. This makes it possible to reduce the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less likely to change. For example, it is suitable for use as part of the pixel transistors of a display device or in an analog circuit. Furthermore, since the conductive layer 12 and the conductive layer 17 of the adjacent transistor can be placed on top of each other, transistors can be arranged at a higher density.

[0258] [Semiconductor Device Configuration Example 14] Figures 14A and 14B show an example of a semiconductor device having a transistor 10N. Figure 14A is a cross-sectional view of the transistor 10N corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 14B is a cross-sectional view of the transistor 10N corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0259] The semiconductor device having the transistor 10N shown in Figures 14A and 14B has a conductive layer 24 and an insulating layer 25. At least a portion of the conductive layer 24 functions as a gate electrode, and at least a portion of the insulating layer 25 functions as a gate insulating layer. Therefore, the transistor 10N has a conductive layer 20 that functions as a first gate electrode, a conductive layer 24 that functions as a second gate electrode, an insulating layer 19 that functions as a first gate insulating layer, and an insulating layer 25 that functions as a second gate insulating layer. The insulating layer 25 is in contact with the side surfaces of the insulating layer 16, the insulating layer 15, the insulating layer 14, and the insulating layer 13 at the opening 90. The insulating layer 25 also has regions that are in contact with the side surfaces of the conductive layer 17, the conductive layer 12, and the conductive layer 24. The semiconductor layer 18 is in contact with the insulating layer 25 at the opening 90. The semiconductor layer 18 is also in contact with the conductive layer 24 at the opening 90, with the insulating layer 25 in between. The semiconductor layer 18 has a first region. This first region faces the conductive layer 20 across the insulating layer 19, and also faces the conductive layer 24 across the insulating layer 25.

[0260] [Semiconductor Device Configuration Example 15] Figures 14C and 14D show an example of a semiconductor device having a transistor 10P. Figure 14C is a cross-sectional view of transistor 10P corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 14D is a cross-sectional view of transistor 10P corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0261] The semiconductor device having the transistor 10P shown in Figures 14C and 14D has a conductive layer 24 and an insulating layer 25. In the cross-section shown in Figure 14C, the conductive layer 24 has a configuration in which the width (P1) of the conductive layer 24 matches the width (P1) of the insulating layer 16. With this configuration, the wiring width of the conductive layer 24 can be increased without excessively increasing the occupied area. As a result, the wiring resistance of the conductive layer 24 can be reduced, and the voltage drop can be reduced, so a semiconductor device with good electrical characteristics can be obtained. At least a portion of the conductive layer 24 functions as a gate electrode, and at least a portion of the insulating layer 25 functions as a gate insulating layer. Therefore, the transistor 10P has a conductive layer 20 that functions as a first gate electrode, a conductive layer 24 that functions as a second gate electrode, an insulating layer 19 that functions as a first gate insulating layer, and an insulating layer 25 that functions as a second gate insulating layer. The insulating layer 25 is in contact with the side surface of the insulating layer 16, the side surface of the insulating layer 15, the side surface of the insulating layer 14, and the side surface of the insulating layer 13 at the opening 90. Furthermore, the insulating layer 25 has regions that are in contact with the side surfaces of the conductive layer 17, the conductive layer 12, and the conductive layer 24. The semiconductor layer 18 has a region that is in contact with the insulating layer 25 at the opening 90. The semiconductor layer 18 also has a region that faces the conductive layer 24 across the insulating layer 25 at the opening 90. The semiconductor layer 18 has a first region. This first region faces the conductive layer 20 across the insulating layer 19, and also faces the conductive layer 24 across the insulating layer 25.

[0262] Furthermore, the semiconductor device shown in Figures 14A to 14D includes a conductive layer 20 that functions as a first gate electrode and a conductive layer 24 that functions as a second gate electrode. By changing the potential applied to the conductive layer 24 independently of the potential applied to the conductive layer 20, the threshold voltage V of the transistor can be controlled. ｔｈ This can be controlled. In particular, by applying a negative potential to the conductive layer 24, the V of the transistor can be controlled. ｔｈThis makes it possible to increase the potential and reduce the off-current. Therefore, applying a negative potential to the conductive layer 24 reduces the drain current when the potential applied to the conductive layer 20 is 0V compared to when no potential is applied. In addition, the conductive layer 20 may function as the second gate electrode and the conductive layer 24 may function as the first gate electrode.

[0263] Alternatively, the conductive layer 24 may be connected to the conductive layer 20. By connecting the conductive layer 20 and the conductive layer 24 and applying the same potential, it is possible to increase the on-current, reduce initial characteristic variations, suppress deterioration of electrical characteristics in negative GBT (Gate Bias-Temperature) stress tests, and suppress DIBL (Drain Induced Barrier Lowering).

[0264] Furthermore, the conductive layer 24 may use the materials and configuration described in the "Conductive Layer" section of the aforementioned "Constituent Materials for Semiconductor Devices." The insulating layer 25 may use the materials and configuration described in the "Insulating Layer" and "Gate Insulating Layer" sections of the aforementioned "Constituent Materials for Semiconductor Devices."

[0265] [Semiconductor Device Configuration Example 16] Figures 15A and 15B show an example of a semiconductor device having a transistor 10Q. Figure 15A is a cross-sectional view of transistor 10Q corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 15B is a cross-sectional view of transistor 10Q corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0266] The semiconductor device having transistor 10Q shown in Figures 15A and 15B has a conductive layer 26. The conductive layer 26 is provided on an insulating layer 22. The conductive layer 20 extends in the Z direction and is in contact with the conductive layer 26. The conductive layer 26 overlaps with the conductive layer 17 mainly via the insulating layers 22 and 21. This increases the physical distance between the conductive layer 26 and the conductive layer 17, thereby reducing the parasitic capacitance between the conductive layer 26 and the conductive layer 17. Transistor 10Q has a configuration that reduces the parasitic capacitance between the source electrode, the other drain electrode, and the gate wiring. Therefore, the frequency characteristics of a circuit using this transistor can be improved.

[0267] Furthermore, the conductive layer 26 can use the materials and configuration described in the [Conductive Layer] section of the [Constituent Materials of Semiconductor Devices] mentioned above.

[0268] [Semiconductor Device Configuration Example 17] Figures 15C and 15D show an example of a semiconductor device having a transistor 10R. Figure 15C is a cross-sectional view of the transistor 10R corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 15D is a cross-sectional view of the transistor 10R corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0269] The semiconductor device having transistor 10R shown in Figures 15C and 15D has a conductive layer 26. The conductive layer 26 is provided on an insulating layer 22. It also has a conductive layer 27 embedded in the insulating layers 21 and 22. The conductive layer 27 functions as a plug or wiring connecting conductive layer 20 and conductive layer 26. The conductive layer 26 overlaps with conductive layer 17 mainly via insulating layers 22 and 21. This increases the physical distance between conductive layer 26 and conductive layer 17, and reduces the parasitic capacitance between conductive layer 26 and conductive layer 17. Transistor 10R has a configuration in which the parasitic capacitance between the source electrode, the other of the drain electrode, and the gate wiring is reduced. Therefore, the frequency characteristics of the circuit using this transistor can be improved.

[0270] Furthermore, the conductive layer 27 can use the materials and configuration described in the [Conductive Layer] section of the [Constituent Materials of Semiconductor Devices] mentioned above.

[0271] [Semiconductor Device Configuration Example 18] Figures 16A and 16B show an example of a semiconductor device having a transistor 10S. Figure 16A is a cross-sectional view of the transistor 10S corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 16B is a cross-sectional view of the transistor 10S corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0272] The semiconductor device having a transistor 10S shown in Figures 16A and 16B has an insulating layer 28. The insulating layer 28 has its bottom surface in contact with the insulating layer 14, its top surface in contact with the insulating layer 16, and its side surface in contact with the insulating layer 15. The insulating layer 15 has a region in contact with the semiconductor layer 18. It is preferable to use an insulating layer 15 that has a region containing excess oxygen. For example, silicon oxide or silicon oxynitride can be used. It is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities and oxygen or insulating layer materials that have barrier properties against oxygen for the insulating layer 28, insulating layer 14, and insulating layer 16. By providing the insulating layer 15 in contact with the semiconductor layer 18 and surrounding the insulating layer 15 with the insulating layer 14, insulating layer 16, and insulating layer 28, the volume of the insulating layer 15 relative to the semiconductor layer 18 can be limited, and the amount of oxygen that can be supplied to the semiconductor layer 18 can be optimized. Alternatively, oxygen can be made less likely to be supplied to the semiconductor layer 18 from locations other than the insulating layer 15. Or, oxygen can be made less likely to be supplied to the semiconductor layer 18 from locations far from the transistor. By adopting such a configuration, it is possible to provide a transistor with high reliability over the long term. In other words, it is possible to control the threshold voltage of the transistor while simultaneously achieving high reliability.

[0273] [Example of Semiconductor Device Configuration 19] Figures 17A and 17B show an example of a semiconductor device having a transistor 10T. Figure 17A is a cross-sectional view of the transistor 10T corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 17B is a cross-sectional view of the transistor 10T corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0274] The semiconductor device having a transistor 10T shown in Figures 17A and 17B has a conductive layer 29. This semiconductor device has a configuration in which the conductive layer 29 is added to the semiconductor device having a transistor 10P shown in Figures 14C and 14D. In the cross-section shown in Figure 17A, the conductive layer 29 has a region that overlaps with the conductive layer 12 via an insulating layer 13. A capacitive element can be formed by having the conductive layer 29 and the conductive layer 12 as a pair of opposing electrodes, and the insulating layer 13 function as a dielectric layer located between the pair of opposing electrodes. A part of the electrode that functions as either the source electrode or the drain electrode of the transistor 10T functions as one of the pair of electrodes of the capacitive element. In this way, by having the transistor 10T and the capacitive element share some components, the transistor and the capacitive element can be formed without excessively increasing the number of steps. Furthermore, because the transistor 10T and the capacitive element have an overlapping region, the capacitive element can be formed without excessively increasing the occupied area.

[0275] Furthermore, the conductive layer 29 can use the materials and configuration described in the "Conductive Layer" section of the aforementioned "Constituent Materials for Semiconductor Devices."

[0276] [Example of semiconductor device configuration 20] Figures 17C and 17D show an example of a semiconductor device having a transistor 10U. Figure 17C is a cross-sectional view of the transistor 10U corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Figure 17B is a cross-sectional view of the transistor 10U corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0277] The semiconductor device having a transistor 10U shown in Figures 17C and 17D has a conductive layer 30. This semiconductor device has a configuration in which the conductive layer 30 is added to the semiconductor device having a transistor 10P shown in Figure 14C. In the cross-section shown in Figure 17C, the conductive layer 30 has a region that overlaps with the conductive layer 17 via an insulating layer 16. A capacitive element can be formed by having the conductive layer 30 and the conductive layer 17 as a pair of opposing electrodes, and the insulating layer 16 function as a dielectric layer located between the pair of opposing electrodes. A part of the electrode that functions as either the source electrode or the drain electrode of the transistor 10U functions as one of the pair of electrodes of the capacitive element. In this way, by having the transistor 10U and the capacitive element share some components, the transistor and the capacitive element can be formed without excessively increasing the number of steps. Furthermore, because the transistor 10U and the capacitive element have an overlapping region, the capacitive element can be formed without excessively increasing the occupied area.

[0278] Furthermore, the conductive layer 30 may use the materials and configurations described in the "Conductive Layer" section of the "Constituent Materials of Semiconductor Devices" section mentioned above.

[0279] [Example of Semiconductor Device Configuration 21] Figures 18A and 18B show an example of a semiconductor device having transistors 10V (transistor 10V_1, transistor 10V_2). Figure 18A is a cross-sectional view of transistor 10V corresponding to the cross-sectional view between the dashed lines A1 and A2 shown in Figure 4A. Also, Figure 18A is a cross-sectional view of transistor 10V corresponding to the cross-sectional view between the dashed lines B1 and B2 shown in Figure 4A.

[0280] The semiconductor device having transistors 10V (transistor 10V_1, transistor 10V_2) shown in Figures 18A and 18B is a configuration in which conductive layers 32, insulating layers 33, and insulating layers 34 are added to the semiconductor device having transistor 10D shown in Figures 9A and 9B. The conductive layer 32 is located on the insulating layer 14. The conductive layer 32 also has conductive layer 32_1, conductive layer 32_2 provided on conductive layer 32_1, and conductive layer 32_3 provided on conductive layer 32_2. The insulating layer 33 is located on the insulating layer 14 and is provided so as to cover the conductive layer 32. The insulating layer 34 is located on the insulating layer 33. The opening 90 is provided in insulating layer 16, insulating layer 15, insulating layer 34, insulating layer 33, insulating layer 14, and insulating layer 13 and reaches the insulating layer 11. With the formation of the opening 90, a part of conductive layer 12_1, a part of conductive layer 12_2, and a part of conductive layer 12_3 are removed. Furthermore, in conjunction with the formation of the opening 90, a portion of the conductive layer 32_1, a portion of the conductive layer 32_2, and a portion of the conductive layer 32_3 are removed. As shown in Figure 18A, the semiconductor layer 18 of transistor 10V_1 has regions in contact with the side surface of conductive layer 12_1, a region in contact with the side surface of conductive layer 12_2, and a region in contact with the side surface of conductive layer 12_3 at the opening 90. Similarly, the semiconductor layer 18 of transistor 10V_2 has regions in contact with the side surface of conductive layer 32_1, a region in contact with the side surface of conductive layer 32_2, and a region in contact with the side surface of conductive layer 32_3 at the opening 90. In addition, the semiconductor layer 18 has a region in contact with the upper surface of the insulating layer 11 at the opening 90. In transistor 10V_1 (transistor 10V_2), the contact surface between the semiconductor layer 18 and the conductive layer 12 (conductive layer 32) can be formed on a plane parallel to the Z direction. Therefore, a semiconductor device with a small occupied area can be obtained. Furthermore, it is possible to obtain a semiconductor device that can arrange semiconductor devices at a higher density. In addition, it is possible to form transistors with different distances from one source electrode to the other without excessively increasing the number of manufacturing steps. Transistors with different channel lengths can be formed using transistor 10V_1 and transistor 10V_2.

[0281] Furthermore, the insulating layer 33 and insulating layer 34 may use the materials and configurations described in the "Insulating Layer" section of the aforementioned "Component Materials for Semiconductor Devices." Also, the conductive layer 32 may use the materials and configurations described in the "Conductive Layer" section of the aforementioned "Component Materials for Semiconductor Devices."

[0282] [Example of Semiconductor Device Configuration 22] Figures 19A and 19B illustrate an example of semiconductor device arrangement in a plan view. Figure 19B shows an example of a configuration in which the openings 90 are connected in the Y direction, compared to Figure 19A. As shown in Figures 19A and 19B, the transistors 10X are arranged such that the conductive layer 17 is located on only one side of the opening 90. Alternatively, if the opening 90 is rectangular in a plan view, the conductive layer 17 is arranged so that it follows one of a pair of opposite sides of the opening 90, and the conductive layer 17 of an adjacent transistor follows the other of the pair of opposite sides of the opening 90. Furthermore, when forming the opening 90, the conductive layer 17 can be used as part of a mask, and etching conditions that do not remove the conductive layer 17 can be selected to form the edges of the conductive layer 17 and the opening 90 in a self-aligned manner. With this configuration, the wiring width of the conductive layer 17 near the opening 90 (W1) does not decrease compared to the width (W2) of the conductive layer 17, and the thickness of the conductive layer 17 near the opening 90 (W1) can be maintained. Therefore, the increase in the wiring resistance of the conductive layer 17 that occurs with a decrease in the width (W1) of the conductive layer 17 near the opening 90 is suppressed, and in Figures 19A and 19B, the wiring resistance of the conductive layer 17 extending in the Y direction can be kept low. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a semiconductor device capable of carrying a large current can be provided.

[0283] Furthermore, this arrangement allows for the creation of self-aligned openings 90 between the conductive layer 17 and the conductive layer 17 of an adjacent transistor, thereby shortening the distance between adjacent transistors 10X. As shown in Figures 19A and 19B, the pitch (W3) between the nth row conductive layer 17 and the (n+1)th row conductive layer 17 can be shortened. This makes it possible to obtain a semiconductor device with a smaller occupied area. It also makes it possible to obtain a semiconductor device in which semiconductor devices can be arranged at a higher density.

[0284] Furthermore, Figure 19A shows an example where the width (G1) of the conductive layer 20 is greater than the width (H1) of the opening 90. In this case, since the conductive layer 20 is etched outside the opening 90 during its formation, processing becomes easier compared to processing inside the opening 90. On the other hand, the width (G1) of the conductive layer 20 may be smaller than the width (H1) of the opening 90. This configuration allows for high-density arrangement of transistors. Also, Figure 19A shows an example where the width (G1) of the conductive layer 20 is greater than the width (S1) of the semiconductor layer 18. This configuration allows for voltage to be applied from the conductive layer 20, which functions as a gate electrode, to the entire surface of the semiconductor layer 18, thus enabling the creation of a semiconductor device with good electrical characteristics. Furthermore, although Figure 19A shows an example where the width (M1) of the conductive layer 12 is greater than the width (S1) of the semiconductor layer 18, the width (M1) of the conductive layer 12 may be smaller than the width (S1) of the semiconductor layer 18. By increasing the contact area between the conductive layer 12 and the semiconductor layer 18, the contact resistance between the semiconductor layer 18 and the conductive layer 12 can be reduced, making it possible to obtain a semiconductor device that can conduct a large current. Furthermore, a semiconductor device with good electrical characteristics can be obtained. Also, although Figure 19A shows an example where the conductive layer 12 is located on a part of the bottom surface of the opening 90, the entire bottom surface of the opening 90 may be made the conductive layer 12. With such a configuration, the contact resistance between the semiconductor layer 18 and the conductive layer 12 can be reduced, making it possible to obtain a semiconductor device that can conduct a large current. Furthermore, a semiconductor device with good electrical characteristics can be obtained. Also, although Figure 19A shows an example where the width (S1) of the semiconductor layer 18 is smaller than the width (H1) of the opening 90, the width (S1) of the semiconductor layer 18 may be larger than the width (H1) of the opening 90. With such a configuration, a semiconductor device that can conduct a large current can be obtained. Furthermore, a semiconductor device with good electrical characteristics can be obtained.

[0285] Figures 20A to 20E illustrate modified examples of the semiconductor device in a plan view. Figures 20A to 20E show an example where two transistors are arranged in the X direction.

[0286] Figure 20A shows an example where the conductive layer 12 is positioned toward the adjacent transistor in the X direction. In this way, the position of the conductive layer 12 can be placed at any position within the range in which at least a part of the conductive layer 12 is exposed in the opening 90. In the opening 90, the semiconductor layer 18 is provided on one of a pair of opposing parts of the side surface of the insulating layer 16, and the conductive layer 12 is provided in a position that overlaps with the other of the pair of opposing parts of the side surface of the insulating layer 16. The conductive layer 12 is located toward the conductive layer 17 of the adjacent transistor. Note that the conductive layer 12 may be made larger, or adjacent transistors may be placed closer together, so that the conductive layer 12 and the conductive layer 17 of the adjacent transistor overlap. Since the conductive layer 12 and the conductive layer 17 of the adjacent transistor can be arranged on top of each other, transistors can be arranged at a higher density. Figure 20B shows an example in which the conductive layer 12 is wider than the bottom of the opening 90. The contact area between the conductive layer 12 and the semiconductor layer 18 can be increased, and contact resistance can be reduced. Therefore, it is possible to obtain a semiconductor device that can carry a large current.

[0287] Figure 20C shows an example where the position of the opening 90 is located on the side of the adjacent transistor in the X direction. It also shows an example where the position of the conductive layer 12 is located on the side of the opening 90 closer to the conductive layer 17. Figure 20D shows an example where the position of the conductive layer 12 is located on the side of the adjacent transistor in the X direction. In the opening 90, the semiconductor layer 18 is provided on one of a pair of opposing portions of the side surface of the insulating layer 16, and the conductive layer 12 is provided in a position that overlaps with the other of the pair of opposing portions of the side surface of the insulating layer 16. The conductive layer 12 is located on the side of the conductive layer 17 of the adjacent transistor. Since the conductive layer 12 and the conductive layer 17 of the adjacent transistor can be arranged on top of each other, transistors can be arranged at a higher density. As shown in Figures 20C and 20D, the position of the conductive layer 12 can be placed at any position within the range in which at least a part of the conductive layer 12 is exposed in the opening 90. Also, Figure 20E shows an example in which the conductive layer 12 is wider than the bottom of the opening 90. The contact area between the conductive layer 12 and the semiconductor layer 18 can be increased, thereby reducing contact resistance. By arranging the openings 90 as shown in Figures 20C to 20E, the channel length of the transistor can be increased, thereby reducing the short-channel effect. Alternatively, when the transistor operates in the saturation region, the drain current becomes less prone to change. For example, it is suitable for use in part of the pixel transistors of a display device or in an analog circuit.

[0288] In addition, in any of the arrangement examples, a portion of the conductive layer 17 may be removed when the opening 90 is formed. With this configuration, the edge of the conductive layer 17 and the opening 90 can be formed in a self-aligned manner. Furthermore, when forming the opening 90, a portion of the conductive layer 17 can be used as a mask to create the opening. In this way, the edge of the conductive layer 17 and the opening 90 can be formed in a self-aligned manner. Thus, a semiconductor device that can be arranged at high density can be obtained.

[0289] [Semiconductor Device Configuration Example 23] Figures 21A and 21B illustrate an example of semiconductor device arrangement in a plan view. Figure 21B shows an example of a configuration in which the openings 90 are connected in the Y direction, compared to Figure 21A. As shown in Figures 21A and 21B, the transistor 10X is arranged such that the conductive layer 17 is located on only one side of the opening 90. Alternatively, if the opening 90 is a semicircle (semi-ellipse) in a plan view, the conductive layer 17 is arranged so that it lies along one side of a pair of opposite sides of the opening 90. Furthermore, by selecting etching conditions that do not remove part of the conductive layer 17 when forming the opening 90, the width of the conductive layer 17 near the opening 90 (W1) can be maintained without reducing the wiring width of the conductive layer 17 near the opening 90 (W1) compared to the width of the conductive layer 17 (W2). Therefore, the increase in wiring resistance of the conductive layer 17 due to the decrease in the width (W1) of the conductive layer 17 near the opening 90 is suppressed, and in Figures 21A and 21B, the wiring resistance of the conductive layer 17 extending in the Y direction is kept low.

[0290] Furthermore, this arrangement allows for a shorter distance between adjacent transistors 10X. As shown in Figures 21A and 21B, the pitch (W3) between the nth row conductive layer 17 and the (n+1)th row conductive layer 17 can be shortened. This also allows for a higher density arrangement of transistors.

[0291] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0292] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0293] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0294] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0295] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 22A shows silicon (Si) and indium oxide (InO Ｘ Figure 22B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0296] First, as indicated by the arrows in Figure 22B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 22A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 22A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 22A.

[0297] In Figure 22A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10１４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0298] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0299] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0300] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0301] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to form in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 22A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0302] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0303] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0304] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0305] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0306] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0307] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0308] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0309] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0310] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0311] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 22C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0312] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0313] Furthermore, as shown in Figure 22C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0314] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0315] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0316]

[0317] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0318] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0319] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0320] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0321] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0322] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0323] (Embodiment 3) This embodiment describes a storage device according to one aspect of the present invention.

[0324] <Example of Memory Device Configuration 1> A memory device according to one aspect of the present invention will be described with reference to Figures 23A to 24. The memory device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element. The transistor can be the same as the transistor described in Embodiment 1. A detailed description of the transistor and the capacitive element will be omitted as it can be described by referring to the description of Embodiment 1.

[0325] The configuration of a semiconductor device having a memory cell 100A will be explained using Figures 23A and 23B. Figure 23A is a plan view of a memory device having a memory cell 100A. Figure 23B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 23A. Figure 23C is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 23B.

[0326] The memory device shown in Figures 23A and 23C has a memory cell 100A on a substrate (not shown). The memory cell 100A has at least a capacitive element 40A and a transistor 10A.

[0327] The memory device shown in Figures 23A to 23C has an insulating layer 41, an insulating layer 42, a conductive layer 43_1, and a conductive layer 43_2 on a substrate (not shown), and a capacitive element 40A on the conductive layer 43.

[0328] The capacitive element 40A has a conductive layer 48, an insulating layer 49, and a conductive layer 12. The insulating layer 49 is provided between the conductive layer 48 and the conductive layer 12. At least a portion of the conductive layer 48 functions as one of a pair of electrodes of the capacitive element. At least a portion of the conductive layer 12 functions as the other of a pair of electrodes of the capacitive element. At least a portion of the conductive layer 12 functions as either the source electrode or the drain electrode of the transistor 10A. At least a portion of the insulating layer 49 functions as the dielectric of the capacitive element.

[0329] The insulating layers 44, 45, and 46 are provided on the insulating layer 42. The opening 91 is provided so as to reach the conductive layer 43 from the insulating layers 44, 45, and 46. The insulating layer 47 is provided along the inside of the opening 91. The conductive layer 48 has a region provided along the inside of the opening 91 and a region that contacts the conductive layer 43 at the bottom of the opening. The conductive layer 48, the insulating layer 49, and a part of the conductive layer 12 are provided so as to be located inside the opening 91. Preferably, the conductive layer 12 is provided so as to embed the opening 91. In this embodiment, an example is shown in which the opening 91 is circular in plan view, but the present invention is not limited thereto. The shapes applicable to the opening 91 are the same as the shapes applicable to the opening 90 described above.

[0330] Since at least a portion of the capacitive element 40A can be placed inside the opening 91, the capacitance per unit area in a plan view can be increased.

[0331] As shown in Figure 23B, the transistor 10A is provided so as to overlap with the capacitive element 40A. Furthermore, the opening 90, through which part of the structure of the transistor 10A is provided, has a region that overlaps with the opening 91, through which part of the structure of the capacitive element 40A is provided. In particular, since the conductive layer 12 functions as one of the pair of electrodes of the capacitive element 40A and as one of the source electrode and drain electrode of the transistor 10A, the capacitive element 40A and the transistor 10A share part of their structure. This configuration reduces the number of processes, thereby improving productivity. In addition, the capacitive element 40A and the transistor 10A can be provided without significantly increasing the occupied area in a plan view. As a result, the occupied area of ​​the memory cell 100A can be reduced, allowing for a high-density arrangement of the memory cells 100A and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0332] For insulating layers such as insulating layer 41, insulating layer 42, insulating layer 44, insulating layer 45, insulating layer 46, and insulating layer 47, the materials and configurations described in the [insulating layer] section of Embodiment 1 can be used. In particular, for insulating layer 41, insulating layer 44, insulating layer 46, and insulating layer 47, it is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, and insulating layer materials that have barrier properties against hydrogen. By using these insulating layers, the diffusion of hydrogen into the semiconductor layer 18 of the transistor 10A arranged on the capacitive element 40A can be suppressed. In addition, the transistor 10A arranged on the capacitive element 40A can be made highly reliable.

[0333] The conductive layers, such as conductive layer 43 and conductive layer 48, can be formed as a single layer or in a laminated structure using the materials and configuration described in [Conductive Layer] of Embodiment 1. For example, conductive layer 43 can have a two-layer structure using titanium nitride for conductive layer 43_1 and tungsten for conductive layer 43_2. Because a highly conductive material such as tungsten can be used, the wiring resistance of conductive layer 43 can be reduced. Alternatively, conductive layer 43 can have a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Furthermore, it is preferable to use a conductive material that is resistant to oxidation for conductive layer 43. Also, conductive layer 43 can have a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer. Alternatively, conductive layer 43 can have a four-layer structure of tantalum, tantalum nitride, titanium nitride, and tungsten from the bottom layer. For conductive layer 48, it is preferable to use a conductive oxide such as titanium nitride or In-Sn oxide.

[0334] The insulating layer, such as the insulating layer 49, can be formed as a single layer or in a laminated form using the materials and configuration described in the [insulating layer] of Embodiment 1. It is preferable to use a material with a high dielectric constant (high-k) and an insulating material with high dielectric strength or that suppresses leakage current for the insulating layer 49. For example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. By using a high-k material as the insulating layer 49, the film thickness of the insulating layer 49 can be increased to a degree that suppresses leakage current, and the capacitance of the capacitive element 40A can be sufficiently secured.

[0335] Furthermore, the insulating layer, such as the insulating layer 49, may be made of a material capable of ferroelectricity. For example, a metal oxide containing one or both of hafnium and zirconium can be used as the material capable of ferroelectricity. By using a ferroelectric material for the dielectric of the capacitive element 40A, the memory device shown in this embodiment can function as a ferroelectric memory.

[0336] The transistors in the memory cell 100A are not limited to transistor 10A, and one or more of the transistors exemplified in Embodiment 1 can be used.

[0337] Figure 24 shows an example of a cross-sectional configuration of a memory device in which a layer having a memory cell 100A, as shown in Figures 23A and 23B, is stacked on a layer on which a drive circuit including a sense amplifier is provided.

[0338] In Figure 24, a memory cell 100A (capacitive element 40A and transistor 10A) is provided above the Si transistor 900. The Si transistor 900 is one of the transistors in the drive circuit, which includes a sense amplifier.

[0339] Let's describe the Si transistor 900. The Si transistor 900 is a Fin-type transistor. Figure 24 shows a schematic cross-sectional view in the channel length direction.

[0340] The Si transistor 900 is provided on a substrate 901 and has a conductive layer 908a that functions as a gate electrode, an insulating layer 907 that functions as a gate insulating film, a semiconductor region 903 that functions as a channel forming region, and a low-resistance region 904 that functions as a source region or drain region.

[0341] For example, a silicon substrate or an SOI substrate can be used as the substrate 901.

[0342] A device isolation layer 902, an insulating layer 905, and dummy gate electrodes 908b and 908c are provided on the substrate 901. The insulating layer 905 functions as a sidewall. In addition, insulating layers 906, 909, 910, 911, 913, 915, and 916 are provided, and these insulating layers function as interlayer insulating films. In addition, insulating layers 909, 911, and 915 function as barrier films. Conductive layers 912 and 914 function as plugs, electrodes, or wiring.

[0343] One of the sources or drains of the Si transistor 900 (in this case, the low-resistance region 904) is connected to the memory cell 100A via a conductive layer.

[0344] A portion of the conductive layer 43a is provided so as to be embedded in the insulating layer 916. The conductive layer 43a is connected to the Si transistor 900 via the conductive layer 914.

[0345] The insulating layers 803 and 804 are provided on the memory cell 100A. The insulating layers such as insulating layer 803 and insulating layer 804 can use the materials and configurations described in the [insulating layer] section of Embodiment 1. In particular, for insulating layers such as insulating layer 803, it is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, insulating layer materials that have the function of capturing or fixing hydrogen, and insulating layer materials that have barrier properties against hydrogen. Furthermore, for insulating layers such as insulating layer 804, it is preferable to use insulating materials with a lower dielectric constant compared to high-k materials. By using these insulating films, the diffusion of hydrogen into the semiconductor layer 18 of the transistor 10A can be suppressed. In addition, the transistor 10A can be made highly reliable.

[0346] The conductive layers 805a, 805b, and 805c are provided so as to be embedded in the insulating layers 803 and 804. The conductive layers such as conductive layers 805a, 805b, and 805c can be formed as single layers or laminates using the materials and configuration described in the [Conductive Layer] section of Embodiment 1. For example, the conductive layer 805 can be a two-layer structure using tungsten on titanium nitride. Because a highly conductive material such as tungsten can be used, the wiring resistance of the conductive layer 805 can be reduced. The conductive layer 805 can also be a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Alternatively, the conductive layer 805 can be a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer.

[0347] The conductive layer 802a is provided to connect the conductive layer 805a and the conductive layer 43a via the conductive layer 801. The conductive layer 43a can be manufactured using the same process as the conductive layer 43.

[0348] The conductive layer 802b is provided to connect the conductive layer 805b and the conductive layer 12a. Alternatively, if, for example, a conductive oxide is used for conductive layer 12a_3 and a lower-resistance material is used for conductive layers 12a_2 and 12a_1, an opening may be provided in conductive layer 12a_3 so that conductive layer 802b is in contact with conductive layer 12a_2. This configuration allows conductive layer 802b to form good contact with conductive layer 12a_2. The conductive layer 12a can be manufactured using the same process as conductive layer 12.

[0349] The conductive layer 802c is provided to connect the conductive layer 805c and the conductive layer 20.

[0350] The conductive layers 805a, 805b, 805c, 802a, 802b, 802c, and 801 function as a plug or wiring.

[0351] The conductive layers 805a, 805b, and 805c may be connected to each other. The conductive layers 12a and 12 may also be connected to each other. Furthermore, the conductive layers 43a and 43 may also be connected to each other.

[0352] <Example of Memory Device Configuration 2> A memory device according to one aspect of the present invention will be described with reference to Figures 25A to 27. The memory device according to one aspect of the present invention has a memory cell. The memory cell has two transistors. The transistors described in Embodiment 1 can be used. A detailed description of the transistors will be omitted as it can be referenced from the description of Embodiment 1.

[0353] The configuration of a semiconductor device having a memory cell 101A will be explained using Figures 25A and 25B. Figure 25A is a plan view of a memory device having a memory cell 101A. Figure 25B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 25A. Figure 25C is a cross-sectional view between the dashed lines C1 and C2 shown in Figure 25B.

[0354] The memory device shown in Figures 25A and 25B has a memory cell 101A on a substrate (not shown). The memory cell 101A has at least a transistor 50A and a transistor 10A on the transistor 50A. The transistor 50A can also be the transistor described in Embodiment 1.

[0355] The memory device shown in Figures 25A to 25C has an insulating layer 51 on a substrate (not shown), and a transistor 50A on the insulating layer 51. The transistor 50A has at least a conductive layer 52 (conductive layer 52_1, conductive layer 52_2, conductive layer 52_3), a conductive layer 57 (conductive layer 57_1, conductive layer 57_2), a conductive layer 12 (conductive layer 12_1, conductive layer 12_2, conductive layer 12_3), a semiconductor layer 58, and an insulating layer 59. Part or all of the conductive layer 52 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 57 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 12 functions as a gate electrode. Part or all of the insulating layer 59 functions as a gate insulating film.

[0356] The insulating layer 51 is provided on a substrate (not shown). The insulating layer 51 functions as an underlay insulating film, an etching stop film, and the like.

[0357] The conductive layer 52 (conductive layer 52_1, conductive layer 52_2, conductive layer 52_3) is provided on the insulating layer 51. The conductive layer 52 may be in an island shape, or it may extend in the X direction, the Y direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions). In the example shown, the conductive layer 52 consists of three layers: conductive layer 52_1, conductive layer 52_2, and conductive layer 52_3, but it can also be formed as a single layer, two layers, or a laminate of four or more layers.

[0358] The insulating layer 53 is provided on the conductive layer 52, covering the conductive layer 52. The insulating layer 54 is provided on the insulating layer 53, and it is desirable that its upper surface is flat. Alternatively, the insulating layer 54 may be provided without the insulating layer 53.

[0359] The insulating layer 55 is provided on insulating layers 53 and 54. The insulating layer 56 is provided on insulating layer 55.

[0360] The conductive layer 57 (conductive layer 57_1, conductive layer 57_2) is provided on the insulating layer 56. The conductive layer 57 may extend in the X direction, the Y direction, or in a direction oblique to the X and Y directions (i.e., a direction intersecting both the X and Y directions).

[0361] The opening 92 is provided in the insulating layer 53, insulating layer 54, insulating layer 55, insulating layer 56 and conductive layer 57, and reaches the conductive layer 52. The conductive layer 52 has a recess in the region that overlaps with the opening 92.

[0362] Although the illustration shows the opening 92 as circular in plan view, it may also be elliptical, polygonal, or rectangular. Furthermore, the shape and size in plan view may differ for each of the insulating layers 53, 54, 55, 56, and 57. For example, the opening diameter of the opening 92 in insulating layer 53 may be smaller than the opening diameter of the opening 92 in insulating layer 56. At least a portion of the side wall of the opening 92 may be tapered.

[0363] The semiconductor layer 58 is provided on the conductive layer 57 and is provided so as to cover the side walls and bottom of the opening 92. The semiconductor layer 58 has a region in contact with the conductive layer 57 and a region in contact with the conductive layer 52. Furthermore, at the opening 92, the semiconductor layer 58 has a region in contact with the insulating layer 56, a region in contact with the insulating layer 55, a region in contact with the insulating layer 54, and a region in contact with the insulating layer 53. In addition, the semiconductor layer 58 has a region in contact with the conductive layer 52 in a recess provided in the conductive layer 52.

[0364] The insulating layer 59 is provided on the semiconductor layer 58 so as to cover the semiconductor layer 58. The insulating layer 59 has a region that is in contact with the semiconductor layer 58 and a region that is located inside the opening 92.

[0365] The conductive layer 12 is provided on the insulating layer 59 and has a region facing the semiconductor layer 58 through the insulating layer 59. Also, the conductive layer 12 has a region facing the semiconductor layer 18 through the insulating layer 59 inside the opening 92. The conductive layer 12 is preferably made up of two layers, the conductive layer 12_1 and the conductive layer 12_2, but it can also be formed as a single layer or a stack of three or more layers. The conductive layer 12 may have an island shape, or may extend in the X direction, the Y direction, or in a direction oblique to the X direction and the Y direction (that is, a direction intersecting both the X direction and the Y direction).

[0366] As shown in FIG. 25B, the transistor 10A is provided so as to overlap the transistor 50A. Also, the opening 90 in which a part of the structure of the transistor 10A is provided has a region overlapping with the opening 92 in which a part of the structure of the transistor 50A is provided. In particular, since the conductive layer 12 functions as one of the source electrode and the drain electrode of the transistor 10A and as the gate electrode of the transistor 50A, the transistor 10A and the transistor 50A share a part of their structures. By adopting such a configuration, the process can be reduced, thus improving productivity. Also, in a plan view, the transistors 10A and 50A can be provided without significantly increasing the occupied area. As a result, the occupied area of the memory cell 101A can be reduced, so that the memory cells 101A can be arranged at a high density and the storage capacity of the storage device can be increased. In other words, the storage device can be highly integrated.

[0367] The transistors included in the memory cell 101A are not limited to the combination of the transistor 10A and the transistor 50A, and one or more types of each transistor exemplified in Embodiment 1 can be used.

[0368] In the memory cell 101A shown in FIG. 25B, since the capacitance generated between the conductive layer 12 and the conductive layer 57 can be used, data can be retained without separately forming a capacitive element.

[0369] Fig. 26 shows a cross-sectional configuration example of a memory device in which a layer having the memory cell 101A shown in Figs. 25A and 25C is laminated on a layer provided with a drive circuit including a sense amplifier.

[0370] In Fig. 26, the memory cell 101A (transistors 10A and 50A) is provided above the Si transistor 900. The Si transistor 900 is one of the transistors included in the drive circuit including the sense amplifier.

[0371] One of the source or drain of the Si transistor 900 (here, the low-resistance region 904) is connected to the memory cell 101A via a conductive layer.

[0372] The conductive layer 810 is provided so as to be embedded in the insulating layer 916. The conductive layer 52a is connected to the Si transistor 900 via the conductive layer 810 and the conductive layer 914.

[0373] The insulating layer 813 and the insulating layer 814 are provided on the memory cell 101A.

[0374] The conductive layers 815a, 815b, and 815c are provided so as to be embedded in the insulating layers 813 and 814.

[0375] The conductive layer 812a is provided to connect the conductive layer 815a and the conductive layer 52a via the conductive layer 811. Also, for example, when a material with lower resistance than this is used for the conductive layers 52a_2 and 52a_1 using a conductive oxide for the conductive layer 52a_3, an opening may be provided in the conductive layer 52a_3 so that the conductive layer 812a contacts the conductive layer 52a_2. By adopting such a configuration, the conductive layer 812a can form a good contact with the conductive layer 52a_2. Note that the conductive layer 52a can be fabricated in the same process as the conductive layer 52.

[0376] The conductive layer 812b is provided to connect the conductive layer 815b and the conductive layer 57a. For example, if a conductive oxide is used for conductive layer 57a_2 and a material with lower resistance is used for conductive layer 57a_1, openings may be provided in the semiconductor layer 58a and conductive layer 57a_2 so that the conductive layer 812b is in contact with the conductive layer 57a_1. With such a configuration, the conductive layer 812b can form good contact with the conductive layer 57a_1.

[0377] The conductive layer 812c is provided to connect the conductive layer 815c and the conductive layer 20.

[0378] Figure 27 shows an example of the wiring configuration in Figure 26. By using a material with a low dielectric constant for the insulating layer 55 (insulating layer 15), parasitic capacitance between the wiring positioned above and below the insulating layer 55 (insulating layer 15) can be reduced. For example, parasitic capacitance between the wiring between the conductive layer 52a located below the insulating layer 55 and the conductive layer 57a located above the insulating layer 55 can be reduced. Also, for example, parasitic capacitance between the wiring between the conductive layer 12a located below the insulating layer 15 and the conductive layer 17a located above the insulating layer 15 can be reduced. Alternatively, stress caused by the insulating film can be reduced.

[0379] Furthermore, since the conductive layer 12a and the conductive layer 57a are opposite each other via the insulating layer 59, they can also be used as a capacitive element. Similarly, since the conductive layer 20a and the conductive layer 17a are opposite each other via the insulating layer 19, they can also be used as a capacitive element. A semiconductor layer 58a may be laminated on the conductive layer 57a. Also, a semiconductor layer 18a may be laminated on the conductive layer 17a.

[0380] The conductive layer 812d is provided to connect the conductive layer 815d and the conductive layer 17a. For example, if a conductive oxide is used for the conductive layer 17a_2 and a material with lower resistance is used for the conductive layer 17a_1, openings may be provided in the semiconductor layer 18a and the conductive layer 17a_2 so that the conductive layer 812d is in contact with the conductive layer 17a_1. With such a configuration, the conductive layer 812d can form good contact with the conductive layer 17a_1.

[0381] Furthermore, the conductive layer 812e is provided to connect the conductive layer 815e and the conductive layer 12a. Also, for example, if a conductive oxide is used for conductive layer 12a_3 and a material with lower resistance is used for conductive layers 12a_2 and 12a_1, an opening may be provided in conductive layer 12a_3 so that conductive layer 812e is in contact with conductive layer 12a_2. With such a configuration, conductive layer 812e can form good contact with conductive layer 12a_2. Note that conductive layer 12a can be manufactured using the same process as conductive layer 12.

[0382] The conductive layers 815a, 815b, 815c, 815d, 815e, 812a, 812b, 812c, 812d, 812e, 810, and 811 function as a plug or wiring.

[0383] The conductive layers 815a, 815b, 815c, 815d, and 815e may be connected to each other. Furthermore, the conductive layers 52 and 52b may be connected to each other.

[0384] The semiconductor layer 58 can use the material and configuration described in the [semiconductor layer] of Embodiment 1.

[0385] For insulating layers such as insulating layer 51, insulating layer 53, insulating layer 54, insulating layer 55, insulating layer 56, insulating layer 59, insulating layer 813, and insulating layer 814, the materials and configurations described in the [Insulating Layer] section of Embodiment 1 can be used. Furthermore, for insulating layer 59, the materials and configurations described in the [Gate Insulating Layer] section of Embodiment 1 can be used. In particular, for insulating layers such as insulating layer 51, insulating layer 53, insulating layer 54, insulating layer 56, and insulating layer 813, it is preferable to use insulating layer materials that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen; insulating layer materials that have the function of capturing or fixing hydrogen; and insulating layer materials that have barrier properties against hydrogen. Furthermore, for insulating layers such as insulating layer 55 and insulating layer 814, it is preferable to use insulating materials with a lower dielectric constant compared to high-k materials. By using these insulating films, the diffusion of hydrogen into the semiconductor layer 18 of transistor 10A and the semiconductor layer 58 of transistor 50A can be suppressed. In addition, transistors 10A and 50A can be made highly reliable.

[0386] The conductive layers, such as conductive layer 52, conductive layer 57, conductive layer 810, conductive layer 811, conductive layer 812a, conductive layer 812b, conductive layer 812c, conductive layer 812d, conductive layer 812e, conductive layer 815a, conductive layer 815b, conductive layer 815c, conductive layer 815d, and conductive layer 815e, can be formed as a single layer or in a laminate using the materials and configuration described in the [Conductive Layer] of Embodiment 1.

[0387] For example, the conductive layer 52 can be titanium nitride deposited by metal CVD as conductive layer 52_1, tungsten deposited by metal CVD as conductive layer 52_2, and a conductive oxide deposited by sputtering as conductive layer 52_3. Alternatively, for example, the conductive layer 52 can be titanium nitride deposited by sputtering as conductive layer 52_1, tungsten deposited by sputtering as conductive layer 52_2, and a conductive oxide deposited by sputtering as conductive layer 52_3. The conductive oxide can be ITO, ITSO, etc.

[0388] For example, the conductive layer 57 can be made of tungsten deposited by sputtering as conductive layer 57_1, or a conductive oxide deposited by sputtering as conductive layer 57_2. The conductive oxide can be ITO, ITSO, or the like.

[0389] The conductive layers 812, 810, and 811 can, for example, be a two-layer structure using tungsten on titanium nitride. Because highly conductive materials such as tungsten can be used, the wiring resistance of the conductive layers 812, 810, and 811 can be reduced.

[0390] The conductive layer 815 can be, for example, a two-layer structure using tungsten on titanium nitride. Because highly conductive materials such as tungsten can be used, the wiring resistance of the conductive layer 815 can be reduced. Alternatively, the conductive layer 815 can be a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Alternatively, the conductive layer 815 can be a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer. Alternatively, the conductive layer 815 can be a four-layer structure of tantalum, tantalum nitride, titanium nitride, and tungsten from the bottom layer.

[0391] The storage device shown in Figure 26 can use memory cell 102A or memory cell 103A, as described below, instead of memory cell 101A.

[0392] Figure 28 shows an example of a memory cell 102A. Memory cell 102A has a configuration in which a capacitive element 60A is added to memory cell 101A. Memory cell 102A has a transistor 50B, a capacitive element 60A on transistor 50B, and a transistor 10A on capacitive element 60A. Note that the transistors in memory cell 102A are not limited to transistors 50B and 10A, and one or more of the transistors exemplified in Embodiment 1 can be used.

[0393] As shown in Figure 28, transistor 10A is provided so as to overlap with capacitive element 60A and transistor 50B. Furthermore, the opening 90, through which part of the structure of transistor 10A is provided, has an overlapping region with the opening 93, through which part of the structure of capacitive element 60A is provided, and the opening 92, through which part of the structure of transistor 50B is provided. In particular, since the conductive layer 12 functions as one of the pair of electrodes of capacitive element 60A and as one of the source electrode and drain electrode of transistor 10A, capacitive element 60A and transistor 10A share part of their structure. This configuration reduces the number of processes, thereby improving productivity. In addition, in a plan view, transistor 10A, capacitive element 60A, and transistor 50B can be provided without significantly increasing the occupied area. As a result, the occupied area of ​​memory cell 102A can be reduced, allowing for a high-density arrangement of memory cells 102A and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0394] The transistor 50B of the memory cell 102A has at least a conductive layer 52 (conductive layer 52_1, conductive layer 52_2, conductive layer 52_3), a conductive layer 57 (conductive layer 57_1, conductive layer 57_2), a conductive layer 60 (conductive layer 60_1, conductive layer 60_2), a semiconductor layer 58, and an insulating layer 59. Part or all of the conductive layer 52 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 57 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 60 functions as a gate electrode. Part or all of the insulating layer 59 functions as a gate insulating film.

[0395] The capacitive element 60A has at least a conductive layer 63, a conductive layer 12, and an insulating layer 66. Part or all of the conductive layer 63 functions as one of a pair of electrodes of the capacitive element. Part or all of the conductive layer 12 functions as the other of a pair of electrodes of the capacitive element. Part or all of the insulating layer 66 functions as the dielectric of the capacitive element.

[0396] The insulating layer 61 and insulating layer 62 are provided on the conductive layer 60. The upper surface of the insulating layer 62 is preferably flat. The conductive layer 63 and insulating layer 64 are provided on the insulating layer 62. The insulating layer 65 is provided on the conductive layer 63 and insulating layer 64. The opening 93 is provided in the insulating layer 61, insulating layer 62, conductive layer 63 and insulating layer 65 and reaches the conductive layer 60. The insulating layer 66 is in contact with the side surface of the insulating layer 61, the side surface of the insulating layer 62, the side surface of the conductive layer 63 and the side surface of the insulating layer 65 at the opening 93. The insulating layer 66 is also in contact with the conductive layer 60 at the bottom of the opening 93. At least a portion of the conductive layer 12 is located in the opening 93 and is in contact with the conductive layer 60 at the bottom of the opening 93. The conductive layer 12 is preferably provided so as to fill the opening 93. The upper surface of the conductive layer 60_2 is located outside the opening 93. In this embodiment, an example is shown in which the opening 93 is circular in plan view, but the present invention is not limited to this. The shapes applicable to the opening 93 are the same as the shapes applicable to the opening 90 described above.

[0397] Since at least a portion of the capacitive element 60A can be placed inside the opening 93, the capacitance per unit area in a plan view can be increased.

[0398] Figure 29 shows an example of a memory cell 103A. Memory cell 103A has a configuration in which a transistor 70A is added to memory cell 102A. Memory cell 103A has a transistor 70A, a transistor 50B on transistor 70A, a capacitive element 60A on transistor 50B, and a transistor 10A on capacitive element 60A. Note that the transistors in memory cell 103A are not limited to transistors 70A, 50B, and 10A, and one or more of the transistors exemplified in Embodiment 1 can be used.

[0399] As shown in Figure 29, transistor 10A is provided so as to overlap with the capacitive element 60A, transistor 50B, and transistor 70A. Furthermore, the opening 90, through which part of the structure of transistor 10A is provided, has an overlapping region with the opening 93, through which part of the structure of the capacitive element 60A is provided, the opening 92, through which part of the structure of transistor 50B is provided, and the opening 94, through which part of the structure of transistor 70A is provided. In particular, the conductive layer 12 functions as one of the pair of electrodes of the capacitive element 60A and as one of the source electrode and drain electrode of transistor 10A, so the capacitive element 60A and transistor 10A share part of their structure. Similarly, the conductive layer 52 functions as one of the source electrode and drain electrode of transistor 50B and as the gate electrode of transistor 70A, so transistor 50B and transistor 70A share part of their structure. This configuration reduces the number of processes, thereby improving productivity. Moreover, in a plan view, transistor 10A, capacitive element 60A, transistor 50B, and transistor 70A can be provided without significantly increasing the occupied area. This reduces the area occupied by the memory cell 103A, allowing for a higher density arrangement of the memory cells 103A and thus increasing the storage capacity of the storage device. In other words, it enables high integration of the storage device.

[0400] The transistor 70A of the memory cell 103A has at least a conductive layer 72 (conductive layer 72_1, conductive layer 72_2, conductive layer 72_3), a conductive layer 77 (conductive layer 77_1, conductive layer 77_2), a conductive layer 52 (conductive layer 52_1, conductive layer 52_2, conductive layer 52_3), a semiconductor layer 78, and an insulating layer 79. Part or all of the conductive layer 72 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 77 functions as either a source electrode or a drain electrode. Part or all of the conductive layer 52 functions as a gate electrode. Part or all of the insulating layer 79 functions as a gate insulating film.

[0401] Since the description of the transistor 70A can refer to the description of the transistor 50A in the present embodiment, a detailed description thereof will be omitted. For example, the conductive layer 72 can be read as the conductive layer 52, the conductive layer 77 can be read as the conductive layer 57, the semiconductor layer 78 can be read as the semiconductor layer 58, and the insulating layer 79 can be read as the insulating layer 59, etc., and thus the description of the transistor 50A can be referred to.

[0402] For insulating layers such as the insulating layer 61, the insulating layer 62, the insulating layer 64, the insulating layer 65, the insulating layer 66, the insulating layer 71, the insulating layer 73, the insulating layer 74, the insulating layer 75, the insulating layer 76, and the insulating layer 79, the materials and configurations described in [Insulating Layer] of Embodiment 1 can be used. In particular, for the insulating layer 61, the insulating layer 62, the insulating layer 65, the insulating layer 73, the insulating layer 74, and the insulating layer 76, materials of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, materials of insulating layers having a function of capturing or fixing hydrogen, and materials of insulating layers having a barrier property against hydrogen are preferably used. By using these insulating layers, the diffusion of hydrogen into the semiconductor layer 18 of the transistor 10A disposed on the capacitor element 60A can be suppressed. Or, the diffusion of hydrogen into the semiconductor layer 58 of the transistor 50B and the semiconductor layer 78 of the transistor 70A disposed under the capacitor element 60A can be suppressed. Also, the transistors 10A, 50B, and 70A disposed above and below the capacitor element 60A can be made to have high reliability.

[0403] Further, for the insulating layer 79, the materials and configurations described in [Gate Insulating Layer] of Embodiment 1 can be used.

[0404] The insulating layer, such as the insulating layer 66, can be formed in a single layer or laminate using the materials and configuration described in the [insulating layer] of Embodiment 1. It is preferable to use a material with a high dielectric constant (high-k) and an insulating material with high dielectric strength or that suppresses leakage current for the insulating layer 66. For example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. By using a high-k material as the insulating layer 66, the film thickness of the insulating layer 66 can be increased to a degree that suppresses leakage current, and the capacitance of the capacitive element 40A can be sufficiently secured.

[0405] Furthermore, the insulating layer, such as the insulating layer 66, may be made of a material capable of ferroelectricity. For example, a metal oxide containing one or both of hafnium and zirconium can be used as the material capable of ferroelectricity. By using a ferroelectric material for the dielectric of the capacitive element 60A, the memory device shown in this embodiment can function as a ferroelectric memory.

[0406] The conductive layers, such as conductive layer 60, conductive layer 63, conductive layer 72, and conductive layer 77, can be formed as single layers or laminates using the materials and configuration described in [Conductive Layer] of Embodiment 1. For example, conductive layer 60 can have a two-layer structure using titanium nitride for conductive layer 60_1 and tungsten for conductive layer 60_2. Conductive layer 63 can also be made of tungsten. Because highly conductive materials such as tungsten can be used, the wiring resistance of conductive layer 60 and conductive layer 63 can be reduced.

[0407] The semiconductor layer 78 can use the material and configuration described in the [semiconductor layer] of Embodiment 1.

[0408] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0409] (Embodiment 4) In this embodiment, a semiconductor device 8000 according to one aspect of the present invention will be described. The semiconductor device 8000 can function as a storage device.

[0410] Figure 30 shows a block diagram illustrating an example configuration of the semiconductor device 8000. The semiconductor device 8000 shown in Figure 30 includes a drive circuit 8110 and a memory array 8120. The memory array 8120 has one or more memory cells 8130. Figure 30 shows an example in which the memory array 8120 has multiple memory cells 8130 arranged in a matrix.

[0411] The memory cell 8130 can be a memory device as described in Embodiment 3.

[0412] The drive circuit 8110 includes a PSW 8001 (power switch), a PSW 8002, and a peripheral circuit 8003. The peripheral circuit 8003 includes a peripheral circuit 8004, a control circuit 8005, and a voltage generation circuit 8006.

[0413] In a semiconductor device, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0414] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 8005.

[0415] The control circuit 8005 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 8000. For example, the control circuit 8005 performs a logic operation on signals CE, GW, and BW to determine the operating mode of the semiconductor device 8000 (e.g., write operation, read operation). Alternatively, the control circuit 8005 generates control signals for the peripheral circuit 8004 so that this operating mode is executed.

[0416] The voltage generation circuit 8006 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 8006. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 8006, and the voltage generation circuit 8006 generates a negative voltage.

[0417] The peripheral circuit 8004 is a circuit for writing and reading data to and from the memory cell 8130. The peripheral circuit 8004 includes a row decoder 8007, a column decoder 8008, a row driver 8009, a column driver 8010, a sense amplifier 8011, an input circuit 8012, and an output circuit 8013.

[0418] The row decoder 8007 and column decoder 8008 have the function of decoding the ADDR signal. The row decoder 8007 is a circuit for specifying the row to access, and the column decoder 8008 is a circuit for specifying the column to access. The row driver 8009 has the function of selecting the row specified by the row decoder 8007. The column driver 8010 has the function of writing data to the memory cell 8130, reading data from the memory cell 8130, and holding the read data.

[0419] The input circuit 8012 has the function of holding the signal WDA. The data held by the input circuit 8012 is output to the column driver 8010. The output data of the input circuit 8012 is the data (Din) to be written to the memory cell 8130. The data (Dout) read by the column driver 8010 from the memory cell 8130 is output to the output circuit 8013. The output circuit 8013 has the function of holding Dout. The output circuit 8013 also has the function of outputting Dout to the outside of the semiconductor device 8000. The data output from the output circuit 8013 is the signal RDA.

[0420] PSW8001 provides V to peripheral circuit 8003 ＤＤ It has the function of controlling the supply. PSW8002 connects to the line driver 8009. ＨＭ It has a function to control the supply. Here, the high power supply potential of semiconductor device 8000 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW8001 is controlled by signal PON1, and the on / off state of PSW8002 is controlled by signal PON2. In Figure 30, in peripheral circuit 8003, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0421] Using Figures 31A to 31H, other examples of memory cell configurations applicable to the memory cell 8130 will be described.

[0422] [DOSRAM] Figure 31A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification and elsewhere, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 8131 has a transistor M1 and a capacitive element CA.

[0423] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0424] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0425] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0426] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0427] Furthermore, the memory cell that can be used in memory cell 8130 is not limited to memory cell 8131, and the circuit configuration can be changed. For example, the memory cell 8132 can be configured as shown in Figure 31B. Memory cell 8132 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0428] In the memory cell 8132, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0429] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8131 and 8132.

[0430] [NOSRAM] Figure 31C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 8133 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0431] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0432] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0433] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0434] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0435] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 31D. Memory cell 8134 is configured such that the wiring WBL and wiring RBL of memory cell 8133 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 8134 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0436] The memory cell 8135 shown in Figure 31E is an example where the capacitive element CB and wiring CAL in memory cell 8133 are omitted. Similarly, the memory cell 8136 shown in Figure 31F is an example where the capacitive element CB and wiring CAL in memory cell 8134 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0437] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

[0438] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. Furthermore, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8133, 8134, 8135, and 8136.

[0439] Memory cells 8133, 8134, 8135, and 8136, which use an OS transistor as transistor M2, represent one embodiment of NOSRAM.

[0440] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0441] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0442] Figure 31G also shows a gain cell type memory cell 8137 with three transistors and one capacitance element. The memory cell 8137 has transistors M4 to M6 and a capacitance element CC.

[0443] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0444] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0445] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and the first terminal of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0446] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0447] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0448] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0449] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0450] [OS-SRAM] Figure 31H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 8138 shown in Figure 31H is a memory cell of a backup-capable SRAM.

[0451] The memory cell 8138 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0452] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0453] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0454] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0455] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0456] Wires BIL and BILB function as bit lines, wire WOL functions as a word line, and wire BRL controls the on and off states of transistors M9 and M10.

[0457] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0458] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0459] Incidentally, since the memory cell 8138 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0460] Data is read by first precharging wiring BIL and wiring BILB to a predetermined potential, then applying a high-level potential to wiring WOL and wiring BRL, thereby refreshing the potential of the first terminal of capacitive element CD1 by the inverter loop of memory cell 8138 and outputting it to wiring BILB. Similarly, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 8138 and outputting it to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively, so the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0461] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether.

[0462] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0463] Figures 32A and 32C show perspective views of the semiconductor device 8200A. The semiconductor device 8200A has a layer 8220 on which memory arrays are provided on the arithmetic unit 8210. Memory arrays 8120L1, 8120L2, and 8120L3 are provided on layer 8220. The arithmetic unit 8210 and each memory array have overlapping regions. To make the configuration of the semiconductor device 8200A easier to understand, Figure 32B shows the arithmetic unit 8210 and layer 8220 separately. The arithmetic unit 8210 can be, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc.

[0464] By stacking the layer 8220 containing the memory array and the arithmetic unit 8210, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0465] As a method for stacking the layer 8220 having a memory array and the arithmetic unit 8210, one may use a method in which the layer 8220 having a memory array is directly stacked on the arithmetic unit 8210 (also called monolithic stacking), or one may use a method in which the arithmetic unit 8210 and the layer 8220 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0466] Here, the arithmetic unit 8210 does not have a cache, and the memory arrays 8120L1, 8120L2, and 8120L3 provided in layer 8220 can each be used as caches. In this case, for example, memory array 8120L1 can be used as an L1 cache (also called a level 1 cache), memory array 8120L2 can be used as an L2 cache (also called a level 2 cache), and memory array 8120L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 8120L3 has the largest capacity and the lowest access frequency. Also, memory array 8120L1 has the smallest capacity and the highest access frequency.

[0467] Furthermore, when the cache provided in the arithmetic unit 8210 is used as the L1 cache, each memory array provided in layer 8220 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0468] Furthermore, as shown in Figure 32B, drive circuits 8110L1, 8110L2, and 8110L3 are provided. Drive circuit 8110L1 is connected to memory array 8120L1 via connecting electrode 8230L1. Similarly, drive circuit 8110L2 is connected to memory array 8120L2 via connecting electrode 8230L2, and drive circuit 8110L3 is connected to memory array 8120L3 via connecting electrode 8230L3.

[0469] Note that while this example shows three memory arrays functioning as a cache, it can also be one, two, or four or more.

[0470] When the memory array 8120L1 is used as a cache, the drive circuit 8110L1 may function as part of the cache interface, or the drive circuit 8110L1 may be configured to be connected to the cache interface. Similarly, the drive circuits 8110L2 and 8110L3 may also function as part of the cache interface, or be configured to be connected to it.

[0471] In Figures 32A and 32B, an example is shown in which one layer 8220 on which a memory array is provided is placed on the arithmetic unit 8210. However, as shown in Figure 32C, two or more layers 8220 on which memory arrays are provided may be placed.

[0472] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0473] (Embodiment 5) A semiconductor device according to one aspect of the present invention will be described. Figure 33A is a schematic perspective view of a semiconductor device 8310 according to one aspect of the present invention. Figure 33B is a schematic perspective view of a part of the semiconductor device 8310. Figure 34 is a schematic perspective view illustrating the configuration of the semiconductor device 8310.

[0474] In Figures 33A, 33B, and 34, the semiconductor device 8310 has an element layer 8370 below an element layer 8320 which includes a substrate 8322 that is a semiconductor substrate, and a support substrate 8340 above the element layer 8320 via an insulating layer 8341. The element layer 8320 has a plurality of transistors 8321 that constitute a functional circuit 8311. The element layer 8370 has a plurality of transistors 8371 that constitute a switch circuit 8315. The transistors 8371 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 8372 that functions as a power line.

[0475] The transistor exemplified in Embodiment 1 can be applied to transistor 8371.

[0476] The transistor 8321 in element layer 8320 is formed on the front side (also called the "first side") of the substrate 8322. The element layer 8370 is formed on the back side (the side opposite to the front side, also called the "second side") of the substrate 8322. Therefore, the transistor 8371 in element layer 8370 is formed on the second side of the substrate 8322.

[0477] In Figure 34, the functional circuit 8311 is exemplified by a CPU 8312, a GPU 8313, and a memory 8314.

[0478] Furthermore, the functional circuit 8311 is not limited to the CPU 8312, GPU 8313, and memory 8314, and one or more of these can be used. It is also possible to include circuits with other functions.

[0479] To improve the operating speed, mounting density, and power consumption of the semiconductor device 8310, the functional circuit 8311 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 8315 can control the supply of externally supplied voltage to each circuit of the functional circuit 8311, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0480] Furthermore, the transistors constituting the switch circuit 8315 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 8321 and 8371 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 8321 and 8371.

[0481] Furthermore, miniaturization and thinning are required for the functional circuit 8311. Therefore, if the switch circuit 8315 is constructed using the same process node as the functional circuit 8311, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, and sufficient power cannot be supplied to the functional circuit 8311. In addition, if the wiring resistance increases due to miniaturization, uneven power potential is likely to occur within the functional circuit 8311 due to voltage drop. In order to stably supply power to the functional circuit 8311, it is preferable that the wiring constituting the switch circuit 8315 has a lower wiring resistance than the wiring constituting the functional circuit 8311. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 8311. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 8311 and the switch circuit 8315.

[0482] In a semiconductor device 8310 according to one aspect of the present invention, by providing the functional circuit 8311 and the switch circuit 8315 on different element layers, different improvement measures can be implemented in the functional circuit 8311 and the switch circuit 8315. Furthermore, the functional circuit 8311 and the switch circuit 8315 can be formed at different process nodes.

[0483] In one aspect of the present invention, a plurality of conductive layers 8372 that function as power lines and a switch circuit 8315 can be arranged below the functional circuit 8311, thereby reducing the occupied area of ​​the semiconductor device 8310. Furthermore, it is preferable that the element layer 8370, which is superimposed on the element layer 8320, be formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 8371 included in the element layer 8370 is preferably a thin-film transistor.

[0484] At least a portion of the multiple conductive layers 8372 of the element layer 8370 can function as power lines. Furthermore, if the element layer 8370 has a clock signal generation circuit, at least a portion of the multiple conductive layers 8372 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 8311 of the element layer 8320 via at least a portion of the multiple conductive layers 8372.

[0485] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 8311 and a die containing the switch circuit 8315 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving alignment accuracy is difficult because the two are bonded mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 8311.

[0486] According to one aspect of the present invention, an element layer 8370 including a switch circuit 8315 is formed on the back side of the substrate 8322 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 8310 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0487] By forming the element layer 8370 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 8311 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 8311. In addition, in the semiconductor device 8310 according to one aspect of the present invention, since the connection distance between the switch circuit 8315 and the functional circuit 8311 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0488] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0489] (Embodiment 6) This embodiment describes an example of the configuration of a display device to which a semiconductor device according to one aspect of the present invention can be applied.

[0490] Since a semiconductor device according to one aspect of the present invention can be made extremely small, a display device to which a semiconductor device according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, a display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR devices such as head-mounted displays and AR devices such as glasses.

[0491] [Display Module] Figure 35A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590. Note that the display panel of the display module 580 is not limited to the display device 500A, but may be a display device 500B, a display device 500C, or a display device 500D, which will be described later.

[0492] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0493] Figure 35B shows a schematic perspective view illustrating the configuration of the substrate 591. On the substrate 591, a circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked. In addition, a terminal section 585 for connecting to the FPC 590 is provided in an area on the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586 composed of multiple wires.

[0494] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 35B. The pixel 584a has a light-emitting element 610R that emits red light, a light-emitting element 610G that emits green light, and a light-emitting element 610B that emits blue light.

[0495] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0496] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0497] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0498] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are stacked on top of the pixel section 584, thereby making the area ratio of the display section 581 to the area of ​​the substrate 591 extremely high. In other words, because one or both of the pixel circuit section 583 and the circuit section 582 are stacked on top of the pixel section 584, a display device with a narrow non-display area and a narrow bezel can be obtained. Furthermore, the pixel aperture ratio can be 40% or more and less than 100%, preferably 50% or more and 95%, more preferably 60% or more and 95%. In addition, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that pixels 584a are arranged in the display unit 581 with a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0499] Because such a display module 580 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0500] [Display device 500A] The display device 500A shown in Figure 36 has a substrate 531, a light-emitting element 610R, a light-emitting element 610G, a light-emitting element 610B, a capacitor 540, and a transistor 520.

[0501] Substrate 531 corresponds to substrate 591 in Figure 35A.

[0502] Transistor 520 can be any of the transistors described in Embodiment 1. Since the description of the transistors in Embodiment 1 is available, a detailed explanation is omitted.

[0503] An insulating layer 532 is provided on the substrate 531, and a transistor 520 is provided on the insulating layer 532. The insulating layer 532 functions as a barrier layer to prevent impurities from diffusing from the substrate 531 to the transistor 520. As the insulating layer 532, insulating films such as aluminum oxide film, hafnium oxide film, and silicon nitride film can be used.

[0504] The plug 574, which is electrically connected to either the source electrode or the drain electrode of the transistor 520, is provided so as to be embedded in the insulating layer 564.

[0505] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 has a conductive layer 541, a conductive layer 545, and an insulating layer 543 located between them. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as the dielectric of the capacitor 540.

[0506] The conductive layer 541 is provided on the insulating layer 564 and embedded in the insulating layer 554. The conductive layer 541 is electrically connected to either the source electrode or the drain electrode of the transistor 520 by a plug 574. The insulating layer 543 is provided covering the conductive layer 541. The conductive layer 545 is provided in the region that overlaps with the conductive layer 541 via the insulating layer 543.

[0507] An insulating layer 555a is provided covering the capacitance 540, an insulating layer 555b is provided on top of the insulating layer 555a, and an insulating layer 555c is provided on top of the insulating layer 555b.

[0508] Insulating layers 555a, 555b, and 555c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and silicon nitride films for insulating layer 555b. This allows insulating layer 555b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 555c is etched and a recess is formed, but the insulating layer 555c does not necessarily have to have a recess.

[0509] A light-emitting element 610R, a light-emitting element 610G, and a light-emitting element 610B are provided on the insulating layer 555c.

[0510] The light-emitting element 610R has a pixel electrode 611R, an organic layer 612R, a common layer 614, and a common electrode 613. The light-emitting element 610G has a pixel electrode 611G, an organic layer 612G, a common layer 614, and a common electrode 613. The light-emitting element 610B has a pixel electrode 611B, an organic layer 612B, a common layer 614, and a common electrode 613. The common layer 614 and the common electrode 613 are provided in common to the light-emitting elements 610R, 610G, and 610B.

[0511] The organic layer 612R of the light-emitting element 610R contains at least a luminescent organic compound that emits red light. The organic layer 612G of the light-emitting element 610G contains at least a luminescent organic compound that emits green light. The organic layer 612B of the light-emitting element 610B contains at least a luminescent organic compound that emits blue light. The organic layers 612R, 612G, and 612B can also be called EL layers and each contains at least a luminescent organic compound (luminescent layer).

[0512] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 612R, 612G, and 612B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0513] An insulating layer 625, a resin layer 626, and a layer 628 are provided in the region between adjacent light-emitting elements.

[0514] The pixel electrodes 611R, 611G, and 611B of the light-emitting element are electrically connected to either the source electrode or the drain electrode of the transistor 520 by plugs 556 embedded in insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in insulating layer 554, and plug 574. The height of the upper surface of insulating layer 555c and the height of the upper surface of plug 556 are equal or approximately equal. Various conductive materials can be used for the plugs.

[0515] Furthermore, protective layers 621 are provided on the light-emitting elements 610R, 610G, and 610B. The substrate 670 is bonded to the protective layer 621 by an adhesive layer 671.

[0516] There is no insulating layer covering the upper edge of the pixel electrode 611 between two adjacent pixel electrodes 611. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0517] [Display Device 500B] The following describes a display device with some configuration differences from the one described above. Note that parts common to the above will be referred to and may be omitted from the explanation.

[0518] The display device 500B shown in Figure 37 is an example in which a planar type transistor 720, in which a semiconductor layer is formed on a plane, and a vertical channel type transistor 520 are stacked.

[0519] The transistor 720 has a semiconductor layer 751, an insulating layer 753, a conductive layer 754, a pair of conductive layers 755, an insulating layer 756, and a conductive layer 757.

[0520] An insulating layer 752 is provided on the substrate 531. Similar to the insulating layer 532, the insulating layer 752 functions as a barrier layer that prevents impurities from diffusing from the substrate 531 to the transistor 520 and prevents oxygen from detaching from the semiconductor layer 751 to the insulating layer 752. As the insulating layer 752, for example, a film that is less permeable to hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0521] A conductive layer 757 is provided on an insulating layer 752, and an insulating layer 756 is provided covering the conductive layer 757. The conductive layer 757 functions as the first gate electrode of the transistor 720, and a portion of the insulating layer 756 functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, in at least the region of the insulating layer 756 that is in contact with the semiconductor layer 751. It is preferable that the upper surface of the insulating layer 756 is flattened.

[0522] The semiconductor layer 751 is provided on the insulating layer 756. Preferably, the semiconductor layer 751 has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor properties. A pair of conductive layers 755 are provided in contact with the semiconductor layer 751 and function as a source electrode and a drain electrode.

[0523] An insulating layer 758 and an insulating layer 750 are provided to cover the top and side surfaces of the pair of conductive layers 755, as well as the side surfaces of the semiconductor layer 751. The insulating layer 758 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 751 and to prevent oxygen from detaching from the semiconductor layer 751. An insulating film similar to that used for the insulating layer 752 can be used for the insulating layer 758.

[0524] The insulating layer 758 and the insulating layer 750 are provided with openings that reach the semiconductor layer 751. An insulating layer 753 that contacts the upper surface of the semiconductor layer 751 and a conductive layer 754 are embedded inside these openings. The conductive layer 754 functions as a second gate electrode, and the insulating layer 753 functions as a second gate insulating layer.

[0525] The upper surfaces of the conductive layer 754, the insulating layer 753, and the insulating layer 750 are flattened so that their heights are the same or approximately the same, and an insulating layer 759 is provided covering them. The insulating layer 759 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 520. An insulating film similar to that used for the insulating layer 752 can be used for the insulating layer 759.

[0526] The transistor 720 employs a configuration in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0527] [Display device 500C] The display device 500C shown in Figure 38 has a configuration in which a transistor 710 with a channel formed on a semiconductor substrate and a transistor 520 which is a vertical channel type transistor are stacked.

[0528] The transistor 710 is a transistor having a channel-forming region in the substrate 701. The substrate 701 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 710 comprises a portion of the substrate 701, a conductive layer 711, a low-resistance region 712, an insulating layer 713, and an insulating layer 714. The conductive layer 711 functions as a gate electrode. The insulating layer 713 is located between the substrate 701 and the conductive layer 711 and functions as a gate insulating layer. The low-resistance region 712 is a region of the substrate 701 doped with impurities and functions as either a source or a drain. The insulating layer 714 is provided covering the side surface of the conductive layer 711.

[0529] Furthermore, an element isolation layer 715 is provided between two adjacent transistors 710 so as to be embedded in the substrate 701.

[0530] [Display Device 500D] The display device 500D shown in Figure 39 is an example in which a transistor 710 with a channel formed on a semiconductor substrate, a planar type transistor 720 with a semiconductor layer formed on a plane, and a vertical channel type transistor 520 are stacked.

[0531] For example, transistor 710 can be used as a transistor that constitutes the drive circuit of the display device (either or both of the gate line drive circuit and the signal line drive circuit). Transistors 720 and 520 can be used as transistors that constitute the pixel circuit.

[0532] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0533] (Embodiment 7) In this embodiment, an example of the configuration of a display device applicable to a display device manufactured using a semiconductor device according to one aspect of the present invention will be described. The display device exemplified below can be applied to the pixel section 584 of Embodiment 6 described above.

[0534] One aspect of the present invention involves processing the EL layer into a fine pattern using photolithography without using a shadow mask such as a Fine Metal Mask (FMM). This makes it possible to realize a display device with high resolution and a large aperture ratio, which has been difficult to achieve until now. Furthermore, since the EL layer can be differentiated, it is possible to realize a display device with extremely vivid colors, high contrast, and high display quality. For example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

[0535] Furthermore, part or all of the EL layer can be physically separated. This suppresses leakage current between light-emitting elements via a common layer (also called a common layer) used between adjacent light-emitting elements. This prevents crosstalk caused by unintended light emission, enabling the realization of a display device with extremely high contrast. In particular, it enables the realization of a display device with high current efficiency at low brightness levels.

[0536] One aspect of the present invention is a display device that combines a white-emitting light-emitting element with a color filter. In this case, the same configuration of light-emitting elements can be applied to the light-emitting elements provided in pixels (sub-pixels) that emit light of different colors, and all layers can be made into a common layer. Furthermore, part or all of each EL layer may be separated by photolithography. This suppresses leakage current through the common layer, enabling the realization of a display device with high contrast. In particular, in an element having a tandem structure in which...

Claims

It comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The first insulating layer has an opening that reaches the first conductive layer, The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer of the opening, and a region in contact with the first conductive layer. The second insulating layer has, at the opening, a portion that contacts the semiconductor layer and a portion that contacts the side surface of the first insulating layer. In the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in a plan view. The third conductive layer faces the semiconductor layer at the opening, via the second insulating layer. The first conductive layer has a fourth conductive layer, The fourth conductive layer is a semiconductor device having a first region that overlaps with the first insulating layer and a second region that is in contact with the semiconductor layer. 　 It comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The first insulating layer has an opening that reaches the first conductive layer, In a plan view, the opening is located inside the first conductive layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer of the opening, and a region in contact with the first conductive layer. The second insulating layer has, at the opening, a portion that contacts the semiconductor layer and a portion that contacts the side surface of the first insulating layer. In the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in a plan view. The third conductive layer faces the semiconductor layer at the opening, via the second insulating layer. The first conductive layer has a fourth conductive layer, The fourth conductive layer is a semiconductor device having a first region that overlaps with the first insulating layer and a second region that is in contact with the semiconductor layer. 　 In claim 1 or claim 2, The first conductive layer has two or more conductive layers, including the fourth conductive layer. The second conductive layer has two or more conductive layers, including a fifth conductive layer. The fourth conductive layer and the fifth conductive layer are conductive oxides. The upper surface of the fourth conductive layer and the upper surface of the fifth conductive layer are in contact with the semiconductor layer, forming a semiconductor device. 　 In claim 1 or claim 2, A semiconductor device in which the thickness of the second region is thinner than the thickness of the first region. 　 It comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer. The first conductive layer is located on the third insulating layer, The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The first insulating layer has an opening that reaches the third insulating layer, The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the side surface of the first insulating layer of the opening, and a region in contact with the side surface of the first conductive layer of the opening. The second insulating layer has, at the opening, a portion in contact with the semiconductor layer, a portion in contact with the side surface of the first insulating layer, and a portion in contact with the third insulating layer. In the opening, one of a pair of opposing portions of the side surface of the first insulating layer is in contact with the semiconductor layer, and the other is in contact with the second insulating layer. The upper end of the side surface of the first insulating layer has a region that overlaps with the lower end of the second conductive layer in a plan view. The third conductive layer faces the semiconductor layer at the opening via the second insulating layer, in a semiconductor device. 　 In claim 1 or claim 5, The semiconductor device wherein the third conductive layer faces the side surface of the first conductive layer at the opening, via the second insulating layer. 　 In claim 5, The first conductive layer is a semiconductor device located in contact with the opening and on the outside of the opening. 　 In claim 5, A semiconductor device wherein, in the opening, the side surface of the first insulating layer and the side surface of the first conductive layer overlap in a plan view. 　 In any one of claims 1, 2, or 5, The aforementioned opening is rectangular in plan view, and the semiconductor device. 　 In any one of claims 1, 2, or 5, The semiconductor device is a crystalline oxide semiconductor containing indium and oxygen, wherein the semiconductor layer is a semiconductor device.

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