Input circuit

Abstract

This input circuit (1) is provided with a voltage conversion circuit (10) for receiving an input signal at an input terminal (IN), converting the input signal into a voltage signal that transitions between a power source (2VDD) and a power source (VDD), and outputting the voltage signal to a node (n3), and a buffer circuit 20 for receiving an output signal from the voltage conversion circuit (10), converting the output signal into a voltage signal that transitions between the power source (VDD) and a ground (VSS), and outputting the voltage signal through an output terminal (OUT). The voltage conversion circuit (10) is provided with a P-type transistor (P1) and an N-type transistor (N1) provided in series between a node (n1) and a node (n2), and an N-type transistor (N2) and a P-type transistor (P2) provided in series between the power source (2VDD) and the power source (VDD).

Description

Input circuit

[0001] The present disclosure relates to an input circuit of an IO cell into which a signal received from the outside of a semiconductor device (LSI (Large Scale Integration)) is input.

[0002] In conventional semiconductor devices, a transistor with a thick film gate (high breakdown voltage transistor) and a transistor with a thin film gate (low breakdown voltage transistor) having a lower breakdown voltage than the thick film gate transistor have been prepared. Generally, a high breakdown voltage transistor has a high allowable voltage stress (breakdown voltage) and is used in an IO cell that communicates a high voltage signal with the outside of the LSI. The low breakdown voltage transistor is used in an internal cell (such as a memory cell or a standard cell) that handles a relatively low voltage signal.

[0003] In recent years, semiconductor devices without high breakdown voltage transistors have been studied due to manufacturing reasons associated with transistor miniaturization. In the future, since communication of a relatively high voltage signal (such as 1.8 V) may occur, an IO cell that handles a high voltage signal using only low breakdown voltage transistors has been studied.

[0004] For example, Patent Documents 1 to 3 disclose an input circuit of an IO cell that enables input of a voltage signal about twice the breakdown voltage of a transistor.

[0005] U.S. Patent No. 11190187 International Publication No. 2015 / 160452 U.S. Patent No. 7173472

[0006] However, further reduction in transistor breakdown voltage due to progress in miniaturization and a decrease in operating voltage associated therewith are assumed, but there is no input circuit that can flexibly and easily adapt to them.

[0007] In view of the above problems, an object of the present disclosure is to solve the above problems.

[0008] An input circuit according to one aspect of the present disclosure includes: a voltage conversion circuit that receives an input signal to an input terminal and converts it into a voltage signal that transitions between a first power supply and a second power supply having a lower power supply voltage than the first power supply, and outputs it to a first node; and a buffer circuit that receives the signal output from the voltage conversion circuit to the first node as an input signal and converts it into a voltage signal that transitions between the second power supply and a third power supply having a lower power supply voltage than the second power supply, and outputs it to an output terminal, wherein the voltage conversion circuit includes: a first P-type transistor whose drain is connected to an input terminal, whose source is connected to a second node, and whose gate is connected to the first node; a first N-type transistor whose drain is connected to an input terminal, whose source is connected to a third node, and whose gate is connected to the first node; a second N-type transistor whose source is connected to the first power supply, whose drain is connected to the first node, and whose gate is connected to the second node; and a second P-type transistor whose drain is connected to the first node, whose source is connected to a second power supply, and whose gate is connected to a third node.

[0009] In this embodiment, the gate voltages of the first P-type transistor and the first N-type transistor are controlled according to the characteristics of the output signal of the voltage conversion circuit, which fluctuates depending on the transistor's breakdown voltage and operating voltage. As a result, the terminal voltage of each transistor is maintained below the transistor's breakdown voltage while the input circuit is operating. This makes it possible to effectively prevent the aging degradation of each transistor constituting the input circuit compared to conventional technology.

[0010] According to this disclosure, in an input circuit that uses low-voltage transistors to input a high-voltage signal, the voltage across each terminal of each transistor is maintained below the transistor's breakdown voltage during the operation of the input circuit, thereby effectively preventing the aging degradation of each transistor.

[0011] The circuit configuration diagram of the input circuit according to the first embodiment. A diagram showing an example of the operating state of the input circuit in Figure 1. A diagram showing another example of the operating state of the input circuit in Figure 1. A waveform diagram showing the operation of the input circuit in Figure 1. A diagram for explaining the effect of parasitic capacitance. The circuit configuration diagram of the input circuit according to the second embodiment. A diagram showing an example of the operating state of the input circuit in Figure 6. A diagram showing another example of the operating state of the input circuit in Figure 6. The circuit configuration diagram of the input circuit according to the third embodiment. A diagram showing an example of the operating state of the input circuit in Figure 9. A diagram showing another example of the operating state of the input circuit in Figure 9.

[0012] The embodiments will be described below with reference to the drawings.

[0013] In this disclosure, "connection" is a broad concept encompassing electrical connection, including not only direct connections but also indirect electrical connections via passive elements, etc. The circuit diagrams shown below are simplified illustrations focusing on the components relevant to this disclosure. Therefore, components shown as directly connected may, in actual circuit configurations, be indirectly connected due to other components being positioned between them. Furthermore, in this disclosure, "terminal" refers to an entry and exit point for current provided for the connection of an electrical circuit. For example, it is not intended to be limited to specific configurations such as semiconductor pads; wiring and vias connecting circuits and components may also qualify as terminals.

[0014] Furthermore, in the following explanation, common symbols or names may be used to describe the nodes and terminals of a circuit and the signals passing through those nodes and terminals, and common symbols may be used to describe the power supply name and the power supply voltage of that power supply. Also, regarding the voltage of terminals and nodes, only the symbol indicating the voltage may be used, and it may be written as "(terminal name or node name) = (symbol indicating voltage)". Specifically, for example, if the voltage of the output terminal OUT is VDD (voltage of the power supply VDD), it may be written as "OUT = VDD".

[0015] <First Embodiment> Figure 1 is a circuit diagram of an input circuit according to the first embodiment. The input circuit 1 in Figure 1 receives an input signal IN at the input terminal IN and outputs an output signal OUT from the output terminal OUT that changes in accordance with this input signal IN. The input circuit 1 is a circuit using a low-voltage transistor and can accept a voltage signal input of approximately three times the transistor's breakdown voltage. This input circuit 1 is provided, for example, in the I / O cell (signal input section) of an LSI. In this case, the input terminal IN of the input circuit 1 is connected to the input pad of the LSI. The output terminal OUT of the input circuit 1 is connected to an internal node of the LSI.

[0016] The input signal IN transitions between VSS and 3VDD, and the output signal OUT transitions between VSS and VDD. In other words, input circuit 1 receives the input signal IN, which transitions between VSS and 3VDD, and outputs the output signal OUT, which transitions between VSS and VDD according to the input signal IN. VDD is the power supply voltage of power supply VDD (corresponding to the second power supply), 2VDD (described later) is the power supply voltage of power supply 2VDD (corresponding to the first power supply), 3VDD is the power supply voltage of power supply 3VDD, and VSS is the voltage of ground VSS (corresponding to the third power supply). The relative magnitudes of these power supply voltages are "VSS < VDD < 2VDD < 3VDD". For example, VDD is a low voltage of less than 1.0 [V], and typically decreases with the miniaturization of transistors. For example, 2VDD is twice the voltage of VDD, and 3VDD is three times the voltage of VDD.

[0017] [Input Circuit Configuration] As shown in Figure 1, the input circuit 1 comprises a voltage conversion circuit 10 and a buffer circuit 20. The transistors described below are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). However, there is no intention to limit the transistors to MOSFETs; alternative transistors or switching elements may be used.

[0018] -Voltage Conversion Circuit- The voltage conversion circuit 10 is a circuit that outputs a voltage signal D1 (amplitude: VDD to 2VDD) which changes in accordance with the input signal IN (amplitude: VSS to 3VDD) input to the input terminal IN, to node n3 (corresponding to the first node). The operation of the voltage conversion circuit 10 will be explained in more detail later.

[0019] The voltage conversion circuit 10 includes P-type transistors P1 and P2 and N-type transistors N1 and N2. The P-type transistors P1 and P2 and the N-type transistors N1 and N2 are so-called low-voltage transistors, and in the following explanation, when they are not distinguished, these transistors may be collectively referred to simply as "low-voltage transistors." In this example, the low-voltage transistors are transistors that, when viewed individually, have a breakdown voltage of VDD + α. α is, for example, a value approximately equal to the threshold voltage of the transistor.

[0020] The P-type transistor P1 (corresponding to the first P-type transistor) has its drain connected to the input terminal IN, its source connected to node n1 (corresponding to the second node), and its gate connected to node n3. The N-type transistor N1 (corresponding to the first N-type transistor) has its drain connected to the input terminal IN, its source connected to node n2 (corresponding to the third node), and its gate connected to node n3. In other words, the P-type transistor P1 and the N-type transistor N1 are connected in series between node n1 and node n2. The gates of the P-type transistor P1 and the N-type transistor N1 are connected to each other and connected to node n3. The drains of the P-type transistor P1 and the N-type transistor N1 are connected to each other and connected to the input terminal IN.

[0021] The N-type transistor N2 (corresponding to the second N-type transistor) has its source connected to power supply 2VDD, its drain connected to node n3, and its gate connected to node n1. The P-type transistor P2 (corresponding to the second P-type transistor) has its drain connected to node n3, its source connected to power supply VDD, and its gate connected to node n2. In other words, the N-type transistor N2 and the P-type transistor P2 are connected in series between power supply 2VDD and power supply VDD. The drains of the N-type transistor N2 and the P-type transistor P2 are connected to each other and connected to node n3.

[0022] - Buffer Circuit - The buffer circuit 20 converts the signal (voltage signal D1) input from the voltage conversion circuit 10 via node n3 into a voltage signal that transitions between the power supply VDD and ground VSS, and outputs it as an output signal OUT to the output terminal OUT. As described above, the output terminal OUT is connected to, for example, an internal node of the LSI, and the output signal OUT is transmitted to the internal circuit of the LSI.

[0023] The buffer circuit 20 only needs to be able to perform the above conversion function, and its specific circuit configuration is not particularly limited. In the example in Figure 1, the buffer circuit 20 includes an input buffer circuit 21 and a step-down circuit 22. The input buffer circuit 21 propagates a signal that changes between VDD and 2VDD to node n8 in response to the change from VDD to 2VDD at node n3. The specific circuit configuration of the input buffer circuit 21 is not particularly limited, and conventionally used general-purpose buffer circuits such as Schmitt circuits can be applied. The step-down circuit 22 steps down the Low potential from VDD to VSS and steps down the High potential from 2VDD to VDD. In other words, it propagates a signal that changes between VSS and VDD in response to the change from VDD to 2VDD at node n8 to the output terminal OUT. The specific circuit configuration of the step-down circuit 22 is not particularly limited, and conventionally known general-purpose step-down circuits such as level shift circuits can be used.

[0024] [Operation of the Input Circuit] In the following, the operation of the input circuit 1 will be explained, focusing on the operation of the voltage conversion circuit 10, with reference to Figure 2.

[0025] - Operation Example 1-1: When IN=VSS, OUT=VSS - Figure 2 shows the voltage at each node and the on / off state of each transistor in the operation when IN=VSS, OUT=VSS, that is, when Low is input to the input terminal IN of the input circuit 1 and Low is output from the output terminal OUT.

[0026] With the on / off operation of the P-type transistor P2 and the N-type transistor N2, the voltage amplitude at node n3 becomes VDD to 2VDD, so when IN = VSS, the N-type transistor N1 turns on. This results in n2 = VSS, and the gate potential of the P-type transistor P2 becomes VSS. This turns on the P-type transistor P2, and node n3 is fixed at VDD. Since IN = VSS and n3 = VDD, the P-type transistor P1 turns off. As a result, node n1 enters a Hi-Z state, but maintains the previous state (the state of node n1 in "Operation Example 1-4" described later), and remains approximately at n1 = VDD. Since n1 = VDD and n3 = VDD, the N-type transistor N2 turns off. As a result, the output of the input buffer circuit 21 becomes n8 = VDD, and the output of the step-down circuit 22 becomes OUT = VSS.

[0027] As can be seen from Figure 2, the gate-source-drain potential differences of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 are all below VDD.

[0028] -Operation Example 1-2: When IN = 3VDD, OUT = VDD- Figure 3 shows the operation of the input circuit 1 when IN = 3VDD, OUT = VDD, that is, when High is input to the input terminal IN and High is output from the output terminal OUT, illustrating the voltage at each node and the on / off state of each transistor.

[0029] The on / off operation of the P-type transistor P2 and the N-type transistor N2 causes the voltage amplitude at node n3 to be between VDD and 2VDD. Therefore, when IN = 3VDD, the P-type transistor P1 turns on. This results in n1 = 3VDD, and the gate potential of the N-type transistor N2 becomes 3VDD. As a result, the N-type transistor N2 turns on, and node n3 is fixed at 2VDD. Since IN = 3VDD and n3 = 2VDD, the N-type transistor N1 turns off. As a result, node n2 enters a Hi-Z state, but maintains its previous state (the state of node n2 in "Operation Example 1-3" described later), and remains approximately at n2 = 2VDD. Since n2 = 2VDD and n3 = 2VDD, the P-type transistor P2 turns off. As a result, the output of the input buffer circuit 21 becomes n8 = 2VDD, and the output of the step-down circuit 22 becomes OUT = VDD.

[0030] As can be seen from Figure 3, the gate-source-drain potential differences of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 are all below VDD.

[0031] - Operation Example 1-3: IN = VSS → 3VDD, OUT = VSS → VDD - The left side of Figure 4 shows the operation of IN = VSS → 3VDD, OUT = VSS → VDD, that is, the waveform when the input signal IN of input circuit 1 transitions from Low to High and the output signal OUT changes from Low to High.

[0032] When the input signal IN transitions from Low to High, the on / off state of each transistor transitions from the state described in "Operation Example 1-1" to the state described in "Operation Example 1-2".

[0033] As the input signal IN begins to transition from Low to High, the voltage at node n2 rises accordingly. During the voltage rise at node n2, the P-type transistor P2 turns off. Also, as the input signal IN transitions from Low to High, the P-type transistor P1 turns on. As a result, the voltages at nodes n1 and n3 begin to rise. During the voltage rise at node n1, the N-type transistor N2 turns on. As a result, the voltage at node n3 rises from VDD to 2VDD. Consequently, the voltage at node n8 rises from VDD to 2VDD, and the output signal OUT rises from VSS to VDD.

[0034] The N-type transistor N1 turns off during the transition of the input signal IN from Low to High. As the voltage at node n3 rises to 2 VDD, the rise in the voltage at node n2, which is the source potential of the N-type transistor N1, stops at around 2 VDD.

[0035] As described above, even while the input signal IN changes from Low to High, the potential difference between the gate, source, and drain terminals of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 is maintained below VDD. In other words, it is maintained at a voltage below the breakdown voltage of the low-voltage transistors.

[0036] - Operation Example 1-4: When IN = 3VDD → VSS and OUT = VDD → VSS - The right side of Figure 4 shows the waveform when IN = 3VDD → VSS and OUT = VDD → VSS, that is, when the input signal IN of input circuit 1 transitions from High to Low and the output signal OUT changes from High to Low.

[0037] When the input signal IN transitions from High to Low, the on / off state of each transistor transitions from the state described in "Operation Example 1-2" to the state described in "Operation Example 1-1".

[0038] As the input signal IN begins to transition from High to Low, the voltage at node n1 decreases accordingly. During the voltage decrease at node n1, the N-type transistor N2 turns off. Also, as the input signal IN transitions from High to Low, the N-type transistor N1 turns on. As a result, the voltages at nodes n2 and n3 begin to decrease. During the voltage decrease at node n2, the P-type transistor P2 turns on. As a result, the voltage at node n3 decreases from 2VDD to VDD. Consequently, the voltage at node n8 decreases from 2VDD to VDD, and the output signal OUT decreases from VDD to VSS.

[0039] The P-type transistor P1 turns off during the transition of the input signal IN from High to Low. As the voltage at node n3 drops to VDD, the decrease in the voltage at node n1, which is the source potential of the P-type transistor P1, stops around VDD.

[0040] As described above, even while the input signal IN changes from High to Low, the potential difference between the gate, source, and drain terminals of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 is maintained below VDD. In other words, it is maintained at a voltage below the breakdown voltage of the low-voltage transistors.

[0041] [Effects of the First Embodiment] According to this embodiment, even when the voltage of the input signal IN changes between VSS and 3VDD, the potential difference between the gate, source, and drain terminals of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 remains below VDD. As a result, even when low-voltage transistors are used as the P-type transistors P1 and P2 and the N-type transistors N1 and N2, the breakdown voltage of the low-voltage transistors is not exceeded, and deterioration over time can be suppressed. Furthermore, since the voltage conversion circuit 10 has a simple configuration of four transistors, the design difficulty is low and the circuit area can be reduced.

[0042] <Second Embodiment> Figure 6 is a circuit diagram of the input circuit according to the second embodiment. In Figure 6, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0043] In the first embodiment, as described above, in nodes n1 and n2, there exists a state where they temporarily become Hi-Z. Specifically, when IN = VSS (Low input) and n3 = VDD (Low output), the P-type transistor P1 turns off, so n1 = Hi-Z. Similarly, when IN = 3VDD (High input) and n3 = 2VDD (High output), the N-type transistor N1 turns off, so n2 = Hi-Z. At this time, due to the potential fluctuation of the input signal IN, the potential is propagated by the parasitic capacitance between the source and drain of the P-type transistor P1, and the potential of node n1 may fall below VDD (see the broken line in the upper part of FIG. 5). Similarly, due to the potential fluctuation of the input signal IN, the potential is propagated by the parasitic capacitance between the source and drain of the N-type transistor N1, and the potential of node n2 may exceed 2VDD (see the broken line in the lower part of FIG. 5). Therefore, the potential difference between the gate and source of the P-type transistor P2 or the N-type transistor N2 may exceed VDD, and there is a possibility of aging degradation. Therefore, in this embodiment, by providing the voltage control circuit 11 described later, it is possible to prevent nodes n1 and n2 from becoming Hi-Z states respectively. Hereinafter, the configuration and operation of the input circuit 1 according to this embodiment will be described.

[0044] [Configuration of Input Circuit] The input circuit 1 in FIG. 6 has a different internal configuration of the voltage conversion circuit 10 compared to the input circuit 1 in FIG. 1.

[0045] In addition to the configuration of FIG. 1, the voltage conversion circuit 10 of FIG. 6 includes a voltage control circuit 11. The voltage control circuit 11 includes an N-type transistor N3 (corresponding to the third N-type transistor) and a P-type transistor P3 (corresponding to the third P-type transistor) connected in series between the node n1 and the node n2. The intermediate node connecting the N-type transistor N3 and the P-type transistor P3 is connected to the node n3 (corresponding to the first node). More specifically, the drain of the N-type transistor N3 is connected to the node n1 (corresponding to the second node), the source is connected to the node n3, and the gate is connected to the power supply 2VDD (corresponding to the first power supply). The source of the P-type transistor P3 is connected to the node n3, the drain is connected to the node n2 (corresponding to the third node), and the gate is connected to the power supply VDD (corresponding to the second power supply). The P-type transistor P3 and the N-type transistor N3 are the aforementioned low breakdown voltage transistors.

[0046] Since the configuration of the buffer circuit 20 can be the same as that of the first embodiment, the description thereof is omitted here.

[0047] [Operation of the input circuit] In this embodiment, the basic operation of the entire input circuit 1 is the same as that of the aforementioned "operation example 1-1", "operation example 1-2", "operation example 1-3", and "operation example 1-4". Here, the description will be centered on the newly added configuration in FIG. 6.

[0048] - Operation example 2-1: When IN = VSS and OUT = VSS - FIG. 7 shows the voltage of each node and the on / off state of each transistor for the operation when a Low is input to the input terminal IN of the input circuit 1 and a Low is output from the output terminal OUT.

[0049] Similar to "operation example 1-1", the N-type transistor N1 is turned on and the P-type transistor P2 is turned on. As a result, the node n3 is fixed at VDD. Since IN = VSS and n3 = VDD, the P-type transistor P1 is turned off.

[0050] N-type transistor N3 turns on because its gate potential is 2VDD and its source potential is VDD (n3 = VDD). This fixes node n1 to VDD. N-type transistor N2 turns off because its gate potential is VDD (n1 = VDD), its source potential is 2VDD, and its drain potential is VDD (n3 = VDD). P-type transistor P3 turns off because its gate potential is VDD, its source potential is VDD (n3 = VDD), and its drain potential is VSS (n2 = VSS).

[0051] -Operation Example 2-2: When IN = 3VDD and OUT = VDD- Figure 8 shows the voltage at each node and the on / off state of each transistor in the operation when High is input to the input terminal IN of the input circuit 1 and High is output from the output terminal OUT.

[0052] Similar to "Operation Example 1-2," the P-type transistor P1 turns on, and the N-type transistor N2 turns on. As a result, node n3 is fixed at 2VDD. Since IN = 3VDD and n3 = 2VDD, the N-type transistor N1 turns off.

[0053] P-type transistor P3 turns on because its gate potential is VDD and its source potential is 2VDD (n3 = 2VDD). This fixes node n2 at 2VDD. P-type transistor P2 turns off because its gate potential is 2VDD (n2 = 2VDD), its source potential is VDD, and its drain potential is 2VDD (n3 = 2VDD). N-type transistor N3 turns off because its gate potential is 2VDD, its source potential is 2VDD (n3 = 2VDD), and its drain potential is 3VDD (n1 = 3VDD).

[0054] - Operation Example 2-3: IN = VSS → 3VDD, OUT = VSS → VDD - This section describes the operation when IN = VSS → 3VDD, OUT = VSS → VDD, that is, when the input signal IN of input circuit 1 transitions from Low to High, and the output signal OUT changes from Low to High.

[0055] When the input signal IN transitions from Low to High, the on / off state of each transistor transitions from the state described in "Operation Example 2-1" to the state described in "Operation Example 2-2". In this embodiment, the N-type transistor N3 changes from On to Off and the P-type transistor P3 changes from Off to On during the process in which the voltage at node n3 rises from VDD to 2VDD, which is different from the first embodiment. The other operations are the same as described in "Operation Example 1-3" (see the left side of Figure 4).

[0056] - Operation Example 2-4: When IN = 3VDD → VSS, OUT = VDD → VSS - This section describes the operation when IN = 3VDD → VSS, OUT = VDD → VSS, that is, when the input signal IN of input circuit 1 transitions from High to Low, and the output signal OUT changes from High to Low.

[0057] When the input signal IN transitions from High to Low, the on / off state of each transistor transitions from the state described in "Operation Example 2-2" to the state described in "Operation Example 2-1". In this embodiment, the difference from the first embodiment is that as the voltage at node n3 decreases from 2VDD to VDD, the N-type transistor N3 changes from off to on, and the P-type transistor P3 changes from on to off. The other operations are the same as described in "Operation Example 1-4" (see the right side of Figure 4).

[0058] [Effects of the Second Embodiment] According to this embodiment, similar to the first embodiment, even when the voltage of the input signal changes between VSS and 3VDD, the potential difference between the gate, source, and drain of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 remains below VDD. As a result, the breakdown voltage of the low-voltage transistors is not exceeded, and even when low-voltage transistors are used as the P-type transistors P1 and P2 and the N-type transistors N1 and N2, degradation over time can be suppressed. Furthermore, it is possible to prevent nodes n1 and n2 from entering a Hi-Z state and suppress the degradation of the transistors over time.

[0059] <Third Embodiment> Figure 9 is a circuit diagram of the input circuit according to the third embodiment. In Figure 9, components corresponding to those in Figure 6 are denoted by the same reference numerals. The following description will focus on the differences from the first or second embodiment.

[0060] In the second embodiment described above, node n3 is connected to the input terminal IN via a path through an N-type transistor N1 and a P-type transistor P3, or via a path through a P-type transistor P1 and an N-type transistor N3. In other words, there is a path between the input signal IN and node n3 that does not go through the gates of transistors. Therefore, if there are unexpected fluctuations in the input signal IN, such as overshoot / undershoot or ringing noise, these may propagate inside the input circuit 1, potentially causing circuit malfunction or applying a voltage exceeding the breakdown voltage to the transistor. The voltage control circuit 12 of the third embodiment is configured to solve this problem. The configuration and operation of the input circuit 1 according to this embodiment will be described below.

[0061] [Input Circuit Configuration] The input circuit 1 in Figure 9 differs from the input circuit 1 in Figure 1 or Figure 6 in the internal configuration of the voltage conversion circuit 10.

[0062] The voltage conversion circuit 10 in Figure 9 includes a voltage control circuit 12 in addition to the configuration in Figure 1. The voltage control circuit 12 includes an N-type transistor N4 (corresponding to the third N-type transistor) and a P-type transistor P4 (corresponding to the third P-type transistor) connected in series between the power supply 2VDD (corresponding to the first power supply) and node n2 (corresponding to the third node). The voltage control circuit 12 also includes an N-type transistor N5 (corresponding to the fourth N-type transistor) and a P-type transistor P5 (corresponding to the fifth P-type transistor) connected in series between node n1 (corresponding to the second node) and the power supply VDD (corresponding to the second power supply). Node n4 (corresponding to the fourth node), which connects the N-type transistor N4 and the P-type transistor P4, is not connected to node n3 (corresponding to the first node). Similarly, node n5 (corresponding to the fifth node), which connects the N-type transistor N5 and the P-type transistor P5, is not connected to node n3. More specifically, the N-type transistor N4 has its drain connected to power supply 2VDD, its source connected to node n4, and its gate connected to node n1. The P-type transistor P4 has its source connected to node n4, its drain connected to node n2, and its gate connected to power supply VDD. The N-type transistor N5 has its drain connected to node n1, its source connected to node n5, and its gate connected to power supply 2VDD. The P-type transistor P5 has its source connected to node n5, its drain connected to power supply VDD, and its gate connected to node n2. The P-type transistors P4 and P5 and the N-type transistors N4 and N5 are the low-voltage transistors described above.

[0063] Since the buffer circuit 20 can be configured in the same way as in the first embodiment, a detailed explanation of it will be omitted here.

[0064] [Operation of the Input Circuit] In this embodiment as well, the basic operation of the input circuit 1 as a whole is the same as in the aforementioned "Operation Example 1-1", "Operation Example 1-2", "Operation Example 1-3", and "Operation Example 1-4". Here, we will mainly explain the configuration newly added in Figure 9.

[0065] -Operation Example 3-1: When IN=VSS and OUT=VSS- Figure 10 shows the voltage at each node and the on / off state of each transistor in the operation when Low is input to the input terminal IN of the input circuit 1 and Low is output from the output terminal OUT.

[0066] Similar to "Operation Example 1-1," the N-type transistor N1 turns on, and the P-type transistor P2 turns on. As a result, node n3 is fixed to VDD. Since IN = VSS and n3 = VDD, the P-type transistor P1 turns off.

[0067] P-type transistor P5 turns on because its gate potential is VSS (n2 = VSS) and its source potential is VDD. This fixes node n5 to VDD. N-type transistor N5 turns on because its gate potential is 2VDD and its source potential is VDD (n5 = VDD). This fixes node n1 to VDD. P-type transistor P4 turns off because its gate potential is VDD and its source potential is VSS (n2 = VSS). N-type transistor N4 turns off because its gate potential is VDD (n1 = VDD) and its source potential is the power supply's 2VDD. N-type transistor N2 turns off because its gate potential is VDD (n1 = VDD), its source potential is 2VDD, and its drain potential is VDD (n3 = VDD).

[0068] -Operation Example 3-2: When IN = 3VDD and OUT = VDD- Figure 11 shows the voltage at each node and the on / off state of each transistor in the operation when High is input to the input terminal IN of the input circuit 1 and High is output from the output terminal OUT.

[0069] Similar to "Operation Example 1-2," the P-type transistor P1 turns on, and the N-type transistor N2 turns on. As a result, node n3 is fixed at 2VDD. Since IN = 3VDD and n3 = 2VDD, the N-type transistor N1 turns off.

[0070] N-type transistor N4 turns on because its gate potential is 3VDD (n1 = 3VDD) and its source potential is 2VDD. This fixes node n4 at 2VDD. P-type transistor P4 turns on because its gate potential is VDD and its source potential is 2VDD (n4 = 2VDD). This fixes node n2 at 2VDD. N-type transistor N5 turns off because its gate potential is 2VDD and its source potential is 3VDD (n1 = 3VDD). P-type transistor P5 turns off because its gate potential is 2VDD (n2 = 2VDD) and its source potential is the power supply VDD. P-type transistor P2 turns off because its gate potential is 2VDD (n2 = 2VDD), its source potential is VDD, and its drain potential is 2VDD (n3 = 2VDD).

[0071] - Operation Example 3-3: IN = VSS → 3VDD, OUT = VSS → VDD - This section describes the operation when IN = VSS → 3VDD, OUT = VSS → VDD, that is, when the input signal IN of input circuit 1 transitions from Low to High, and the output signal OUT changes from Low to High.

[0072] When the input signal IN transitions from Low to High, the on / off state of each transistor transitions from the state described in "Operation Example 3-1" to the state described in "Operation Example 3-2". In this embodiment, the N-type transistor N5 and P-type transistor P5 change from on to off, and the N-type transistor N4 and P-type transistor P4 change from off to on, in the process of the voltage at node n3 rising from VDD to 2VDD, which is different from the first embodiment. The other operations are the same as described in "Operation Example 1-3" (see the left side of Figure 4).

[0073] - Operation Example 3-4: When IN = 3VDD → VSS and OUT = VDD → VSS - This section describes the operation when IN = 3VDD → VSS and OUT = VDD → VSS, that is, when the input signal IN of input circuit 1 transitions from High to Low and the output signal OUT changes from High to Low.

[0074] When the input signal IN transitions from High to Low, the on / off state of each transistor transitions from the state described in "Operation Example 3-2" to the state described in "Operation Example 3-1". In this embodiment, the N-type transistor N5 and P-type transistor P5 change from off to on, and the N-type transistor N4 and P-type transistor P4 change from on to off, in the process of the voltage at node n3 decreasing from 2VDD to VDD, which is different from the first embodiment. The rest of the operation is the same as described in "Operation Example 1-4" (see the right side of Figure 4).

[0075] [Effects of the Third Embodiment] According to this embodiment, similar to the first embodiment, even when the voltage of the input signal changes between VSS and 3VDD, the potential difference between the gate, source, and drain of the P-type transistors P1 and P2 and the N-type transistors N1 and N2 remains below VDD. As a result, even when low-voltage transistors are used as the P-type transistors P1 and P2 and the N-type transistors N1 and N2, the breakdown voltage of the low-voltage transistors is not exceeded, and deterioration over time can be suppressed. Furthermore, since nodes n1 and n2 are prevented from entering a Hi-Z state and the problems of the second embodiment do not occur, deterioration over time can be suppressed.

[0076] <Other Embodiments> The technology in this disclosure is not limited to the configurations described in the embodiments above, and many modifications, such as changes, substitutions, additions, and omissions, can be made as appropriate by a person with ordinary skill in the art within the technical concept of this disclosure. Furthermore, it is possible to combine the components described in the embodiments above to create new embodiments.

[0077] For example, in each of the above embodiments, the power supply voltage of power supply 3VDD is not limited to three times the voltage of VDD. In other words, the amplitude of the input signal voltage is not limited to three times VDD. For example, by adjusting the voltage of each node, it is possible to input voltages greater than three times VDD and voltages less than three times VDD to the input circuit 1.

[0078] This disclosure effectively prevents the aging degradation of transistors, making it useful as an input circuit for LSIs.

[0079] 1 Input circuit 10 Voltage conversion circuit 20 Buffer circuit IN Input terminal, input signal N1 N-type transistor (first N-type transistor) N2 N-type transistor (second N-type transistor) N3 N-type transistor (third N-type transistor) N4 N-type transistor (third N-type transistor) N5 N-type transistor (fourth N-type transistor) P1 P-type transistor (first P-type transistor) P2 P-type transistor (second P-type transistor) P3 P-type transistor (third P-type transistor) P4 P-type transistor (third P-type transistor) P5 P-type transistor (fourth P-type transistor) OUT Output terminal, output signal VDD Power supply (second power supply) 2VDD Power supply (first power supply) VSS Ground (third power supply) n1 Node (second node) n2 Node (third node) n3 Node (first node) n4 node (4th node) n5 node (5th node)

Claims

1. An input circuit comprising: a voltage conversion circuit that receives an input signal to an input terminal and converts it into a voltage signal that transitions between a first power supply and a second power supply having a lower power supply voltage than the first power supply, and outputs it to a first node; and a buffer circuit that receives the signal output from the voltage conversion circuit to the first node as an input signal and converts it into a voltage signal that transitions between the second power supply and a third power supply having a lower power supply voltage than the second power supply, and outputs it to an output terminal, wherein the voltage conversion circuit comprises: a first P-type transistor whose drain is connected to an input terminal, whose source is connected to a second node, and whose gate is connected to the first node; a first N-type transistor whose drain is connected to an input terminal, whose source is connected to a third node, and whose gate is connected to the first node; a second N-type transistor whose source is connected to the first power supply, whose drain is connected to the first node, and whose gate is connected to the second node; and a second P-type transistor whose drain is connected to the first node, whose source is connected to a second power supply, and whose gate is connected to the third node.

2. The input circuit according to claim 1, wherein the voltage conversion circuit comprises: a third N-type transistor whose drain is connected to the second node, whose source is connected to the first node, and whose gate is connected to the first power supply; and a third P-type transistor whose source is connected to the first node, whose drain is connected to the third node, and whose gate is connected to the second power supply.

3. The input circuit according to claim 1, wherein the voltage conversion circuit comprises: a third N-type transistor whose drain is connected to the first power supply, whose source is connected to the fourth node, and whose gate is connected to the second node; a third P-type transistor whose source is connected to the fourth node, whose drain is connected to the third node, and whose gate is connected to the second power supply; a fourth N-type transistor whose drain is connected to the second node, whose source is connected to the fifth node, and whose gate is connected to the first power supply; and a fourth P-type transistor whose source is connected to the fifth node, whose drain is connected to the second power supply, and whose gate is connected to the third node.

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