Integrated semiconductor device and method for operating same

Abstract

The objective of the present invention is to increase the degree of freedom of control over bit manipulation, readout, etc. in a two-dimensional quantum bit array.　One aspect of the present invention is an integrated semiconductor device characterized by including at least three first gate electrodes arranged on an insulating film formed on a semiconductor substrate so as to extend in a first direction in a plane, at least three second gate electrodes arranged so as to extend in a second direction orthogonal to the first direction, and a third gate electrode formed between the plurality of second gate electrodes so as to be parallel to the second gate electrodes, wherein, in plan view, the third gate electrode is disposed in an upper part of a portion surrounded by the plurality of first gate electrodes and the plurality of second gate electrodes.

Description

Integrated semiconductor device and its operating method

[0001] This invention relates to a device that performs quantum computing using spin state information of electrons or holes held in a plurality of micro-dots arranged in a two-dimensional array on a semiconductor substrate.

[0002] A quantum computer is a computer that is thought to be capable of processing information at a much faster speed than existing computers. This is because, while existing computers deal with binary values ​​of 0 and 1, quantum computers have the characteristic of being able to deal with superposition states of these two values. In the devices that constitute a quantum computer, which performs quantum operations by using the spin states of one or more electrons as information carriers, the devices that hold basic information are called qubits. Computers using qubits can perform quantum operations using spin superposition states and quantum entanglement states, enabling high-speed computation.

[0003] With advancements in silicon semiconductor technology enabling microfabrication on the order of 10 nm, it has become clear that single electrons can be confined to a region surrounded by an electrical potential at extremely low temperatures and function as qubits. (See Patent Documents 1 and 2) For example, the spin state of a single electron can be reversed by applying an external magnetic field, allowing it to take on a binary state of up and down. Furthermore, this spin state can be manipulated as desired by applying microwaves, leading to the idea of ​​using this as an information carrier for quantum computation.

[0004] First, we will show a typical configuration and structure of a qubit known as a MOS (Metal Oxide Semiconductor) type, which uses an insulated gate, and then explain its operation.

[0005] Figure 1 is a plan view of the device. Figure 2 is a cross-sectional view of the X-X' section in Figure 1. Figure 3 shows the distribution of the electrical potential along the Y-Y' section in Figure 2. Here, the electrical potential is shown as the potential for negatively charged electrons, following convention, and is expressed in inverse notation to electric potential.

[0006] As shown in Figure 3, an electrical potential barrier is created around the outer periphery of the quantum dot Q, which confines electrons, by the field field effect of the gates indicated by a, b, c, and d surrounding Q. Q is a region that confines electrons, surrounded by a potential barrier, and is not a physical structure, so it is shown as a region by a dashed line in Figures 1 and 2. The gate e placed directly above Q traps electrons by creating a pocket-like potential distribution near the semiconductor surface of the Q region.

[0007] Figure 3 shows how an electron with spin is held within a potential well. The spin state of this electron is used as information for quantum computation. That is, as shown in the lower part of Figure 3, an upward spin is associated with 0, and a downward spin is associated with 1, which is how information is held and computations are performed.

[0008] In quantum computing, it is necessary to perform a single-qubit operation, which involves manipulating the spin of an electron captured by a single quantum dot, and a double-qubit operation, which involves manipulating multiple electrons held by two quantum dots. While operations between more than two qubits are also possible, it is known that in principle all operations can be performed by combining single-qubit and double-qubit operations. Therefore, here we will explain single-qubit and double-qubit operations as the basic operations.

[0009] Figure 4 shows an example configuration of two quantum dots, Q1 and Q2. Q1 is composed of gates a1, b1, c1, d12 and e1, and Q2 is composed of gates a2, b2, c2, d12 and e2. The gate d12, which separates Q1 and Q2, is a common gate, and by manipulating this gate, two-qubit operations can be performed using Q1 and Q2.

[0010] JP 2023-67999 US 12,009,813 Bl

[0011] As shown in Figures 1 and 4, one qubit of this type requires five gates, and two qubits require nine gates. In order to actually perform quantum computing to solve problems using qubits, a large number of qubits are needed, and since each of them requires multiple gates, a vast number of gates must be formed.

[0012] Of course, each gate exerts an electric field effect on the qubit, so it is necessary to apply an electric potential, which requires connecting to some kind of voltage source by electrical wiring. Even if this wiring could be formed with the minimum processing dimensions in semiconductor manufacturing, multiple wires would need to be placed for each qubit, making even a single qubit enormous.

[0013] On the other hand, the charge-holding portion of a quantum dot needs to be small in order to capture a single electron, and the spacing between qubits also needs to be short in order to allow interactions such as two-qubit operations with neighboring qubits. Under these conditions, forming a large number of isolated gates is incompatible.

[0014] To solve this problem, the method described in Patent Document 1 has been proposed. This structure proposes a method for controlling multiple qubits by using a linear gate electrode. However, while a high degree of freedom of operation is achieved in one direction of the two-dimensionally arranged qubits, element isolation regions are formed in the orthogonal directions, limiting the degree of freedom and leaving room for improvement in operating as a complete two-dimensional array with expandability.

[0015] Furthermore, Patent Document 2 discloses multiple gate electrodes extending horizontally, multiple gate electrodes extending vertically, and multiple gate electrodes extending diagonally, with a quantum dot region below the grid opening formed by two vertical gate electrodes and two horizontal gate electrodes. In this structure, a region that is difficult to control is created in the overlapping area of ​​the vertical and horizontal gate electrodes, which may prevent high-precision control during two-qubit operations. In addition, providing gate electrodes in the diagonal direction is extremely difficult from a process standpoint.

[0016] The present invention aims to increase the degree of freedom in controlling bit manipulation, reading, and other operations in a two-dimensional qubit array.

[0017] One aspect of the present invention is an integrated semiconductor device having, on an insulating film formed on a semiconductor substrate, at least three first gate electrodes arranged extending in a first in-plane direction, at least three second gate electrodes arranged extending in a second direction perpendicular to the first direction, and a third gate electrode formed parallel to the second gate electrodes between the plurality of second gate electrodes, wherein, in a plan view, the third gate electrode is arranged above the area surrounded by the plurality of first gate electrodes and the plurality of second gate electrodes.

[0018] Another aspect of the present invention is a method for operating an integrated semiconductor device, characterized in that by applying a specific potential to the first gate electrode, the second gate electrode, and the third gate electrode, a specific qubit in the qubit array is given a different potential state from the other qubits in the qubit array, thereby making the resonance frequency of the electron spin in the specific qubit different from that of the other qubits.

[0019] Another aspect of the present invention is a method for operating an integrated semiconductor device, characterized in that a first potential for electrons is formed on the outer periphery of two adjacent qubits in a qubit array by applying a specific potential to the first gate electrode, the second gate electrode, and the third gate electrode, and a quantum operation is performed between the two adjacent qubits by making the potential barrier between the two adjacent qubits lower than the first potential.

[0020] Another aspect of the present invention is a method for operating an integrated semiconductor device, characterized in that the height of the potential barrier formed by the electric field effect on the first gate electrode is effectively changed by applying an electric field effect from both sides of the first gate electrode using the second gate electrode formed to straddle the first gate electrode.

[0021] Another aspect of the present invention is an integrated semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a second semiconductor layer formed on the first insulating film; a second insulating film formed on the second semiconductor layer; at least three equally spaced parallel first gate electrodes extending in a first in-plane direction within the first insulating film; at least three equally spaced parallel second gate electrodes on the second insulating film in a direction parallel to the first direction; at least three equally spaced parallel third gate electrodes arranged in a direction perpendicular to the first direction and straddling the second gate electrodes; and at least two fourth gate electrodes formed between the third gate electrodes, wherein the third gate electrode is positioned to cover a qubit formed by being surrounded by two of the second gate electrodes and two of the fourth gate electrodes.

[0022] According to the present invention, the degree of freedom for controlling bit manipulation, reading, and other operations in a two-dimensional qubit array can be increased.

[0023] Planar configuration of a single qubit device made of semiconductor. Diagram explaining the cross-sectional structure of a qubit. Potential distribution diagram explaining the mechanism by which a qubit holds electrons, and the correspondence between the state of child spins and numerical values. Planar configuration of two qubits made of semiconductor. Planar configuration of a qubit array according to an example. Cross-sectional structure diagram of a qubit array according to an example. Diagram explaining the potential distribution in a qubit according to an example. Diagram explaining the potential distribution in a qubit according to an example. Planar configuration of a qubit array according to an example. Cross-sectional structure diagram of a qubit array according to an example. Image diagram of the potential distribution in a qubit according to an example. Image diagram of the potential distribution in a qubit according to an example. Graph diagram of the potential distribution in a qubit according to an example. Diagram explaining the shuttle operation between two qubits according to an example. Diagram explaining the shuttle operation between two qubits according to an example. Model diagram explaining spin-charge conversion between two qubits according to an example. Model diagram explaining spin-charge conversion between two qubits according to an example. Model diagram explaining spin-charge conversion between two qubits according to an example. Model diagram explaining spin-charge conversion between two qubits according to an example. Model diagram explaining spin-charge conversion between two qubits according to an example. A plan view illustrating the manufacturing process of a qubit array according to an example. A cross-sectionalCross-sectional diagram illustrating the manufacturing process of a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit array according to an example. Planar layout diagram illustrating the readout operation of a qubit array according to an example. Potential diagram illustrating the readout operation of a qubit array according to an example. Potential diagram illustrating the readout operation of a qubit array according to an example. Planar layout diagram of another qubit array according to an example. Cross-sectional diagram illustrating another method of manufacturing a qubit array according to an example. Diagram illustrating the block configuration of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Cross-sectional diagram illustrating the manufacturing process of a qubit chip with a qubit array according to an example. Diagram illustrating the outer periphery of the array by the block configuration of the qubit chip. Planar arrangement diagram illustrating the array-outer boundary of the qubit array according to an example. Planar arrangement diagram illustrating other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating the manufacturing method of other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating the manufacturing method of other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating the manufacturing method of other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating other structures of the qubit array according to an example. Cross-sectional structure diagram illustrating other structures of the qubit array according to an example.

[0024] Embodiments will be described in detail with reference to the drawings. However, the present invention is not to be construed as being limited to the embodiments described below. It will be readily apparent to those skilled in the art that the specific configuration can be modified without departing from the spirit or intent of the present invention.

[0025] In the configurations of the embodiments described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and redundant explanations may be omitted.

[0026] When there are multiple elements with the same or similar function, they may be described using the same symbol but with different subscripts. However, if there is no need to distinguish between multiple elements, the subscript may be omitted in the description.

[0027] In this specification, notations such as "Part 1," "Part 2," and "Part 3" are used to identify components and do not necessarily limit their number, order, or content. Furthermore, the numbers used to identify components are used on a context-by-context basis, and a number used in one context does not necessarily indicate the same component in another context. Moreover, this does not prevent a component identified by one number from also performing the function of a component identified by another number.

[0028] The positions, sizes, shapes, and ranges of each component shown in drawings, etc., may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in drawings, etc.

[0029] The publications, patents, and patent applications cited herein constitute part of the description herein.

[0030] In this specification, elements expressed in the singular form shall include the plural form unless otherwise clearly indicated in the context.

[0031] The following describes embodiments of the present invention. This embodiment relates to a device having an element that performs quantum computation using the spin state information of one to several electrons held in a plurality of fine dots arranged in a two-dimensional array on a semiconductor substrate, converts it into electron charge information, amplifies the charge information, and outputs it.

[0032] In this embodiment, in an integrated qubit where multiple qubits are arranged in a two-dimensional array, multiple linear gate electrodes that control the operation of the qubits are arranged in a planar orthogonal network so that they intersect for each qubit. By controlling the potential difference between gate electrodes, this method provides a way to perform different controls on individual qubits connected to a single gate electrode, even if a specific potential is applied to that gate electrode.

[0033] Here, we will explain the four basic operations required in a quantum computing device using this embodiment's structure: single-qubit operation, double-qubit operation, electron transfer (shutting operation), initialization operation, and readout operation. This will demonstrate that this embodiment provides a solution to the problem.

[0034] First, we will explain the basic concepts of the configuration and operating mechanism of integrated qubits using a simplified system. A characteristic of silicon MOS-type qubits is that they are used at extremely low temperatures, and unlike at room temperature, they operate in a situation where carriers are almost nonexistent. Therefore, the electrical potential distribution does not need to be affected by the charge of the carriers, and can be determined solely by the field effect from gates that are almost in close proximity.

[0035] The formation of the potential distribution will be explained in detail using Figure 5. A silicon substrate is prepared using single-crystal silicon. Multiple first gate electrodes (FGs) are formed on the gate insulating film on the silicon substrate, arranged in parallel with a fine and uniform pitch. Multiple second gate electrodes (SGs) are formed in parallel with a fine and uniform pitch in a direction perpendicular to the FG in the substrate plane. The second gates SGs are formed so as to sandwich the first gates FGs by crossing over them, and the two gates are arranged in an orthogonal mesh.

[0036] Figure 5 shows a planar layout example when using six each of FG (solid line) and SG (dotted line). Quantum bits are formed in a two-dimensional array in the hatched area surrounded by FG and SG.

[0037] Figure 6 shows the A-A cross-sectional structure of Figure 5, indicating how SG straddles FG. In Figure 5, a total of 25 quantum bits are created in five columns in the vertical direction with i = 1 to 5 and five columns in the horizontal direction with j = 1 to 5, denoted as Qij. Since these gates are repeatedly arranged at equal pitches, it is clear that a two-dimensional array can be expanded by repeating the arrangement so that FG and SG can obtain the required number of quantum bits.

[0038] Here, since electrons are confined in quantum dots, a potential notation for electrons is used. By applying a negative potential to the gate, a potential barrier is formed on the semiconductor surface by the electric field effect. By applying a larger negative potential, a higher barrier can be obtained.

[0039] In the structure where SG of the present embodiment straddles FG, SG affects the electric field from both sides of FG, changing the electrical potential barrier created by FG on the semiconductor surface through the insulating film. Therefore, the potential barrier under FG in the area sandwiched by SG can be changed.

[0040] Figure 7 shows the potential at the B-B' cross-section of Figure 5. By applying a negative potential to FG3 and FG4 in Figures 5 and 6, as shown in Figure 7, a groove sandwiched by potential barriers in the SG direction is formed between FG3 and FG4.

[0041] Figure 8 shows the potential at the C-C' cross-section of Figure 5. Furthermore, by applying a negative potential to SG3 and SG4 in Figures 5 and 6, a potential barrier can be created in the FG direction between SG3 and SG4. Therefore, only Q33 surrounded by FG3, FG4, SG3, and SG4 can have an area surrounded by barriers.

[0042] At this time, if a potential that creates a barrier is not applied to other gate electrodes, a quantum bit can be obtained by confining a single electron at the intersection Q33. In this embodiment, in order to more effectively control the potential of the quantum bit, a third gate TG formed parallel to the SG is formed.

[0043] In this embodiment, the TG is also orthogonal to the FG and is formed so as to straddle it, similar to the SG. Therefore, the potential barrier formed under the FG can be changed by the potential of the TG, similar to the SG. This can be particularly usefully utilized when performing multi-quantum bit operations in the vertical direction, which will be described later, or when performing a charge reading operation using a single electron transistor (SET) that exhibits highly sensitive operating characteristics with respect to charge. FIG. 9 shows a plan layout diagram of a quantum bit array according to an embodiment. In addition to the FG and SG, the arrangement of the TG is shown by a dotted line. Individual potentials can be applied to a plurality of TGs. In this quantum bit array, different operations can be performed on the formed quantum bits by controlling the signals applied to the plurality of gate electrodes. Also, the formed quantum bits can be shuttled (moved) along different paths.

[0044] In this embodiment, the TG is arranged so as to cover the quantum bit formed by being surrounded by two SGs and two FGs. The SG and TG exist in the same plane and are separated via an insulating film. Thereby, the SG and TG can be independently potential-controlled. As shown in FIG. 9, in the planar layout, the SG and TG are laid out in the same plane, and the TG is arranged to separate the SGs. FIG. 10 shows the cross-sectional structure of D - D' in FIG. 9. The TG is arranged so as to straddle the FG, similar to the SG. The potential of Q33 is more precisely controlled by the TG3 placed directly above it. That is, the potential of Q33 is mainly composed of FG3, FG4, TG3, the substrate electrode, and further capacitances (C FG3 、C FG4 、C TG3 、C SG3 (not shown), C SG4(not shown), it can be determined by capacitive coupling with Csub. Similar to TG, individual potentials can also be applied to SG and FG.

[0045] Also, as an example under the gate forming the barrier layer, regarding the potential barrier (B FG6 / TG3 ) at the intersection of FG6 and TG3, even if shown, similarly the capacitance (C TG3 , C FG6 , C TG3 , C SG3 (not shown), C SG4 (not shown) and Csub) can be determined by capacitive coupling.

[0046] By applying a predetermined microwave to the electrons confined in Q33 surrounded by the potential barrier, a single qubit operation can be performed. At this time, only the potential distribution of the target Q33 can be made different from that of other qubits, so the splitting width of the energy levels of Q33 can be made different from that of other qubits by the Stark effect due to the electric field. Therefore, by setting the frequency of the microwave so that resonance is obtained in the qubit of Q33, only this qubit can be selectively operated within the array.

[0047] Next, a method of operating electrons between adjacent qubits by arranging a plurality of intersecting gates in a mesh pattern for a plurality of qubits arranged in a two-dimensional array will be described.

[0048] First, as an operation between a plurality of qubits, consider the operation of moving an electron from Q32 to Q33 that sandwich SG3, that is, between two qubits sandwiching SG in the array and adjacent horizontally.

[0049] By applying a strong negative potential to FG3 and FG4, high potential barriers are induced above and below Q32 and Q33. This operation is in the same state as in FIG. 8 in the D-D' cross section of FIG. 9.

[0050] Figure 11A shows how each quantum dot can be individually configured as an electron-trapping site using a 3D device simulator. It is shown that the 4x4 quantum dots corresponding to Q11-Q44 in Figure 9 can be formed as potential depressions.

[0051] Furthermore, by applying a strong negative potential to SG2 and SG4, a high potential barrier is induced on both sides of Q32 and Q33. A positive potential is applied to TG3 compared to TG2 so that the potential of Q33 is lower than that of Q32. In this state, by applying a potential to SG3 so that the potential barrier between Q32 and Q33 created by SG3 is reduced or eliminated, a single electron that was in Q32 can be transferred to Q33.

[0052] Figure 11B shows the operation of the two qubits enclosed by the dashed line in Figure 11A in a coupled state. The potential barrier that separated the two qubits is removed, and it is shown that only specific two qubits can be selectively coupled.

[0053] Figure 11C shows the potential distribution near the silicon substrate surface along E-E' in Figure 9. At this time, by applying a positive potential to FG1, FG2, FG5, FG6, SG1, SG5, SG6, TG1, TG4, and TG5, the potentials of the other qubits are made lower than those of Q32 and Q33, so that they are not affected by operations performed between Q32 and Q33.

[0054] Figures 11A to 11C show that electrons can be moved between two quantum dots and that trapped electrons can interact with each other. Extending this operation, it can be seen that by using an array, qubits in regions unrelated to the operation can be relegated. This is achieved by lowering the potential of quantum dots in unwanted regions and raising the potential barrier forming the quantum dots, thereby avoiding the effects of the operation.

[0055] As explained using the electron transfer operation, this operation allows us to surround the outer perimeter of the two qubits Q32 and Q33 with a potential barrier. Therefore, by applying microwaves while controlling the potential of SG3, which acts as a barrier between the qubits, we can perform a two-qubit operation that enables interaction between the qubits.

[0056] Furthermore, by operating FG1, FG2, FG5, and FG6 in the same way as FG3 and FG4, the same operation as between Q32 and Q33—in this case, electron transfer—can be performed simultaneously between Q12-Q13, Q22-Q23, Q42-Q43, and Q52-Q53.

[0057] Next, consider the case of two qubits flanking an FG, that is, the operation of moving electrons from Q23 to Q33, which are adjacent to FG3 in the vertical direction of the paper in Figure 9, in an array. By applying a strong negative potential to FG2 and FG4, high potential barriers are induced above and below Q23 and Q33. Furthermore, by applying a strong negative potential to SG3 and SG4, high potential barriers are induced to the left and right of Q23 and Q33.

[0058] To perform a two-qubit operation between Q23 and Q33, it is necessary to lower the potential barrier created by FG3 between them. Therefore, since the potential barrier created by FG3 is lower, the potential barrier under FG3 can be increased by applying a strong negative potential to SG3 and SG4. As a result, even if a weak potential is applied to the FG3 separating Q23 and Q33, a high potential barrier can be formed around Q23 and Q33. In other words, since the potential barrier created by FG3 can be lowered, electron movement between Q23 and Q33 and two-qubit operations using microwaves can be performed.

[0059] According to this method, electron transfer and two-qubit operations can be performed between adjacent qubits in both the horizontal and vertical directions, as described above. To arrange and separate two qubits in the vertical and horizontal directions, it is necessary to have at least three orthogonal gate connections arranged at equal intervals. Furthermore, although two adjacent qubits were used here to explain the basic two-qubit operation, operations with multiple qubits, such as operations with three qubits, can be performed by forming a potential barrier with SG2 and SG5 to surround, for example, three qubits Q32, Q33, and Q34 between FG3 and FG4. With the method of this embodiment, quantum operations can be obtained with qubits arranged in a two-dimensional array.

[0060] Figures 11A to 11C illustrate a method for moving an electron from Q32 to Q33. In this case, the potential barrier is eliminated, and the electron is moved to a quantum dot with a lower potential. However, if the electron gains electrical energy through this movement, its previously held spin state may change. Therefore, another method for moving an electron while preserving its spin state is shown below.

[0061] Figure 12 is an explanatory diagram of the shuttle operation between two qubits according to an embodiment. Q32 and Q33 are set to maintain the same energy state, and the potential barrier separating Q32 and Q33 is set to a low state by biasing SG3. In this case, because the potential barrier is low, electrons held in Q32 can be moved to Q33 by a tunneling mechanism.

[0062] This movement mechanism does not involve a change in energy state, thus preserving the spin state. Here, the movement was manipulated by a gate electrode that creates a barrier between two qubits, but the same operation can also be achieved by controlling the relative barrier height by manipulating the potentials of the two quantum dots. Such a movement is called a shuttle operation and is one of the fundamental operations between qubits.

[0063] Figure 13 illustrates an alternative method of shuttle operation. Basically, this method involves applying a phase-shifted, for example, sinusoidal voltage to parallel gates to generate a traveling wave in the desired direction, thereby achieving electron movement. Figure 13 shows the potential changes of Q32 and Q33 during the shuttle operation.

[0064] The potential distribution shown by the dotted line 1301 represents the initial state where an electron is held in Q32. Next, by applying bias to SG2, SG3, SG4, and TG2, the potential valley that holds the electron is moved from Q32 towards Q33, as shown by the dashed line 1302. Furthermore, by applying potential to multiple gates, the potential valley is moved towards Q33, resulting in the potential distribution shown by the solid line 1303. During this operation, gate operations can be performed to maintain the potential shape in the region near the bottom of the potential valley, as shown by the hatching 1304 in Figure 13.

[0065] As shown by the dashed line 1302, the shape changes significantly in the high-potential region, but the potential shape near the ground level that traps the electron is maintained. Therefore, this operation allows for movement while preserving the spin state. This indicates that electrons in the ground state can be moved to the desired quantum dot, demonstrating that qubits can be initialized.

[0066] Next, we will demonstrate that the spin blockade operation, which is considered a fundamental operation of qubits using electron spin, can be performed with this embodiment structure. The spin blockade operation is an operation that converts the spin information of an electron into charge information by using Pauli's spin blockade law, which states that two electrons with the same spin state cannot occupy the same energy level.

[0067] Figure 14A shows the case where the ground state of the qubit is split by applying an upward external magnetic field from the bottom of the figure, resulting in an electron with upward spin being held in Q32 and an electron with downward spin being held in Q33. Due to the Zeeman splitting, Q32 is in a slightly higher energy state.

[0068] As shown in Figure 14B, if the potential barrier hindering Q32 and Q33 is lowered, allowing movement by tunneling, electrons can enter Q33 from Q32, thus enabling Q33 to have two electrons.

[0069] As shown in Figure 15A, if electrons with a downward spin state exist in both qubits, two electrons with the same spin state cannot enter Q33, and therefore the movement from Q32 to Q33 is blocked.

[0070] As shown in Figure 15B, even if the potential barrier is lowered, Q33 will maintain a state in which it holds one electron. In this way, in the structure of this embodiment, a spin-charge conversion operation can be performed to convert spin information into charge information.

[0071] Therefore, after performing this operation, by measuring the number of electrons in Q33 in a readout operation, it is possible to determine whether the spin state of the electrons present in Q32 was upward or downward. This operation will be explained in detail in a later example, after clearly illustrating the array structure according to this example based on the manufacturing process.

[0072] From the above, it is clear that the structure of this embodiment can perform all four basic operations required for a qubit: initialization, single-qubit operation, double-qubit operation, and readout operation. That is, by controlling the potentials of FG, SG, and TG, it is possible to perform at least one of the following: perform different operations on the formed qubit, or move the formed qubit along different paths.

[0073] This specification describes quantum computers using electron spin as the information carrier, but it is known that quantum computers can be constructed using hole spin instead of electrons as the information carrier. The manipulation of hole spin is known to be easy because spin-orbit interaction can be used. It is clear that a quantum computer system using hole spin as the information carrier can be obtained by reversing the polarity and applied voltage relationship of the semiconductor material described here.

[0074] As described above, in the embodiments of the present invention, in an integrated qubit in which multiple qubits are arranged in a two-dimensional array, multiple planar linear gate electrodes that control the operation of the qubits are arranged in a mesh pattern so as to intersect. By controlling the potential difference between gate electrodes, even if a specific potential is applied to one gate electrode, it becomes possible to perform different controls on the individual qubits connected to it. Therefore, it is possible to provide a method for performing all the operations necessary for qubit operation with multiple qubits formed in an array.

[0075] This method allows for the creation of a Si qubit array with complete two-dimensional scalability, thus enabling the realization of a highly practical quantum computer.

[0076] The embodiments will be described in more detail below with reference to the drawings. The positions, sizes, shapes, and ranges of each component shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0077] Using the planar layout diagram in Figure 16, a typical manufacturing method for a semiconductor device according to a specific embodiment is shown. For explanatory purposes, a 3x3 qubit array structure shown in the planar layout of Figure 16 is used. In the following Figures 17A to 20C, the structure in the F-F', G-G', H-H', and II' sections of Figure 16 at each step is shown as shown in the figures.

[0078] As shown in Figures 17A to 17D, phosphorus or boron is ion-implanted into the silicon substrate 100 and activated by annealing to form an n-type impurity diffusion layer region 201 and a p-type impurity diffusion layer region 302 (not shown as it does not appear in the illustrated cross-sectional structure). In this embodiment, it is also effective to use a silicon single crystal substrate 100 that has been purified to contain only silicon with 28 atoms by reducing the number of silicon isotopes (29) present in a typical silicon substrate, in order to lengthen the spin relaxation time.

[0079] As shown in Figures 18A to 18D, a 10 nm silicon oxide film 900 is formed over the entire surface of the substrate by thermal oxidation. A highly phosphorus-containing conductive silicon 10 is deposited to a thickness of 50 nm by CVD, and then a silicon oxide film 910 is deposited to a thickness of 50 nm by CVD. Using the first gate pattern with photolithography technology, the gate electrode 10, which was referred to as FG in the above explanation, is formed by dry etching.

[0080] As shown in Figures 19A to 19D, a silicon oxide film 920 is deposited at a thickness of 5 nm using the CVD method, and then a polycrystalline silicon 20 containing a high concentration of phosphorus and made conductive is deposited at a thickness of 50 nm. In the qubit array, the second gate SG, orthogonal to the FG, is patterned using photography, and the gate electrode 20 corresponding to the SG in the above description is processed from the polycrystalline silicon using a dry etching method. At this time, by performing a CMP (Chemical Mechanical Polishing) treatment before gate patterning to planarize the polycrystalline silicon layer before patterning, fine patterning can be made easier. Through this process, a gate insulating film of a different thickness from that of the FG can be formed on the SG.

[0081] As shown in Figures 20A to 20D, a silicon oxide film 930 is deposited at a thickness of 5 nm using the CVD method, and then a conductive polycrystalline silicon 30 containing a high concentration of phosphorus is deposited at a thickness of 50 nm. This allows the gate film thickness of the TG to be different from that of the FG and SG gate films.

[0082] Using photolithography technology, TGs are patterned and processed between SGs so that they are parallel to them. During this processing, by performing an etch-back process on polycrystalline silicon 30, the TGs can be formed self-aligned between SGs without the need for fine patterning, and the heights of the SGs and TGs can be made uniform, which facilitates subsequent processing.

[0083] Figure 21A shows the HH' cross-section of Figure 16. SG20 and TG30 are laid out on the same plane on the substrate with an insulating film in between. Figure 21B shows the I-I' cross-section of Figure 16.

[0084] As shown in Figures 21A and 21B, an oxide film with a thickness of 700 nm is deposited from the substrate using the CVD method, and then planarized using the CMP method. After that, contact holes are drilled in the necessary areas, and metal wiring such as tungsten or aluminum is formed. Although not shown in plan view 16 in the figure, metal wiring 60 is formed. These are normal LSI processes, and further explanation is omitted.

[0085] In Figures 21A and 21B, by aligning the heights of the second gate 20 and the third gate 30, the depth of the contact holes from the metal wiring layer 60 can be kept constant.

[0086] As shown in Figure 21C, even if the third gate 30 is formed to ride on top of the second gate 20, the same operation can be obtained as long as it is separated on the second gate 20.

[0087] Here, using Figures 22 to 24, we will explain why the structure of this embodiment is effective for reading out charge information.

[0088] Figure 22 is a redrawing of the plan view of the manufacturing process shown in Figure 16, showing the function of each gate electrode and the arrangement of qubits. The arrangement of FG, SG, TG and qubits is shown. The amount of charge on the central quantum dot, Q22, can be determined by operating Q23 as a single-electron transistor (SET) and determining the amount of current flowing along TG3 to read out the spin information. Here, by placing the TG parallel to the direction of extension of the SG and arranging the TGs to fill the spaces between multiple SGs, it is possible to determine the amount of current flowing along the TG closest to the target quantum dot and read out the spin information. The direction of extension of the TG is effective not only when performing multi-qubit operations in the vertical direction, but also when reading out spin information.

[0089] Figure 23 shows the horizontal potential distribution including Q22 and Q23 with a solid line, and the potential distribution below FG2 and FG3 with a dashed line. By applying a strong negative bias to SG2, SG3, and SG4, potential barriers are formed at each location. Electrons in Q22 are sandwiched between the barriers of SG2 and SG3 in the left-right direction. Also, in the up-down direction, as indicated by the higher position of the dashed line compared to the solid line, electrons are retained in Q22 due to the barriers created by FG2 and FG3. On the other hand, by making TG3 more negative than TG2, the potential of Q23 is increased compared to Q22. In this case, the difference between the solid and dashed lines becomes the vertical barrier to the qubit, but the height of the potential barrier of Q23 created by FG2 and FG3 is considerably lower than that of Q22.

[0090] Figure 24 illustrates this situation with potential distributions in the SG and TG directions. SG2, SG3, and SG4 create high barriers, blocking electron movement in the horizontal direction of Figure 9. In the potential distribution along TG2, FG creates a potential barrier, blocking electron movement in the vertical direction of Figure 9. On the other hand, in the potential barrier along TG3, FG2 and FG3 only create low potential barriers, allowing electrons to move. By adjusting the height of these vertical barriers using FG2, FG3, and TG3, the barriers can be made to pass through using tunneling, thus enabling the system to function as a SET. Therefore, the charge amount of Q22 can be read out using this SET.

[0091] Here, we focused on Q22 and Q23 in our explanation. In the structure of this embodiment, it is clear that the same procedure can be performed using any adjacent qubit, and readout operations can be performed on all qubits in the two-dimensional array.

[0092] Another example is shown in Figure 25. Instead of constructing a SET using the electrons described above and reading out the charge information, as shown in Figure 25, the SG can be connected to the P-type diffusion layer 202, and the charge amount can be read out by the hole current flowing through it. For example, the number of electrons held in Q22 can be amplified into a change in current by passing a hole current along the underside of the SG adjacent to the right side of Q22. Since the current path of holes acts in a direction that strengthens the potential barrier for electrons, the captured electrons can be stably held. Therefore, by using holes for captured electrons, the sensor can be placed closer, and thus the sensitivity can be increased.

[0093] Furthermore, a reflection measurement method is known that reads out the difference in charge amount as an impedance change of adjacent gate electrodes, instead of reading out by current. Reflection measurements can be performed using SG or TG. In this case, by applying RF signals of different frequencies to orthogonal FGs, the resonant frequency can be changed with respect to the extension direction of SG or TG. This makes it possible to obtain resolution for each individual bit from the superimposed reflection waveform of multiple bits connected in the direction of SG or TG.

[0094] Figure 26 shows a cross-sectional structure of another embodiment. The structure of this embodiment basically relates to the arrangement of multiple insulating gate electrodes formed on a flat semiconductor substrate. Therefore, instead of a silicon substrate, a substrate having a so-called "quantum well structure," as shown in Figure 26, may be used, in which a uniform silicon-germanium mixed crystal layer 170 and single-crystal silicon 175 are stacked near the surface of the silicon substrate using heteroepitaxial technology. This makes it possible to reduce noise from the interface.

[0095] Figure 27 shows an example of a qubit chip configuration. Here, to illustrate the connections with the surrounding environment, a representative example is shown with 3x3 9 qubits corresponding to Figure 22. Black circles represent contacts to the gate electrodes, and white circles represent contacts to the diffusion layer electrodes. Metal wiring to FG is shown with thin solid lines, metal wiring to SG with thin dotted lines, metal wiring to TG with thin dashed lines, and metal wiring to the diffusion layer electrodes with thin dashed lines. The chip consists of peripheral circuit sections such as electrode drivers formed on the outer periphery of the qubit array, and input / output sections and their control sections.

[0096] When integrating qubits and peripheral circuitry, the peripheral circuitry requires the application of conventional analog and digital circuitry technologies. In this case, digital circuits, in particular, require the use of CMOS technology, and transistor integration becomes essential. In that case, using the array structure of this embodiment presents a problem: it lacks an element isolation structure.

[0097] In that case, as shown in Figures 28 to 31 based on the manufacturing process, it is effective to form a chip with an element isolation region only in the peripheral area. Specifically, the element isolation region is formed by placing a thick oxide film called a field oxide film on the silicon substrate. As methods for forming the field oxide film, the LOCOS method, which selectively thermally oxidizes the silicon substrate, the shallow groove element isolation method, which forms shallow grooves on the substrate surface and fills them with silicon oxide film, or a method in which a thick oxide film is deposited over the entire substrate surface and the oxide film in the active region, which is other than the element isolation region, is known. In addition, a method called the field plate method, which forms an insulating gate electrode instead of a field oxide film, is also known. Here, the shallow groove element isolation method will be used for explanation, but any known element isolation method can be used.

[0098] Figures 28 to 31 schematically show the cross-sectional structure of the qubit array and its peripheral circuits, such as gate drivers, placed around its periphery, as shown in Figure 27. The peripheral regions are located on both sides of the qubit array region.

[0099] As shown in Figure 28, a silicon oxide film 901 is formed on the surface of the silicon substrate 100 as a 10 nm thermal oxide film, and a silicon nitride film 902 is deposited at a thickness of 100 nm by CVD.

[0100] As shown in Figure 29, the activation region and the qubit array region are protected using a known photolithography method, and the resist in the device isolation region is opened. A known dry etching method is used to form 300 nm shallow grooves in the silicon nitride film 902, the silicon oxide film 901, and the silicon substrate.

[0101] As shown in Figure 30, a silicon oxide film is deposited, planarized using the CMP method, the silicon nitride film 902 and silicon oxide film 901 are removed, and the element isolation oxide film 905 is placed at a desired position on the silicon substrate 100. This process is a technique known as shallow groove element isolation.

[0102] As shown in Figure 31, by using this substrate structure and performing the manufacturing process of the structure of this embodiment shown in Figures 17 to 21, the qubit array region and the peripheral region can be integrated and formed. Figure 31 shows an example in which the first gate FG is formed by sharing it as the gate electrode of the peripheral region.

[0103] As an alternative manufacturing method for Example 3, Figures 32 to 35 show a silicon substrate 100 that has been replaced with an SOI (Silicon On Insulator) substrate having a 200 nm silicon oxide film 950 and a silicon thin film layer 110 on a silicon substrate 120.

[0104] As shown in Figure 32, similar to Figure 28, a silicon oxide film 901 and a silicon nitride film 902, which are thermal oxide films, are deposited on the silicon thin film layer 110 of the SOI substrate, the active region is patterned, and the silicon nitride film 902, silicon oxide film 901, and silicon thin film layer 110 are etched to form shallow grooves.

[0105] As shown in Figure 33, the element isolation oxide film 905 is formed by deposition of a silicon oxide film and planarization by the CMP method, similar to Figure 30.

[0106] As shown in Figure 34, phosphorus and boron ions are implanted into the region that will become the diffusion layer electrode to form impurity regions. In this embodiment, impurity regions 201 and 202 are formed only in the qubit array region. Subsequently, the gate insulating film 900 and polycrystalline silicon are deposited by thermal oxidation and patterned to form the gate electrode 10.

[0107] As shown in Figure 35, a resist mask is applied to the transistor region in the peripheral area, and the necessary conductive impurities are doped by ion implantation. In this case, the gate electrode 10 can be used as a mask, so a MOSFET can be formed in the peripheral region by a normal self-alignment process.

[0108] Furthermore, this structure can also be applied to the vicinity of the array.

[0109] As shown by the thick lines indicating the outer boundary in the block diagram of Figure 36, by providing an element isolation region on the outer periphery of the qubit array, in the contact formation area, it is possible to prevent the occurrence of unintended charge leakage paths caused by bias settings between gates that wrap around the gate ends.

[0110] Figure 37 shows a specific planar arrangement near the array. The area indicated by the hatching at 980 in the figure is the active region, and a thick oxide film layer for device isolation is formed outside of it. Here, the TG gate is extended by placing an FG gate electrode 10 to connect the three vertically extending TG gates and the diffusion layer electrode 201. With the structure of this embodiment, the ends of all gate electrodes constituting the array, except for the gates directly connected to the diffusion layer, can be terminated in the device isolation region. Furthermore, since the device isolation region is formed at a location away from the qubits, it is clear that the impact on qubit performance can be avoided.

[0111] As another structure of this embodiment, a structure having a fourth gate on the channel substrate side will be described. In this embodiment, a qubit array with even better controllability than in Embodiment 1 can be realized by using an SOI substrate.

[0112] The planar arrangement example shown in Figure 38 is the same as Example 1 shown in Figure 9, except for QG. That is, in the planar arrangement of Figure 9, QG is placed between the lines of FG, parallel to FG.

[0113] Figure 39 shows the D-D' cross-section of Figure 36. In the QG, a fourth gate QG40 is formed beneath the silicon thin film layer 110 that traps electrons, controlling the silicon thin film layer 110 from below. By controlling the potential of FG and QG, the potential selectivity of the qubit between FG and FG can be increased in the vertical direction (direction perpendicular to FG). The manufacturing process will be explained below using Figures 40 to 44.

[0114] As shown in Figure 40, a 500 nm thick silicon oxide film 950 is formed on a silicon substrate 100. A known photolithography method is used to pattern the film and form grooves with a depth of 50 nm.

[0115] As shown in Figure 41, a polycrystalline silicon layer 40 is deposited by doping it with a high concentration of impurities to make it conductive.

[0116] As shown in Figure 42, a gate 40 is formed in the groove by flattening using the CMP method.

[0117] As shown in Figure 43, a 20 nm oxide film 960 is formed on the silicon thin film layer 110 of the SOI substrate 160. Then, the wafer is flipped over so that it faces the substrate formed in Figure 42, and the two layers are bonded together by applying heat treatment.

[0118] As shown in Figure 44, the silicon 160 and oxide film 970 of the bonded substrate are etched to obtain a silicon thin film layer 110. By performing the manufacturing process described in Figures 32 to 35 on this silicon thin film layer 110, the inventive structure of Example 5 can be obtained.

[0119] As shown in Figure 45, as a method of applying gate electrodes from above and below, FG and QG can be placed on the lower side and SG and TG on the upper side. After applying the manufacturing method for QG shown in Figure 42 to FG, QG can be formed between FG and FG. The steps from Figure 43 onwards can be carried out similarly, except for the FG manufacturing step in Example 5. In this case, SG and TG do not need to cross over FG, so they can be easily processed and formed.

[0120] To realize a quantum computer using qubits that utilize silicon electron spin, it is necessary to integrate a large number of qubits and to form many gates that control each of these qubits. However, the requirement to miniaturize the qubit that holds a single electron and the requirement to form multiple control gates that require a large space are conflicting requirements. In the embodiment described above, in an integrated qubit in which multiple qubits are arranged in a two-dimensional array, multiple planar linear gate electrodes that control the operation of the qubits are arranged in an intersecting network. By controlling the potential difference between gate electrodes, it becomes possible to apply different controls to individual qubits connected to a single gate electrode even if a specific potential is applied to it, and a quantum computer using this qubit can be realized.

[0121] According to the above embodiment, a quantum computer with a high degree of control freedom can be realized, resulting in lower energy consumption, reduced carbon emissions, prevention of global warming, and contribution to the realization of a sustainable society.

[0122] FG: First gate electrode, SG: Second gate electrode, TG: Third gate electrode, QG: Fourth gate electrode, Q: Qubit, a, b, c, d, e, a1, b1, c1, d12: Control gate, a2, b2, c2, e1, e2, 10, 20, 30, 40: Gate electrodes, 50: Contact hole, 60: Metal wiring, 150, 160, 175: Single crystal silicon, 170: Silicon germanium crystal layer, 201, 202: Diffusion layer electrodes, 900, 910, 920, 930, 940, 950, 960, 970, 980, 901: Silicon oxide film, 902: Silicon nitride film

Claims

1. An integrated semiconductor device comprising: at least three first gate electrodes arranged on an insulating film formed on a semiconductor substrate, extending in a first in-plane direction; at least three second gate electrodes arranged in a second direction perpendicular to the first direction; and a third gate electrode formed parallel to the second gate electrodes between a plurality of the second gate electrodes, wherein, in a plan view, the third gate electrode is positioned above the area surrounded by the plurality of the first gate electrodes and the plurality of the second gate electrodes.

2. An integrated semiconductor device according to claim 1, characterized in that the third gate electrode is arranged to cover the quantum dot formed at the said location.

3. An integrated semiconductor device according to claim 1, characterized in that the second gate electrode and the third gate electrode are separated by an insulating film.

4. An integrated semiconductor device according to claim 3, characterized in that the second gate electrode and the third gate electrode are independently given potential.

5. An integrated semiconductor device according to claim 3, characterized in that the third gate electrode separates a plurality of the second gate electrodes.

6. An integrated semiconductor device according to claim 5, characterized in that the third gate electrode and the second gate electrode are located in the same plane.

7. An integrated semiconductor device according to claim 6, characterized in that the third gate electrode and the second gate electrode are arranged in the same plane with an insulating film in between.

8. An integrated semiconductor device according to claim 1, characterized in that a plurality of third gate electrodes are supplied with individual potentials.

9. An integrated semiconductor device according to claim 1, wherein the second gate electrode is arranged across the first gate electrode, and the electric field effect is applied from both sides of the first gate electrode to change the electrical potential that the first gate electrode creates on the semiconductor surface via an insulating film.

10. An integrated semiconductor device according to claim 1, characterized in that both ends of the third gate electrode are connected to the diffusion layer electrode via a diffusion layer electrode or another gate electrode.

11. An integrated semiconductor device according to claim 1, characterized in that the charge of an electron held by a quantum dot formed below the third gate electrode in a plan view is read out by forming a single-electron transistor using the third gate electrode adjacent to the second gate electrode.

12. An integrated semiconductor device according to claim 1, characterized in that, by controlling the first gate electrode, the second gate electrode, and the third gate electrode, at least one of the following is performed: performing different operations on a formed qubit, and moving the formed qubit along different paths.

13. An integrated semiconductor device according to claim 1, wherein a first gate insulating film is provided below the first gate electrode, and a second gate insulating film is provided below the second gate electrode, characterized in that the thickness of the first gate insulating film and the second gate insulating film are different.

14. An integrated semiconductor device according to claim 1, characterized in that it has a plurality of third gate electrodes, and in a plan view, the plurality of third gate electrodes are separated at the position of the second gate electrode.

15. An integrated semiconductor device according to claim 1, characterized in that the at least three first gate electrodes are arranged at equal intervals and parallel to each other, and the at least three second gate electrodes are arranged at equal intervals and parallel to each other.

16. An integrated semiconductor device according to claim 1, characterized in that a quantum dot is formed by a region surrounded by an electrical potential barrier formed by the field effect of a plurality of first gate electrodes, a plurality of second gate electrodes, and a plurality of third gate electrodes.

17. An integrated semiconductor device characterized by integrating the integrated semiconductor device according to claim 1 and an outer peripheral portion for operating the integrated semiconductor device on a semiconductor substrate.

18. An integrated semiconductor device according to claim 17, characterized in that an element isolation region is formed between the integrated semiconductor device and the outer peripheral portion.

19. An integrated semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a second semiconductor layer formed on the first insulating film; a second insulating film formed on the second semiconductor layer; at least three equally spaced parallel first gate electrodes extending in a first in-plane direction within the first insulating film; at least three equally spaced parallel second gate electrodes arranged on the second insulating film in a direction parallel to the first direction; at least three equally spaced parallel third gate electrodes arranged in a direction perpendicular to the first direction, straddling the second gate electrodes; and at least two fourth gate electrodes formed between the third gate electrodes, wherein the third gate electrodes are arranged to cover a qubit formed by being surrounded by two of the second gate electrodes and two of the fourth gate electrodes.

20. A method for operating an integrated semiconductor device according to claim 1, characterized in that by applying a specific potential to the first gate electrode, the second gate electrode, and the third gate electrode, a specific qubit in the qubit array is given a different potential state from the other qubits in the qubit array, thereby making the resonance frequency of the electron spin in the specific qubit different from that of the other qubits.

21. A method for operating an integrated semiconductor device according to claim 1, characterized in that a first potential for electrons is formed on the outer periphery of two adjacent qubits in a qubit array by applying a specific potential to the first gate electrode, the second gate electrode, and the third gate electrode, and a quantum operation is performed between the two adjacent qubits by making the potential barrier between the two adjacent qubits lower than the first potential.

22. A method for operating an integrated semiconductor device according to claim 1, characterized in that the height of the potential barrier formed by the electric field effect on the first gate electrode is effectively changed by applying an electric field effect from both sides of the first gate electrode with the second gate electrode formed so as to straddle the first gate electrode.

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