Frequency detection device, frequency detection method, and frequency detection circuit

Abstract

A frequency detection device (7) comprises: a data thinning-out unit (10) that extracts, as first thinned-out data, data of every other sample from a sample sequence of quantized data, which is a signal obtained by quantizing a signal to be measured, and extracts the remaining data as second thinned-out data; a frequency / phase calculation unit (11) that calculates the frequency of the first thinned-out data and the phase of the first thinned-out data; a phase difference calculation unit (12) that calculates the phase of the second thinned-out data and calculates the phase difference between the phase of the first thinned data and the phase of the second thinned data; a phase difference calibration unit (13) that acquires calibration data corresponding to the phase difference and calibrates the phase difference in accordance with the calibration data; a folding order calculation unit (14) that calculates the Nyquist folding order of the first thinned data on the basis of the calibrated phase difference; and a frequency calculation unit (15) that uses the frequency and the Nyquist folding order to calculate the frequency of the signal to be measured.

Description

Frequency detection device, frequency detection method, and frequency detection circuit

[0001] This disclosure relates to a frequency detection device, a frequency detection method, and a frequency detection circuit.

[0002] There is a frequency detection circuit that calculates the frequency of a signal to be measured. As such a frequency detection circuit, for example, Patent Document 1 discloses a frequency detection circuit comprising a first sample-and-hold circuit, a second sample-and-hold circuit, and a frequency calculation circuit. The first sample-and-hold circuit undersamples the signal to be measured using a first clock signal and outputs the signal to be measured after undersampling. The second sample-and-hold circuit undersamples the signal to be measured using a second clock signal that has the same frequency as the first clock signal but a different phase from the first clock signal, and outputs the signal to be measured after undersampling. The frequency calculation circuit comprises a first quantizer that quantizes the output signal of the first sample-and-hold circuit and outputs first quantized data, which is the signal after quantization, and a second quantizer that quantizes the output signal of the second sample-and-hold circuit and outputs second quantized data, which is the signal after quantization. The frequency calculation circuit calculates the frequency of the first quantized data, calculates the order of undersampling for the signal under test from the phase difference between the phase of the first quantized data and the phase of the second quantized data, and calculates the frequency of the signal under test from the frequency of the first quantized data and the order of undersampling.

[0003] International Publication No. 2020-152764

[0004] The frequency detection circuit disclosed in Patent Document 1 had the problem that it required the implementation of a first sample-and-hold circuit and a second sample-and-hold circuit before the frequency calculation circuit.

[0005] This disclosure was made to solve the above-mentioned problems, and aims to provide a frequency detection device that can calculate the frequency of a signal under measurement without implementing two sample-and-hold circuits.

[0006] The frequency detection device according to this disclosure includes: a data decimation unit that extracts every other sample data from a sample sequence of quantized data, where the signal to be measured is a quantized signal, as first decimated data, and extracts the remaining data as second decimated data; a frequency-phase calculation unit that calculates the frequency and phase of the first decimated data extracted by the data decimation unit; and a phase difference calculation unit that calculates the phase of the second decimated data extracted by the data decimation unit and calculates the phase difference between the phase of the first decimated data and the phase of the second decimated data. The frequency detection device also includes: a phase difference calibration unit that acquires calibration data corresponding to the phase difference calculated by the phase difference calculation unit and calibrates the phase difference according to the calibration data; an aliasing order calculation unit that calculates the Nyquist aliasing order of the first decimated data based on the phase difference after calibration by the phase difference calibration unit; and a frequency calculation unit that calculates the frequency of the signal to be measured using the frequency calculated by the frequency-phase calculation unit and the Nyquist aliasing order calculated by the aliasing order calculation unit.

[0007] According to this disclosure, the frequency of the signal under test can be calculated without implementing two sample-and-hold circuits.

[0008] This is a diagram showing a frequency detection circuit including a frequency detection device 7 according to Embodiment 1. This is a hardware diagram showing the hardware of the frequency detection device 7 according to Embodiment 1. This is a hardware diagram of a computer when the frequency detection device 7 is implemented by software or firmware, etc. This is a flowchart showing the frequency detection method, which is the processing procedure of the frequency detection device 7. This is an explanatory diagram showing a sample sequence of the delayed clock signal output from the first delay circuit 3 to the first T / H circuit 4, the doubled clock signal output from the multiplier 5 to the quantizer 6, the signal to be measured given to the first T / H circuit 4, and the quantized data output from the quantizer 6. This is an explanatory diagram showing the frequency of the clock signal, the Nyquist frequency, and the Nyquist zone. Calibration data θ ｃａｌ (f ｏｕｔ ) and phase difference Δθ ｃｌｋ This is an explanatory diagram illustrating an example. Calibration data θ for each phase difference Δθ.ｃａｌ (f ｏｕｔ ) and the phase difference Δθ ｃｌｋ is an explanatory diagram showing them. It is a configuration diagram showing a frequency detection circuit including the frequency detection device 7 according to Embodiment 2. It is a hardware configuration diagram showing the hardware of the frequency detection device 7 according to Embodiment 2. The frequency f ｏｕｔｍ (m = 1, ···, M) when the first calibration quantization data is given to the data decimation unit 10, the frequency f ｏｕｔｍ of the first phase difference Δθ １，ｍ is an explanatory diagram showing the linear interpolation result. The frequency f ｏｕｔｍ (m = 1, ···, M) when the nth calibration quantization data is given to the data decimation unit 10, the frequency f ｏｕｔｍ (m = 1, ···, M) of the second phase difference Δθ ２，ｍ is an explanatory diagram showing the linear interpolation result. It is a configuration diagram showing a frequency detection circuit including the frequency detection device 7 according to Embodiment 3. The delayed clock signal output from the first delay circuit 3 to the first track-and-hold circuit 4, the delayed clock signal output from the second delay circuit 3a to the second track-and-hold circuit 4a, the doubled clock signal output from the doubler 5 to the quantizer 6, the measurement signal applied to the first track-and-hold circuit 4, and the sample sequence of the quantization data output from the quantizer 6 are shown in the explanatory diagram.

[0009] Hereinafter, in order to explain the present disclosure in more detail, embodiments for implementing the present disclosure will be described according to the attached drawings.

[0010] Embodiment 1. FIG. 1 is a configuration diagram showing a frequency detection circuit including the frequency detection device 7 according to Embodiment 1. FIG. 2 is a hardware configuration diagram showing the hardware of the frequency detection device 7 according to Embodiment 1. The frequency detection circuit shown in FIG. 1 includes a quantization unit 1 and a frequency detection device 7.

[0011] The quantization unit 1 includes a clock signal source 2, a first delay circuit 3, a first track-and-hold circuit (hereinafter referred to as "the first T / H circuit") 4, a doubler 5, and a quantizer 6. The quantization unit 1 quantizes the measurement signal and outputs quantization data, which is the measured signal after quantization, to the frequency detection device 7.

[0012] The clock signal source 2 is implemented, for example, by a voltage-controlled oscillator, a crystal oscillator, or a general-purpose signal generator. The clock signal source 2 has a frequency f ｃｌｋ The clock signal is generated and output to the first delay circuit 3 and the frequency multiplier 5, respectively. The first delay circuit 3 delays the clock signal output from the clock signal source 2 by a first delay time τ １ The clock signal is delayed by a certain amount, and the delayed clock signal is output to the first T / H circuit 4.

[0013] The first T / H circuit 4 uses the clock signal output from the first delay circuit 3 to temporarily hold the given signal under test and outputs either the held signal under test or the given signal under test to the quantizer 6. Specifically, the first T / H circuit 4 holds the signal under test at the timing when the clock signal changes from L level to H level for the period until the clock signal changes to L level. The first T / H circuit 4 outputs the held signal under test to the quantizer 6 while the clock signal is at H level, and outputs the given signal under test to the quantizer 6 as is while the clock signal is at L level.

[0014] The frequency multiplier 5 receives the frequency f output from the clock signal source 2. ｃｌｋ The clock signal is doubled. The multiplier 5 uses a frequency of 2f as the clock signal after doubling. ｃｌｋ The clock signal is output to the quantizer 6. The quantizer 6 is implemented, for example, by an ADC (Analog to Digital Converter). The quantizer 6 receives the frequency 2f output from the frequency multiplier 5. ｃｌｋ The clock signal is used to quantize the signal to be measured output from the first T / H circuit 4. The quantizer 6 outputs the quantized data, which is the signal to be measured after quantization, to the frequency detection device 7.

[0015] The frequency detection device 7 includes a data decimation unit 10, a frequency phase calculation unit 11, a phase difference calculation unit 12, a phase difference calibration unit 13, an aliasing order calculation unit 14, a frequency calculation unit 15, and a calibration data storage unit 16. The data decimation unit 10 is implemented, for example, by the data decimation circuit 20 shown in Figure 2. The data decimation unit 10 acquires quantized data from the quantizer 6. The data decimation unit 10 extracts every other sample from the sample sequence of quantized data as first decimated data, and extracts the remaining data as second decimated data. Each set of decimated data is a sample sequence containing every other sample. The data decimation unit 10 outputs the first decimated data to the frequency phase calculation unit 11 and the second decimated data to the phase difference calculation unit 12.

[0016] The frequency phase calculation unit 11 is implemented, for example, by the frequency phase calculation circuit 21 shown in Figure 2. The frequency phase calculation unit 11 acquires first decimated data from the data decimation unit 10. The frequency phase calculation unit 11 calculates the frequency f of the first decimated data. ｏｕｔ and the phase θ of the first decimated data ｏｕｔ１ Each of these is calculated. Specifically, the frequency phase calculation unit 11 converts the first decimated data into a signal in the frequency domain, and calculates the frequency f of the first decimated data from the frequency bin of the peak frequency component in the signal in the frequency domain. ｏｕｔ and the phase θ of the first decimated data ｏｕｔ１ Each of these is identified. The frequency phase calculation unit 11 calculates the frequency f of the first decimated data. ｏｕｔ The frequency calculation unit 15 outputs information indicating the phase θ of the first decimated data. ｏｕｔ１ Information indicating this is output to the phase difference calculation unit 12.

[0017] The phase difference calculation unit 12 is implemented, for example, by the phase difference calculation circuit 22 shown in Figure 2. The phase difference calculation unit 12 acquires second decimated data from the data decimation unit 10 and the phase θ of the first decimated data from the frequency phase calculation unit 11. ｏｕｔ１ Information indicating this is obtained. The phase difference calculation unit 12 calculates the phase θ of the second decimated data. ｏｕｔ２Specifically, the phase difference calculation unit 12 converts the second decimated data into a frequency domain signal and calculates the phase θ of the second decimated data from the frequency bins of the peak frequency components in the frequency domain signal. ｏｕｔ２ The phase difference calculation unit 12 identifies the phase θ of the first decimated data. ｏｕｔ１ and the phase θ of the second decimated data ｏｕｔ２ The phase difference Δθ is calculated. The phase difference calculation unit 12 outputs information indicating the phase difference Δθ to the phase difference calibration unit 13.

[0018] The phase difference calibration unit 13 is implemented, for example, by the phase difference calibration circuit 23 shown in Figure 2. The phase difference calibration unit 13 acquires information indicating the phase difference Δθ from the phase difference calculation unit 12. The phase difference calibration unit 13 acquires calibration data θ corresponding to the phase difference Δθ from the calibration data storage unit 16. ｃａｌ (f ｏｕｔ The phase difference calibration unit 13 obtains the calibration data θ. ｃａｌ (f ｏｕｔ The phase difference Δθ is calibrated according to the following. The phase difference calibration unit 13 calibrates the phase difference Δθ after calibration. ｃａｌ Information indicating this is output to the loopback order calculation unit 14.

[0019] The aliasing order calculation unit 14 is implemented, for example, by the aliasing order calculation circuit 24 shown in Figure 2. The aliasing order calculation unit 14 receives the phase difference Δθ after calibration from the phase difference calibration unit 13. ｃａｌ Information indicating the phase difference Δθ is obtained from the calibration data storage unit 16. ｃｌｋ Information indicating the phase difference Δθ is obtained. ｃｌｋ Δθ is the phase difference between the phase of a first calibration signal having a frequency in the first-order Nyquist region and the phase of an nth calibration signal having a frequency in the nth-order Nyquist region. n is an integer greater than or equal to 2. The frequencies of the first calibration signal and the nth calibration signal are the same. The aliasing order calculation unit 14 calculates the phase difference Δθ after calibration by the phase difference calibration unit 13. ｃａｌ Based on this, the Nyquist aliasing order Fo of the quantized data is calculated and the Nyquist aliasing order Fo is output to the frequency calculation unit 15. Specifically, the aliasing order calculation unit 14 calculates the phase difference Δθ ｃｌｋ Phase difference Δθ ｃｌｋThe function is divided by , and the result of that division is output to the frequency calculation unit 15 as the Nyquist aliasing order Fo.

[0020] The frequency calculation unit 15 is implemented, for example, by the frequency calculation circuit 25 shown in Figure 2. The frequency calculation unit 15 receives the frequency f of the first decimated data from the frequency phase calculation unit 11. ｏｕｔ The unit obtains information indicating the following, and the Nyquist aliasing order Fo is obtained from the aliasing order calculation unit 14. The frequency calculation unit 15 calculates the frequency f of the first decimated data. ｏｕｔ Using the Nyquist aliasing order Fo, the frequency f of the signal under measurement is used. ＲＦ Calculate.

[0021] The calibration data storage unit 16 is implemented, for example, by the calibration data storage circuit 26 shown in Figure 2. The calibration data storage unit 16 stores calibration data θ corresponding to the phase difference Δθ. ｃａｌ (f ｏｕｔ ) and the phase difference Δθ ｃｌｋ It stores the following. The frequency detection device 7 shown in Figure 1 has a built-in calibration data storage unit 16. However, this is just one example, and the calibration data storage unit 16 may be provided outside the frequency detection device 7.

[0022] In Figure 1, it is assumed that the components of the frequency detection device 7—the data decimation unit 10, the frequency phase calculation unit 11, the phase difference calculation unit 12, the phase difference calibration unit 13, the aliasing order calculation unit 14, the frequency calculation unit 15, and the calibration data storage unit 16—are each implemented by dedicated hardware as shown in Figure 2. Specifically, it is assumed that the frequency detection device 7 is implemented by a data decimation circuit 20, a frequency phase calculation circuit 21, a phase difference calculation circuit 22, a phase difference calibration circuit 23, an aliasing order calculation circuit 24, a frequency calculation circuit 25, and a calibration data storage circuit 26.

[0023] The calibration data storage circuit 26 may include, for example, non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), magnetic disks, flexible disks, optical disks, compact disks, minidiscs, or DVDs (Digital Versatile Discs). Furthermore, each of the data decimation circuit 20, frequency phase calculation circuit 21, phase difference calculation circuit 22, phase difference calibration circuit 23, aliasing order calculation circuit 24, and frequency calculation circuit 25 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0024] The components of the frequency detection device 7 are not limited to those implemented by dedicated hardware; the frequency detection device 7 may also be implemented by software, firmware, or a combination of software and firmware. The software or firmware is stored as a program in the computer's memory. A computer refers to the hardware that executes the program, and includes, for example, a CPU (Central Processing Unit), GPU (Graphics Processing Unit), central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor).

[0025] Figure 3 is a hardware configuration diagram of a computer when the frequency detection device 7 is implemented by software or firmware. When the frequency detection device 7 is implemented by software or firmware, the calibration data storage unit 16 is configured on the computer's memory 31. Programs that cause the computer to execute the respective processing procedures in the data decimation unit 10, frequency phase calculation unit 11, phase difference calculation unit 12, phase difference calibration unit 13, aliasing order calculation unit 14, and frequency calculation unit 15 are stored in the memory 31. The computer's processor 32 then executes the programs stored in the memory 31.

[0026] Furthermore, Figure 2 shows an example in which each component of the frequency detection device 7 is implemented by dedicated hardware, and Figure 3 shows an example in which the frequency detection device 7 is implemented by software or firmware. However, this is merely one example, and some components of the frequency detection device 7 may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware.

[0027] Next, the operation of the frequency detection circuit shown in Figure 1 will be explained. Figure 4 is a flowchart of the frequency detection method, which is the processing procedure of the frequency detection device 7. Figure 5 is an explanatory diagram showing a sample sequence of the delayed clock signal output from the first delay circuit 3 to the first T / H circuit 4, the doubled clock signal output from the multiplier 5 to the quantizer 6, the signal to be measured applied to the first T / H circuit 4, and the quantized data output from the quantizer 6.

[0028] The clock signal source 2 has a frequency f ｃｌｋ The clock signal is generated and output to the first delay circuit 3 and the frequency multiplier 5, respectively. When the first delay circuit 3 receives the clock signal from the clock signal source 2, it delays the clock signal by a first delay time τ, as shown in Figure 5. １ The clock signal is delayed by a certain amount, and the delayed clock signal (labeled "T / H clock" in Figure 5) is output to the first T / H circuit 4.

[0029] The first T / H circuit 4 holds the signal under test at the timing when the delayed clock signal from the first delay circuit 3 changes from L level to H level, for the period until the clock signal changes to L level. As shown in Figure 5, the first T / H circuit 4 outputs the held signal under test (the signal in Hold mode in the figure) to the quantizer 6 during the period when the delayed clock signal is at H level. As shown in Figure 5, the first T / H circuit 4 outputs the given signal under test (the signal in Track mode in the figure) to the quantizer 6 as is during the period when the delayed clock signal is at L level.

[0030] The frequency multiplier 5 receives the frequency f output from the clock signal source 2. ｃｌｋ The clock signal is doubled. The multiplier 5 uses a frequency of 2f as the doubled clock signal, as shown in Figure 5. ｃｌｋ The clock signal (labeled "quantization clock" in Figure 5) is output to the quantizer 6. As shown in Figure 5, the quantizer 6 outputs the frequency 2f from the frequency multiplier 5. ｃｌｋ The clock signal is used to quantize the signal to be measured output from the first T / H circuit 4. The quantizer 6 outputs the quantized data, which is the signal to be measured after quantization, to the data decimation unit 10. In the example in Figure 5, the sample sequence of quantized data is represented as s0, s1, s2, s3, ... In the figure, the circles and black dots represent the sample points of the signal to be measured by the quantizer 6.

[0031] Here, the frequency f of the signal under measurement ＲＦ However, the frequency of the clock signal used by the quantizer 6 is 2f ｃｌｋ The Nyquist frequency f is half the frequency of f. ｃｌｋ If it is higher than this, a phenomenon called aliasing occurs. As a result, the frequency f of the first decimated data calculated by the frequency phase calculation unit 11 ｏｕｔ The calculation result is the Nyquist frequency f ｃｌｋ This indicates frequencies that exist in the first Nyquist zone, which is lower than the specified frequency.

[0032] Figure 6 is an explanatory diagram showing the frequency, Nyquist frequency, and Nyquist zone of the clock signal. In the example in Figure 6, the frequency of the clock signal is 2f ｃｌｋ Since is α [MHz], the Nyquist frequency f ｃｌｋ The frequency is α / 2 [MHz]. The first Nyquist zone is the bandwidth from DC (direct current) to α / 2 [MHz], the second Nyquist zone is the bandwidth from α / 2 [MHz] to α [MHz], the third Nyquist zone is the bandwidth from α [MHz] to 3α / 2 [MHz], the fourth Nyquist zone is the bandwidth from 3α / 2 [MHz] to 2α [MHz], and the fifth Nyquist zone is the bandwidth from 2α [MHz] to 5α / 2 [MHz]. The frequency f of the signal under measurement ＲＦ However, if the frequency is in the second to fifth Nyquist zones, the frequency f of the first decimated data calculated by the frequency phase calculation unit 11 ｏｕｔ The calculation result indicates the frequencies present in the first Nyquist zone.

[0033] The data decimation unit 10 acquires quantized data from the quantizer 6. The data decimation unit 10 extracts every other sample from the sample sequence of quantized data as first decimated data, and extracts the remaining data as second decimated data (step ST1 in Figure 4). If the sample sequence of quantized data is s0, s1, s2, s3, ..., the first decimated data will be a sample sequence such as s0, s2, s4, s6, ... and the second decimated data will be a sample sequence such as s1, s3, s5, s7, .... The data decimation unit 10 outputs the first decimated data to the frequency phase calculation unit 11 and the second decimated data to the phase difference calculation unit 12.

[0034] The frequency phase calculation unit 11 obtains first decimated data from the data decimation unit 10. The frequency phase calculation unit 11 converts the first decimated data into a frequency domain signal, for example, by performing an FFT (Fast Fourier Transform) on the first decimated data. The frequency phase calculation unit 11 calculates the frequency f of the first decimated data from the frequency bins of the frequency components of the peaks in the frequency domain signal. ｏｕｔand the phase θ of the first decimated data ｏｕｔ１ Identify each of them (step ST2 in Figure 4). From the frequency bin of the peak frequency component, the frequency f of the first decimated data. ｏｕｔ and the phase θ of the first decimated data ｏｕｔ１ The process of identifying each of these is a well-known technique, so a detailed explanation will be omitted. The frequency phase calculation unit 11 calculates the frequency f of the first decimated data. ｏｕｔ The frequency calculation unit 15 outputs information indicating the phase θ of the first decimated data. ｏｕｔ１ Information indicating this is output to the phase difference calculation unit 12.

[0035] The phase difference calculation unit 12 acquires second decimated data from the data decimation unit 10, and the phase θ of the first decimated data from the frequency phase calculation unit 11. ｏｕｔ１ Information indicating this is obtained. The phase difference calculation unit 12 converts the second decimated data into a frequency domain signal by, for example, performing an FFT on the second decimated data. The phase difference calculation unit 12 calculates the phase θ of the second decimated data from the frequency bins of the frequency components of the peaks in the frequency domain signal. ｏｕｔ２ Identify the phase θ of the second decimated data from the frequency bin of the peak frequency component. ｏｕｔ２ The process of identifying the phase difference is a well-known technique, so a detailed explanation will be omitted. The phase difference calculation unit 12 calculates the phase θ of the first decimated data as shown in the following equation (1). ｏｕｔ１ and the phase θ of the second decimated data ｏｕｔ２ The phase difference Δθ is calculated (step ST3 in Figure 4). Δθ = θ ｏｕｔ２ -θout1 (1) The phase difference calculation unit 12 outputs information indicating the phase difference Δθ to the phase difference calibration unit 13.

[0036] The calibration data storage unit 16 stores calibration data θ corresponding to the phase difference Δθ. ｃａｌ (f ｏｕｔ ) and the phase difference Δθ ｃｌｋ And is stored. Figure 7, Calibration data θ ｃａｌ (f ｏｕｔ ) and phase difference Δθ ｃｌｋ This is an explanatory diagram illustrating an example. In Figure 7, the horizontal axis represents the frequency f of the first decimated data. ｏｕｔwhere the vertical axis is the phase θ of the first decimation data ｏｕｔ１ and the phase θ of the second decimation data ｏｕｔ２ and the phase difference Δθ therebetween. In FIG. 7, the phase difference Δθ with respect to the frequency f ｏｕｔ of the first decimation data is shown when a calibration signal existing in the first Nyquist zone is given as a measurement signal to the first T / H circuit 4 ｏｕｔ The phase difference Δθ with respect to the frequency f ｏｕｔ of the first decimation data is, for example, when f １ is Δθ １ The calibration data θ ｃａｌ (f ｏｕｔ ) is expressed as in the following formula (2).

[0037] In the calibration data storage unit 16, as shown in FIG. 8, calibration data θ ｃａｌ (f ｏｕｔ ) corresponding to each of a plurality of different phase differences Δθ is stored. FIG. 8 is an explanatory diagram showing the calibration data θ ｃａｌ (f ｏｕｔ ) and the phase difference Δθ ｃｌｋ for each phase difference Δθ

[0038] Also, in FIG. 7, the phase difference Δθ ｏｕｔ exists in the second Nyquist zone and the folded frequency is the same as the frequency f １ The phase difference Δθ with respect to the frequency f ｏｕｔ of the first decimation data is shown when a calibration signal is given as a measurement signal to the first T / H circuit 4 ｏｕｔ The phase difference Δθ when the frequency f １ of the first decimation data is, for example, f is Δθ ２ Also, in FIG. 7, the phase difference Δθ １ and the phase difference Δθ ２ and the phase difference Δθ ｃｌｋ which is the difference therebetween is shown. The phase difference Δθ ｃｌｋ corresponds to the sampling phase difference between the first decimation data and the second decimation data. In the calibration data storage unit 16, as shown in FIG. 8, a phase difference Δθ ｃｌｋIt is remembered.

[0039] The phase difference calibration unit 13 acquires information indicating the phase difference Δθ from the phase difference calculation unit 12. The phase difference calibration unit 13 acquires calibration data θ corresponding to the phase difference Δθ from the calibration data storage unit 16. ｃａｌ (f ｏｕｔ ) is obtained. The phase difference Δθ is, for example, Δθ １ If so, Δθ １ Corresponding calibration data θ ｃａｌ (f ｏｕｔ ) １ The following is obtained, and the phase difference Δθ is, for example, Δθ ２ If so, Δθ ２ Corresponding calibration data θ ｃａｌ (f ｏｕｔ ) ２ The following is obtained. The phase difference calibration unit 13 obtains calibration data θ as shown in the following equation (3). ｃａｌ (f ｏｕｔ The phase difference Δθ is calibrated according to (step ST4 in Figure 4). The phase difference calibration unit 13 then calibrates the phase difference Δθ after calibration. ｃａｌ Information indicating this is output to the loopback order calculation unit 14.

[0040]

[0041] The folding order calculation unit 14 receives the phase difference Δθ after calibration from the phase difference calibration unit 13. ｃａｌ Information indicating the following is obtained. The folding order calculation unit 14 calculates the phase difference Δθ corresponding to the phase difference Δθ. ｃｌｋ Information indicating this is obtained. The folding order calculation unit 14 calculates the phase difference Δθ as shown in the following equation (4). ｃａｌ Phase difference Δθ ｃｌｋ The Nyquist aliasing order Fo is calculated by dividing by (step ST5 in Figure 4). The aliasing order calculation unit 14 outputs the Nyquist aliasing order Fo to the frequency calculation unit 15.

[0042]

[0043] The frequency calculation unit 15 receives the frequency f of the quantized data from the frequency phase calculation unit 11. ｏｕｔInformation indicating the frequency is obtained. The frequency calculation unit 15 obtains the Nyquist aliasing order Fo from the aliasing order calculation unit 14. The frequency f of the clock signal oscillated by the clock signal source 2 ｃｌｋ Information indicating this is stored, for example, in the internal memory of the frequency calculation unit 15. Alternatively, the frequency f ｃｌｋ Information indicating this is provided to the frequency calculation unit 15 from outside the frequency detection device 7, for example.

[0044] If the Nyquist aliasing order Fo is 0 or greater (in step ST6: YES in Figure 4), the frequency calculation unit 15 calculates the frequency f of the clock signal as shown in the following equation (5): the Nyquist aliasing order Fo and the frequency f of the clock signal. ｃｌｋ The result of multiplying by the frequency f of the first decimated data ｏｕｔ By adding this, the frequency f of the signal under measurement is obtained. ＲＦ The frequency calculation unit 15 calculates the frequency f of the clock signal, as shown in equation (6) below, if the Nyquist aliasing order Fo is negative (step ST6 in Figure 4: NO). ｃｌｋ From the result of multiplication, the frequency f of the first decimated data is ｏｕｔ By subtracting the frequency f of the signal under measurement, ＲＦ The frequency f of the signal under test is calculated (step ST8 in Figure 4). ＲＦ Information indicating this is provided, for example, to a signal processing device (not shown) or a display device (not shown).

[0045]

[0046] In the above embodiment 1, the frequency detection device 7 is configured to include a data decimation unit 10 that extracts every other sample data as first decimated data and the remaining data as second decimated data from a sample sequence of quantized data, the signal to be measured being a quantized signal; a frequency-phase calculation unit 11 that calculates the frequency and phase of the first decimated data extracted by the data decimation unit 10; and a phase difference calculation unit 12 that calculates the phase of the second decimated data extracted by the data decimation unit 10 and calculates the phase difference between the phase of the first decimated data and the phase of the second decimated data. Furthermore, the frequency detection device 7 includes a phase difference calibration unit 13 that acquires calibration data corresponding to the phase difference calculated by the phase difference calculation unit 12 and calibrates the phase difference according to the calibration data, an aliasing order calculation unit 14 that calculates the Nyquist aliasing order of the first decimated data based on the phase difference after calibration by the phase difference calibration unit 13, and a frequency calculation unit 15 that calculates the frequency of the signal under test using the frequency calculated by the frequency phase calculation unit 11 and the Nyquist aliasing order calculated by the aliasing order calculation unit 14.Therefore, the frequency detection device 7 can calculate the frequency of the signal under test without implementing two sample-and-hold circuits.

[0047] Embodiment 2. Embodiment 2 describes a frequency detection device 7 that includes a calibration data calculation unit 17 for calculating calibration data.

[0048] Figure 9 is a configuration diagram showing a frequency detection circuit including a frequency detection device 7 according to Embodiment 2. In Figure 9, the same reference numerals as in Figure 1 indicate the same or corresponding parts, so a detailed explanation is omitted. Figure 10 is a hardware configuration diagram showing the hardware of the frequency detection device 7 according to Embodiment 2. In Figure 10, the same reference numerals as in Figure 2 indicate the same or corresponding parts, so a detailed explanation is omitted. The frequency detection device 7 shown in Figure 9 includes a data decimation unit 10, a frequency phase calculation unit 11, a phase difference calculation unit 12, a phase difference calibration unit 13, an aliasing order calculation unit 14, a frequency calculation unit 15, a calibration data storage unit 16, and a calibration data calculation unit 17.

[0049] In the frequency detection circuit shown in Figure 9, a first calibration signal and an nth calibration signal are sequentially supplied to the first T / H circuit 4 before the signal to be measured is supplied to the first T / H circuit 4. n is an integer of 2 or more. The first calibration signal is a calibration signal having a frequency in the first-order Nyquist region, and the nth calibration signal is a calibration signal having a frequency in the nth-order Nyquist region. The first calibration signal and the nth calibration signal are signals supplied to calculate calibration data to be stored in the calibration data storage unit 16.

[0050] The calibration data calculation unit 17 is implemented, for example, by the calibration data calculation circuit 27 shown in Figure 10. The calibration data calculation unit 17 calculates the calibration data θ by the phase difference calculation unit 12 when the first calibration signal is provided to the first T / H circuit 4 instead of the signal under measurement, and the first calibration quantized data, which is a signal obtained by quantizing the first calibration signal, is provided to the data decimation unit 10, and the phase difference calculated by the phase difference calculation unit 12 is used to calculate the calibration data θ. ｃａｌ (f ｏｕｔ ) is calculated as follows. Specifically, the calibration data calculation unit 17 calculates the frequency f from among M first calibration quantization data with different frequencies. ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the phase difference calculated by the phase difference calculation unit 12 is the calibration data θ ｃａｌ (f ｏｕｔ ) ｍ It is calculated as follows: M is an integer greater than or equal to 2.

[0051] The calibration data calculation unit 17 calculates the calibration data θ ｃａｌ (f ｏｕｔ ) ｍIn addition to calculating the above, the phase difference between the calibration signals, which is the difference between the first phase difference and the second phase difference, is calculated. The first phase difference is the phase difference between the phase of the first decimated data extracted by the data decimation unit 10 and the phase of the second decimated data extracted by the data decimation unit 10 when the first calibration quantized data is given to the data decimation unit 10. The second phase difference is the phase difference between the phase of the first decimated data extracted by the data decimation unit 10 and the phase of the second decimated data extracted by the data decimation unit 10 when the nth calibration quantized data, which is a signal in which the nth calibration signal has been quantized, is given to the data decimation unit 10. The phase difference between the calibration signals is the phase difference between the phase of the first calibration signal and the phase of the nth calibration signal, that is, the phase difference Δθ, which is the difference between the first phase difference and the second phase difference. ｃｌｋｍ This corresponds to the following. Specifically, the calibration data calculation unit 17 calculates the frequency f of the M first calibration signals, which have different frequencies from each other. ｏｕｔｍ When a first calibration signal (m = 1, ..., M) is applied to the distributor, the frequency phase calculation unit 11 obtains information indicating the phases of multiple first decimated data with different frequencies from each other, as the phase of the first decimated data. The calibration data calculation unit 17 also calculates the frequency f ｏｕｔｍ When a first calibration signal (m = 1, ..., M) is applied to the distributor, the phase difference calculation unit 12 obtains information indicating the phases of a plurality of second decimated data with different frequencies from each other, as the phase of the second decimated data. The calibration data calculation unit 17 selects from the M nth calibration signals with different frequencies, the frequency f ｏｕｔｍ When the nth calibration signal (m=1, ..., M) is applied to the distributor, the frequency phase calculation unit 11 obtains information indicating the phases of multiple first decimated data with different frequencies from each other, as the phase of the first decimated data. The calibration data calculation unit 17 also calculates the frequency f ｏｕｔｍ When the nth calibration signal is applied to the distributor, the phase difference calculation unit 12 obtains information indicating the phases of multiple second decimated data with different frequencies, as the phase of the second decimated data. Then, the calibration data calculation unit 17 calculates the frequency f ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the frequency fｏｕｔｍ Phase and frequency f of the first decimated data (m=1, ..., M) ｏｕｔｍ The first phase difference is the phase difference with the phase of the second decimated data, and the frequency f ｏｕｔｍ When the nth calibration quantization data is provided to the data decimation unit 10, the frequency f ｏｕｔｍ Phase and frequency f of the first decimated data ｏｕｔｍ The difference between the second phase difference, which is the phase difference with the phase of the second decimated data, and the frequency f ｏｕｔｍ Phase difference Δθ between calibration signals related to the calibration signal ｃｌｋｍ The calibration data calculation unit 17 calculates the calibration data θ. ｃａｌ (f ｏｕｔ ) ｍ (m = 1, ..., M) and phase difference Δθ ｃｌｋｍ Each of these is output to the calibration data storage unit 16.

[0052] In Figure 9, it is assumed that each of the components of the frequency detection device 7, namely the data decimation unit 10, frequency phase calculation unit 11, phase difference calculation unit 12, phase difference calibration unit 13, aliasing order calculation unit 14, frequency calculation unit 15, calibration data storage unit 16, and calibration data calculation unit 17, is implemented by dedicated hardware as shown in Figure 10. That is, it is assumed that the frequency detection device 7 is implemented by a data decimation circuit 20, a frequency phase calculation circuit 21, a phase difference calculation circuit 22, a phase difference calibration circuit 23, an aliasing order calculation circuit 24, a frequency calculation circuit 25, a calibration data storage circuit 26, and a calibration data calculation circuit 27. Each of the data decimation circuit 20, frequency phase calculation circuit 21, phase difference calculation circuit 22, phase difference calibration circuit 23, aliasing order calculation circuit 24, frequency calculation circuit 25, and calibration data calculation circuit 27 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0053] The components of the frequency detection device 7 are not limited to those implemented by dedicated hardware; the frequency detection device 7 may also be implemented by software, firmware, or a combination of software and firmware. When the frequency detection device 7 is implemented by software or firmware, the calibration data storage unit 16 is configured on the memory 31 shown in Figure 3. Programs for causing a computer to execute the respective processing procedures in the data decimation unit 10, frequency phase calculation unit 11, phase difference calculation unit 12, phase difference calibration unit 13, aliasing order calculation unit 14, frequency calculation unit 15, and calibration data calculation unit 17 are stored in the memory 31. Then, the processor 32 shown in Figure 3 executes the programs stored in the memory 31.

[0054] Furthermore, Figure 10 shows an example in which each component of the frequency detection device 7 is implemented by dedicated hardware, while Figure 3 shows an example in which the frequency detection device 7 is implemented by software or firmware. However, this is merely one example, and some components of the frequency detection device 7 may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware.

[0055] Next, the operation of the frequency detection circuit shown in Figure 9 will be explained. The frequency f of the signal under measurement ＲＦ The process for detecting the frequency is the same as that of the frequency detection circuit shown in Figure 1. The frequency detection circuit shown in Figure 9 differs from the frequency detection circuit shown in Figure 1 in that it includes a process for calculating calibration data, etc.

[0056] The frequency detection device 7 detects the frequency f of the signal under measurement. ＲＦ Before detecting the frequency f, in order to calculate calibration data, etc., first, M first calibration signals with different frequencies are sequentially supplied to the first T / H circuit 4. ｏｕｔｍWhen a first calibration signal (m = 1, ..., M) is provided, the first T / H circuit 4 holds the first calibration signal at the timing when the delayed clock signal changes from L level to H level for the duration until the clock signal changes to L level. The first T / H circuit 4 outputs the held first calibration signal to the quantizer 6 during the period when the delayed clock signal is at H level. The first T / H circuit 4 outputs the given first calibration signal to the quantizer 6 as is during the period when the delayed clock signal is at L level.

[0057] The quantizer 6 receives the frequency 2f output from the frequency multiplier 5. ｃｌｋ The clock signal is used to quantize the first calibration signal output from the first T / H circuit 4. The quantizer 6 outputs the quantized data, which is the first calibration signal after quantization, to the data decimation unit 10 as the first calibration quantized data.

[0058] The data decimation unit 10 acquires first calibration quantization data from the quantizer 6. The data decimation unit 10 extracts every other sample from the sample sequence of the first calibration quantization data as first decimated data, and extracts the remaining data as second decimated data. The data decimation unit 10 outputs the first decimated data to the frequency phase calculation unit 11 and the second decimated data to the phase difference calculation unit 12.

[0059] The frequency phase calculation unit 11 acquires first decimated data from the data decimation unit 10. The frequency phase calculation unit 11 converts the first calibration quantized data into a frequency domain signal by, for example, performing an FFT on the first decimated data. The frequency phase calculation unit 11 calculates the phase θ of the first decimated data from the frequency bins of the frequency components of the peaks in the frequency domain signal. ｏｕｔｍ The (m = 1, ..., M) values ​​are identified. The frequency phase calculation unit 11 determines the phase θ of the first decimated data. ｏｕｔｍ Information indicating this is output to the phase difference calculation unit 12 and the calibration data calculation unit 17, respectively.

[0060] The phase difference calculation unit 12 acquires second decimated data from the data decimation unit 10, and the phase θ of the first decimated data from the frequency phase calculation unit 11.ｏｕｔｍ Information indicating (m = 1, ..., M) is obtained. The phase difference calculation unit 12 converts the second decimated data into a frequency domain signal by, for example, performing an FFT on the second decimated data. The phase difference calculation unit 12 calculates the phase θ of the second decimated data from the frequency bins of the frequency components of the peaks in the frequency domain signal. ｏｕｔｍ The phase difference calculation unit 12 determines the phase θ of the first decimated data as shown in the following equation (7). ｏｕｔｍ and the phase θ of the second decimated data ｏｕｔｍ The first phase difference Δθ is the phase difference with ' １，ｍ Calculate Δθ. １，ｍ = θ ｏｕｔｍ '-θoutm (7) The phase difference calculation unit 12 calculates the first phase difference Δθ １，ｍ The calibration data calculation unit 17 outputs information indicating this.

[0061] Next, M nth calibration signals with different frequencies are sequentially applied to the first T / H circuit 4. The first T / H circuit 4 receives frequency f ｏｕｔｍ When the nth calibration signal (m = 1, ..., M) is given, the first delay circuit 3 holds the nth calibration signal at the timing when the delayed clock signal changes from L level to H level for the duration until the clock signal changes to L level. The first T / H circuit 4 outputs the held nth calibration signal to the quantizer 6 during the period when the delayed clock signal is at H level. The first T / H circuit 4 outputs the given nth calibration signal to the quantizer 6 as is during the period when the delayed clock signal is at L level.

[0062] The quantizer 6 receives the frequency 2f output from the frequency multiplier 5. ｃｌｋ The clock signal is used to quantize the nth calibration signal output from the first T / H circuit 4. The quantizer 6 outputs the quantized data, which is the nth calibration signal after quantization, to the data decimation unit 10 as the nth calibration quantized data.

[0063] The data decimation unit 10 acquires the nth calibration quantized data from the quantizer 6. The data decimation unit 10 extracts every other sample from the sample sequence of the nth calibration quantized data as the first decimated data, and extracts the remaining data as the second decimated data. The data decimation unit 10 outputs the first decimated data to the frequency phase calculation unit 11 and the second decimated data to the phase difference calculation unit 12.

[0064] The frequency-phase calculation unit 11 acquires first decimated data from the data decimation unit 10. The frequency-phase calculation unit 11 converts the first decimated data into a frequency domain signal, for example, by performing an FFT on the first decimated data. The frequency-phase calculation unit 11 calculates the phase θ of the first decimated data from the frequency bins of the peak frequency components in the frequency domain signal. ｏｕｔｍ The (m = 1, ..., M) values ​​are identified. The frequency phase calculation unit 11 determines the phase θ of the first decimated data. ｏｕｔｍ Information indicating this is output to the phase difference calculation unit 12 and the calibration data calculation unit 17, respectively.

[0065] The phase difference calculation unit 12 acquires second decimated data from the data decimation unit 10, and the phase θ of the first decimated data from the frequency phase calculation unit 11. ｏｕｔｍ Information indicating (m = 1, ..., M) is obtained. The phase difference calculation unit 12 converts the second decimated data into a frequency domain signal by, for example, performing an FFT on the second decimated data. The phase difference calculation unit 12 calculates the phase θ of the second decimated data from the frequency bins of the frequency components of the peaks in the frequency domain signal. ｏｕｔｍ The phase difference calculation unit 12 determines the phase θ of the first decimated data as shown in equation (8) below. ｏｕｔｍ and the phase θ of the second decimated data ｏｕｔｍ The second phase difference Δθ is the phase difference with ' ２，ｍ Calculate Δθ. ２，ｍ = θ ｏｕｔｍ '-θoutm (8) The phase difference calculation unit 12 calculates the second phase difference Δθ ２，ｍ The calibration data calculation unit 17 outputs information indicating this.

[0066] The calibration data calculation unit 17 receives the first phase difference Δθ from the phase difference calculation unit 12. １，ｍ Information indicating and the second phase difference Δθ ２，ｍ Information indicating the above is obtained. The calibration data calculation unit 17 calculates the first phase difference Δθ as shown in the following equation (9). １，ｍ and the second phase difference Δθ ２，ｍ The difference between these is the phase difference Δθ ｃｌｋｍ It is calculated as follows: Δθ ｃｌｋｍ = Δθ １，ｍ -Δθ2,m (9)

[0067] The calibration data calculation unit 17 calculates the frequency f from among M first calibration quantization data with different frequencies. ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the phase difference calculated by the phase difference calculation unit 12 is the calibration data θ ｃａｌ (f ｏｕｔ ) ｍ It is calculated as follows.

[0068] The calibration data calculation unit 17 calculates the calibration data θ ｃａｌ (f ｏｕｔ ) ｍ Information indicating (m=1, ..., M) and the phase difference Δθ ｃｌｋｍ Information indicating the phase difference Δθ is output to the calibration data storage unit 16. ｍ Calibration data θ corresponding to (m = 1, ..., M) ｃａｌ (f ｏｕｔ ) ｍ And, the phase difference Δθ ｍ The corresponding phase difference Δθ ｃｌｋｍ This is remembered.

[0069] In the above embodiment 2, instead of quantized data, a first calibration quantized data, which is a signal obtained by quantizing a first calibration signal having a frequency in the first-order Nyquist region, is provided to the data decimation unit 10. The frequency detection device 7 is configured such that when quantized data is provided to the data decimation unit 10, the phase difference calculated by the phase difference calculation unit 12 is used to calculate the phase difference as calibration data. The frequency detection device 7 is configured such that when quantized data is provided to the data decimation unit 10, the phase difference calibration unit 13 calibrates the phase difference calculated by the phase difference calculation unit 12 according to the calibration data calculated by the calibration data calculation unit 17. Therefore, the frequency detection device 7 can calculate the frequency of the signal under test without implementing two sample-and-hold circuits, and can also calculate calibration data before calculating the frequency of the signal under test.

[0070] In Embodiment 2, the frequency detection device 7 is configured such that, in addition to calculating calibration data, the calibration data calculation unit 17 also calculates the difference between the phase of the first calibration signal and the phase of the nth calibration signal, which is the phase difference between the phase of the first calibration signal and the phase of the nth calibration signal. This difference is calculated as the phase difference between the phase of the first calibration signal and the phase of the nth calibration signal.

[0071] In the frequency detection device 7 shown in Figure 9, the frequency f ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is provided to the data decimation unit 10, the phase difference calculation unit 12 calculates the frequency f ｏｕｔｍ Phase θ of the first decimated data ｏｕｔｍ and frequency f ｏｕｔｍ Phase θ of the second decimation dataｏｕｔｍ The first phase difference Δθ is the phase difference with ' １，ｍ The phase difference calculation unit 12 calculates the frequency f ｏｕｔｍ When the nth calibration quantization data is provided to the data decimation unit 10, the phase difference calculation unit 12 calculates the frequency f ｏｕｔｍ Phase θ of the first decimated data ｏｕｔｍ and frequency f ｏｕｔｍ Phase θ of the second decimation data ｏｕｔｍ The second phase difference Δθ is the phase difference with ' ２，ｍ The calibration data calculation unit 17 calculates the frequency f ｏｕｔｍ The first phase difference Δθ of (m = 1, ..., M) １，ｍ By linear interpolating, the frequency f ｏｕｔｍ The first phase difference Δθ with respect to frequencies different from (m = 1, ..., M) １，ｍ The calibration data calculation unit 17 calculates the frequency f. ｏｕｔｍ The second phase difference Δθ of (m=1, ..., M) ２，ｍ By linear interpolating, the frequency f ｏｕｔｍ (m=1, ..., M) and the second phase difference Δθ related to different frequencies ２，ｍ The calibration data calculation unit 17 then calculates the frequency f ｏｕｔｍ The first phase difference Δθ with respect to frequencies different from (m = 1, ..., M) １，ｍ and frequency f ｏｕｔｍ (m=1, ..., M) and the second phase difference Δθ related to different frequencies ２，ｍ The difference between this and the frequency f ｏｕｔｍ The calculation may also be performed as the phase difference between calibration signals with different frequencies (m = 1, ..., M).

[0072] frequency f ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the frequency f ｏｕｔｍ The phase difference between the phase of the first decimated data having a different frequency and the phase of the second decimated data is, for example, as shown in Figure 11, frequency f ｏｕｔｍ and frequency f ｏｕｔｍ＋１ This is the phase difference corresponding to the frequency between [the specified frequency] and [the specified frequency]. ｏｕｔｍWhen the nth calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the frequency f ｏｕｔｍ The phase difference between the phase of the first decimated data having a different frequency and the phase of the second decimated data is, for example, as shown in Figure 12, frequency f ｏｕｔｍ and frequency f ｏｕｔｍ＋１ This is the phase difference corresponding to the frequency between [the specified point] and [the specified point]. Figure 11 shows the frequency f. ｏｕｔｍ When the first calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the frequency f ｏｕｔｍ The first phase difference Δθ １，ｍ This is an explanatory diagram showing the linear interpolation result for frequency f. ｏｕｔｍ When the nth calibration quantization data (m=1, ..., M) is given to the data decimation unit 10, the frequency f ｏｕｔｍ The second phase difference Δθ of (m=1, ..., M) ２，ｍ This is an explanatory diagram showing the linear interpolation results. In Figures 11 and 12, the horizontal axis represents the frequency of the calibration signal, and the vertical axis represents the phase difference of the calibration signal.

[0073] Embodiment 3. Embodiment 3 describes a frequency detection circuit in which the quantization unit 1 further includes a second delay circuit 3a and a second T / H circuit 4a.

[0074] Figure 13 is a configuration diagram showing a frequency detection circuit including a frequency detection device 7 according to Embodiment 3. In Figure 13, the same reference numerals as in Figures 1 and 9 indicate the same or corresponding parts, so a detailed explanation is omitted. The second delay circuit 3a delays the clock signal output from the clock signal source 2 by a second delay time τ ２ The clock signal is delayed by a certain amount, and the delayed clock signal is output to the second T / H circuit 4a.

[0075] The second track-and-hold circuit, the second T / H circuit 4a, uses the clock signal output from the second delay circuit 3a to temporarily hold the signal under test output from the first T / H circuit 4, and outputs either the held signal under test or the signal under test output from the first T / H circuit 4 to the quantizer 6. Specifically, the second T / H circuit 4a holds the signal under test at the timing when the clock signal changes from L level to H level for the period until the clock signal changes to L level. While the clock signal is at H level, the second T / H circuit 4a outputs the held signal under test to the quantizer 6, and while the clock signal is at L level, it outputs the signal under test output from the first T / H circuit 4 to the quantizer 6 as is.

[0076] In the frequency detection circuit shown in Figure 13, a quantization unit 1 further comprising a second delay circuit 3a and a second T / H circuit 4a is applied to the frequency detection circuit shown in Figure 1. However, this is merely one example, and a quantization unit 1 further comprising a second delay circuit 3a and a second T / H circuit 4a may also be applied to the frequency detection circuit shown in Figure 9.

[0077] Next, the operation of the frequency detection circuit shown in Figure 13 will be explained. Except for the quantization unit 1, it is the same as the frequency detection circuit shown in Figure 1, so here only the operation of the quantization unit 1 will be explained. Figure 14 is an explanatory diagram showing a sample sequence of the delayed clock signal output from the first delay circuit 3 to the first T / H circuit 4, the delayed clock signal output from the second delay circuit 3a to the second T / H circuit 4a, the doubled clock signal output from the multiplier 5 to the quantizer 6, the signal to be measured applied to the first T / H circuit 4, and the quantized data output from the quantizer 6.

[0078] The first delay time τ is set such that the rising edge of the doubled clock signal used by the quantizer 6 (labeled "quantized clock" in Figure 14) is earlier than the rising edge of the clock signal delayed by the first delay circuit 3 (labeled "first T / H clock" in Figure 14), and later than the falling edge of the clock signal delayed by the previous delay circuit 3a (labeled "second T / H clock" in Figure 14), as shown in Figure 14. １ and the second delay time τ ２ And are adjusted. In the example in Figure 14, τ １ >τ ２ That is the case.

[0079] The clock signal source 2 has a frequency f ｃｌｋ The clock signal is generated and output to the first delay circuit 3, the second delay circuit 3a, and the frequency multiplier 5, respectively. When the first delay circuit 3 receives a clock signal from the clock signal source 2, it delays the clock signal for a first delay time τ, as shown in Figure 14. １ The clock signal is delayed by a certain amount of time, and the first T / H clock, which is the clock signal after the delay, is output to the first T / H circuit 4. When the second delay circuit 3a receives a clock signal from the clock signal source 2, as shown in Figure 14, the clock signal is delayed by a second delay time τ ２ The clock signal is delayed by a certain amount, and the second T / H clock, which is the clock signal after the delay, is output to the second T / H circuit 4.

[0080] The first T / H circuit 4 holds the signal under test at the timing when the delayed clock signal from the first delay circuit 3 changes from L level to H level, for the period until the clock signal changes to L level. As shown in Figure 14, the first T / H circuit 4 outputs the signal under test (the signal in Hold mode in the figure) that it has been holding to the second T / H circuit 4a during the period when the delayed clock signal is at H level. As shown in Figure 14, the first T / H circuit 4 outputs the given signal under test (the signal in Track mode in the figure) to the second T / H circuit 4a as is during the period when the delayed clock signal is at L level.

[0081] The second T / H circuit 4a holds the signal under test output from the first T / H circuit 4 at the timing when the clock signal delayed by the second delay circuit 3a changes from L level to H level, for the period until the clock signal changes to L level. As shown in Figure 14, the second T / H circuit 4a outputs the held signal under test (the signal in Hold mode in the figure) to the quantizer 6 during the period when the delayed clock signal is at H level. As shown in Figure 14, the second T / H circuit 4a outputs the signal under test output from the first T / H circuit 4 (the signal in Track mode in the figure) directly to the quantizer 6 during the period when the delayed clock signal is at L level.

[0082] The frequency multiplier 5 receives the frequency f output from the clock signal source 2. ｃｌｋ The clock signal is doubled. The multiplier 5 uses a frequency of 2f as the doubled clock signal, as shown in Figure 14. ｃｌｋ The quantization clock, which is the clock signal, is output to the quantizer 6. As shown in Figure 14, the quantizer 6 receives the frequency 2f output from the frequency multiplier 5. ｃｌｋ The clock signal is used to quantize the signal to be measured output from the second T / H circuit 4a. The quantizer 6 outputs the quantized data, which is the signal to be measured after quantization, to the data decimation unit 10.

[0083] In the frequency detection circuit shown in Figure 13, the quantization unit 1 further includes a second delay circuit 3a and a second T / H circuit 4a, so that the frequency f calculated by the frequency calculation unit 15 is ＲＦ The calculation accuracy is the frequency f calculated by the frequency calculation unit 15 of the frequency detection circuit shown in Figure 1. ＲＦ This improves upon the calculation accuracy of the previous method.

[0084] Furthermore, this disclosure allows for free combination of each embodiment, modification of any component in each embodiment, or omission of any component in each embodiment.

[0085] The frequency detection device described herein can be used, for example, to detect the frequency of a signal under measurement.

[0086] 1 Quantization unit, 2 Clock signal source, 3 First delay circuit, 3a Second delay circuit, 4 First T / H circuit, 4a Second T / H circuit, 5 Frequency multiplier, 6 Quantizer, 7 Frequency detection device, 10 Data decimation unit, 11 Frequency phase calculation unit, 12 Phase difference calculation unit, 13 Phase difference calibration unit, 14 Alias ​​order calculation unit, 15 Frequency calculation unit, 16 Calibration data storage unit, 17 Calibration data calculation unit, 20 Data decimation circuit, 21 Frequency phase calculation circuit, 22 Phase difference calculation circuit, 23 Phase difference calibration circuit, 24 Alias ​​order calculation circuit, 25 Frequency calculation circuit, 26 Calibration data storage circuit, 27 Calibration data calculation circuit, 31 Memory, 32 Processor.

Claims

1. A frequency detection device comprising: a data decimation unit that extracts every other sample data from a sample sequence of quantized data, where the signal to be measured is a quantized signal, as first decimated data, and extracts the remaining data as second decimated data; a frequency-phase calculation unit that calculates the frequency and phase of the first decimated data extracted by the data decimation unit; a phase difference calculation unit that calculates the phase of the second decimated data extracted by the data decimation unit and calculates the phase difference between the phase of the first decimated data and the phase of the second decimated data; a phase difference calibration unit that acquires calibration data corresponding to the phase difference calculated by the phase difference calculation unit and calibrates the phase difference according to the calibration data; an aliasing order calculation unit that calculates the Nyquist aliasing order of the first decimated data based on the phase difference after calibration by the phase difference calibration unit; and a frequency calculation unit that calculates the frequency of the signal to be measured using the frequency calculated by the frequency-phase calculation unit and the Nyquist aliasing order calculated by the aliasing order calculation unit.

2. The frequency detection device according to claim 1, wherein when a first calibration quantized data is provided to the data decimation unit, which is a signal in which a first calibration signal having a frequency in the first-order Nyquist region has been quantized, the device comprises a calibration data calculation unit which calculates the phase difference calculated by the phase difference calculation unit as the calibration data, and when the quantized data is provided to the data decimation unit, the phase difference calibration unit calibrates the phase difference calculated by the phase difference calculation unit according to the calibration data calculated by the calibration data calculation unit.

3. The frequency detection device according to claim 2, characterized in that the calibration data calculation unit calculates the respective phase differences calculated by the phase difference calculation unit as the calibration data when each of a plurality of first calibration quantization data sets with different frequencies are provided to the data decimation unit as the first calibration quantization data.

4. The frequency detection device according to claim 2 or 3, characterized in that, in addition to calculating the calibration data, the calibration data calculation unit calculates, when the first calibration quantization data is provided to the data decimation unit, the difference between a first phase difference, which is the phase difference between the phase of the first decimated data extracted by the data decimation unit and the phase of the second decimated data extracted by the data decimation unit, and when the nth calibration quantization data, which is a signal in which the nth calibration signal having a frequency in the nth order Nyquist region is quantized, is provided to the data decimation unit, the difference between the phase of the first decimated data extracted by the data decimation unit and the phase difference between the phase of the second decimated data extracted by the data decimation unit, as the phase difference between the phase of the first calibration signal and the phase of the nth calibration signal.

5. When a plurality of first calibration quantization data with different frequencies are provided to the data decimation unit, the calibration data calculation unit obtains the phases of the plurality of first decimation data with different frequencies from the frequency phase calculation unit as the phase of the first decimation data, and obtains the phases of the plurality of second decimation data with different frequencies from the phase difference calculation unit as the phase of the second decimation data. When a plurality of nth calibration quantization data with different frequencies are provided to the data decimation unit, the calibration data calculation unit obtains the phases of the plurality of first decimation data with different frequencies from the frequency phase calculation unit as the phase of the first decimation data, and obtains the phases of the plurality of second decimation data with different frequencies from the phase difference calculation unit as the phase of the second decimation data. The frequency detection device according to any one of claims 2 to 4, characterized in that when a first calibration quantization data having each frequency is provided to the data decimation unit, the difference between a first phase difference, which is the phase difference between the phase of the first decimated data having each frequency and the phase of the second decimated data having each frequency, and when an nth calibration quantization data having each frequency is provided to the data decimation unit, the difference between a first phase difference, which is the phase difference between the phase of the first decimated data having each frequency and the phase of the second decimated data having each frequency, is calculated as the phase difference between calibration signals for each frequency, and the aliasing order calculation unit calculates the Nyquist aliasing order of the first decimated data using the phase difference after calibration by the phase difference calibration unit and the phase difference between calibration signals corresponding to the frequency calculated by the frequency phase calculation unit among the phase differences between calibration signals for a plurality of frequencies calculated by the calibration data calculation unit.

6. The frequency detection device according to any one of claims 2 to 5, characterized in that the calibration data calculation unit calculates a first phase difference, which is the phase difference between the phase of a first decimated data having a different frequency and the phase of a second decimated data having a different frequency, by linearly interpolating the phase difference between the phase of a first decimated data having a different frequency and the phase of a second decimated data having a different frequency, when a first calibration quantization data having a different frequency is provided to the data decimation unit, and calculates a second phase difference, which is the phase difference between the phase of a first decimated data having a different frequency and the phase of a second decimated data having a different frequency, when an nth calibration quantization data having a different frequency is provided to the data decimation unit, by linearly interpolating the phase difference between the phase of a first decimated data having a different frequency and the phase of a second decimated data having a different frequency, and calculates the difference between the first phase difference relating to a different frequency and the second phase difference relating to a different frequency as the phase difference between calibration signals relating to a different frequency.

7. A frequency detection method comprising: a data decimation unit extracts every other sample data from a sample sequence of quantized data, where the signal to be measured is a quantized signal, as first decimated data, and extracts the remaining data as second decimated data; a frequency-phase calculation unit calculates the frequency and phase of the first decimated data extracted by the data decimation unit; a phase difference calculation unit calculates the phase of the second decimated data extracted by the data decimation unit and calculates the phase difference between the phase of the first decimated data and the phase of the second decimated data; a phase difference calibration unit acquires calibration data corresponding to the phase difference calculated by the phase difference calculation unit and calibrates the phase difference according to the calibration data; an aliasing order calculation unit calculates the Nyquist aliasing order of the first decimated data based on the phase difference after calibration by the phase difference calibration unit; and a frequency calculation unit calculates the frequency of the signal to be measured using the frequency calculated by the frequency-phase calculation unit and the Nyquist aliasing order calculated by the aliasing order calculation unit.

8. A quantization unit that quantizes the signal to be measured and outputs quantized data, which is the signal to be measured after quantization; a data decimation unit that extracts every other sample from a sample sequence of quantized data output from the quantization unit as first decimated data and extracts the remaining data as second decimated data; a frequency-phase calculation unit that calculates the frequency and phase of the first decimated data extracted by the data decimation unit; a phase difference calculation unit that calculates the phase of the second decimated data extracted by the data decimation unit and calculates the phase difference between the phase of the first decimated data and the phase of the second decimated data; a phase difference calibration unit that acquires calibration data corresponding to the phase difference calculated by the phase difference calculation unit and calibrates the phase difference according to the calibration data; and a folding order calculation unit that calculates the Nyquist folding order of the first decimated data based on the phase difference after calibration by the phase difference calibration unit. A frequency detection circuit comprising a frequency calculation unit that calculates the frequency of the signal to be measured using the frequency calculated by the frequency phase calculation unit and the Nyquist aliasing order calculated by the aliasing order calculation unit.

9. The frequency detection circuit according to claim 8, characterized in that the quantization unit comprises: a clock signal source that oscillates a clock signal; a first delay circuit that delays the clock signal oscillated by the clock signal source by a first delay time and outputs the delayed clock signal; a first track-and-hold circuit that uses the clock signal output from the first delay circuit to temporarily hold a given signal under test and outputs either the held signal under test or the given signal under test; a frequency multiplier that doubles the clock signal oscillated by the clock signal source and outputs the doubled clock signal; and a quantizer that uses the clock signal output from the frequency multiplier to quantize the signal under test output from the first track-and-hold circuit and outputs quantized data, which is the signal under test after quantization, to the data decimation unit.

10. The frequency detection circuit according to claim 9, wherein the quantization unit further comprises a second delay circuit that delays the clock signal oscillated by the clock signal source by a second delay time and outputs the delayed clock signal, and a second track and hold circuit that uses the clock signal output from the second delay circuit to temporarily hold the signal to be measured output from the first track and hold circuit and outputs either the held signal to be measured or the signal to be measured output from the first track and hold circuit, and the quantizer uses the clock signal output from the multiplier to quantize the signal to be measured output from the second track and hold circuit instead of the signal to be measured output from the first track and hold circuit, and outputs the quantized data, which is the signal to be measured after quantization, to the data decimation unit.

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