Display device

Abstract

This display device includes a first laminated structure provided in a first region of a substrate, and a second laminated structure provided in a second region, which is different from the first region, of the substrate. Each of the first laminated structure and the second laminated structure includes an alignment layer, a first semiconductor layer that contains gallium nitride and that is on the alignment layer, a second semiconductor on the first semiconductor layer, and a third semiconductor layer that contains gallium nitride and that is on the second semiconductor. A first electrode is provided on the third semiconductor layer of the first laminated structure with an insulating layer interposed therebetween, and the first laminated structure and the second laminated structure are electrically connected via a second electrode.

Description

Display device

[0001] One embodiment of the present invention relates to a display device using a semiconductor layer containing gallium nitride.

[0002] In recent years, the development of a technique for forming a semiconductor layer containing gallium nitride (hereinafter referred to as "gallium nitride-based semiconductor layer") on a glass substrate by a sputtering method or the like has been progressing. By this technique, it becomes possible to form a light-emitting diode (LED) using a gallium nitride-based semiconductor layer on a glass substrate. For example, Patent Document 1 discloses a display device having a plurality of pixels including a light-emitting diode containing a gallium nitride-based semiconductor layer and a transistor electrically connected to the light-emitting diode.

[0003] International Publication No. 2020 / 188851

[0004] When manufacturing a display device by separately forming a light-emitting diode and a transistor on the same substrate as in the above prior art, there is a problem that the structure becomes complicated and the manufacturing process increases. In particular, such a problem becomes prominent when the semiconductor layer constituting the light-emitting diode and the semiconductor layer constituting the transistor are made of different materials as in the above prior art.

[0005] An object of one embodiment of the present invention is to simplify the structure of a display device having a plurality of pixels including a light-emitting diode and a transistor.

[0006] A display device according to one embodiment of the present invention includes a first stacked structure provided in a first region of a substrate and a second stacked structure provided in a second region of the substrate different from the first region, wherein each of the first and second stacked structures includes an alignment layer, a first semiconductor layer containing gallium nitride on the alignment layer, a second semiconductor on the first semiconductor layer, and a third semiconductor layer containing gallium nitride on the second semiconductor, wherein each of the alignment layer, first semiconductor layer, second semiconductor, and third semiconductor layer of the first stacked structure is the same layer as the alignment layer, first semiconductor layer, second semiconductor, and third semiconductor layer of the second stacked structure, and a first electrode is provided on the third semiconductor layer of the first stacked structure via an insulating layer, and the first and second stacked structures are electrically connected via a second electrode.

[0007] This is a schematic diagram showing an overview of a display device according to one embodiment of the present invention. This is a circuit diagram showing the configuration of the pixel circuit of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic plan view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the manufacturing method of the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the manufacturing method of the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the manufacturing method of the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the manufacturing method of the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the manufacturing method of the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic plan view showing the pixel structure of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment of the present invention.

[0008] Embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its essence. The present invention is not to be interpreted as being limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the drawings are merely examples and do not limit the interpretation of the present invention.

[0009] When describing embodiments of the present invention, the direction from the substrate toward the semiconductor layer is referred to as "up," and the opposite direction is referred to as "down." However, the expressions "up" or "down" merely describe the relative positional relationship of each element. Furthermore, the expressions "up" or "down" include not only the case where a third element is interposed between the first and second elements, but also the case where it is not interposed. Moreover, the expressions "up" or "down" include not only the case where each element overlaps in a plan view, but also the case where they do not overlap.

[0010] When describing embodiments of the present invention, elements having similar functions to those already described may be referred to by the same reference numeral or by adding an alphabet or other symbol to the same reference numeral, and their description may be omitted. Furthermore, if it is necessary to describe a part of an element separately, the reference numeral representing that element may be added to distinguish it. However, if there is no particular need to distinguish between the parts of an element, only the reference numeral representing that element will be used for description.

[0011] When describing embodiments of the present invention, multiple elements formed by applying a processing treatment such as etching to a single film may be described as elements having different functions or roles. Since these multiple elements are formed from the same material and by the same process, they are described as elements in the "same layer".

[0012] When describing embodiments of the present invention, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] <First Embodiment> [Overview of Display Device] Figure 1 is a schematic diagram showing an overview of a display device 10 in one embodiment of the present invention. The display device 10 has a display unit 110, a drive circuit unit 120, and a terminal unit 130 provided on a substrate 100. The drive circuit unit 120 is provided on the outside of the display unit 110 and can control the operation of the display unit 110. The terminal unit 130 is provided at the end of the substrate 100 and can supply video signals, control signals, and power to the display device 10. The terminal unit 130 is connected to, for example, a flexible printed circuit board 140. A driver IC 150 or the like may be provided on the flexible printed circuit board 140. The driver IC 150 controls the video signals transmitted to the display device 10.

[0014] The display unit 110 displays a still image or a moving image. The display unit 110 includes a plurality of pixels 111 arranged in a matrix. Each of the plurality of pixels 111 includes a transistor formation region 111a and an LED formation region 111b. A transistor and a light-emitting diode (LED) are formed in the transistor formation region 111a and the LED formation region 111b, respectively. In addition to the transistor, a capacitive element may also be formed in the transistor formation region 111a.

[0015] Figure 2 is a circuit diagram showing the configuration of the pixel circuit of a display device 10 in one embodiment of the present invention. In other words, Figure 2 shows a pixel circuit composed of the pixels 111 shown in Figure 1. The pixel 111 includes a selection transistor 11, a drive transistor 12, a capacitive element 13, and an LED 14.

[0016] The selection transistor 11 is an element whose conduction state is controlled by the scan signal line 15. When the selection transistor 11 becomes conductive, the video signal is transmitted from the video signal line 16 into the pixel 111. The gate, source, and drain of the selection transistor 11 are electrically connected to the scan signal line 15, the video signal line 16, and the gate of the drive transistor 12, respectively.

[0017] The drive transistor 12 is an element that controls the luminescence brightness of the light-emitting diode (LED) 14. The gate, source, and drain of the drive transistor 12 are electrically connected to the drain of the selection transistor 11, the first drive power line 17, and the anode (p-type electrode) of the LED 14, respectively.

[0018] The capacitive element 13 is an element for maintaining the potential of the node connecting the drain of the selection transistor 11 and the gate of the drive transistor 12. One of the two electrodes of the capacitive element 13 is electrically connected to the drain of the selection transistor 11 and the gate of the drive transistor 12. The other of the two electrodes of the capacitive element 13 is electrically connected to the first drive power line 17.

[0019] LED 14 is a light-emitting element whose luminescence can be adjusted by the amount of current flowing through it. The anode (p-type electrode) of LED 14 is electrically connected to the drain of the drive transistor 12. The cathode (n-type electrode) of LED 14 is electrically connected to the second drive power line 18.

[0020] In the display device 10, a selection transistor 11, a drive transistor 12, and a capacitive element 13 are formed in the transistor formation region 111a shown in Figure 1, and an LED 14 is formed in the LED formation region 111b. In this embodiment, the structure formed in the transistor formation region 111a is called the first stacked structure, and the structure formed in the LED formation region 111b is called the second stacked structure. Specific examples of the first and second stacked structures will be described below.

[0021] [Pixel Structure] Figure 3 is a schematic cross-sectional view showing the pixel structure of the display device 10 in one embodiment of the present invention. Specifically, Figure 3 shows the cross-sectional structure of the first laminated structure 200 and the second laminated structure 300 provided on the substrate 100. Figure 4 is a schematic plan view showing the pixel structure of the display device 10 in one embodiment of the present invention. Figure 3 corresponds to a cross-sectional view cut along the line segment A-A' shown in Figure 4.

[0022] The transistor formed by the first multilayer structure shown in Figure 3 corresponds to the drive transistor 12 shown in Figure 2. However, the structure of the drive transistor 12 and the selection transistor 11 are the same. Also, the light-emitting diode (LED) formed by the second multilayer structure shown in Figure 3 corresponds to the light-emitting diode 14 shown in Figure 2.

[0023] The substrate 100 is a support substrate that supports the first laminated structure 200 and the second laminated structure 300. For example, an amorphous substrate or a resin substrate can be used as the substrate 100. As an amorphous substrate, an amorphous glass substrate can be used. As a resin substrate, a substrate made of a resin material such as polyimide resin, acrylic resin, siloxane resin, or fluororesin can be used. Although not shown in Figure 3, an underlayer may be provided on the substrate 100. The underlayer can prevent the diffusion of impurities from the substrate 100 or from the outside (for example, moisture or sodium (Na)). For example, a film made of silicon oxide (SiOx) or silicon nitride (SiNx) can be used as the underlayer.

[0024] The first stacked structure 200 includes an alignment layer 201 and semiconductor layers 202 to 207. Furthermore, the first stacked structure 200 has an insulating layer 101, a gate electrode 102, a terminal electrode 103, and a common terminal electrode 104 on top of the semiconductor layer 207. In this case, the semiconductor layer 207, insulating layer 101, gate electrode 102, terminal electrode 103, and common terminal electrode 104 constitute a transistor.

[0025] In this embodiment, the semiconductor layer 207 functions as the active layer (channel formation region) of the transistor. That is, the transistor is composed of the semiconductor layer 207, the insulating layer 101, and the gate electrode 102.

[0026] The second laminated structure 300 includes an alignment layer 301 and semiconductor layers 302 to 308. Furthermore, the second laminated structure 300 has an insulating layer 101 and a common terminal electrode 104 on the semiconductor layer 308, and a terminal electrode 105 on the exposed surface 31 formed on the semiconductor layer 302.

[0027] In this embodiment, semiconductor layers 302 to 308 function as an electron injection layer, a first electron transport layer, a second electron transport layer, an active layer, a hole transport layer, a hole injection layer, and an electrode layer, respectively. That is, the semiconductor layers 302 to 307 constitute a light-emitting diode. However, the configuration of the light-emitting diode is not limited to the configuration shown in Figure 3. For example, only one of the electron injection layer and the electron transport layer may be provided. Similarly, only one of the hole injection layer and the hole transport layer may be provided.

[0028] As described above, the display device 10 of this embodiment is provided with a first stacked structure 200 and a second stacked structure 300 for each pixel 111. The first stacked structure 200 includes a transistor, and the second stacked structure 300 includes a light-emitting diode. As shown in Figure 3, the first stacked structure 200 and the second stacked structure 300 are composed of multiple layers of the same layer, thus simplifying their structure.

[0029] First, the first stacked structure 200 will be described. In Figure 3, the orientation layer 201 has the function of improving the crystal orientation of the gallium nitride layer when forming the n-type gallium nitride layer as the semiconductor layer 202.

[0030] The orientation layer 201 may be conductive or insulating, but it is preferable that it has crystallinity oriented along a specific axis (for example, the c-axis). The orientation layer 201 is preferably a crystal with rotational symmetry, for example, its crystal surface is preferably 6-fold rotationally symmetry. Furthermore, the orientation layer 201 is preferably a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto. Here, a hexagonal close-packed structure or a structure similar thereto includes a crystal structure in which the c-axis is not at a 90-degree angle with respect to the a-axis and b-axis. An orientation layer 201 having a hexagonal close-packed structure or a structure similar thereto is preferably oriented in the (0001) direction, i.e., in the c-axis direction, with respect to the substrate 100. An orientation layer 201 having a face-centered cubic structure or a structure similar thereto is preferably oriented in the (111) direction with respect to the substrate 100.

[0031] The surface state of the orientation layer 201 is desirable to be flat, as it affects the crystallinity of the gallium nitride layer. For example, it is preferable that the arithmetic mean roughness (Ra) of the surface of the orientation layer 201 is less than 2.3 nm.

[0032] As the orientation layer 201 mentioned above, titanium (Ti), titanium nitride (TiNx), titanium oxide (TiOx), graphene, zinc oxide (ZnO), magnesium diboride (MgB2), aluminum (Al), aluminum nitride (AlN), aluminum oxide (Al2O3), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), lithium niobate (LiNbO), BiLaTiO, SrFeO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT can be used. In particular, it is preferable to use titanium, graphene, zinc oxide, aluminum nitride, or aluminum oxide as the orientation layer 201. In this embodiment, a titanium layer is used as the orientation layer 201.

[0033] The thickness of the orientation layer 201 is, for example, 50 nm or more (preferably 50 nm to 100 nm). The orientation layer 201 can be formed by any method. For example, the orientation layer 201 can be formed by sputtering, CVD, vacuum deposition, electron beam deposition, etc.

[0034] As described above, the semiconductor layer 202 is composed of n-type gallium nitride (n-GaN). The n-type gallium nitride layer can be formed, for example, by using a sputtering target composed of silicon (Si)-doped gallium nitride (GaN).

[0035] In this embodiment, the semiconductor layer 202 is formed on the orientation layer 201, and since its c-axis is oriented in the film thickness direction, it has excellent crystallinity. In this embodiment, since the semiconductor layer 202 is formed by sputtering, even if an amorphous glass substrate is used as the substrate 100, it can withstand the film deposition temperature sufficiently. Normally, in order to form a semiconductor layer with good crystallinity, methods such as epitaxial growth on a semiconductor substrate at high temperatures are employed, but in this embodiment, a semiconductor layer with crystallinity comparable to that of an epitaxially grown semiconductor layer can be formed by sputtering at a relatively low film deposition temperature.

[0036] Both semiconductor layer 203 and semiconductor layer 204 are composed of n-type aluminum gallium nitride (n-AlGaN). The n-type aluminum gallium nitride layer can be formed, for example, by using a sputtering target composed of silicon (Si)-doped aluminum gallium nitride (AlGaN).

[0037] The semiconductor layer 205 is composed of intrinsic indium gallium nitride (InGaN) without added impurities. The semiconductor layer 205 can be formed, for example, by using a sputtering target composed of undoped indium gallium nitride. Furthermore, the semiconductor layer 205 is not limited to the use of a single layer of indium gallium nitride; it may also be a laminated structure in which indium gallium nitride layers and gallium nitride layers are alternately stacked. Such a laminated structure is called a multiple quantum well (MQW) structure.

[0038] The semiconductor layer 206 is composed of p-type aluminum gallium nitride (p-AlGaN). The p-type aluminum gallium nitride layer can be formed, for example, by using a sputtering target composed of magnesium (Mg)-doped aluminum gallium nitride (AlGaN).

[0039] The semiconductor layer 207 is composed of p-type gallium nitride (p-GaN). The p-type gallium nitride layer can be formed, for example, by using a sputtering target composed of magnesium (Mg)-doped gallium nitride (GaN). As described above, the semiconductor layer 207 of this embodiment functions as the active layer (channel formation region) of the transistor.

[0040] As described above, the first stacked structure 200 includes, in order from the bottom layer (the layer closest to the substrate 100), an alignment layer 201 and semiconductor layers 202 to 207. All of the semiconductor layers 202 to 207 are oriented in the c-axis direction. That is, the c-axis of the semiconductor layers 202 to 207 is aligned in a direction perpendicular to the substrate 100. In this embodiment, since the crystallinity of the semiconductor layer 202 is oriented in the c-axis direction by the alignment layer 201, the semiconductor layer 203 formed on top of the semiconductor layer 202 is also oriented in the c-axis direction. Similarly, the semiconductor layers 204 to 207 are also formed inheriting the crystallinity of the semiconductor layer on the lower side, and are therefore oriented in the c-axis direction. In this way, by continuously stacking the semiconductor layers 202 to 207 on top of the alignment layer 201, the crystallinity of the semiconductor layers 202 to 207 can be improved.

[0041] An insulating layer 101 is provided on the semiconductor layer 207. The insulating layer 101 functions as a gate insulating layer for the transistor and also functions as a protective layer covering the first laminated structure 200. In this embodiment, as shown in Figure 3, the insulating layer 101 also functions as a protective layer covering a part of the adjacent second laminated structure 300 (a part other than the part that forms the exposed surface 31 described later). As shown in Figure 3, the insulating layer 101 covers the sides of the first laminated structure 200 and the second laminated structure 300. By forming the insulating layer 101 in this way, defects that occur on the sides of the semiconductor layers 202-207 and 302-307 during the formation of the insulating layer 101 can be reduced.

[0042] In this embodiment, aluminum nitride (AlN) is used as the material of the insulating layer 101, but silicon oxide (SiO₂) may also be used. The thickness of the insulating layer 101 only needs to be within a range that can sufficiently fulfill the function as a gate insulating layer. However, from the perspective of the protective layer, it is preferable that the thickness of the insulating layer 101 is as thick as possible.

[0043] A gate electrode 102 is provided on the insulating layer 101. As the material of the gate electrode 102, a metal material is used. In this embodiment, tantalum (Ta) is used as the material of the gate electrode 102, but other metal materials may also be used.

[0044] The terminal electrode 103 is connected to the semiconductor layer 207 through an opening 21 provided in the insulating layer 101. The terminal electrode 103 functions as a source electrode or a drain electrode of the transistor. As the material of the terminal electrode 103, a metal material is used. In this embodiment, a Ti / Al / Ti structure in which aluminum (Al) and titanium (Ti) are laminated is used as the material of the terminal electrode 103, but other metal materials may also be used.

[0045] The common terminal electrode 104 is connected to the semiconductor layer 207 through an opening 22 provided in the insulating layer 101. The common terminal electrode 104 functions as a source electrode or a drain electrode of the transistor. Also, the common terminal electrode 104 functions as a bridge wiring for electrically connecting the transistor of the first stacked structure 200 and the light-emitting diode of the second stacked structure 300. In this embodiment, since the common terminal electrode 104 is formed in the same process as the terminal electrode 103, it is in the same layer as the terminal electrode 103. That is, as the material of the common terminal electrode 104, the same metal material as that of the terminal electrode 103 is used.

[0046] Next, the second stacked structure 300 will be described. Among the second stacked structure 300, the alignment layer 301 and the semiconductor layers 302 to 307 are each composed of the same layers as the alignment layer 201 and the semiconductor layers 202 to 207 of the first stacked structure 200. That is, each corresponding layer is formed using the same material and the same process. Therefore, the specific description of the alignment layer 301 and the semiconductor layers 302 to 307 is the same as that of the alignment layer 201 and the semiconductor layers 202 to 207 described above. However, an exposed surface 31 for connection to the terminal electrode 105 described later is formed in the semiconductor layer 302. The semiconductor layer 302 has a stepped portion formed by reducing a part of the film thickness by half etching. That is, the semiconductor layer 302 has a first portion with the film thickness as it is during film formation and a second portion with a thinner film thickness than the first portion. The exposed surface 31 corresponds to the upper surface of the second portion.

[0047] The semiconductor layer 308 is provided on the semiconductor layer 307 and is composed of p-type gallium nitride (p-GaN). However, the semiconductor layer 308 has a higher impurity concentration than the semiconductor layer 307. That is, although the semiconductor layer 308 is composed of a semiconductor material, it contains impurities at a high concentration and thus functions substantially as an electrode layer. The semiconductor layer 308 can be formed in the same manner as the semiconductor layer 307, for example, by using a sputtering target composed of gallium nitride (GaN) doped with magnesium (Mg). Note that, instead of the semiconductor layer 308, an electrode layer may be formed using a metal material or a metal oxide material.

[0048] An insulating layer 101 is provided on the semiconductor layer 308. The insulating layer 101 functions as a common protective layer for the first stacked structure 200. As described above, in this embodiment, aluminum nitride (AlN) is used as the material of the insulating layer 101. A detailed description of the insulating layer 101 will be omitted.

[0049] The common terminal electrode 104 is connected to the semiconductor layer 308 via an opening 23 provided in the insulating layer 101. As shown in Figures 3 and 4, the common terminal electrode 104 functions as a bridge wiring that electrically connects the transistor of the first laminated structure 200 and the light-emitting diode of the second laminated structure 300. As mentioned above, in this embodiment, aluminum (Al) and titanium (Ti) are used as the material for the common terminal electrode 104. A detailed explanation of the common terminal electrode 104 is omitted.

[0050] As described above, the terminal electrode 105 is provided on a flat surface (exposed surface 31) created by forming a step in the semiconductor layer 302. A metallic material can be used as the material for the terminal electrode 105. For example, tantalum (Ta), tungsten (W), molybdenum (Mo), gold (Au), or alloys thereof can be used as the metallic material.

[0051] As described above, each pixel 111 in the display device 10 of this embodiment includes a first laminated structure 200 and a second laminated structure 300 provided on the same substrate 100. The first laminated structure 200 and the second laminated structure 300 are insulated and separated via a separation portion 51. In Figure 3, the separation portion 51 is shown as a groove between the first laminated structure 200 and the second laminated structure 300. However, in reality, as shown in Figure 4, the first laminated structure 200 and the second laminated structure 300 are patterned in an island-like manner by the separation portion 51.

[0052] Here, the first stacked structure 200 includes a transistor, and the second stacked structure 300 includes a light-emitting diode. In this case, the semiconductor layer 207 of the first stacked structure 200 is used as the active layer (channel formation region) of the transistor, and the semiconductor layer 307 of the second stacked structure 300 is used as a hole injection layer for injecting holes into the light-emitting diode. In this embodiment, the structure of the pixel 111 is simplified by sharing a part of the layer structure between the first stacked structure 200 and the second stacked structure 300.

[0053] The orientation layer 201 and semiconductor layers 202-207 of the first laminated structure 200 are identical layers formed from the same material and using the same process as the orientation layer 301 and semiconductor layers 302-307 of the second laminated structure 300. Therefore, in this embodiment, the film thickness of each corresponding layer is also identical. However, "identical" in this specification includes within the range of errors caused by the manufacturing process.

[0054] Strictly speaking, the second laminated structure 300 is not formed by the exact same process as the first laminated structure 200, because an additional process is added to form the exposed surface 31 after the semiconductor layers 302 to 308 have been stacked. In this embodiment, "same process" is used in the sense that the process of stacking multiple semiconductor layers is the same. Also, the semiconductor layer 302 will have both thick and thin portions due to the formation of the exposed surface 31, but the thickness of the thick portion will be the same as the thickness of the semiconductor layer 202 of the first laminated structure 200.

[0055] [Method for Manufacturing Pixel Structure] Figures 5A to 5F are schematic cross-sectional views showing a method for manufacturing the pixel structure of a display device 10 in one embodiment of the present invention. In Figures 5A to 5F, each element is indicated by the same reference numerals as in Figure 3, so detailed explanations may be omitted.

[0056] First, as shown in Figure 5A, an alignment film 501 is formed on the substrate 100. Although not shown in the figure, the surface of the substrate 100 has a silicon nitride layer and a silicon oxide layer stacked on top of each other as underlayers. In this embodiment, the alignment film 501 is formed on the substrate 100 by sputtering, CVD, vacuum deposition, electron beam deposition, or the like.

[0057] Next, as shown in Figure 5B, a plurality of semiconductor films 502 to 508 are sequentially formed on the alignment film 501 by sputtering. It is preferable to form the plurality of semiconductor films 502 to 508 continuously without exposing each semiconductor film to air. In this case, by appropriately changing the sputtering target used, semiconductor films with different impurity concentrations or compositions can be formed.

[0058] In this embodiment, semiconductor film 502 is composed of n-type gallium nitride (n-GaN). Specifically, semiconductor film 502 contains silicon-doped gallium nitride. Semiconductor films 503 and 504 are composed of n-type aluminum gallium nitride (n-AlGaN). Specifically, semiconductor films 503 and 504 contain silicon-doped aluminum gallium nitride. Semiconductor film 505 is composed of intrinsic indium gallium nitride (InGaN) without added impurities. Semiconductor film 506 is composed of p-type aluminum gallium nitride (p-AlGaN). Specifically, semiconductor film 506 contains magnesium-doped aluminum gallium nitride. Semiconductor film 507 is composed of p-type gallium nitride (p-GaN). Specifically, semiconductor film 507 contains magnesium-doped gallium nitride. Semiconductor film 508 is composed of p-type gallium nitride (p-GaN). Specifically, the semiconductor film 508 contains magnesium-doped gallium nitride and contains more magnesium than the semiconductor film 507.

[0059] When forming semiconductor films 502 to 507, the substrate 100 may be heated to a temperature of 400°C or higher and less than 600°C. Within this temperature range, even if a glass substrate is used as the substrate 100, it can sufficiently withstand the heat during film formation. The sputtering gas used is an inert argon gas or krypton gas, but nitrogen may be included in addition to argon gas.

[0060] Next, as shown in Figure 5C, the semiconductor film 508 is etched using photolithography to form a semiconductor layer 308. The amount of etching of the semiconductor film 508 is controlled by time, and etching is stopped when a portion of the semiconductor film 507 is exposed.

[0061] Next, as shown in Figure 5D, the alignment film 501, semiconductor films 502-507, and a portion of the semiconductor layer 308 are etched simultaneously using photolithography to form a separation portion 51 that reaches the surface of the substrate 100. For the etching process when forming the separation portion 51, it is preferable to use an anisotropic etching method such as reactive ion etching (RIE).

[0062] By forming the separation section 51, the alignment film 501 is separated into alignment layers 201 and 301. Furthermore, each semiconductor film 502 to 507 is separated into semiconductor layers 202 and 302, semiconductor layers 203 and 303, semiconductor layers 204 and 304, semiconductor layers 205 and 305, semiconductor layers 206 and 306, and semiconductor layers 207 and 307, respectively. In other words, the separation section 51 plays a role in insulatingly separating the first stacked structure 200 and the second stacked structure 300 shown in Figure 3, and functions as a boundary defining the transistor formation region 111a and the LED formation region 111b shown in Figure 1.

[0063] Next, as shown in Figure 5E, an aluminum nitride film is formed as the insulating layer 101 by sputtering or CVD. The insulating layer 101 is formed to cover the upper surfaces of the semiconductor layers 207 and 308, the sides of the alignment layers 201 and 301, the sides of the semiconductor layers 202 to 207, and the sides of the semiconductor layers 302 to 307.

[0064] After forming the insulating layer 101, the gate electrode 102 is formed on the insulating layer 101. In this embodiment, a tantalum film is formed by sputtering, and then the gate electrode 102 is formed by etching using photolithography.

[0065] Next, as shown in Figure 5F, the insulating layer 101 is etched to form openings 21 to 23, and then the terminal electrode 103 and common terminal electrode 104 are formed. In this embodiment, a structure is formed by stacking titanium film, aluminum film, and titanium film in that order using a sputtering method, and the terminal electrode 103 and common terminal electrode 104 are formed by etching them all at once using photolithography. The openings 21 to 23 formed in the insulating layer 101 expose a part of the semiconductor layers 207 and 308, respectively. Therefore, the terminal electrode 103 is connected to the semiconductor layer 207, and the common terminal electrode 104 is connected to the semiconductor layers 207 and 308.

[0066] Next, as shown in Figure 5G, a portion of the semiconductor layers 302 to 308 is etched using photolithography to form an exposed surface 31 on the semiconductor layer 302. The exposed surface 31 can be formed by performing half-etching on the semiconductor layer 302. For the etching process, it is preferable to use an anisotropic etching method such as reactive ion etching (RIE), similar to the method used to form the separation portion 51.

[0067] Finally, by forming the terminal electrode 105 on the exposed surface 31 formed on the semiconductor layer 302, the pixel structure shown in Figure 3 is completed.

[0068] As described above, the pixel structure of the display device 10 of this embodiment is formed by a common process for a portion of the layer structure of the first stacked structure 200 and the second stacked structure 300. Specifically, the alignment layer 201 and the alignment layer 301 are made up of the same layer, and the semiconductor layers 202 to 207 and the semiconductor layers 302 to 307 are each made up of the same layer. According to the manufacturing method of this embodiment, the semiconductor layer constituting the active layer of the transistor (specifically, the gallium nitride-based semiconductor layer) and the semiconductor layer constituting the light-emitting diode can be formed in the same layer. Therefore, according to this embodiment, the manufacturing cost of the display device can be reduced and the throughput can be improved.

[0069] <Second Embodiment> In this embodiment, an example of a display device having a pixel structure different from that of the first embodiment will be described. The same elements as in the first embodiment will be indicated by the same reference numerals, and detailed descriptions will be omitted.

[0070] Figure 6 is a schematic cross-sectional view showing the pixel structure of a display device 10a in one embodiment of the present invention. The difference from the display device 10 of the first embodiment shown in Figure 3 is that the display device 10a of this embodiment does not have a semiconductor layer 308 provided in the second stacked structure 300a. Thus, the semiconductor layer 308 may be omitted if the materials for the common terminal electrode 104 and the semiconductor layer 307 are selected so that ohmic contact between the common terminal electrode 104 and the semiconductor layer 307 is ensured.

[0071] According to this embodiment, the process for forming the semiconductor layer 308 can be omitted, thereby further reducing manufacturing costs and improving throughput compared to the first embodiment.

[0072] <Third Embodiment> In this embodiment, an example of a display device having a pixel structure different from that of the first embodiment will be described. The same elements as in the first embodiment will be indicated by the same reference numerals, and detailed descriptions will be omitted.

[0073] Figure 7 is a schematic cross-sectional view showing the pixel structure of the display device 10b in one embodiment of the present invention. The difference from the display device 10 of the first embodiment shown in Figure 3 is that in the display device 10b of this embodiment, an exposed surface 32 is provided on the semiconductor layer 202a of the first stacked structure 200a, and terminal electrodes 106 are connected to it. As with the second embodiment, the second stacked structure 300a does not have a semiconductor layer 308.

[0074] The terminal electrode 106 maintains the potential of the semiconductor layer 202a at a predetermined potential, thereby preventing the current that has passed through the transistor (specifically, the drive transistor 12 shown in Figure 1) from flowing downwards, and instead allowing it to flow to the light-emitting diode (specifically, the LED 14 shown in Figure 1) via the common terminal electrode 104.

[0075] As shown in Figure 1, a first drive power line 17 supplying voltage VDD is connected to the source of the drive transistor 12, and a second drive power line 18 supplying voltage VSS is connected to the cathode (n-type electrode) of the LED 14. In other words, in Figure 7, voltage VDD is applied to terminal electrode 103, and voltage VSS is applied to terminal electrode 105. At this time, if the voltage applied to terminal electrode 106 in this embodiment is V, then the relationship VSS ≤ V ≤ VDD (or V - VSS ≤ VDD - V) exists between each voltage. By making each voltage such a relationship, it is possible to suppress the current input from terminal electrode 103 from flowing downwards through the first laminated structure 200a, and to efficiently supply current to the second laminated structure 300a (i.e., the LED 14).

[0076] In this embodiment, an example is shown in which a predetermined voltage is applied to the semiconductor layer 202a of the first laminated structure 200a, but this does not negate the possibility of keeping the semiconductor layer 202a in a floating state. In this embodiment, it merely demonstrates that by maintaining a constant potential of the semiconductor layer 202a, current can be sent to the second laminated structure 300a more efficiently.

[0077] The first laminated structure 200a of this embodiment can be formed using the same process as the second laminated structure 300a. When forming the exposed surface 32 and terminal electrodes 106 on the first laminated structure 200a, the terminal electrodes 103, gate electrode 102, and common terminal electrode 104 can be protected with a resist mask (not shown) or the like.

[0078] <Fourth Embodiment> In this embodiment, an example of a display device having a pixel structure different from that of the first embodiment will be described. The same elements as in the first embodiment will be indicated by the same reference numerals, and detailed descriptions will be omitted.

[0079] Figure 8 is a schematic cross-sectional view showing the pixel structure of the display device 10c in one embodiment of the present invention. The difference from the display device 10 of the first embodiment shown in Figure 3 is that the display device 10c of this embodiment does not have semiconductor layers 203 to 207 provided in the first stacked structure 200b, and the thickness of the semiconductor layer 202b is reduced. As with the second embodiment, the semiconductor layer 308 is not provided in the second stacked structure 300b.

[0080] In this embodiment, the semiconductor layer 202b is half-etched all over until the film thickness reaches T1. As shown in Figure 8, the film thickness T1 corresponds to the height from the bottom surface to the exposed surface 31 of the semiconductor layer 302 of the second laminated structure 300b. That is, with respect to the surface of the substrate 100, the position of the top surface of the semiconductor layer 202b of the first laminated structure 200b and the position of the exposed surface 31 of the semiconductor layer 302 of the second laminated structure 300b are aligned.

[0081] In this embodiment, unlike the first embodiment, a semiconductor film (semiconductor film 507 in Figure 5B) that functions as a semiconductor layer 307 is formed first, and then the separation portion 51 is formed. After the separation portion 51 is formed, the exposed surface 31 is formed before the insulating layer 101 is formed. At this time, the semiconductor layer 202b can be formed by etching each semiconductor layer of the second laminated structure 300b to form the exposed surface 31. That is, in the process of forming the exposed surface 31 on the semiconductor layer 302 in the second laminated structure 300b, the semiconductor layers 202 to 207 in the first laminated structure 200b can be etched. After the semiconductor layer 202b is formed in this way, the insulating layer 101, gate electrode 102, terminal electrode 103, common terminal electrode 104, and terminal electrode 105 are formed.

[0082] As described above, in this embodiment, the pixel structure is simplified by sharing a part of the layer structure between the first stacked structure 200 and the second stacked structure 300. Also, similar to the first embodiment, a part of the layer structure between the first stacked structure 200b and the second stacked structure 300b can be formed using a common process. Therefore, according to this embodiment, the manufacturing cost of the display device can be reduced and the throughput can be improved.

[0083] In addition to the effects described above, according to this embodiment, an n-type semiconductor layer (gallium nitride layer) can be used as the active layer of the transistor. Furthermore, since the film thickness of the active layer of the transistor can be arbitrarily set by the height of the exposed surface 31, the degree of freedom in transistor design is improved.

[0084] <Fifth Embodiment> In this embodiment, an example of a display device having a pixel structure different from that of the first embodiment will be described. The same elements as in the first embodiment will be indicated by the same reference numerals, and detailed descriptions will be omitted.

[0085] Figure 9 is a schematic cross-sectional view showing the pixel structure of a display device 10d in one embodiment of the present invention. The difference from the display device 10 of the first embodiment shown in Figure 3 is that the display device 10d of this embodiment does not have semiconductor layers 202 to 207 provided on the first stacked structure 200b, and intrinsic semiconductor layers 209 and 309 are provided on the alignment layers 201 and 301, respectively. As with the second embodiment, the second stacked structure 300c does not have a semiconductor layer 308.

[0086] The first laminated structure 200c of this embodiment includes an intrinsic semiconductor layer 209 provided in contact with the alignment layer 201. The second laminated structure 300c includes an intrinsic semiconductor layer 309 provided in contact with the alignment layer 301. In this embodiment, the thickness of the semiconductor layers 209 and 309 is denoted as T2. The semiconductor layers 209 and 309 are identical layers formed from the same material and using the same process.

[0087] When forming the pixel structure of this embodiment, an intrinsic semiconductor film is formed between the alignment film 501 and the semiconductor film 502 in the process shown in Figure 5B of the first embodiment, without the addition of impurities. In this embodiment, indium gallium nitride (InGaN) is used as the material for the intrinsic semiconductor film, but the embodiment is not limited to this example.

[0088] Subsequently, similar to the fourth embodiment, a semiconductor film (semiconductor film 507 in Figure 5B) that functions as a semiconductor layer 307 is formed, and then the separation portion 51 is formed. After the separation portion 51 is formed, the exposed surface 31 is formed before the insulating layer 101 is formed. At this time, in the process of forming the exposed surface 31, in the first laminated structure 200c, all of the other semiconductor layers 203 to 207 (see Figure 5B) are removed, leaving only a part of the semiconductor layer 202 (see Figure 5B).

[0089] Subsequently, the remaining semiconductor layer 202 in the first laminated structure 200c is removed to expose the semiconductor layer 209. After exposing the semiconductor layer 209 in this manner, the insulating layer 101, gate electrode 102, terminal electrode 103, common terminal electrode 104, and terminal electrode 105 are formed.

[0090] As described above, in this embodiment, the pixel structure is simplified by sharing a part of the layer structure between the first stacked structure 200 and the second stacked structure 300. Also, similar to the first embodiment, a part of the layer structure between the first stacked structure 200b and the second stacked structure 300b can be formed using a common process. Therefore, according to this embodiment, the manufacturing cost of the display device can be reduced and the throughput can be improved.

[0091] In addition to the effects described above, according to this embodiment, an intrinsic semiconductor layer (indium gallium nitride layer) can be used as the active layer of the transistor. Furthermore, since the film thickness of the active layer (semiconductor layer 209) of the transistor can be set independently of the characteristics of the light-emitting diode, the degree of freedom in transistor design is improved.

[0092] <Sixth Embodiment> This embodiment describes an example of a display device having a pixel structure different from that of the first and fourth embodiments. Specifically, while the transistor in the fourth embodiment had a top-gate structure, in this embodiment the transistor has a bottom-gate structure. The same elements as in the first and fourth embodiments are indicated by the same reference numerals, and detailed explanations are omitted.

[0093] Figure 10 is a schematic cross-sectional view showing the pixel structure of the display device 10e in one embodiment of the present invention. Figure 11 is a schematic plan view showing the pixel structure of the display device 10e in one embodiment of the present invention. Figure 10 corresponds to a cross-sectional view cut along the line segment B-B' shown in Figure 11. The structure shown in Figure 10 is similar to the structure shown in Figure 8 of the fourth embodiment. In other words, the top-gate transistor in the structure shown in Figure 8 has been changed to a bottom-gate transistor in the structure shown in Figure 10.

[0094] In this embodiment, the semiconductor layer (n-type gallium nitride layer) that functions as semiconductor layer 202b functions as the active layer (channel formation region) of the transistor. In this respect, it is the same as in the fourth embodiment. However, in this embodiment, an insulating alignment layer 401 is provided between the conductive alignment layer 201 (specifically, the titanium layer) and the semiconductor layer 202b. In other words, in the transistor of this embodiment, the alignment layer 201 functions as the gate electrode, and the alignment layer 401 functions as the gate insulating layer. An alignment layer 402 is provided between the alignment layer 301 and the semiconductor layer 302.

[0095] When forming the pixel structure of this embodiment, an insulating alignment film is formed between the alignment film 501 and the semiconductor film 502 in the process shown in Figure 5B of the first embodiment. In this embodiment, an insulating film containing aluminum nitride (AlN) is used as the insulating alignment film, but the invention is not limited to this example. For example, in addition to aluminum nitride (AlN), gallium oxide (GaO) and aluminum oxide (AlN) can also be used as the insulating alignment film. ２ O ３ ), lithium niobate (LiNbO), BiLaTiO, SrFeO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT can be used.

[0096] The process after forming the insulating alignment film is almost the same as in the fourth embodiment, but the process for forming the separation portion 51 is different. Specifically, when forming the separation portion 51, the etching process is stopped once each semiconductor film and the insulating alignment film have been etched. Then, a different pattern of resist mask (not shown) is used to etch the alignment film 501 and expose the surface of the substrate 100. Specifically, as shown in Figure 11, in the first stacked structure 200e in plan view, the area of ​​the alignment layer 201 is made larger than that of the semiconductor layer 202b.

[0097] In this embodiment, since the orientation layer 201 is used as the gate electrode, a gate voltage needs to be applied. Therefore, as shown in Figure 11, the orientation layer 201 is stretched out and used as a connecting wire until it is connected to the gate wiring (not shown). In this case, it is preferable to widen the line width in order to reduce the resistance of the orientation layer 201 as much as possible.

[0098] As described above, in this embodiment, a laminated structure is used in which a conductive alignment layer 201 and an insulating alignment layer 401 are stacked as alignment layers for aligning each semiconductor of the first laminated structure 200 in the c-axis direction. The conductive alignment layer 201 is used as the gate electrode of the transistor, and the insulating alignment layer 401 is used as the gate insulating layer of the transistor. Therefore, the first laminated structure 200 includes a bottom gate structure transistor with the semiconductor layer 202b as the active layer.

[0099] <Seventh Embodiment> This embodiment describes an example of a display device having a pixel structure different from that of the first embodiment. Specifically, a structure in which high electron mobility transistors (HEMTs) are provided as transistors will be described. The same elements as in the first embodiment will be indicated by the same reference numerals, and detailed explanations will be omitted.

[0100] Figure 12 is a schematic cross-sectional view showing the pixel structure of a display device 10f in one embodiment of the present invention. The difference from the display device 10 of the first embodiment shown in Figure 3 is that the display device 10f of this embodiment has semiconductor layers 601 and 602 added to the first stacked structure 200f and the second stacked structure 300f, respectively. Specifically, in this embodiment, in the first stacked structure 200f, a semiconductor layer 601 which serves as a carrier supply layer (here, a hole supply layer) is provided between the semiconductor layer 207 (the active layer of the transistor) and the insulating layer 101 (the gate insulating layer of the transistor).

[0101] Semiconductor layer 601 and semiconductor layer 602 are identical layers formed from the same material and using the same process. In this embodiment, semiconductor layers 601 and 602 contain p-type aluminum gallium nitride (p-AlGaN). The p-type gallium nitride layer may have the same configuration as semiconductor layer 206. However, this is not the only example; any material that forms a heterojunction structure between it and the semiconductor layer on the lower side (farthest from the gate insulating layer) (in this case, semiconductor layer 207) should be selected.

[0102] According to this embodiment, a high electron mobility transistor can be formed by a simple structure in which a semiconductor layer that functions as a carrier supply layer is provided between the semiconductor layer that functions as the active layer of the transistor and the gate insulating layer in the first laminated structure 200f and the second laminated structure 300f.

[0103] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Based on these embodiments, any additions, deletions, or design changes made by those skilled in the art, or additions, omissions, or changes in processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0104] Furthermore, any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0105] 10, 10a-10f...Display device, 11...Selection transistor, 12...Drive transistor, 13...Capacitance element, 14...Light-emitting diode, 15...Scanning signal line, 16...Video signal line, 17...First drive power line, 18...Second drive power line. 21-23...Opening, 31, 32...Exposed surface, 51...Separation part, 100...Substrate, 101...Insulating layer, 102...Gate electrode, 103...Terminal electrode, 104...Common terminal electrode, 105...Terminal electrode, 106...Terminal electrode, 110...Display part, 111...Pixel, 111a...Transistor formation area, 111b...LED formation area, 120...Drive circuit part, 130...Terminal part, 140...Flex Blueprint circuit board, 200, 200a-200f...First stacked structure, 201...Alignment layer, 202, 202a, 202b, 203-207, 209...Semiconductor layer, 300, 300a-300f...Second stacked structure, 301...Alignment layer, 302-309...Semiconductor layer, 401, 402...Alignment layer, 501...Alignment film, 502-508...Semiconductor film, 601, 602...Semiconductor layer

Claims

1. A display device comprising: a first laminated structure provided in a first region of a substrate; and a second laminated structure provided in a second region of the substrate different from the first region, wherein each of the first and second laminated structures comprises: an alignment layer; a first semiconductor layer containing gallium nitride on the alignment layer; a second semiconductor layer on the first semiconductor layer; and a third semiconductor layer containing gallium nitride on the second semiconductor layer, wherein each of the alignment layer, first semiconductor layer, second semiconductor layer, and third semiconductor layer of the first laminated structure is the same layer as the alignment layer, first semiconductor layer, second semiconductor layer, and third semiconductor layer of the second laminated structure, and a first electrode is provided on the third semiconductor layer of the first laminated structure via an insulating layer, and the first and second laminated structures are electrically connected via a second electrode.

2. The display device according to claim 1, wherein the third semiconductor layer, the insulating layer, and the first electrode of the first stacked structure constitute a transistor, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer of the second stacked structure constitute a light-emitting diode.

3. The display device according to claim 1, wherein the second stacked structure further comprises a third semiconductor layer having a higher impurity concentration than the third semiconductor layer on top of the third semiconductor layer.

4. The display device according to claim 3, wherein the second electrode electrically connects the third semiconductor layer of the first stacked structure and the third semiconductor layer of the second stacked structure.

5. The display device according to claim 1, wherein the insulating layer covers a portion of the second laminated structure.

6. The display device according to claim 1, wherein the insulating layer covers the sides of the first laminated structure and the second laminated structure.

7. The display device according to claim 5 or 6, wherein the insulating layer comprises aluminum nitride.

8. The display device according to claim 1, wherein the first laminated structure further includes a third electrode connected to the third semiconductor layer via an opening provided in the insulating layer.

9. The display device according to claim 1, wherein the first semiconductor layer of the second laminated structure has a first portion having a first film thickness and a second portion having a second film thickness thinner than the first film thickness, and the second laminated structure further includes a fourth electrode provided on the second portion.

10. The display device according to claim 9, wherein the second semiconductor layer and the third semiconductor layer of the second stacked structure are provided on the first portion.

11. The display device according to claim 1, wherein the first semiconductor layer is a semiconductor layer having an n-type conductivity, and the third semiconductor layer is a semiconductor layer having a p-type conductivity.

12. The display device according to claim 1, wherein the first semiconductor layer and the third semiconductor layer of the second stacked structure include at least one of a carrier injection layer and a carrier transport layer.

13. The display device according to claim 1, wherein the second semiconductor layer is an intrinsic semiconductor layer without added impurities.

14. The display device according to claim 1, wherein the second semiconductor layer includes a multiple quantum well structure in which layers with different band gaps are alternately stacked.

Images