Semiconductor device, light detection device, and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a first substrate including a first semiconductor layer that has a first surface and a second surface facing each other and is provided with a plurality of first functional elements, and a first wiring layer provided on the first surface side and forming a first bonding surface; a second substrate including a second semiconductor layer that has a third surface and a fourth surface facing each other and is provided with a plurality of second functional elements, and a second wiring layer provided on the third surface side and forming a second bonding surface bonded to the first bonding surface; a plurality of bonding electrodes electrically connecting the plurality of first functional elements and the plurality of second functional elements, and provided in a first direction and a second direction orthogonal to the first direction; and one or a plurality of shield electrodes disposed between at least one set of the plurality of bonding electrodes adjacent to each other in a third direction that is an oblique direction to the first direction and the second direction, on at least one of the first bonding surface and the second bonding surface.

Description

Semiconductor device, photodetector, and electronic device

[0001] The present disclosure relates to a semiconductor device, a photodetector, and an electronic device having a plurality of semiconductor layers stacked on one another.

[0002] For example, in Non-Patent Document 1, a three-layer stacked image sensor with improved FD conversion gain due to the mirror effect caused by reducing the capacitance of through-wiring (DCNT) penetrating a wafer has been reported.

[0003] Gwi-Deok Ryan Lee*, Dae-Hoon Kim, Doowon Kwon, Jong-Eun Park, Dongseok Cho, Jeongsoon Kang, Gyunha Park, Junha Kang, Minho Jang, Seungjae Oh, Doyeon Kim, Sol Yoon, Yongjun Kim, Sejin Park, Kyungtae Lim, Dongjun Oh, SooYoung Kang, Keunhyoung Park, Changhwa Kim, Hyoju Kim, Taeyeong Kim, Kyu-Ha Lee, Hyoukyung Cho, Son-Kwan Hwang, Hojin Lee, Jae-Kyu Lee, Hyunchul Kim, Chang-rok Moon, Jaihyuk Song, IEDM 2023, 40-1

[0004] By the way, miniaturization of pixels is required in a photodetector.

[0005] It is desirable to provide a semiconductor device, a photodetector, and an electronic device capable of realizing miniaturization of pixels.

[0006] A semiconductor device according to one embodiment of the present disclosure comprises: a first substrate having a first and second opposing surface and a first semiconductor layer on which a plurality of first functional elements are provided, and a first wiring layer provided on the first surface side and forming a first bonding surface; a second substrate having a third and fourth opposing surface and a second semiconductor layer on which a plurality of second functional elements are provided, and a second wiring layer provided on the third surface side and forming a second bonding surface that is bonded to the first bonding surface; a plurality of bonding electrodes at the first bonding surface and the second bonding surface that electrically connect a plurality of first functional elements and a plurality of second functional elements, respectively, and arranged in a first direction and a second direction orthogonal to the first direction, respectively; and one or more shield electrodes disposed between at least one pair of adjacent bonding electrodes in a third direction oblique to the first direction and the second direction at least one of the first bonding surface and the second bonding surface.

[0007] A photodetector according to one embodiment of the present disclosure has opposing first and second surfaces, and a first semiconductor layer having a plurality of photoelectric conversion units provided for each pixel and a plurality of charge holding units provided for one or more pixels for temporarily holding the charge transferred from the plurality of photoelectric conversion units, and the plurality of charge holding units are provided in a first direction and a second direction orthogonal to the first direction, respectively, and a first substrate having a first wiring layer provided on the first surface side and forming a first junction surface, and opposing third and fourth surfaces, one provided for each of one or more pixels, and a picture based on the charge carrier output from the pixel The device comprises a second semiconductor layer provided with a plurality of readout circuits that output elementary signals, and a second wiring layer provided on the third surface side that forms a second junction surface which is joined to the first junction surface, and a plurality of junction electrodes arranged in a first direction and a second direction, respectively, which electrically connect a plurality of charge holding units and a plurality of readout circuits at the first junction surface and the second junction surface, respectively, and one or more shield electrodes arranged between at least one pair of adjacent junction electrodes in a third direction which is oblique to the first direction and the second direction at least one of the first junction surface and the second junction surface.

[0008] An electronic device according to one embodiment of the present disclosure is equipped with the light detection device according to the above embodiment as a light detection device.

[0009] In a semiconductor device according to one embodiment of the present disclosure, a photodetector according to one embodiment of the present disclosure, and an electronic device according to one embodiment of the present disclosure, a first substrate including a first semiconductor layer having opposing first and second surfaces and a first wiring layer provided on the first surface side and forming a first bonding surface, and a second substrate including a second semiconductor layer having opposing third and fourth surfaces and a second wiring layer provided on the third surface side and forming a second bonding surface that is bonded to the first bonding surface, are bonded via a plurality of bonding electrodes. The first semiconductor layer constituting the first substrate has a plurality of first functional elements, and the second semiconductor layer has a plurality of second functional elements. The plurality of bonding electrodes electrically connect the plurality of first functional elements and the plurality of second functional elements, respectively, at the bonding surface (first bonding surface and second bonding surface) between the first substrate and the second substrate, and are arranged in a first direction and a second direction, respectively. At least one of the bonding surfaces between the first substrate and the second substrate is further provided with one or more shield electrodes between at least one pair of adjacent bonding electrodes in a third direction oblique to the first and second directions. This reduces the area of ​​the shield electrodes at the bonding surface between the first and second substrates and reduces the capacitance between the bonding electrodes and the shield electrodes.

[0010] Figure 1 is a block diagram showing an example of the functional configuration of a photodetector according to the first embodiment of this disclosure. Figure 2 is a schematic plan view showing the general configuration of the photodetector shown in Figure 1. Figure 3 is a schematic diagram showing the cross-sectional configuration along the line A-A' shown in Figure 2. Figure 4 is an equivalent circuit diagram of the pixel sharing unit shown in Figure 1. Figure 5 is a schematic cross-sectional view showing an example of a specific configuration of the photodetector shown in Figure 3. Figure 6A is a schematic diagram showing an example of the planar configuration of pixels on the first substrate shown in Figure 5. Figure 6B is a schematic diagram showing the planar configuration of the pad portion provided on the first substrate shown in Figure 6A. Figure 7 is a schematic cross-sectional view showing an enlarged part of the photodetector shown in Figure 5. Figure 8 is a schematic diagram for explaining the path of input signals, etc., to the photodetector shown in Figure 3. Figure 9 is a schematic diagram for explaining the signal path of the pixel signal of the photodetector shown in Figure 3. Figure 10A is a schematic plan view showing an example of the layout of bonding electrodes and shield electrodes at the bonding surface between the first substrate and the second substrate. Figure 10B is a schematic plan view showing an example of misalignment of the bonding electrode and shield electrode shown in Figure 10A. Figure 11A is a schematic plan view showing another example of the layout of the bonding electrode and shield electrode at the bonding surface between the first substrate and the second substrate. Figure 11B is a schematic plan view showing an example of misalignment of the bonding electrode and shield electrode shown in Figure 11A. Figure 12 is a schematic view showing another example of the planar shape of the shield electrode. Figure 13 is a schematic view showing another example of the planar shape of the shield electrode. Figure 14 is a schematic view showing another example of the planar shape of the shield electrode. Figure 15 is a schematic view showing another example of the planar shape of the shield electrode. Figure 16 is a schematic plan view showing an example of the layout of the bonding electrode and shield electrode at the bonding surfaces of the first substrate and the second substrate, respectively. Figure 17 is a diagram illustrating an example of the readout mode of the photodetector shown in Figure 10A. Figure 18 is a diagram illustrating another example of the readout mode of the photodetector shown in Figure 10A. Figure 19 is a diagram illustrating another example of the readout mode of the photodetector shown in Figure 10A. Figure 20 illustrates another example of the readout method of the photodetector shown in Figure 10A.Figure 21 is a schematic plan view showing an example of the layout of bonding electrodes and shield electrodes on the bonding surfaces of the first and second substrates of a photodetector according to Modification 1 of the present disclosure. Figure 22 is a diagram illustrating an example of a readout mode of the photodetector shown in Figure 21. Figure 23 is a diagram illustrating another example of a readout mode of the photodetector shown in Figure 21. Figure 24 is a schematic plan view illustrating another example of a readout mode of the photodetector shown in Figure 21. Figure 25 is a schematic plan view illustrating another example of a readout mode of the photodetector shown in Figure 21. Figure 26 is a schematic diagram showing another example of the planar shape of the shield electrode in the photodetector shown in Figure 24. Figure 27 is a schematic diagram showing another example of the planar shape of the shield electrode in the photodetector shown in Figure 24. Figure 28 is a schematic cross-sectional view showing an example of the configuration of a photodetector according to a second embodiment of the present disclosure. Figure 29 is a schematic diagram showing an example of the planar configuration of the pixel circuit and connecting electrode on the second substrate of the photodetector shown in Figure 28. Figure 30 is a schematic plan view showing another example of the formation location of the mirror capacitance in the photodetector shown in Figure 28. Figure 31 is a schematic plan view showing another example of the formation location of the mirror capacitance in the photodetector shown in Figure 28. Figure 32 is a schematic plan view showing an example of the formation location of the mirror capacitance in the photodetector shown in Figure 28. Figure 33A is a schematic cross-sectional view illustrating an example of a method for manufacturing the main part of the photodetector shown in Figure 28. Figure 33B is a schematic cross-sectional view showing the process following Figure 33A. Figure 33C is a schematic cross-sectional view showing the process following Figure 33B. Figure 33D is a schematic cross-sectional view showing the process following Figure 33C. Figure 33E is a schematic cross-sectional view showing the process following Figure 33D. Figure 33F is a schematic cross-sectional view showing the process following Figure 33E. Figure 33G is a schematic cross-sectional view showing the process following Figure 33F. Figure 33H is a schematic cross-sectional view showing the process following Figure 33G. Figure 34A is a schematic cross-sectional diagram illustrating another example of the manufacturing method for the main part of the light detection device shown in Figure 28. Figure 34B is a schematic cross-sectional diagram showing the process following Figure 34A. Figure 34C is a schematic cross-sectional diagram showing the process following Figure 34B. Figure 34D is a schematic cross-sectional diagram showing the process following Figure 34C. Figure 34E is a schematic cross-sectional diagram showing the process following Figure 34D. Figure 34F is a schematic cross-sectional diagram showing the process following Figure 34E.Figure 35 is a schematic cross-sectional view showing an example of the configuration of the main part of a photodetector according to Modification 2 of this disclosure. Figure 36 is a schematic cross-sectional view showing another example of the configuration of the main part of a photodetector according to Modification 2 of this disclosure. Figure 37 is a schematic cross-sectional view showing another example of the configuration of the main part of a photodetector according to Modification 2 of this disclosure. Figure 38 is a schematic view showing an example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of a photodetector according to Modification 3 of this disclosure. Figure 39 is a schematic view showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of a photodetector according to Modification 3 of this disclosure. Figure 40 is a schematic view showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of a photodetector according to Modification 3 of this disclosure. Figure 41 is a schematic view showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of a photodetector according to Modification 3 of this disclosure. Figure 42 is a schematic view showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of a photodetector according to Modification 3 of this disclosure. Figure 43 is a schematic diagram showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of the photodetector according to Modification 3 of the present disclosure. Figure 44 is a schematic diagram showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of the photodetector according to Modification 3 of the present disclosure. Figure 45 is a schematic diagram showing another example of the planar configuration of the pixel circuit and connecting electrodes on the second substrate of the photodetector according to Modification 3 of the present disclosure. Figure 46 is a block diagram showing an example of the configuration of an electronic device having the photodetector shown in Figure 1. Figure 47A is a schematic diagram showing an example of the overall configuration of a photodetector system using the photodetector shown in Figure 1, etc. Figure 47B is a diagram showing an example of the circuit configuration of the photodetector system shown in Figure 47A. Figure 48 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. Figure 49 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Figure 50 is a block diagram showing an example of the schematic configuration of a vehicle control system. Figure 51 is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit.

[0011] The embodiments for implementing this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. First Embodiment (An example of a photodetector in which, at the junction surface between the first and second substrates, a number of junction electrodes are arranged in a zigzag pattern in the row and column directions, and shield electrodes are spaced apart from each other only between the junction electrodes that are closest to each other in a plan view.) 2. Modification 1 (Another example of the configuration of a photodetector.) 3. Second Embodiment (An example of a photodetector in which a part of the shield electrodes arranged at the junction surface between the first and second substrates is electrically connected to the source of the amplifying transistor via through wiring.) 4. Modification 2 5. Modification 3 6. Application Examples 7. Application Examples

[0012] <1. First Embodiment> The semiconductor device (photodetector 1) according to the first embodiment of the present disclosure is used, for example, as a CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0013] The photodetector 1 of this embodiment has a structure in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked, and the first substrate 100 and the second substrate 200 are joined to each other via a plurality of bonding electrodes 125, 215. The first substrate 100 includes a semiconductor layer 100S having a pair of opposing surfaces (front surface 100S1 and back surface 100S2), and a wiring layer 100T provided on the front surface 100S1 side of the semiconductor layer 100S to form a bonding surface 124S. The second substrate 200 includes a semiconductor layer 200S having a pair of opposing surfaces (front surface 200S1 and back surface 200S2), and a wiring layer 200T-1 provided on the back surface 200S2 side to form a bonding surface 221S. The semiconductor layer 100S is provided with a plurality of photodiodes PD and a plurality of floating diffusion electrodes FD, for example, for each pixel 541. The semiconductor layer 200S is provided with a plurality of pixel circuits 210 that output pixel signals based on the charge output from each pixel 541. The plurality of junction electrodes 125, 215 electrically connect the plurality of floating diffusion FDs and the plurality of pixel circuits 210 at the junction surface (junction surface 124S, 221S) between the first substrate 100 and the second substrate 200, and are arranged in the X-axis direction and the Y-axis direction, respectively. Further, at the junction surface between the first substrate 100 and the second substrate 200, a plurality of junction electrodes 126, 216 are arranged, for example, spaced apart from each other, between the plurality of adjacent junction electrodes 125, 215 in the diagonal directions of the X-axis and Y-axis directions.

[0014] Here, the first substrate 100 corresponds to a specific example of the "first substrate" as one embodiment of the present disclosure, and the second substrate 200 corresponds to a specific example of the "second substrate" as one embodiment of the present disclosure. The semiconductor layer 100S corresponds to a specific example of the "first semiconductor layer" as one embodiment of the present disclosure. The surface 100S1 corresponds to a specific example of the "first surface" as one embodiment of the present disclosure, and the back surface 100S2 corresponds to a specific example of the "second surface" as one embodiment of the present disclosure. The semiconductor layer 200S corresponds to a specific example of the "second semiconductor layer" as one embodiment of the present disclosure. The surface 200S1 corresponds to a specific example of the "fourth surface" as one embodiment of the present disclosure, and the back surface 200S2 corresponds to a specific example of the "third surface" as one embodiment of the present disclosure. The photodiode PD corresponds to a specific example of the "photoelectric conversion unit" as one embodiment of the present disclosure. The floating diffusion FD corresponds to a specific example of the "first functional element" and "charge holding unit" as one embodiment of the present disclosure. The pixel circuit 210 corresponds to a specific example of the "second functional element" and "readout circuit" as one embodiment of the present disclosure. The bonding surface 124S corresponds to a specific example of the "first bonding surface" as one embodiment of the present disclosure, and the bonding surface 221S corresponds to a specific example of the "second bonding surface" as one embodiment of the present disclosure. The bonding electrodes 125 and 215 correspond to a specific example of the "bonding electrode" as one embodiment of the present disclosure. The bonding electrodes 126 and 216 correspond to a specific example of the "shielding electrode" as one embodiment of the present disclosure, and in particular, bonding electrode 126 corresponds to a specific example of the "first shielding electrode" as one embodiment of the present disclosure, and bonding electrode 216 corresponds to a specific example of the "second shielding electrode" as one embodiment of the present disclosure.

[0015] [Functional Configuration of the Light Detection Device] Figure 1 is a block diagram showing an example of the functional configuration of the light detection device 1.

[0016] The light detection device 1 in Figure 1 includes, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0017] In the pixel array section 540, multiple pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 containing multiple pixels 541 serves as the repeating unit, and these are repeatedly arranged in an array consisting of row and column directions. For convenience, in this specification, the row direction may be referred to as the H direction or X-axis direction, and the column direction, which is orthogonal to the row direction, may be referred to as the V direction or Y-axis direction. In the example in Figure 1, one pixel sharing unit 539 contains eight pixels (pixels 541A to 541H). Each of the pixels 541A to 541H has a photodiode PD (illustrated in Figure 5, etc., described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in Figure 4, described later). In other words, there is one pixel circuit (pixel circuit 210 described later) for every eight pixels (pixels 541A to 541H). By operating this pixel circuit in a time-division multiplexing manner, the pixel signals of each of the pixels 541A to 541H are read out sequentially. The pixels 541A to 541H are arranged, for example, in a 2x4 grid. The pixel array section 540 is provided with the pixels 541A to 541H, as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column read lines) 543. The row drive signal lines 542 drive the pixels 541 included in each of the plurality of pixel sharing units 539 that are arranged in the row direction in the pixel array section 540. The row drive signal lines 542 drive each pixel of the pixel sharing unit 539 that is arranged in the row direction. As will be explained in detail later with reference to Figure 4, the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of these plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal lines (column read lines) 543. Pixel signals are read out from each of the pixels 541A to 541H included in the pixel sharing unit 539 via vertical signal lines (column readout lines) 543.

[0018] The row drive unit 520 includes, for example, a row address control unit that determines the position of a row for driving pixels, in other words, a row decoder unit, and a row drive circuit unit that generates signals for driving pixels 541A to 541H.

[0019] The timing control unit 530 supplies timing control signals to the row drive unit 520 and the column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.

[0020] The column signal processing unit 550 includes, for example, a load circuit section connected to the vertical signal line 543 and forming a source follower circuit with the pixels 541A to 541H (pixel sharing unit 539). The column signal processing unit 550 may also have an amplification circuit section that amplifies the signal read from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may also have a noise processing unit. In the noise processing unit, for example, the noise level of the system is removed from the signal read from the pixel sharing unit 539 as a result of photoelectric conversion.

[0021] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared with it. In the counter unit, the time until the comparison result in the comparator unit is reversed is measured. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout column.

[0022] The image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the photodetector 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0023] One example of signal processing performed in the image signal processing unit 560 is tone curve correction processing, which increases the tonal range of AD-converted imaging data if it is data of a dark subject, and decreases the tonal range if it is data of a bright subject. In this case, it is desirable to store in advance the characteristic data of the tone curve on which the tonal range of the imaging data will be corrected in the data storage unit of the image signal processing unit 560.

[0024] The input unit 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, and characteristic data from outside the device to the light detection device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, stored in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0025] The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is for taking the signal input to the input terminal 511 into the photodetector 1. The input amplitude changing section 513 changes the amplitude of the signal taken in by the input circuit section 512 to an amplitude that is easy to use inside the photodetector 1. The input data conversion circuit section 514 changes the order of the data sequence of the input data. The input data conversion circuit section 514 is configured, for example, by a serial-to-parallel conversion circuit. In this serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in the input section 510A, the input amplitude changing section 513 and the input data conversion circuit section 514 may be omitted. The power supply section supplies power set to various voltages required inside the photodetector 1, based on the power supply supplied to the photodetector 1 from the outside.

[0026] When the light detection device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0027] The output unit 510B outputs image data to the outside of the device. This image data includes, for example, image data captured by the light detection device 1 and image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0028] The output data conversion circuit 515 is configured, for example, by a parallel-to-serial conversion circuit, in which the parallel signal used inside the photodetector 1 is converted into a serial signal. The output amplitude modification unit 516 modifies the amplitude of the signal used inside the photodetector 1. The signal with the modified amplitude is made easier to use by external devices connected outside the photodetector 1. The output circuit 517 is a circuit that outputs data from inside the photodetector 1 to outside the device, and the output circuit 517 drives the wiring outside the photodetector 1 connected to the output terminal 518. At the output terminal 518, data is output from the photodetector 1 to outside the device. In the output unit 510B, the output data conversion circuit 515 and the output amplitude modification unit 516 may be omitted.

[0029] When the light detection device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit for outputting data to the external memory device. The external memory device may be, for example, flash memory, SRAM, or DRAM.

[0030] [Schematic Configuration of the Photodetector] Figures 2 and 3 show an example of the schematic configuration of the photodetector 1. The photodetector 1 comprises three substrates (first substrate 100, second substrate 200, and third substrate 300). Figure 2 schematically shows the planar configuration of each of the first substrate 100, second substrate 200, and third substrate 300, and Figure 3 schematically shows the cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 stacked on top of each other. Figure 3 corresponds to the cross-sectional configuration along the line A-A' shown in Figure 2. The photodetector 1 is a three-dimensional photodetector constructed by bonding together three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the wiring contained in each of the first substrate 100, the second substrate 200, and the third substrate 300, along with the interlayer insulating film surrounding it, are conveniently referred to as the wiring layers (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and are arranged in the order of semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows shown in Figure 3 indicate the direction of incidence of light L to the photodetector 1. In this specification, for convenience, the side on which light is incident in the photodetector 1 may be referred to as "bottom," "lower side," or "downward," and the side opposite to the side on which light is incident may be referred to as "top," "upper side," or "upward" in the following cross-sectional diagrams. Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the side with the wiring layer may be referred to as the front surface and the side with the semiconductor layer as the back surface. However, the description in this specification is not limited to the above terminology. The photodetector 1 is, for example, a back-illuminated photodetector in which light is incident from the back surface of a first substrate 100 having a photodiode.

[0031] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A to 541H of the pixel sharing unit 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) of the pixel sharing unit 539. The pixel circuit reads out the pixel signal transferred from the photodiode of each of the pixels 541A to 541H via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has power lines 544 (power lines VDD, etc., described later) extending in the row direction. The third substrate 300 has, for example, an input unit 510A, a row drive unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row drive unit 520 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the row drive unit 520 is provided in a region that overlaps near the H-direction end of the pixel array unit 540 in the stacking direction. The column signal processing unit 550 is provided, for example, in a region that partially overlaps the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is located in a region that overlaps with the vicinity of the V-direction end of the pixel array section 540 in the stacking direction. Although not shown in the figures, the input section 510A and the output section 510B may be located in a part other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be located on the back surface (light incident surface) of the first substrate 100. The pixel circuit located on the second substrate 200 may also be referred to as a pixel transistor circuit, a group of pixel transistors, a pixel transistor, a pixel readout circuit, or a readout circuit.In this specification, the term "pixel circuit" is used.

[0032] The first substrate 100 and the second substrate 200 are electrically connected, for example, via a plurality of contact portions, as will be described in detail later. The second substrate 200 and the third substrate 300 are electrically connected, for example, via contact portions 201, 202, 301, and 302. Contact portions 201 and 202 are provided on the second substrate 200, and contact portions 301 and 302 are provided on the third substrate 300. Contact portion 201 of the second substrate 200 is in contact with contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 is in contact with contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R provided with a plurality of contact portions 201, and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array portion 540 and the row drive portion 520 in the stacking direction, as shown in Figure 3, for example. In other words, the contact regions 201R and 301R are provided in the region where the row drive portion 520 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact regions 201R and 301R are provided, for example, at the ends in the H direction of such a region. In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row drive portion 520, specifically the end of the row drive portion 520 in the H direction. The contact sections 201 and 301 connect, for example, the row drive unit 520 provided on the third substrate 300 to the row drive signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may also connect, for example, the input unit 510A provided on the third substrate 300 to the power line 544 and the reference potential line (for example, ground GND). The contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction.In other words, the contact areas 202R and 302R are provided, for example, in the region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact areas 202R and 302R are located, for example, at the V-direction end of such a region. On the third substrate 300, for example, the contact area 301R is provided at a position overlapping with a part of the column signal processing unit 550, specifically the V-direction end of the column signal processing unit 550. The contact areas 202 and 302 are for connecting, for example, the pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion by a photodiode) output from each of the multiple pixel sharing units 539 of the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0033] Figure 3 is an example of a cross-sectional view of the photodetector 1, as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the photodetector 1 has an electrical connection section that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact sections 201, 202, 301, and 302 are formed with electrodes made of a conductive material. The conductive material is made of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly joining wirings formed as electrodes, for example, enabling signal input and / or output between the second substrate 200 and the third substrate 300.

[0034] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at any desired location. For example, as described in Figure 3 as contact regions 201R, 202R, 301R, and 302R, it may be provided in a region that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it may be provided in a region that overlaps with the peripheral portion located outside the pixel array portion 540 in the stacking direction.

[0035] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200. The connection holes H1 and H2 are located outside the pixel array portion 540 (or the portion overlapping the pixel array portion 540). For example, connection hole H1 is located outside the pixel array portion 540 in the H direction, and connection hole H2 is located outside the pixel array portion 540 in the V direction. For example, connection hole H1 reaches the input portion 510A provided on the third substrate 300, and connection hole H2 reaches the output portion 510B provided on the third substrate 300. The connection holes H1 and H2 may be cavities, or they may contain conductive material in at least part of them. For example, there is a configuration in which bonding wires are connected to electrodes formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which electrodes formed as input section 510A and / or output section 510B are connected to conductive material provided in connection holes H1 and H2. The conductive material provided in connection holes H1 and H2 may be embedded in part or all of connection holes H1 and H2, or the conductive material may be formed on the side walls of connection holes H1 and H2.

[0036] In Figure 3, the input section 510A and output section 510B are provided on the third board 300, but the design is not limited to this. For example, the input section 510A and / or output section 510B can be provided on the second board 200 by sending the signals from the third board 300 to the second board 200 via wiring layers 200T and 300T. Similarly, the input section 510A and / or output section 510B can be provided on the first board 100 by sending the signals from the second board 200 to the first board 100 via wiring layers 100T and 200T.

[0037] Figure 4 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4, eight pixels 541A to 541H are represented), one pixel circuit 210 connected to these plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 operates the one pixel circuit 210 in a time-division manner, thereby sequentially outputting the pixel signals of each of the eight pixels 541 (pixels 541A to 541H) included in the pixel sharing unit 539 to the vertical signal line 543. In a configuration where multiple pixels 541 are connected to a single pixel circuit 210, and the pixel signals of these multiple pixels 541 are output by the single pixel circuit 210 in a time-division manner, this is referred to as "multiple pixels 541 sharing a single pixel circuit 210."

[0038] Pixels 541A to 541H share common components. Hereafter, in order to distinguish the components of pixels 541A to 541H from one another, the following identification numbers are added to the end of the code of the component of pixel 541A: identification number 1, identification number 2, identification number 3, identification number 4, identification number 4, identification number 5, identification number 541E, identification number 6, identification number 7, identification number 7, and identification number 8. When it is not necessary to distinguish the components of pixels 541A to 541H from one another, the identification number at the end of the code of the component of pixel 541A to 541H is omitted.

[0039] Each pixel 541A to 541H includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1 to PD8), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground GND). The photodiode PD converts incident light into photoelectric energy and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1 to TR8) are, for example, N-type MOS (Metal Oxide Semiconductor) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 (see Figure 1) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (Floating Diffusion FD1 to FD8) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage corresponding to the amount of charge due to the capacitance Cfd of the floating diffusion FD.

[0040] The eight floating diffusion FDs (floating diffusion FD1 to FD8) included in the pixel sharing unit 539 are electrically connected to each other, as well as to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to a drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to the pixel sharing unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539.

[0041] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and extends from the surface of the semiconductor layer (semiconductor layer 100S in Figure 5, described later) to a depth that reaches the photodiode PD, as shown in Figure 6 below. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. This amplification transistor AMP, together with the load circuit connected to the vertical signal line 543, constitutes a source follower in the column signal processing unit 550. When the selection transistor SEL is turned ON, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, amplification transistor AMP, and selection transistor SEL are, for example, N-type MOS transistors. The feedback capacitance Cfb is the capacitance that enters between the floating diffusion FD and the source of the amplification transistor AMP. When operating as a source follower, the feedback capacitance Cfb is significantly reduced, for example to about 1 / 10, compared to when not operating as a source follower (for example, in common-source operation), due to the positive feedback effect (Miller effect).

[0042] The FD conversion gain switching transistor FDG is used when changing the gain of the charge-voltage conversion in the floating diffusion FD. Generally, when shooting in a dark place, the pixel signal is small. Based on Q = CV, when performing charge-voltage conversion, if the capacitance (capacitance Cfd) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will become small. On the other hand, in a bright place, since the pixel signal becomes large, if the capacitance Cfd is not large, the floating diffusion FD cannot receive all the charge of the photodiode PD. Furthermore, it is necessary for the capacitance Cfd to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, becomes small). Considering these, when the FD conversion gain switching transistor FDG is turned on, since the gate capacitance corresponding to the FD conversion gain switching transistor FDG increases, the overall capacitance Cfd becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall capacitance Cfd becomes small. Thus, by switching the FD conversion gain switching transistor FDG on and off, the capacitance Cfd can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type MOS transistor.

[0043] Note that a configuration without the FD conversion gain switching transistor FDG is also possible. At this time, for example, the pixel circuit 210 is composed of, for example, three transistors: an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor such as, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0044] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542. The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figure, the number of pixels 541 sharing one pixel circuit 210 may be other than eight. For example, two or four pixels 541 may share one pixel circuit 210.

[0045] [Specific Configuration of Photo-Detection Device] FIG. 5 schematically shows an example of the specific cross-sectional configuration of the photo-detection device 1. Note that FIG. 5 is schematically shown to make the positional relationship of the components easy to understand, and it may differ from the actual cross-section. The photo-detection device 1 is, for example, a back-illuminated photo-detection device. The photo-detection device 1 includes three substrates, namely, a first substrate 100, a second substrate 200, and a third substrate 300, which are laminated in this order from the light incident side. The photo-detection device 1 further has a light receiving lens 401 on the light incident side (the back side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The photo-detection device 1 has a pixel array portion 540 in which a plurality of pixels 541 are repeatedly arranged in an array, and a peripheral portion 540B disposed around the pixel array portion 540. The light receiving lens 401 is provided, for example, for each of the plurality of pixels 541.

[0046] The first substrate 100 has a semiconductor layer 100S and a wiring layer 100T. The semiconductor layer 100S has a pair of opposing surfaces (front surface 100S1 and back surface 100S2), and the wiring layer 100T is provided on the front surface 100S1 side. The back surface 100S2 of the semiconductor layer 100S is a light-receiving surface, and a light-receiving lens 401 is arranged on the back surface 100S2 side for each pixel 541. Between the semiconductor layer 100S and the light-receiving lens 401, an insulating film 111 and a fixed charge film 112 are provided in order from the light-receiving lens 401 side. The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided for each pixel 541.

[0047] The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface 100S1 and its vicinity, and an n-type semiconductor region 114 in the remaining region (a region deeper than the p-well layer 115). For example, this n-type semiconductor region 114 and the p-well layer 115 constitute a pn-junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0048] A floating diffusion FD and a VSS contact region 118 are provided spaced apart from each other near the surface 100S1 of the semiconductor layer 100S.

[0049] The floating diffusion FD is composed of an n-type semiconductor region provided within the p-well layer 115. The floating diffusion FD is connected from the first substrate 100 to the second substrate 200 via electrical means. For example, the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG via a through-wiring 120E that penetrates the semiconductor layer 200S constituting the second substrate 200.

[0050] The VSS contact region 118 is an area electrically connected to a reference potential line (e.g., ground GND) and is composed of a p-type semiconductor region provided within the p-well layer 115. The VSS contact region 118 is connected to the pad portion 121 via, for example, a connecting via 121C, and is connected to a bonding electrode 125 exposed on the surface of the bonding surface 124S of the first substrate 100 via wiring 121D, etc. The bonding electrode 125 electrically connected to the VSS contact region 118 is bonded to a bonding electrode 215 exposed on the bonding surface 221S of the second substrate 200 with the first substrate 100. The VSS contact region 118 may also be connected to the ground potential or a fixed potential via, for example, through wiring that penetrates the semiconductor layer 200S constituting the second substrate 200. This supplies a reference potential to the semiconductor layer 100S.

[0051] The transfer transistor TR is provided on the surface 100S1 side of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 114. By configuring the transfer transistor TR as such a vertical transistor, the occurrence of pixel signal transfer failures becomes less likely, and the readout efficiency of the pixel signal can be improved.

[0052] As described above, the transfer gate TG is electrically connected to the drive signal line. The transfer gate TG and the drive signal line are electrically connected, for example, via a through-wiring 122E that penetrates the semiconductor layer 200S constituting the second substrate 200. The through-wiring 122E is provided in the peripheral portion 540B. The transfer gate TG is connected, for example, to the through-wiring 122E provided in the peripheral portion 540B via a wiring layer W11 and bonding electrodes 125B and 215B routed from the pixel array portion 540 to the peripheral portion 540B. By providing the through-wiring 122E in the peripheral portion 540B in this way, the area of ​​the insulating region 213 for inserting the through-wiring 122E in the second substrate 200 can be reduced. Therefore, the area of ​​the semiconductor layer 200S on which the pixel circuit 210 is formed can be increased, contributing to improved image quality through noise reduction and the like.

[0053] The transfer transistor TR may be composed of a planar transistor. In this case, for example, a transfer gate TG is provided on the surface of the semiconductor layer 100S. For example, the side surface of the transfer gate TG is covered by a sidewall SW. The sidewall SW contains, for example, silicon nitride (SiN). A gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG.

[0054] The semiconductor layer 100S is further provided with a pixel separation portion 117, a first pinning region 113, and a second pinning region 116.

[0055] The pixel separation section 117 separates adjacent pixels 541 from each other and is formed extending between the front surface 100S1 and the back surface 100S2 of the semiconductor layer 100S. The pixel separation section 117 is provided, for example, in a grid pattern to partition adjacent pixels 541 from each other, as shown in Figures 6A and 6B. The pixel separation section 117 electrically and optically separates pixels 541A to 541H from each other. The pixel separation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B. For example, tungsten (W) is used for the light-shielding film 117A. The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separation portion 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S.

[0056] The first pinning region 113 is provided near the back surface 100S2 of the semiconductor layer 100S and is located between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side surface of the pixel separation portion 117, specifically between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are composed of, for example, p-type semiconductor regions.

[0057] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. The electric field induced by the fixed charge film 112 forms a first pinning region 113 of the hole storage layer at the interface on the back surface 100S2 side of the semiconductor layer 100S, which is the light-receiving surface. This suppresses the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, by an insulating film having a negative fixed charge. As a material for this insulating film having a negative fixed charge, for example, hafnium oxide (HfO) ｘ), zirconium oxide (ZrO ｘ ), aluminum oxide (AlO ｘ ), titanium oxide (TiO ｘ ) or tantalum oxide (TaO ｘ ) are some examples.

[0058] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light-shielding film 117A may be provided continuously with the light-shielding film 117A that constitutes the pixel separation portion 117. This light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is formed of, for example, a single layer film made of one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or a laminated film made of two or more of these.

[0059] The light-receiving lens 401 faces the semiconductor layer 100S with, for example, a fixed charge film 112 and an insulating film 111 in between. The light-receiving lens 401 is provided, for example, for each pixel 541, at a position facing the photodiode PD.

[0060] The wiring layer 100T has, in this order from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120, 121, a passivation film 123, and an interlayer insulating film 124. Within the interlayer insulating film 124, for example, from the semiconductor layer 100S side, the wiring layer W11 and bonding electrodes 125 (, 125B), 126 are provided, and these are insulated from each other by the interlayer insulating film 124. The interlayer insulating film 124 forms a bonding surface 124S with the second substrate 200, and the bonding electrodes 125 (, 125B), 126 are exposed on the bonding surface 124S. Within the interlayer insulating film 124, vias V1 are further provided as connection parts that connect the wiring 120D, 121D and bonding electrodes 125 (, 125B), 126, which extend in the thickness direction (Z-axis direction) of the interlayer insulating film 124, to the wiring layer W11.

[0061] The interlayer insulating films 119, 124 and the passivation film 123 are formed from a single layer film made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a multilayer film made of two or more of these materials. The pad portions 120, 121 are formed from, for example, polysilicon (PolySi), more specifically, doped polysilicon with added impurities. It is preferable that the pad portions 120, 121 are formed from a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The pad portions 120, 121 may also be formed from metallic materials such as tantalum nitride (TaN), aluminum (Al), and copper (Cu). The wiring 120D, through-wiring 120E, wiring layer W11, and junction electrodes 125 (125B), 126 are formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc.

[0062] Figure 6A schematically shows an example of the planar configuration of pixels 541 on the first substrate 100. As described above, the first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact area 118, and a transfer transistor TR for each pixel 541. Figure 6A shows the planar configuration of the photodiode PD, floating diffusion FD, VSS contact area 118, and transfer transistor TR in a pixel sharing unit 539, which consists of eight pixels 541A to 541H arranged in 2 rows x 4 columns. Note that multiple pixel sharing units 539 that are repeatedly arranged in the pixel array section 540 have substantially the same configuration as each other.

[0063] The floating diffusion FD1 to FD8 provided for each of the pixels 541A to 541H are, for example, arranged in 2 rows x 2 columns for pixels 541A to 541D in the upper part of the pixel sharing unit 539, and for each of the pixels 541D to 541H in the lower part of the pixel sharing unit 539, and are located close to each other approximately in the center of each. The floating diffusion FD1 to FD4 and floating diffusion FD5 to FD8, which are located close to each other within the pixel sharing unit 539, are each electrically connected to each other via the pad portion 120.

[0064] The VSS contact areas 118 provided for each of the pixels 541A to 541H are each located diagonally with respect to the floating diffusion FD. In other words, the VSS contact areas 118 provided for each of the pixels 541A to 541H are located at the four corners of the outer periphery of each pixel 541A to 541D, which are arranged in a 2x2 grid on the upper side of the pixel sharing unit 539, and for each of the pixels 541D to 541H on the lower side of the pixel sharing unit 539. As a result, the VSS contact areas 118 provided for pixels 541D and 541E, and pixels 541C and 541F, which are adjacent in the X-axis direction within the pixel sharing unit 539, are in close proximity to each other. Furthermore, the VSS contact areas 118 of pixels 541D and 541E, and pixels 541C and 541F, which are adjacent to each other, are in close proximity to the VSS contact areas 118 provided on each pixel 541 of other adjacent pixel sharing units 539 in the Y-axis direction. On the other hand, the VSS contact areas 118 provided on pixels 541A and 541B in the upper part of the pixel sharing unit 539, and the VSS contact areas 118 provided on pixels 541G and 541H in the lower part of the pixel sharing unit 539, are in close proximity to the VSS contact areas 118 provided on each pixel 541 of other adjacent pixel sharing units 539 in the X-axis direction, Y-axis direction, and diagonal direction, respectively. These VSS contact areas 118, which are provided in close proximity to each other, are electrically connected to each other via pad portions 121.

[0065] The transfer gates TGTG1 to TG8 provided for each of the pixels 541A to 541H are, for example, provided to surround floating diffusion gates FD1 to FD4 and floating diffusion gates FD5 to FD8, which are located close to each other in the approximate center of pixels 541A to 541D and pixels 541D to 541H, which are arranged in a 2x2 configuration in the upper and lower parts of the pixel sharing unit 539.

[0066] Figure 6B schematically shows an example of the planar configuration of the pad portions 120 and 121, along with the planar configuration of the pixel 541 on the first substrate 100 shown in Figure 6A. The pad portions 120 and 121 are each provided in a selective region on the interlayer insulating film 119.

[0067] The pad portion 120 is for connecting floating diffusions FD1 to FD4 and floating diffusions FD5 to FD8, which are located close to each other in the approximate center of pixels 541A to 541D and pixels 541D to 541H, which are arranged in a 2x2 configuration on the upper and lower sides of the pixel sharing unit 539. One pad portion 120 is located on the upper and lower sides of the pixel sharing unit 539, straddling the pixel separation portion 117, and is positioned to overlap at least a portion of each of the floating diffusions FD1 to FD4 and floating diffusions FD5 to FD8. These two pad portions 120 and the floating diffusions FD1 to FD4 and floating diffusions FD5 to FD8 located below them are electrically connected by connection vias 120C provided in the interlayer insulating film 119. A connection via 120C is provided for each of the pixels 541A to 541H. For example, by embedding a portion of the pad portion 120 in the connection via 120C, the two pad portions 120 are electrically connected to the floating diffusions FD1 to FD4 and the floating diffusions FD5 to FD8, respectively.

[0068] Furthermore, as shown in Figure 6B, the two pad portions 120 located within the pixel sharing unit 539 are electrically connected to each other via a wiring layer W11 extending in the X-axis direction and through-wirings 120E connected to each of them. This wiring layer W11 extending in the X-axis direction is connected to a bonding electrode 125 via a via V1, and is further electrically connected to a pixel circuit 210 provided for each pixel sharing unit 539 via a bonding electrode 215, through-wirings 120E, a first wiring layer W21, and via V2, which will be described later.

[0069] The pad portion 121 is for connecting multiple VSS contact regions 118 that are located close to each other. The pad portion 121 spans the pixel separation portion 117 and is arranged to overlap at least a portion of each of the four adjacent VSS contact regions 118. As an example, as described above, it is arranged to overlap at least a portion of each of the four adjacent VSS contact regions 118 provided on pixels 541D and 541E adjacent in the X-axis direction within the pixel sharing unit 539, and on each of the pixels 541 of another pixel sharing unit 539 adjacent in the Y-axis direction. In this way, six pad portions 121 are provided for one pixel sharing unit 539. These six pad portions 121 and the four VSS contact regions 118 located below them are electrically connected by connecting vias 121C provided in the interlayer insulating film 119. Connecting vias 121C are provided for each of the pixels 541A to 541H. For example, by embedding a portion of the pad portion 121 in the connecting via 121C, the six pad portions 120 and the four VSS contact regions 118 located below each of them are electrically connected.

[0070] Furthermore, the multiple pad portions 121 arranged in the pixel array portion 540 as described above are electrically connected to each other, for example, via a wiring layer W12. The wiring layer W12 is provided, for example, in a grid pattern to connect the multiple pad portions 121 arranged in the pixel array portion 540 as described above. The grid-like wiring layer W12 is connected to the bonding electrode 126 via vias V1. The bonding electrode 126 is bonded to a bonding electrode 216 exposed on the bonding surface 221S of the second substrate 200 with the first substrate 100.

[0071] In this way, by providing the pad portion 120, the amount of wiring connecting each floating diffusion FD to the pixel circuit 210 can be reduced throughout the entire chip. Similarly, by providing the pad portion 121, the amount of wiring supplying potential to each VSS contact area 118 can be reduced throughout the entire chip. This makes it possible to reduce the overall chip area, suppress electrical interference between wirings in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0072] The pad portions 120 and 121 may, for example, be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be configured to be directly connected to at least a portion of each of the floating diffusion FD and / or VSS contact regions 118.

[0073] Furthermore, when viewed as a whole, the multiple pad portions 120 and 121 are arranged alternately in the Y-axis direction, as shown in Figure 6, for example. Specifically, the multiple pad portions 120 are each positioned between adjacent pixels 541 in the Y-axis direction within the pixel sharing unit 539. The multiple pad portions 121 are each positioned between other adjacent pixel sharing units 539 in the Y-axis direction. Moreover, as described above, one of the multiple pad portions 120 is positioned approximately in the center of each of the pixels 541A to 541D and pixels 541D to 541H, which are arranged in a 2x2 grid, in the upper and lower parts of the pixel sharing unit 539. In other words, in a pixel array section 540 where multiple pixels 541 are arranged in an array, if we consider that four pixels 541 arranged in a 2x2 configuration are used as repeating units, and these four pixels 541 arranged in a 2x2 configuration are repeatedly arranged in an array in the row direction and column direction, then the multiple pad sections 120 are arranged alternately across adjacent two rows and adjacent two columns. On the other hand, as described above, the multiple pad sections 121 are arranged in a 1x2 configuration, shifted upward or downward by one pixel relative to the multiple pad sections 120, for example, across other adjacent pixel sharing units 539 in the X-axis direction, Y-axis direction and diagonally relative to one pixel sharing unit 539. In other words, in a pixel array section 540 in which multiple pixels 541 are arranged in an array, if we consider that four pixels arranged in a 2x2 grid are used as a repeating unit, and these four pixels arranged in a 2x2 grid are repeatedly arranged in an array in the row direction and the column direction, then the multiple pad sections 121 are arranged in a matrix such that one pad section 121 is placed between each of the multiple pad sections 120 that are alternately arranged across two adjacent rows and two adjacent columns.

[0074] The second substrate 200 has a semiconductor layer 200S and wiring layers 200T-1 and 200T-2. The semiconductor layer 200S has a pair of opposing surfaces (front surface 200S1 and back surface 200S2), with wiring layer 200T-1 on the back surface 200S2 side and wiring layer 200T-2 on the front surface 200S1 side. The front surface 200S1 of the semiconductor layer 100S is the element formation surface. In the photodetector 1, the first substrate 100 and the second substrate 200 are stacked by bonding between electrodes such that the front surface 100S1 of the semiconductor layer 100S and the back surface 200S2 of the semiconductor layer 200S face each other. In other words, the first substrate 100 and the second substrate 200 are bonded so that the front surface of the first substrate 100 and the back surface of the second substrate 200 face each other. This bonding method is called face-to-back bonding. The first substrate 100 and the second substrate 200 may be joined to each other by a so-called hybrid bond. That is, electrodes exposed on the bonding surface 124S of the first substrate 100 (bonding electrodes 125 (, 125B), 126) and electrodes exposed on the bonding surface (bonding surface 221S) of the second substrate 200 (bonding electrodes 215 (, 215B), 216) are joined, and the interlayer insulating film 124 forming the bonding surface 124S and the interlayer insulating film 221 forming the bonding surface 221S are joined. When the bonding electrodes 125 (, 125B), 126 and the bonding electrodes 215 (, 215B), 216 are all made of copper (Cu), the joining of bonding electrodes 125 (, 125B), 126 and bonding electrodes 215 (, 215B), 216 is sometimes called a Cu-Cu bond. The second substrate 200 is provided with a pixel circuit 210 and through-wirings 120E and 122E. The through-wirings 120E and 122E each penetrate the semiconductor layer 200S.

[0075] The semiconductor layer 200S is made of, for example, a silicon substrate. The semiconductor layer 200S has well regions 211 in the thickness direction. The well regions 211 are, for example, p-type semiconductor regions. The semiconductor layer 200S further has well regions 212 around through-wiring 120E that penetrates the semiconductor layer 200S. The well regions 212 are, for example, n-type semiconductor regions.

[0076] The semiconductor layer 200S is further provided with an insulating region 213 and an element isolation region 214.

[0077] The insulating region 213 is a region for providing multiple through-wirings 120E, 122E for electrically connecting the first substrate 100 and the second substrate 200, insulated from the semiconductor layer 200S. The insulating region 213 has approximately the same thickness as the semiconductor layer 200S and divides the semiconductor layer 200S into multiple sections. The through-wirings 120E, 122E are arranged in this insulating region 213. The insulating region 213 is formed of, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0078] The element isolation region 214 isolates the multiple transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The element isolation region 214 is provided on the surface 200S1 side of the semiconductor layer 200S. The element isolation region 214 has an STI (Shallow Trench Isolation) structure. A well region 211 extends below the element isolation region 214 (deep within the semiconductor layer 200S). In the element isolation region 214, the semiconductor layer 200S is recessed in the thickness direction, and an insulating film is embedded in this recess. This insulating film is formed from, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0079] As described above, the through-wirings 120E and 122E are arranged in the insulating region 213 and penetrate the insulating region 213 in the thickness direction. The upper ends of the through-wirings 120E and 122E are connected to the wiring of the wiring layer 200T-2 (first wiring layer W1, second wiring layer W2, third wiring layer W3, fourth wiring layer W4). The through-wirings 120E and 122E are provided penetrating the insulating region 213 and the interlayer insulating film 221, and their lower ends are connected to bonding electrodes 215 (, 215B) and 216 provided on the bonding surface 221S of the wiring layer 200T-1 which is bonded to the first substrate 100.

[0080] The through-wiring 120E is for electrically connecting the floating diffusion FD provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200. More specifically, the through-wiring 120E is one of the connection means for electrically connecting the floating diffusion FD1 to FD8 provided on the pixel sharing unit 539 on the first substrate 100 and the pixel circuit 210, one of which is provided for each pixel sharing unit 539 on the second substrate 200. The floating diffusion FD1 to FD8 and the pixel circuit 210 are connected in order from the first substrate 100 side via connection via 120C, pad portion 120, wiring 120D, wiring layer W11, via V1, bonding electrodes 125, 215, through-wiring 120E, first wiring layer W21, and via V2. As a result, the pixel signals of each of the pixels 541A to 541H constituting the pixel sharing unit 539 are read out.

[0081] Figure 7 shows a schematic, enlarged view of the cross-sectional configuration of a through-wiring 120E penetrating the semiconductor layer 200S and its surrounding area. As shown in Figure 7, the semiconductor layer 200S is provided with an opening H that penetrates between the surface 200S1 and the back surface 200S2 of the semiconductor layer 200S. The through-wiring 120E is inserted through the opening H. The side surface of the through-wiring 120E is covered with an insulating film, which constitutes part of the insulating region 213. The upper end of the through-wiring 120E is connected to, for example, a first wiring layer W21, and is electrically connected to the gate 224G of the amplification transistor AMP via this connected first wiring layer W21. The lower end of the through-wiring 120E is connected to a junction electrode 215 exposed on the junction surface 221S with the first substrate 100. As described above, the semiconductor layer 200S surrounding the through-wiring 120E is provided with a well region 212 consisting of an n-type semiconductor region. The well region 212 contains a contact region 217 in which the n-type impurity concentration is higher than that of the surrounding area. The contact region 217 is provided on the surface 200S1 of the semiconductor layer 200S and is electrically connected to the source 224S of the amplification transistor AMP provided on the surface 200S1 of the semiconductor layer 200S via via V2 and the first wiring layer W21. As a result, the parasitic capacitance between the through-wiring 120E and the surrounding well region 212 is reduced due to the Miller effect.

[0082] The through-hole wiring 122E is for electrically connecting the gate (transfer gate TG) of the transfer transistor TR provided on the first substrate 100 to the drive signal line provided on the second substrate 200. The through-hole wiring 122E is located in the peripheral portion 540B. The transfer gate TG and the drive signal line are connected in order from the first substrate 100 side via wiring 122D, wiring layer W11, via V1, junction electrodes 124B, 215B and first wiring layer W21, etc. This ensures that a drive signal is sent to each of the transfer transistors TR provided for each pixel 541.

[0083] When viewed as a whole, the multiple through-wirings 120E are located in an insulating region 213 that overlaps with multiple pad portions 120 that are alternately arranged across two adjacent rows and two adjacent columns, assuming that four pixels 541 arranged in a 2x2 grid are used as repeating units, and these four pixels 541 arranged in a 2x2 grid are repeatedly arranged in an array consisting of rows and columns. The multiple through-wirings 121E are located in an insulating region 213 that overlaps with multiple pad portions 121 that are arranged in a matrix such that one pad portion 121 is placed between each of the multiple pad portions 120 that are alternately arranged across two adjacent rows and two adjacent columns, assuming that four pixels arranged in a 2x2 grid are used as repeating units, and these four pixels arranged in a 2x2 grid are repeatedly arranged in an array consisting of rows and columns. Multiple through-wirings 122E are arranged in an insulating region 213 provided in the peripheral area 540B.

[0084] The wiring layer 200T-1 has an interlayer insulating film 221 and bonding electrodes 215 (, 215B) and 216. The interlayer insulating film 221 forms a bonding surface 221S with the first substrate 100, and the bonding electrodes 215 (, 215B) and 216 are exposed on the bonding surface 221S.

[0085] The wiring layer 200T-2 has a passivation film 222 and an interlayer insulating film 223 from the semiconductor layer 200S side. The passivation film 222 is in contact with, for example, the surface 200S1 of the semiconductor layer 200S and covers the entire surface 200S1 of the semiconductor layer 200S. The passivation film 222 covers the gates of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG. Multiple wiring layers are provided within the interlayer insulating film 223. For example, within the interlayer insulating film 223, a first wiring layer W21, a second wiring layer W22, a third wiring layer W23, and a fourth wiring layer W24 are provided from the semiconductor layer 200S side, and these are insulated from each other by the interlayer insulating film 223. The interlayer insulating film 223 forms a bonding surface with the third substrate 300, and 201 and 202 are exposed at the bonding surface. The contact portions 201 and 202 are provided, for example, in the peripheral portion 540B. The contact portions 201 and 202 may be provided in a position that overlaps the pixel array portion 540 in a plan view. Multiple connection portions are provided within the interlayer insulating film 223 to connect the first wiring layer W21, the second wiring layer W22, the third wiring layer W23, or the fourth wiring layer W24 with the layers below them. Within the interlayer insulating film 223, for example, via V2 is provided as a connection portion to connect the first wiring layer W21 to the transistor gate or source / drain.

[0086] The interlayer insulating films 221, 223 and the passivation film 222 are formed from a single layer made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a multilayer film made of two or more of these materials. The gates of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, the first wiring layer W21, the second wiring layer W22, the third wiring layer W23, the fourth wiring layer W24, the junction electrodes 215 (, 215B), 216, and the contact portions 201, 202 are formed using materials such as aluminum (Al), copper (Cu), tungsten (W), and polysilicon (Poly-Si).

[0087] The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. The semiconductor layer 300S has a pair of opposing surfaces, and the wiring layer 300T is provided on one of these surfaces (front surfaces). In the photodetector 1, the second substrate 200 and the third substrate 300 are laminated together by bonding between electrodes, such that the surface 200S1 of the semiconductor layer 200S and the surface of the semiconductor layer 300S face each other. In other words, the second substrate 200 and the third substrate 300 are bonded together such that the surface of the second substrate 200 and the surface of the third substrate 300 face each other. This bonding method is called face-to-face bonding. The second substrate 200 and the third substrate 300 may also be bonded together by a so-called hybrid bonding. Specifically, electrodes (contact portions 201, 202) exposed on the bonding surface of the second substrate 200 and electrodes (contact portions 301, 302) exposed on the bonding surface of the third substrate 300 are bonded together, and the interlayer insulating film 223 forming the bonding surface of the second substrate 200 and the interlayer insulating film 311 forming the bonding surface of the third substrate 300 are bonded together. When both contact portions 201, 202 and contact portions 301, 302 are made of copper (Cu), the bonding between contact portions 201, 202 and contact portions 301, 302 is sometimes called a Cu-Cu bond.

[0088] The semiconductor layer 300S is made of, for example, a silicon substrate. Circuits are provided on the surface side of the semiconductor layer 300S. Specifically, at least a portion of the following are provided on the surface side of the semiconductor layer 300S: the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B.

[0089] The wiring layer 300T has, for example, an interlayer insulating film 311. Within the interlayer insulating film 311 are multiple wiring layers and contact portions 301 and 302. The interlayer insulating film 311 forms a bonding surface with the second substrate 200, and the contact portions 301 and 302 are exposed on this bonding surface. The contact portions 301 and 302 are electrically connected to at least one of the following, for example, an input portion 510A, a row drive portion 520, a timing control portion 530, a column signal processing portion 550, an image signal processing portion 560, and an output portion 510B formed on the semiconductor layer 300S.

[0090] The interlayer insulating film 311 is formed from a single layer made of one of the following materials: silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or from a laminated layer made of two or more of these materials. The wiring layer and contact portions 301 and 302 provided within the interlayer insulating film 311 are formed from materials such as aluminum (Al), copper (Cu), tungsten (W), and polysilicon (Poly-Si).

[0091] In the light detection device 1, for example, the external terminal TA is connected to the input unit 510A via the connection hole H1, and the external terminal TB is connected to the output unit 510B via the connection hole H2.

[0092] Figure 5 shows an example in which peripheral circuits are provided on the peripheral portion 540B of the second substrate 200. These peripheral circuits may include a part of the row drive unit 520 or a part of the column signal processing unit 550, etc. Alternatively, as shown in Figure 3, peripheral circuits may not be placed on the peripheral portion 540B of the second substrate 200, and connection holes H1 and H2 may be placed near the pixel array unit 540.

[0093] [Operation of the Photodetector] Next, the operation of the photodetector 1 will be explained using Figures 8 and 9. Figures 8 and 9 are the same as Figure 3 with arrows added to represent the paths of each signal. Figure 8 shows the paths of the input signal input to the photodetector 1 from the outside, and the power supply potential and reference potential, represented by arrows. Figure 9 shows the signal path of the pixel signal output from the photodetector 1 to the outside, represented by arrows. For example, the input signal (for example, the pixel clock and synchronization signal) input to the photodetector 1 via the input unit 510A is transmitted to the row drive unit 520 of the third substrate 300, where the row drive unit 520 generates a row drive signal. This row drive signal is sent to the second substrate 200 via the contact units 301 and 201. Furthermore, this row drive signal reaches each of the pixel sharing units 539 of the pixel array unit 540 via the row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing unit 539 on the second substrate 200, drive signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The drive signal for the transfer gate TG is input to the transfer gates TG1 to TG8 on the first substrate 100 via the through wiring 122E, and pixels 541A to 541H are driven. In addition, the power supply potential and reference potential supplied from outside the photodetector 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and supplied to each pixel circuit 210 of the pixel sharing unit 539 via the wiring in the wiring layer 200T. Meanwhile, the pixel signals photoelectrically converted by pixels 541A to 541H on the first substrate 100 are sent to the pixel circuit 210 on the second substrate 200 for each pixel sharing unit 539 via wiring 120D, bonding electrodes 125, 215, and through wiring 120E. The pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via vertical signal lines 543 and contact parts 202, 302. These pixel signals are processed by the column signal processing unit 550 and the image signal processing unit 560 on the third substrate 300, and then output to the outside via the output unit 510B.

[0094] [Configuration of the bonding surface between the first substrate and the second substrate] Figure 10A schematically shows an example of the layout of multiple bonding electrodes 125, 215 and multiple bonding electrodes 126, 216 that are bonded to each other at the bonding surface between the first substrate 100 and the second substrate 200. Figure 10B schematically shows an example of misalignment of the multiple bonding electrodes 125, 215 and multiple bonding electrodes 126, 216 shown in Figure 10A. Figure 11A schematically shows another example of the layout of multiple bonding electrodes 125, 215 and multiple bonding electrodes 126, 216 that are bonded to each other at the bonding surface between the first substrate 100 and the second substrate 200. Figure 11B schematically shows an example of misalignment of the multiple bonding electrodes 125, 215 and multiple bonding electrodes 126, 216 shown in Figure 11A.

[0095] The multiple bonding electrodes 125, 215 are one of the connection means that electrically connect the floating diffusion FD1 to FD8 provided on the pixel sharing unit 539 on the first substrate 100 and the pixel circuit 210 provided one per pixel sharing unit 539 on the second substrate 200, and are connected to the through wiring 120E described above. The multiple bonding electrodes 126, 216 are shield electrodes between bonding electrodes 125, 215 that are in close proximity in the in-plane direction of the bonding surface between the first substrate 100 and the second substrate 200, in order to reduce signal interference (crosstalk) due to FD-FD coupling.

[0096] The multiple bonding electrodes 125, 215 are arranged alternately across two adjacent rows and two adjacent columns in a pixel array section 540 where multiple pixels 541 are arranged in an array, with four pixels 541 arranged in a 2x2 grid as the repeating unit, and these four pixels 541 arranged in a 2x2 grid are repeatedly arranged in an array consisting of rows and columns, similar to the multiple pad sections 120 and multiple through-wirings 121E described above. On the other hand, the multiple bonding electrodes 126, 216 are arranged in a matrix in a pixel array section 540 where multiple pixels 541 are arranged in an array, with four pixels 541 arranged in a 2x2 grid as the repeating unit, and these four pixels 541 arranged in a 2x2 grid are repeatedly arranged in an array consisting of rows and columns, similar to the multiple pad sections 121 and multiple through-wirings 121E described above, with one pad section 121 placed between each of the multiple bonding electrodes 125, 215 that are alternately arranged across two adjacent rows and two adjacent columns. In other words, the multiple junction electrodes 126, 216 are selectively positioned between the closest junction electrodes 125, 215, which are arranged alternately across two adjacent rows and two adjacent columns. More specifically, the multiple junction electrodes 126, 216 are selectively positioned between junction electrodes A2, A3, which are positioned diagonally to and in close proximity to junction electrode A1, which is arranged within the pixel sharing unit 539 shown in Figure 10A, and are not positioned between junction electrodes B1, B2, which are positioned in the X-axis and Y-axis directions and are further away than junction electrodes A2, A3.

[0097] The bonding electrodes 126 and 216 have an anisotropic planar shape. Specifically, the bonding electrodes 126 and 216 have a cross-shaped planar shape in which the lengths of the straight portions extending in the X-axis and Y-axis directions are different, as shown in Figure 10A, for example. The bonding electrodes 126 and 216 have a rectangular planar shape in which the longer side is perpendicular to the direction of the nearest bonding electrodes 125 and 215, as shown in Figure 11A, for example. In addition, the bonding electrodes 126 and 216 may have a roughly rhombic shape as shown in Figure 12, or an elliptical planar shape as shown in Figure 13. The bonding electrodes 126 and 216 may have a planar shape in which each side of a rhombus is recessed inward, as shown in Figure 14, or a planar shape that combines a circle and a straight line, as shown in Figure 15. Note that the bonding electrodes 126 and 216 shown in Figures 12 to 15 are examples where the longitudinal direction (or long side direction, or long axis direction) of each shape extends in the X-axis direction, similar to Figure 10A, but the design is not limited to this. The extension direction of the longitudinal direction (or long side direction, or long axis direction) of each shape may be the Y-axis direction. Alternatively, the extension direction of the longitudinal direction (or long side direction, or long axis direction) of each shape may be perpendicular to the direction of the nearest bonding electrodes 125 and 215, similar to Figure 11A.

[0098] Furthermore, the bonding electrodes 126 and 216 may have different shapes from each other. For example, as shown in Figure 16, one of the bonding electrodes 126 and 216 (for example, bonding electrode 126) may have a rectangular shape extending in the X-axis direction, while the other (for example, bonding electrode 216) may have a shorter rectangular shape extending in the Y-axis direction. By bonding these together, the bonding electrodes 126 and 216 at the bonding surface between the first substrate 100 and the second substrate 200 will have a cross shape as shown in Figure 10A.

[0099] Furthermore, the bonding electrodes 126 and 216 only need to be spaced apart from each other between bonding electrodes 125 and 215, at least one of which is in nearest contact with the other. In other words, although not shown, the other bonding electrode 126 and 216 may be provided, for example, in a grid pattern to connect the bonding electrodes 126 and 216 that are spaced apart from each other. For example, if the bonding electrode 126 is connected to ground GND, the bonding electrode 216 does not need to be connected to ground GND. This makes it possible to reduce the number of through-wirings in the entire chip, which in turn makes it possible to reduce the overall chip area, suppress electrical interference between wirings in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0100] Furthermore, as shown in Figure 11A, when the bonding electrodes 126 and 216 have a rectangular planar shape with their longer sides in the same direction, unlike the case where the bonding electrodes 126 and 216 have a cross shape as shown in Figure 10B, for example, there is a possibility that they will not contact each other due to misalignment, as shown in Figure 11B. For this reason, it is preferable that the bonding electrode 126 on the second substrate 200 side is electrically connected to a reference potential line (for example, ground GND) provided on the second substrate 200.

[0101] Figures 17 to 20 illustrate an example of a readout method for a photodetector 1 having the layout of multiple junction electrodes 125, 215 and multiple junction electrodes 126, 216 shown in Figure 10A.

[0102] In the photodetector 1, in the pixel sharing unit 539 consisting of eight pixels 541A to 541H arranged in a 2x4 grid, the multiple junction electrodes 125, 215, each connected to the floating diffusion FD1 to FD8 provided for each of the pixels 541A to 541H, are arranged alternately across two adjacent rows and two adjacent columns, as described above. In such a photodetector 1, a red filter 402R, a green filter 402G, and a blue filter 402B are arranged in a Bayer configuration for each of the four pixels 541 arranged in a 4x4 grid. For example, when reading out each of the four columns (region 531) where each color filter 402R, 402G, and 402B is arranged, the pixel signal is read out, for example, every single pixel, every 2x2 pixels, or every 4x4 pixels. When reading out pixel signals one pixel at a time or 2x2 pixels at a time, as shown in Figure 17, there is a risk of crosstalk occurring between the nearest contact junction electrodes 125 and 215 within the same-colored color filters 402R, 402G, and 402B that are read out simultaneously, and between the different-colored color filters 402R, 402G, and 402B. When reading out pixel signals 4x4 pixels at a time, as shown in Figure 18, there is a risk of crosstalk occurring between the nearest contact A1 junction electrodes 125 and 215 between the different-colored color filters 402R, 402G, and 402B that are read out simultaneously.

[0103] Furthermore, if the 4x4 pixel area where pixel signals are read out simultaneously is zigzag-shaped (for example, when reading out the signals of green pixels simultaneously), as shown in Figure 19, when reading out the pixel signals of pixels 541A to 541H in the pixel sharing unit 539 in 4x4 pixel increments, there is a risk of crosstalk occurring between the nearest junction electrodes 125 and 215 indicated by the solid lines. When reading out the pixel signals one pixel at a time or 2x2 pixel increments, there is a risk of crosstalk occurring between the nearest junction electrodes 125 and 215 indicated by the solid lines, as well as between the nearest junction electrodes 125 and 215 indicated by the dotted lines.

[0104] In a photodetector 1 where a red filter 402R, a green filter 402G, and a blue filter 402B are arranged in a Bayer configuration for each of the 2x2 pixels 541, for example, when reading out every two columns (region 531) where each color filter 402R, 402G, and 402B is arranged, crosstalk may occur between the nearest contact junction electrodes 125 and 215, as shown in Figure 20, when reading out the pixel signal for each of the four pixels 541 where each color filter 402R, 402G, and 402B is arranged, when reading out the pixel signal for every 2x2 pixels, or when reading out the pixel signals for diagonally adjacent 2x2 pixel regions where the green filter 402G is arranged in a zigzag pattern.

[0105] In contrast, in the photodetector 1 of this embodiment, as described above, a plurality of junction electrodes 126, 216 that also serve as shield electrodes are selectively arranged between the nearest junction electrodes 125, 215, so that any of the above-mentioned crosstalk can be suppressed.

[0106] [Function and Effects] In the photodetector 1 of this embodiment, a plurality of photodiodes PD and a plurality of floating diffusion FDs are joined to a first substrate 100 having a semiconductor layer 100S provided for each pixel 541, and a second substrate 200 having a semiconductor layer 200S provided for a plurality of pixel circuits 210 that output pixel signals based on the charge output from each pixel 541, via a plurality of junction electrodes 125, 215. The plurality of junction electrodes 125 provided on the first substrate 100 side are each connected to the plurality of floating diffusion FDs provided for each pixel 541, and the plurality of junction electrodes 215 provided on the second substrate 200 side are each connected to the pixel circuits 210 provided for each of the plurality of pixels 541. At the joining surface between the first substrate 100 and the second substrate 200, a plurality of junction electrodes 126, 216 that also serve as shield electrodes are selectively arranged spaced apart from each other between the nearest junction electrodes 125, 215. This will be explained below.

[0107] In a three-dimensional imaging device, for example, one of two stacked semiconductor substrates (a first substrate and a second substrate) (for example, the first substrate) is provided with photodiodes or floating diffusions for each pixel arranged in a two-dimensional array, while the other substrate (for example, the second substrate) is provided with a readout circuit for reading the voltage signal of the floating diffusion for each of one or more pixels. The first substrate and the second substrate are electrically connected by joining metal electrodes provided on their respective bonding surfaces. The voltage signal of the floating diffusion is transmitted from the first substrate to the second substrate by connecting a signal terminal (for example, a floating diffusion) formed on the first substrate side to a connection terminal on the second semiconductor substrate side.

[0108] In imaging devices with a three-dimensional structure as described above, a shielding electrode is placed between the metal electrodes used to join the first and second substrates, where signal interference is likely to occur, in order to prevent signal interference between the signal terminals of adjacent pixels. In typical three-dimensional imaging devices, the shielding electrode is arranged in a grid pattern surrounding the metal electrode.

[0109] In recent years, there has been a demand for further miniaturization of imaging devices and higher pixel density, leading to efforts to reduce pixel size. In imaging devices with a reduced pixel size and a three-dimensional structure, it is difficult to reduce the pitch of metal electrodes due to misalignment during bonding between the first and second substrates. As a result, it is becoming increasingly difficult to place shield electrodes. Furthermore, placing shield electrodes between adjacent metal electrodes increases the floppy disk capacitance, leading to a decrease in conversion efficiency and an increase in dark noise.

[0110] In contrast, in this embodiment, as described above, at the bonding surface between the first substrate 100 and the second substrate 200, where multiple bonding electrodes 125 connected to multiple floating diffusion FDs provided for each pixel 541 on the first substrate 100 and multiple bonding electrodes 215 connected to multiple pixel circuits 210 provided for each pixel 541 on the second substrate 200 are bonded together, multiple bonding electrodes 126, 216 that also serve as shield electrodes are selectively arranged spaced apart between the nearest bonding electrodes 125, 215. This reduces the area of ​​the shield electrodes (bonding electrodes 126, 216) at the bonding surface between the first substrate 100 and the second substrate 200, while also reducing the capacitance between the bonding electrodes 125, 215 and the shield electrodes (bonding electrodes 126, 216).

[0111] As described above, the light detection device 1 of this embodiment makes it possible to achieve pixel miniaturization.

[0112] The following describes a second embodiment and modifications 1 to 3 of this disclosure, as well as application examples and application examples. In the following modifications, components common to the first embodiment are denoted by the same reference numerals.

[0113] <2. Modification 1> Figure 21 schematically shows an example of the layout of multiple bonding electrodes 125, 215 and multiple shielding electrodes (multiple bonding electrodes 126, 216) on the bonding surfaces of the first substrate 100 and the second substrate 200 of the photodetector 2 according to Modification 1 of the present disclosure. Figures 22 to 25 illustrate other examples of the readout mode of the photodetector 2 according to Modification 1 of the present disclosure.

[0114] In the first embodiment described above, a pixel sharing unit 539 consisting of eight pixels 541 arranged in a 2x4 grid in the pixel array section 540 is shown as a repeating unit, and this is repeatedly arranged in an array consisting of rows and columns, with a pixel circuit 210 provided for each of these pixel sharing units 539. However, the embodiment is not limited to this. In this modified example, the photodetector 2 consists of a pixel sharing unit 539A consisting of four pixels 541 arranged in a 2x2 grid as a repeating unit, and this is repeatedly arranged in an array consisting of rows and columns, with a pixel circuit 210 provided for each of these pixel sharing units 539A. In such a photodetector 2, as shown in Figure 21, the multiple junction electrodes 125, 215 are arranged in a matrix across two adjacent rows and two adjacent columns. The multiple junction electrodes 126, 216, which also serve as shield electrodes, are arranged spaced apart from each other in a matrix across two adjacent rows and two adjacent columns between diagonally adjacent junction electrodes 125, 215. Except for this point, the photodetector 2 has substantially the same configuration as the photodetector 1 of the first embodiment described above.

[0115] In the photodetector 2, as described above, in the pixel sharing unit 539A consisting of four pixels 541 arranged in a 2x2 grid, the multiple junction electrodes 125, 215 connected to the floating diffusion FD provided on each of the four pixels 541 are arranged in a matrix across two adjacent rows and two adjacent columns. In such a photodetector 2, a red filter 402R, a green filter 402G, and a blue filter 402B are arranged in a Bayer configuration for each of the four pixels 541 arranged in a 4x4 grid. For example, when reading out every two columns (region 531), the pixel signal is read out every pixel, every 2x2 pixels, or every 4x4 pixels. When reading out pixel signals one pixel at a time or 2x2 pixels at a time, as shown in Figure 21, there is a risk of crosstalk occurring between the nearest junction electrodes 125 and 215 in the row direction (Y-axis direction) within the same-colored color filters 402R, 402G, and 402B that are read out simultaneously, and between the same-colored color filters 402R, 402G, and 402B that are read out simultaneously. When reading out pixel signals one pixel at a time or 2x4 pixels at a time, as shown in Figure 22, there is a risk of crosstalk occurring between the nearest junction electrodes 125 and 215 in the row direction (Y-axis direction) and column direction (X-axis direction) within the same-colored color filters 402R, 402G, and 402B that are read out simultaneously, and between the same-colored color filters 402R, 402G, and 402B that are read out simultaneously.

[0116] Furthermore, if the 4x4 pixel area where pixel signals are read out simultaneously is zigzag-shaped (for example, when reading out the signals of green pixels simultaneously), as shown in Figure 23, when reading out the pixel signals of the four pixels 541 in the pixel sharing unit 539A one pixel at a time, or 2x2 pixels at a time, or 4x4 pixels at a time where the green filter 402G is arranged, crosstalk may occur not only between the junction electrodes 125 and 215 that are closest to each other in the row direction (Y-axis direction), but also between the junction electrodes 125 and 215 that are closest to each other in the diagonal direction.

[0117] In a photodetector 2 where a red filter 402R, a green filter 402G, and a blue filter 402B are arranged in a Bayer configuration for each of the 2 rows x 2 columns of pixels 541, for example, when reading out every two columns (region 531) where each color filter 402R, 402G, and 402B is arranged, there is a risk of crosstalk occurring between the nearest junction electrodes 125 and 215 in the row direction (Y-axis direction), as shown in Figure 24, when reading out the pixel signal for each of the four pixels 541 where each color filter 402R, 402G, and 402B is arranged, or when reading out the pixel signal every 2 x 2 pixels.

[0118] Furthermore, if the 2x2 pixel region where pixel signals are read out simultaneously is zigzag-shaped (for example, when reading out the signals of green pixels simultaneously), when reading out the pixel signals of the four pixels 541 in the pixel sharing unit 539A one pixel at a time, or 2x2 pixels at a time, or 4x4 pixels at a time where the green filter 402G is located, crosstalk may occur between the nearest junction electrodes 125 and 215 that are in diagonal contact, as shown in Figure 25.

[0119] In contrast, in the photodetector 2 of this embodiment, multiple junction electrodes 126, 216 that selectively serve as shield electrodes are arranged between diagonally adjacent junction electrodes 125, 215 arranged in a matrix, thereby suppressing any of the aforementioned crosstalk.

[0120] As described above, the modified photodetector 2 can obtain the same effects as the photodetector 1 of the above embodiment.

[0121] In this modified photodetector 2, the planar shape of the junction electrodes 126 and 216 is not limited to, for example, the cross shape with the X-axis direction being the longitudinal direction as shown in Figure 21. The planar shape of the junction electrodes 126 and 216 may be a cross shape with the Y-axis direction being the longitudinal direction as shown in Figure 26, or an isotropic cross shape as shown in Figure 27. Furthermore, the planar shape of the junction electrodes 126 and 216 is not limited to a cross shape, and may be a roughly rhombic or elliptical shape as mentioned in the first embodiment above, or an isotropic square or circular shape.

[0122] <3. Second Embodiment> Figure 28 schematically shows an example of a specific cross-sectional configuration of the photodetector 3 according to the second embodiment of the present disclosure. Figure 29 schematically shows an example of a planar configuration of the pixel circuit 210 and bonding electrodes 215, 216 on the second substrate 200 of the photodetector 3.

[0123] The light detection device 3 is, for example, a back-illuminated light detection device. Similar to the light detection device 1 of the first embodiment described above, the light detection device 3 has three substrates, namely a first substrate 100, a second substrate 200, and a third substrate 300, stacked in this order from the light incident side. Furthermore, similar to the light detection device 1 of the first embodiment described above, the light detection device 3 has a light-receiving lens (not shown) on the light incident side of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. In the light detection device 3, a pixel sharing unit 539 consisting of eight pixels 541 arranged in a 2x4 grid is used as a repeating unit, and this is repeatedly arranged in an array in the row direction and column direction to constitute a pixel array section 540. A peripheral section 540B is provided around the pixel array section 540. The light-receiving lens 401 is provided, for example, for each of the multiple pixels 541.

[0124] [Specific Configuration of the Photodetector] The first substrate 100, second substrate 200, and third substrate 300 of the photodetector 2 each have the same configuration as the photodetector 1 of the first embodiment described above. For example, the first substrate 100 has a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 has a semiconductor layer 200S and wiring layers 200T-1 and 200T-2. The third substrate 300 has a semiconductor layer 300S and a wiring layer 300T. However, the photodetector 2 differs from the photodetector 1 of the first embodiment described above in the following respects.

[0125] In the photodetector 2, the well region 212, which consists of an n-type semiconductor region provided around the through-wiring 120E, and the source 224S of the amplification transistor AMP are electrically connected on the junction surface 221S side with the first substrate 100. Specifically, the well region 212 and the source 224S of the amplification transistor AMP are electrically connected via a junction electrode 216, which also serves as a shield electrode.

[0126] The semiconductor layer 200S is provided with an opening H that penetrates between the surface 200S1 and the back surface 200S2 of the semiconductor layer 200S. A through-wiring 120E is inserted through the opening H. This through-wiring 120E corresponds to a specific example of the "first through-wiring" as one embodiment of the present disclosure. The side surface of the through-wiring 120E is covered with an insulating film, which constitutes part of the insulating region 213. The upper end of the through-wiring 120E is connected to, for example, the first wiring layer W21. Multiple transistors constituting the pixel circuit 210 are provided on the surface 200S1 of the semiconductor layer 200S. The upper end of the through-wiring 120E is electrically connected to the gate 224G of the amplification transistor AMP, one of the multiple transistors, via the first wiring layer W21. The lower end of the through-wiring 120E is connected to a junction electrode 215 exposed on the junction surface 221S with the first substrate 100.

[0127] A well region 212 is provided in the semiconductor layer 200S surrounding the through-wiring 120E. The well region 212 includes a contact region 217 in which the n-type impurity concentration is higher than that of the surrounding area. The contact region 217 is provided on the back surface 200S2 of the semiconductor layer 200S and is connected via a via 218 to a junction electrode 216 exposed on the junction surface 221S with the first substrate 100. Near the surface 200S1 of the semiconductor layer 200S, the source 224S and drain 224D of an amplification transistor AMP are provided. The source 224S and drain 224D are, for example, n-type semiconductor regions. Furthermore, a contact portion 219 is embedded in the surface 200S1 of the semiconductor layer 200S, adjacent to the source 224S which is made up of this n-type semiconductor region. The second substrate 200 is provided with a through-wiring 220E extending from the back surface 200S2 side of the semiconductor layer 200S toward the surface 200S1. This through-wiring 220E corresponds to a specific example of the "second through-wiring" as one embodiment of the present disclosure. The side surface of the through-wiring 220E is covered with an insulating film. The upper end of the through-wiring 220E is connected to the contact portion 219. The lower end of the through-wiring 220E is connected to the junction electrode 216 exposed on the junction surface 221S with the first substrate 100. In other words, the well region 212 (specifically, the contact region 217) and the source 224S of the amplification transistor AMP are electrically connected via the via 218, the junction electrode 216, the through-wiring 220E, and the contact portion 219.

[0128] Figures 30 to 32 schematically show an example of the formation location of Miller capacitance at the junction surface between the first substrate 100 and the second substrate 200 of the photodetector 3. In the photodetector 3, the junction electrode 216 is part of the connection means that electrically connects the well region 212 (specifically, the contact region 217) and the source 224S of the amplification transistor AMP. Therefore, the capacitance between the junction electrodes 125, 215 and the junction electrodes 126, 216 is added to the capacitance between the floating diffusion FD and the source of the amplification transistor AMP. Thus, the parasitic capacitance between the through-wiring 120E due to the Miller effect and the surrounding well region 212 is further reduced. In this way, the junction electrodes 126, 216 with which Miller effect capacitance is formed may be one of the four junction electrodes 126, 216 around the junction electrodes 125, 215, for example, as shown in Figure 30, or two of them, for example, as shown in Figures 31 and 32.

[0129] Furthermore, junction electrodes 126 and 216, which form Miller effect capacitance with junction electrodes 125 and 215, are not connected to a reference potential line (e.g., ground GND). In other words, the through-wiring 121E connected to junction electrode 216 is omitted. Junction electrodes 126 and 216, which do not form Miller effect capacitance with junction electrodes 125 and 215, may be connected to a reference potential line (e.g., ground GND) via through-wiring 121E, similar to the first embodiment described above.

[0130] The vias 218 and through-wiring 220E are formed using, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), etc. The contact portion 219 is formed using, for example, polysilicon (Poly-Si), more specifically, doped polysilicon with added impurities.

[0131] [Manufacturing Method for Photodetector] Next, an example of a manufacturing method for the photodetector 3 will be described. Here, an example of a manufacturing method for the connection portion and its surrounding area between the well region 212 (specifically, the contact region 217) of the second substrate 200 and the source 224S of the amplification transistor AMP will be described with reference to Figures 33A to 33H.

[0132] First, as shown in Figure 33A, a laminated structure is prepared having a semiconductor layer 200S on which an amplifying transistor AMP or the like is provided on its surface 200S1, and a wiring layer 200R-2, and an interlayer insulating film 221 is formed on the surface 200S1 of the semiconductor layer 200S.

[0133] Next, as shown in Figure 33B, a photoresist pattern 501 is selectively formed on the interlayer insulating film 221. The photoresist pattern 501 has openings at locations where through-wirings 120E, 220E and vias 218 are formed.

[0134] Next, as shown in Figure 33C, the interlayer insulating film 221, the semiconductor layer 200S, and the interlayer insulating film 223 are selectively removed sequentially by an etching process (for example, reactive ion etching (RIE)) using the photoresist pattern 501 as a mask. This forms openings H3 that reach the first wiring layer W21, the contact region 217, and the contact portion 219, respectively.

[0135] Next, as shown in Figure 33D, after removing the photoresist pattern 501, an interlayer insulating film 221 is further deposited to form an insulating film along each wall surface of the opening H3. One example of a method for forming this interlayer insulating film 221 is atomic layer deposition (ALD). This is because even if the opening H3 has a shape with a high aspect ratio, an insulating film with high homogeneity in terms of film quality and thickness can be formed along each wall surface of the opening H3.

[0136] Next, as shown in Figure 33E, etching is performed to remove the insulating film deposited on each bottom surface of the opening H3. This exposes the first wiring layer W21, the contact region 217, and the contact portion 219 on each bottom surface of the opening H3.

[0137] Next, as shown in Figure 33F, an n-type impurity (for example, phosphorus (P)) is doped to form a well region 212 around the opening H3 that penetrates the semiconductor layer 200S.

[0138] Next, as shown in Figure 33G, conductive material is embedded in each of the openings H3 to form through-wiring 120E, via 218, and through-wiring 220E.

[0139] Subsequently, as shown in Figure 33H, a junction electrode 215 and via 218 connected to the through-wiring 120E and a junction electrode 216 connected to the through-wiring 220E are formed, respectively. Then, the interlayer insulating film 221 formed on the junction electrodes 215 and 216 is ground down by chemical mechanical polishing (CMP) to expose the junction electrodes 215 and 216.

[0140] Next, an example of a method for manufacturing the photodetector 3 will be described. Here, in particular, other examples of methods for manufacturing the connection portion and its surrounding area between the well region 212 (specifically, the contact region 217) on the second substrate 200 and the source 224S of the amplification transistor AMP will be described with reference to Figures 34A to 34F.

[0141] First, as shown in Figure 34A, through-wiring 120E, via 218, and through-wiring 220E are formed in the same manner as described above, and then TEOS film 221A is further formed.

[0142] Next, as shown in Figure 34B, the surface of the TEOS film 221A is planarized by CMP, and then a photoresist pattern 502 is selectively formed on the TEOS film 221A. The photoresist pattern 502 has openings in the locations where the junction electrodes 215 and 216 are formed.

[0143] Next, as shown in Figure 34C, the TEOS film 221A is selectively removed by an etching process (for example, reactive ion etching (RIE)) using the photoresist pattern 502 as a mask. This forms an opening H4 facing the junction electrodes 215 and 216.

[0144] Next, as shown in Figure 34D, after removing the photoresist pattern 501, a photoresist pattern 503 is selectively formed on the TEOS film 221A. The photoresist pattern 503 has openings in locations corresponding to the first wiring layer W21, the contact region 217, and the contact portion 219.

[0145] Next, as shown in Figure 34E, the TEOS film 221A is selectively removed by an etching process (for example, reactive ion etching (RIE)) using the photoresist pattern 503 as a mask. This forms openings H5 that reach the first wiring layer W21, the contact region 217, and the contact portion 219, respectively.

[0146] Next, as shown in Figure 34F, after removing the photoresist pattern 503, copper (Cu) films are embedded in the openings H4 and H5 to form through-wirings 120E, vias 218, and junction electrodes 216 connected to through-wirings 220E, respectively. Subsequently, the Cu film embedded on the TEOS film 211A is removed by CMP, and the surface is planarized.

[0147] In the photodetector 3 of this embodiment, the well region 212, which consists of an n-type semiconductor region provided around the through-wiring 120E, and the source 224S of the amplification transistor AMP are electrically connected on the junction surface 221S side with the first substrate 100. Specifically, the well region 212 and the source 224S of the amplification transistor AMP are electrically connected via a junction electrode 216, which also serves as a shield electrode. As a result, the capacitance between the floating diffusion FD and the source of the amplification transistor AMP is increased by the capacitance between the junction electrodes 125, 215 and junction electrodes 126, 216, thereby further reducing the parasitic capacitance between the through-wiring 120E and the surrounding well region 212 due to the Miller effect.

[0148] As described above, the light detection device 3 of this embodiment makes it possible to achieve pixel miniaturization, similar to the first embodiment.

[0149] Furthermore, in the photodetector 3 of this embodiment, as described above, the well region 212 consisting of an n-type semiconductor region provided around the through-wiring 120E and the source 224S of the amplification transistor AMP are electrically connected on the junction surface 221S side with the first substrate 100, thereby reducing the wiring density on the surface 200S1 side of the semiconductor layer 200S. Moreover, in the photodetector 3 of this embodiment, the junction electrode 216 is connected to the well region 212 and the source 224S of the amplification transistor AMP without being connected to a reference potential line (for example, ground GND), thereby reducing the number of through-wirings in the entire chip, enabling a reduction in the overall chip area, suppression of electrical interference between wirings in miniaturized pixels, and / or cost reduction by reducing the number of components.

[0150] <4. Modification 2> Figures 35 and 36 schematically show an example of a specific cross-sectional configuration of a photodetector according to Modification 2 of the present disclosure (photodetector 3A, 3B).

[0151] In the second embodiment described above, an example was shown in which the well region 212 (specifically, the contact region 217) and the source 224S of the amplification transistor AMP are electrically connected via vias 218, junction electrodes 216, through-wiring 220E, and contact portions 219 embedded in the surface 200S1 of the semiconductor layer 200S, but the embodiment is not limited to this. In this modified example, the photodetector 3A has the contact portion 219 embedded in the surface 200S1 of the semiconductor layer 200S formed on the surface 200S1 of the semiconductor layer 200S. In this modified example, the photodetector 3B has the contact portion 219 embedded in the surface 200S1 of the semiconductor layer 200S formed within the interlayer insulating film 223. Except for this point, the photodetectors 3A and 3B have substantially the same configuration as the photodetector 3 of the second embodiment described above.

[0152] Even with this configuration, the modified photodetectors 3A and 3B can achieve the same effects as the photodetector 3 of the second embodiment described above.

[0153] In the photodetectors 3, 3A, and 3B, examples were shown in which the well region 212 (specifically, the contact region 217) and the source 224S of the amplification transistor AMP are electrically connected via the junction electrode 216. However, the well region 212 (specifically, the contact region 217) and the junction electrode 216 do not necessarily have to be connected.

[0154] Figure 37 schematically shows another example (photodetector 3C) of the specific cross-sectional configuration of a photodetector according to Modification 2 of the present disclosure. In photodetector 3C, the junction electrode 216 and the source 224S of the amplification transistor AMP are electrically connected via the through-wiring 121E, without providing a well region 212 around the through-wiring 120E. In photodetector 3C, Miller effect capacitance is formed only between the junction electrodes 125, 215 and the junction electrodes 126, 216. Even in such a configuration, parasitic capacitance between the through-wiring 120E and the surrounding semiconductor layer 200S can be reduced.

[0155] <5. Modification 3> Figures 38 to 45 schematically show another example of the planar configuration of the pixel circuit 210 and bonding electrodes 215, 216 on the second substrate 200 of the light detection device 3, as a modification of the second embodiment described above.

[0156] Figure 29 shows a wiring layout in which a Miller effect capacitance is formed between one of the four junction electrodes 126, 216 surrounding the junction electrodes 125, 215 and one of them. However, the layout is not limited to this. The junction electrodes 126, 216 that form a Miller effect capacitance with the junction electrodes 125, 215 may be two of the four junction electrodes 126, 216 surrounding the junction electrodes 125, 215.

[0157] For example, Figure 38 shows that the source 224S of the amplification transistor AMP is widened in the X-axis direction and connected to two adjacent junction electrodes 216 in the X-axis direction. Figure 39 shows that two junction electrodes 216, which are located diagonally among the four junction electrodes 126, 216 surrounding the junction electrodes 125, 215, are connected to the source 224S of the amplification transistor AMP by, for example, a first wiring layer W21.

[0158] Figure 40 shows the wiring layout shown in Figure 29, but with an additional shield electrode 216X added between the junction electrode 216 connected to the source 224S of the amplification transistor AMP and the junction electrode 215, among the four junction electrodes 126, 216 surrounding the junction electrodes 125, 215. This shield electrode 216X is connected to a reference potential line (for example, ground GND). Figure 41 combines the wiring layout shown in Figure 38 and the wiring layout shown in Figure 40. As shown in Figure 38, when the source 224S of the amplification transistor AMP is widened in the X-axis direction and connected to two adjacent junction electrodes 216 in the X-axis direction, an additional shield electrode 216X may be added between the two junction electrodes 216 on the opposite side of the junction electrode 215 and the junction electrode 215. Figure 42 combines the wiring layout shown in Figure 39 and the wiring layout shown in Figure 40. As shown in Figure 39, when two junction electrodes 216, which are arranged diagonally among the four junction electrodes 126, 216 surrounding the junction electrodes 125, 215, are connected to the source 224S of the amplification transistor AMP by, for example, the first wiring layer W21, additional shield electrodes 216X may be provided between the two junction electrodes 216 and the junction electrode 215, which are arranged in positions symmetric to these two junction electrodes 216.

[0159] Figure 43 shows the wiring layout shown in Figure 40, but with a rectangular planar shape for the junction electrode 216 connected to the source 224S of the amplification transistor AMP. Figure 44 combines the wiring layout shown in Figure 41 and the wiring layout shown in Figure 43. Figure 45 combines the wiring layout shown in Figure 42 and the wiring layout shown in Figure 43. Thus, the multiple junction electrodes 216 exposed on the junction surface 221S of the second substrate 200 may be rectangular, or there may be a mixture of junction electrodes 216 having different planar shapes.

[0160] In any of the above configurations, the modified photodetector 3 can obtain the same effects as the second embodiment described above.

[0161] <6. Application Examples> (Application Example 1) The above-mentioned light detection device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, and mobile phones with imaging capabilities. Figure 46 shows a schematic configuration of the electronic device 1000.

[0162] The electronic device 1000 includes, for example, a lens group 1001, a light detection device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0163] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the light detection device 1. The light detection device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0164] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the light detection device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the light detection device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0165] The display unit 1004 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the light detection device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0166] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0167] (Application Example 2) Figure 47A schematically shows an example of the overall configuration of a photodetection system 2000 equipped with a photodetector 1. Figure 47B shows an example of the circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light-emitting device 2001 as a light source that emits infrared light L2, and a photodetector 2002 as a light-receiving unit having a photoelectric conversion element. The photodetector 1 described above can be used as the photodetector 2002. The photodetection system 2000 may further include a system control unit 2003, a light source drive unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0168] The photodetector 2002 can detect light L1 and light L2. Light L1 is light reflected from ambient light from the outside by the subject (object to be measured) 2100 (Figure 47A). Light L2 is light that has been emitted by the light-emitting device 2001 and then reflected by the subject 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 is detectable in the photoelectric conversion unit of the photodetector 2002, and light L2 is detectable in the photoelectric conversion region of the photodetector 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted on, for example, electronic devices such as smartphones or mobile devices such as cars. The light-emitting device 2001 can be, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the iTOF method can be used, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100 by, for example, the time-of-flight (TOF). As a detection method for the light L2 emitted from the light-emitting device 2001 by the photodetector 2002, for example, the structured light method or the stereo vision method can also be used. For example, in the structured light method, the distance between the photodetector 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern. In the stereo vision method, for example, the distance between the photodetector 2000 and the subject can be measured by using two or more cameras to acquire two or more images of the subject 2100 from two or more different viewpoints. Furthermore, the light-emitting device 2001 and the light-detecting device 2002 can be synchronously controlled by the system control unit 2003.

[0169] <7. Application Examples> (Application to Endoscopic Surgical Systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0170] Figure 48 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0171] Figure 48 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0172] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0173] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0174] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0175] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0176] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0177] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0178] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0179] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0180] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0181] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0182] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength range corresponding to special light observation. In special light observation, for example, so-called narrow-band imaging is performed, in which a predetermined tissue such as blood vessels on the surface of the mucosa is imaged with high contrast by irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), utilizing the wavelength dependence of light absorption in body tissue. Alternatively, fluorescence observation may be performed in special light observation, in which an image is obtained from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence can be obtained by irradiating body tissue with excitation light and observing the fluorescence from the body tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0183] Figure 49 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 48.

[0184] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0185] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0186] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0187] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0188] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0189] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0190] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0191] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0192] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0193] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0194] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0195] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0196] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0197] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0198] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0199] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0200] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 11402 of the configuration described above. By applying the technology described herein to the imaging unit 11402, the detection accuracy is improved.

[0201] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0202] (Examples of application to mobile devices) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0203] Figure 50 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0204] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 50, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0205] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0206] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0207] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0208] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0209] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0210] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0211] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0212] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0213] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 50, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0214] Figure 51 shows an example of the installation position of the imaging unit 12031.

[0215] In Figure 51, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0216] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0217] Figure 51 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0218] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0219] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0220] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0221] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0222] The above describes an example of a mobile object control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, the light detection device according to the above embodiment and its modified example 1 can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, high-resolution images with low noise can be obtained, so that high-precision control using the captured images can be performed in the mobile object control system.

[0223] The present disclosure has been described above with reference to the first and second embodiments and their 1 to 3 modified examples and application examples. However, the present disclosure is not limited to the above embodiments, and various modifications are possible. For example, in the above embodiments, an example was shown in which a plurality of bonding electrodes 126, 216, which correspond to a specific example of a "shield electrode" as one embodiment of the present disclosure, are arranged between a plurality of adjacent bonding electrodes 125, 215 in diagonal directions in the X-axis and Y-axis directions. However, the direction in which the plurality of bonding electrodes 126, 216 are arranged is not particularly limited as long as it is in a direction different from the X-axis and Y-axis directions.

[0224] The effects described herein are for illustrative purposes only. The effects of this disclosure are not limited to those described herein. This disclosure may have effects other than those described herein.

[0225] Furthermore, for example, this disclosure can take the following configuration. In an optical detection device having the following configuration, the capacity of the through-wiring (FD capacity) is reduced, and pixel miniaturization becomes possible. (1) A semiconductor device comprising: (1) a first substrate having a first semiconductor layer having opposing first and second surfaces and on which a plurality of first functional elements are provided, and a first wiring layer provided on the first surface side and forming a first bonding surface; a second substrate having opposing third and fourth surfaces and on which a plurality of second functional elements are provided, and a second wiring layer provided on the third surface side and forming a second bonding surface that is bonded to the first bonding surface; a plurality of bonding electrodes at the first bonding surface and the second bonding surface that electrically connect the plurality of first functional elements and the plurality of second functional elements, respectively, and arranged in a first direction and a second direction perpendicular to the first direction, respectively; and one or more shielding electrodes disposed between at least one pair of adjacent bonding electrodes at least one set in a third direction oblique to the first direction and the second direction at least one of the first bonding surface and the second bonding surface. (2) The semiconductor device according to (1), wherein, when the first direction is the row direction and the second direction is the column direction, the plurality of junction electrodes are arranged alternately across two adjacent rows and two adjacent columns. (3) The semiconductor device according to (2), wherein the spacing between the plurality of junction electrodes arranged alternately across two adjacent rows and two adjacent columns is narrower than the spacing between adjacent plurality of junction electrodes in the first direction and the second direction. (4) The semiconductor device according to (2) or (3), wherein the plurality of shield electrodes are arranged in a matrix, spaced apart from each other, between the plurality of junction electrodes arranged alternately across two adjacent rows and two adjacent columns. (5) The semiconductor device according to any one of (1) to (4), wherein, when the first direction is the row direction and the second direction is the column direction, the plurality of junction electrodes are arranged in a matrix. (6) The semiconductor device according to (5), wherein the plurality of shield electrodes are arranged in a matrix with space between them between adjacent junction electrodes in a third direction which is oblique to the first and second directions.(7) The semiconductor device according to any one of (1) to (6), wherein the plurality of shield electrodes have an anisotropic planar shape. (8) The semiconductor device according to (7), wherein the plurality of shield electrodes include a first shield electrode provided on the first junction surface and a second shield electrode provided on the second junction surface. (9) The semiconductor device according to (8), wherein at least one of the first shield electrode and the second shield electrode has a substantially rectangular or substantially elliptical planar shape, and its long side or major axis is longer than the other side or axis, and extends between adjacent first functional elements among the plurality of first functional elements that are driven at the same timing. (10) The semiconductor device according to (8), wherein at least one of the first shield electrode and the second shield electrode has a substantially rectangular or substantially elliptical planar shape, and its long side or major axis is longer than the other side or axis, and is perpendicular to a straight line connecting adjacent first functional elements among the plurality of first functional elements that are driven at the same timing. (11) The semiconductor device according to any one of (8) to (10), wherein a reference potential is applied to the first shield electrode and the second shield electrode, respectively.(12) A first semiconductor layer having opposing first and second surfaces, and having a plurality of photoelectric conversion units provided for each pixel and a plurality of charge holding units provided for one or more pixels for temporarily holding charges transferred from the plurality of photoelectric conversion units, wherein the plurality of charge holding units are provided in a first direction and a second direction orthogonal to the first direction, and a first substrate including a first wiring layer provided on the first surface side and forming a first junction surface; A second semiconductor layer having opposing third and fourth surfaces, and having a plurality of readout circuits provided one for each of the one or more pixels for outputting pixel signals based on charge carriers output from the pixels, and a second substrate including a second wiring layer provided on the third surface side and forming a second junction surface that is joined to the first junction surface; A plurality of junction electrodes provided in the first direction and the second direction, respectively, electrically connecting the plurality of charge holding units and the plurality of readout circuits at the first junction surface and the second junction surface, respectively. A photodetector comprising one or more shield electrodes disposed between at least one pair of adjacent junction electrodes in a third direction oblique to the first and second directions on at least one of the first and second junction surfaces. (13) The photodetector according to (12), wherein the plurality of readout circuits are provided on the fourth surface side of the second semiconductor layer, and the second substrate further has a plurality of first through-wirings that penetrate between the third and fourth surfaces of the second semiconductor layer and are connected to a plurality of junction electrodes that electrically connect the plurality of charge holding portions and the plurality of readout circuits. (14) The photodetector according to (13), wherein each of the plurality of readout circuits includes an amplifying transistor, and each of the plurality of first through-wirings is electrically connected to the gate of the amplifying transistor. (15) The photodetector according to (14), wherein the second substrate further has a plurality of second through-wirings that penetrate between the third and fourth surfaces of the second semiconductor layer, and each of the plurality of second through-wirings electrically connects the source of the amplification transistor to the shield electrode.(16) The photodetector according to (15), wherein the second through-wiring and the source of the amplification transistor are electrically connected via an embedded conductive film embedded in the fourth surface of the second semiconductor layer, a polysilicon film formed on the fourth surface of the second semiconductor layer, or a metal wiring provided on the fourth surface side of the second semiconductor layer. (17) The photodetector according to (15) or (16), wherein the second semiconductor layer has a plurality of openings through which the plurality of first through-wirings each pass through, and the sides of the openings and their vicinity have well layers of a first conductivity type different from the surrounding area, and the plurality of shield electrodes are electrically connected to the source of the amplification transistor and the well layer of the first conductivity type, respectively. (18) The photodetector according to any one of (12) to (17), wherein the readout circuit is provided on the third surface side of the second semiconductor layer. (19) The photodetector according to any one of (12) to (18), further comprising a third substrate having a control circuit for driving the pixels and the readout circuit, wherein the first substrate, the second substrate and the third substrate are stacked in this order.(20) A photodetector comprising: a first semiconductor layer having opposing first and second surfaces, and having a plurality of photoelectric conversion units provided for each pixel and a plurality of charge holding units provided for each pixel for temporarily holding charges transferred from the plurality of photoelectric conversion units, and the plurality of charge holding units being provided in a first direction and a second direction orthogonal to the first direction, and a first substrate including a first wiring layer provided on the first surface side and forming a first junction surface; a second semiconductor layer having opposing third and fourth surfaces, and having a plurality of readout circuits provided one for each of the plurality of pixels and for outputting pixel signals based on charge carriers output from the pixels, and a second substrate including a second wiring layer provided on the third surface side and forming a second junction surface that is joined to the first junction surface; and a plurality of junction electrodes provided in the first direction and the second direction, respectively, which electrically connect the plurality of charge holding units and the plurality of readout circuits at the first junction surface and the second junction surface, respectively. An electronic device having one or more shielding electrodes disposed between at least one pair of adjacent bonding electrodes in a third direction oblique to the first and second directions, on at least one of the first bonding surface and the second bonding surface.

[0226] This application claims priority based on Japanese Patent Application No. 2024-196296, filed with the Japan Patent Office on 8 November 2024, and all contents of that application are incorporated herein by reference.

[0227] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A semiconductor device comprising: a first substrate having a first and second opposing surface and a plurality of first functional elements provided on a first semiconductor layer, and a first wiring layer provided on the first surface side and forming a first bonding surface; a second substrate having a third and fourth opposing surface and a plurality of second functional elements provided on a second semiconductor layer, and a second wiring layer provided on the third surface side and forming a second bonding surface that is bonded to the first bonding surface; a plurality of bonding electrodes at the first bonding surface and the second bonding surface, respectively, electrically connecting the plurality of first functional elements and the plurality of second functional elements, and arranged in a first direction and a second direction orthogonal to the first direction, respectively; and one or more shielding electrodes disposed between at least one pair of adjacent bonding electrodes at least one set in a third direction oblique to the first direction and the second direction at least one of the first bonding surface and the second bonding surface.

2. The semiconductor device according to claim 1, wherein, when the first direction is the row direction and the second direction is the column direction, the plurality of bonding electrodes are arranged alternately across two adjacent rows and two adjacent columns.

3. The semiconductor device according to claim 2, wherein the spacing between the plurality of bonding electrodes, which are alternately arranged across two adjacent rows and two adjacent columns, is narrower than the spacing between adjacent plurality of bonding electrodes in the first and second directions.

4. The semiconductor device according to claim 2, wherein the plurality of shield electrodes are arranged in a matrix with spacing between them, between the plurality of bonding electrodes which are alternately arranged across two adjacent rows and two adjacent columns.

5. The semiconductor device according to claim 1, wherein, when the first direction is the row direction and the second direction is the column direction, the plurality of junction electrodes are arranged in a matrix.

6. The semiconductor device according to claim 5, wherein the plurality of shield electrodes are arranged in a matrix with spaces between them between adjacent junction electrodes in a third direction which is oblique to the first and second directions.

7. The semiconductor device according to claim 1, wherein the plurality of shield electrodes have an anisotropic planar shape.

8. The semiconductor device according to claim 7, wherein the plurality of shield electrodes include a first shield electrode provided on the first bonding surface and a second shield electrode provided on the second bonding surface.

9. The semiconductor device according to claim 8, wherein at least one of the first shield electrode and the second shield electrode has a substantially rectangular or substantially elliptical planar shape, and its long side or major axis is longer than the other side or axis, and extends between adjacent first functional elements among the plurality of first functional elements that are driven at the same timing.

10. The semiconductor device according to claim 8, wherein at least one of the first shield electrode and the second shield electrode has a substantially rectangular or substantially elliptical planar shape, the longer side or major axis thereof is longer than the other side or axis, and is perpendicular to a straight line connecting adjacent first functional elements among the plurality of first functional elements that are driven at the same timing.

11. The semiconductor device according to claim 8, wherein a reference potential is applied to the first shield electrode and the second shield electrode, respectively.

12. A first semiconductor layer having opposing first and second surfaces, and having a plurality of photoelectric conversion units provided for each pixel, and a plurality of charge holding units provided for each pixel for temporarily holding charges transferred from the plurality of photoelectric conversion units, wherein the plurality of charge holding units are provided in a first direction and a second direction orthogonal to the first direction, and a first substrate including a first wiring layer provided on the first surface side and forming a first junction surface; a second semiconductor layer having opposing third and fourth surfaces, and having a plurality of readout circuits provided one for each of the plurality of pixels, for outputting pixel signals based on charge carriers output from the pixels, and a second substrate including a second wiring layer provided on the third surface side and forming a second junction surface that is joined to the first junction surface; a plurality of junction electrodes provided on the first junction surface and the second junction surface, respectively, electrically connecting the plurality of charge holding units and the plurality of readout circuits, and arranged in the first direction and the second direction, A photodetector comprising one or more shielding electrodes disposed between at least one pair of adjacent bonding electrodes in a third direction oblique to the first and second directions, on at least one of the first bonding surface and the second bonding surface.

13. The photodetector according to claim 12, wherein the plurality of readout circuits are provided on the fourth side of the second semiconductor layer, and the second substrate further has a plurality of first through-wirings that penetrate between the third and fourth surfaces of the second semiconductor layer and are connected to a plurality of junction electrodes that electrically connect the plurality of charge holding portions and the plurality of readout circuits.

14. The photodetector according to claim 13, wherein each of the plurality of readout circuits includes an amplifying transistor, and each of the plurality of first through-wirings is electrically connected to the gate of the amplifying transistor.

15. The photodetector according to claim 14, wherein the second substrate further has a plurality of second through-wirings penetrating between the third and fourth surfaces of the second semiconductor layer, and each of the plurality of second through-wirings electrically connects the source of the amplification transistor to the shield electrode.

16. The photodetector according to claim 15, wherein the second through-wiring and the source of the amplification transistor are electrically connected via an embedded conductive film embedded in the fourth surface of the second semiconductor layer, a polysilicon film formed on the fourth surface of the second semiconductor layer, or a metal wiring provided on the fourth surface side of the second semiconductor layer.

17. The photodetector according to claim 15, wherein the second semiconductor layer has a plurality of openings through which the plurality of first through-wirings each pass through, the sides of the openings and their vicinity have well layers of a first conductivity type different from the surrounding area, and the plurality of shield electrodes are each electrically connected to the source of the amplification transistor and the well layer of the first conductivity type.

18. The photodetector according to claim 12, wherein the readout circuit is provided on the third surface side of the second semiconductor layer.

19. The photodetector according to claim 12, further comprising a third substrate having a control circuit for driving the pixels and the readout circuit, wherein the first substrate, the second substrate and the third substrate are stacked in this order.

20. A photodetector comprising: a first semiconductor layer having opposing first and second surfaces, and having a plurality of photoelectric conversion units provided for each pixel, and a plurality of charge holding units provided for each pixel for temporarily holding charges transferred from the plurality of photoelectric conversion units, and the plurality of charge holding units provided in a first direction and a second direction orthogonal to the first direction, respectively; and a first substrate including a first wiring layer provided on the first surface side and forming a first junction surface; a second semiconductor layer having opposing third and fourth surfaces, and having a plurality of readout circuits provided one for each of the plurality of pixels, and for outputting pixel signals based on charge carriers output from the pixels; and a second substrate including a second wiring layer provided on the third surface side and forming a second junction surface that is joined to the first junction surface; and a plurality of junction electrodes provided in the first direction and the second direction, respectively, which electrically connect the plurality of charge holding units and the plurality of readout circuits, respectively, at the first junction surface and the second junction surface, An electronic device having one or more shielding electrodes disposed between at least one pair of adjacent bonding electrodes in a third direction oblique to the first and second directions, on at least one of the first bonding surface and the second bonding surface.

Images