Semiconductor device

Abstract

Provided is a semiconductor device comprising a semiconductor substrate, an emitter electrode, and an interlayer insulating film, wherein: the semiconductor substrate includes a first dummy trench portion having a length in a first direction and connected to the emitter electrode via a first contact hole, a first gate trench portion disposed side by side with the first dummy trench portion in a second direction, and a first active mesa portion in contact with the first gate trench portion; the first active mesa portion includes a first emitter region connected to the emitter electrode via a second contact hole; in the first direction, an end portion of the first contact hole is located inside an end portion of the second contact hole; and the first contact hole is not provided outside the second contact hole in the first direction and is provided in a range overlapping the second contact hole in the second direction.

Description

Semiconductor device

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes that "In this example, the dummy conductive portion 34 of the dummy trench portion 30 and the emitter electrode 52 are connected via a contact hole 156 provided in the interlayer insulating film 26." Patent Document 2 describes that "In addition, the dummy trench portion 30 is directly connected to the emitter electrode 52 via a contact hole 56." [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-28563 [Patent Document 2] Japanese Patent Application Laid-Open No. 2024-73632 General disclosure

[0003] (Problems to be Solved) Broaden the area of the active portion of the semiconductor substrate. (Means for Solving the Problems)

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, an emitter electrode provided above the upper surface of the semiconductor substrate, and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode. In the above semiconductor device, the semiconductor substrate may have a drift region of a first conductivity type, a first dummy trench portion having a longitudinal direction in a first direction and connected to the emitter electrode by a first contact hole provided in the interlayer insulating film, a first gate trench portion having a longitudinal direction in a first direction and arranged alongside the first dummy trench portion in a second direction intersecting the first direction, to which a gate voltage is applied, and a first active mesa portion in contact with the first gate trench portion. In any of the above semiconductor devices, the first active mesa portion may include a first emitter region of a first conductivity type on the upper surface of the semiconductor substrate, connected to the emitter electrode by a second contact hole provided in the interlayer insulating film. In any of the above semiconductor devices, the end of the first contact hole in the first direction may be located inward from the end of the second contact hole. In any of the above semiconductor devices, the first contact hole may not be located outward from the second contact hole in the first direction, but may be located in a range that overlaps with the second contact hole in the second direction.

[0005] In any of the semiconductor devices described above, the first contact hole may not be located outside the outermost first emitter region of the first active mesa in the first direction, but rather inside it.

[0006] In any of the above semiconductor devices, the first active mesa portion may include a first contact region of a second conductivity type connected to the emitter electrode by a second contact hole provided in the interlayer insulating film on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first contact hole may not be located outside the outermost first contact region of the first active mesa portion in the first direction, but rather inside it.

[0007] In any of the above semiconductor devices, the semiconductor substrate may have a second conductivity type well region located at a position that overlaps with the first dummy trench portion and the first gate trench portion in the first direction when viewed from above. In any of the above semiconductor devices, the first contact hole may not be located at a position that overlaps with the well region when viewed from above, but rather located inside the well region.

[0008] In any of the semiconductor devices described above, at least a portion of the first contact hole may face the first emitter region of the first active mesa in the second direction.

[0009] In any of the above semiconductor devices, the first active mesa portion may include a first contact region of a second conductivity type connected to the emitter electrode by a second contact hole provided in the interlayer insulating film on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first emitter region and the first contact region may be arranged alternately along the first direction. In any of the above semiconductor devices, the first active mesa portion may be a mesa portion sandwiched between the first dummy trench portion and the first gate trench portion. In any of the above semiconductor devices, in the second direction, the portion of the first contact hole facing the first emitter region may have a longer length in the first direction than the portion facing the first contact region.

[0010] In any of the semiconductor devices described above, the entirety of the first contact hole may face the first emitter region in the second direction.

[0011] In the first direction of any of the above semiconductor devices, a plurality of the first contact holes may be discretely arranged.

[0012] In the first direction of any of the semiconductor devices described above, the first contact hole may be shorter than the second contact hole.

[0013] In any of the above semiconductor devices, the first dummy trench portion may include a central region that includes the center of the first dummy trench portion in the first direction. In any of the above semiconductor devices, the first dummy trench portion may include an outer region that is located outside the central region in the first direction and has a higher density of first contact holes than the central region.

[0014] Any of the above semiconductor devices may include connecting wiring connected to the emitter electrode. In a top view of any of the above semiconductor devices, the density of the first contact holes in the area overlapping with the connection region to which the connecting wiring is connected may be lower than the density of the first contact holes in the area not overlapping with the connection region.

[0015] Any of the above semiconductor devices may include an outer peripheral gate wiring provided above the upper surface of the semiconductor substrate along the edge of the semiconductor substrate, surrounding the first dummy trench and the first gate trench, and an active side gate wiring provided above the upper surface, branching from the outer peripheral gate wiring and extending in the second direction, sandwiched in the first direction by the first active mesa, and electrically connected to the first gate trench. In any of the above semiconductor devices, the first dummy trench may include a central region that includes a point in the first direction where the distance from the outer peripheral gate wiring and the active side gate wiring are equal. In any of the above semiconductor devices, the first dummy trench may include an inner region provided on the side of the active side gate wiring than the central region in the first direction, and where the density of the first contact holes is higher than in the central region.

[0016] In any of the semiconductor devices described above, the width of the portion of the second contact hole that faces the first contact hole in the second direction may be smaller than the width of the portion of the second contact hole that does not face the first contact hole in the second direction.

[0017] In any of the above semiconductor devices, the semiconductor substrate may have a second dummy trench portion arranged in the second direction alongside the first dummy trench portion on the side opposite to the first gate trench portion and connected to the emitter electrode by a third contact hole provided in the interlayer insulating film, a second gate trench portion arranged in the second direction alongside the second dummy trench portion on the side opposite to the first dummy trench portion, and a second active mesa portion in contact with the second gate trench portion. In any of the above semiconductor devices, the second active mesa portion may include a second emitter region of a first conductivity type and a second contact region of a second conductivity type on the upper surface of the semiconductor substrate, connected to the emitter electrode by a fourth contact hole provided in the interlayer insulating film. In any of the above semiconductor devices, the third contact hole may not be located outside the fourth contact hole in the first direction, but may be located in a range that overlaps with the fourth contact hole in the second direction. In any of the above semiconductor devices, the second emitter region and the second contact region may be arranged alternately along the first direction. In any of the above semiconductor devices, the third contact hole may have a longer length in the first direction in the portion facing the second emitter region than in the portion facing the second contact region in the second direction.

[0018] In any of the above semiconductor devices, the first contact hole and the third contact hole may be arranged facing each other in the second direction.

[0019] In any of the semiconductor devices described above, at least a portion of the third contact hole may be provided in a position that does not face the first contact hole in the second direction.

[0020] In any of the above semiconductor devices, the semiconductor substrate may have a dummy mesa portion sandwiched between the first dummy trench portion and the second dummy trench portion. In any of the above semiconductor devices, the dummy mesa portion may include a third emitter region of a first conductivity type and a third contact region of a second conductivity type, on the upper surface of the semiconductor substrate, connected to the emitter electrode by a fifth contact hole provided in the interlayer insulating film. In any of the above semiconductor devices, the third emitter region and the third contact region may be arranged alternately along the first direction.

[0021] In any of the semiconductor devices described above, the first contact hole and the third contact hole may be connected in the second direction via the fifth contact hole.

[0022] The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention.

[0023] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. This is an enlarged view of region D in Figure 1. This is an enlarged view of region D of the semiconductor device 200 in a comparative example. This is a diagram showing a modified example of region D in Figure 1. This is an enlarged view of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is an enlarged view showing a modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is an enlarged view showing another modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is an enlarged view showing another modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is an enlarged view showing another modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is an enlarged view showing another modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. This is a diagram showing an example of the arrangement of the first contact hole 54-1 and the third contact hole 54-3 in a top view. This is a diagram showing another example of the arrangement of the first contact hole 54-1 and the third contact hole 54-3 in a top view. This figure shows another example of the arrangement of the first contact hole 54-1 and the third contact hole 54-3 in a top view. This figure shows an example of the A-A' cross section in Figure 2. This figure shows an example of the B-B' cross section in Figure 2. This figure shows what happens when a shape abnormality occurs in the B-B' cross section in Figure 2. This figure shows another example of the A-A' cross section in Figure 2. This figure shows another example of the B-B' cross section in Figure 2.

[0024] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0026] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0027] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0028] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0029] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0030] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0031] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is NＤ , the acceptor concentration is N Ａ Therefore, the net doping concentration at any given position is N Ｄ -N Ａ In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0032] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacturing of the ingot that forms the basis of the semiconductor substrate. The bulk donor dopants are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by any of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0033] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. Unless otherwise specified, the units used in this specification are the SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m). In addition, each concentration in this invention may be the value at room temperature. As an example, the value at room temperature may be the value at 300 K (Kelvin) (approximately 26.9°C).

[0034] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0035] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to one of the edges 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0036] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode in a top view, the region that overlaps with the emitter region described later, the region in which the emitter region is provided periodically, the region that overlaps with the contact region described later, or the region in which the contact region is provided periodically. However, the region sandwiched between the active areas 160 in a top view does not need to be included in the active area 160. For example, the vicinity of the active-side gate wiring 131 described later does not need to be included in the active area 160.

[0037] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). However, the diode section 80 may be omitted.

[0038] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0039] The diode portion 80 has an N+ type cathode region in the area that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region when viewed from above.

[0040] The transistor section 70 has a P+ type collector region in the area that is in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0041] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0042] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive part of the gate trench part of the active part 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench part. In FIG. 1, the gate wiring is hatched with oblique lines.

[0043] The gate wiring in this example has an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is provided along the end side 162 above the upper surface of the semiconductor substrate 10 and is arranged between the active part 160 and the end side 162 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 in this example surrounds the active part 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active part 160. Also, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region to be described later and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be regarded as the active part 160.

[0044] The outer peripheral gate wiring 130 is connected to the gate pad 164. The outer peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0045] The active side gate wiring 131 is provided so as to branch from the outer peripheral gate wiring 130 and cross the active part 160. The active side gate wiring 131 in this example extends in the X-axis direction. By providing the active side gate wiring 131 in the active part 160, for each region of the semiconductor substrate 10, the variation in the wiring length from the gate pad 164 can be reduced. However, since no main current flows in the vicinity of the active side gate wiring 131, it may not be included in the active part 160.

[0046] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed of a semiconductor such as polysilicon doped with impurities, or they may be wirings in which metal and semiconductor are laminated.

[0047] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active portion 160, crossing the active portion 160 approximately in the center in the Y-axis direction. When the active portion 160 is divided by the active gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0048] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of the transistor unit 70 provided in the active unit 160.

[0049] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. The edge termination structure 90 in this example is located between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0050] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70 and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, and a base section 14 provided inside the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 may further include a contact section 15. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52, an active-side gate wiring 131, and a gate polysilicon layer 133 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0051] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. Contact holes 54 and 64 are provided in the interlayer insulating film, penetrating the film. In Figure 2, the respective contact holes 54 and 64 are hatched with diagonal lines.

[0052] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. The emitter electrode 52 is also connected to the dummy conductive portion in the dummy trench 30 through the contact hole 54 provided in the interlayer insulating film.

[0053] The active gate wiring 131 connects to the gate polysilicon layer 133 through a contact hole 64 provided in the interlayer insulating film. The gate polysilicon layer 133 is provided above the upper surface of the semiconductor substrate 10 and is a wiring of polysilicon doped with impurities. The gate polysilicon layer 133 extends from a position overlapping with the active gate wiring 131 to the negative side in the Y-axis direction and connects to the gate trench portion 40. The gate polysilicon layer 133 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. As a result, a gate voltage is applied from the gate pad 164 to the gate trench portion 40. The gate polysilicon layer 133 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0054] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum, etc. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum, etc.

[0055] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 connecting the emitter region 12 and the emitter electrode 52, towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0056] The transistor section 70 has a plurality of trench sections, including gate trench sections 40 and dummy trench sections 30 arranged side by side in the arrangement direction. In this example, the arrangement direction is the X-axis direction. In this example, the transistor section 70 is provided with two gate trench sections 40 and two dummy trench sections 30 alternately along the arrangement direction. Each gate trench section 40 and dummy trench section 30 has an elongated length in a predetermined direction. In this example, the gate trench sections 40 and dummy trench sections 30 have an elongated length in the Y-axis direction. The direction in which the gate trench sections 40 and dummy trench sections 30 have their elongated lengths is called the first direction. In this example, the first direction is the Y-axis direction. The direction in which the gate trench sections 40 and dummy trench sections 30 are arranged is called the second direction. In this example, the second direction is the X-axis direction. The first and second directions are intersecting directions. In this example, the first and second directions are orthogonal.

[0057] In this example, the two gate trench sections 40 are connected at their leading ends in the first direction by a tip section 41. Preferably, at least a portion of the tip section 41 is provided in a curved shape when viewed from above. By connecting the ends of the two gate trench sections 40 in the Y-axis direction with the tip section 41, electric field concentration at the ends of the gate trench sections 40 can be mitigated.

[0058] In the transistor section 70 of this example, the two dummy trench sections 30 are provided between the gate trench section 40. The dummy trench sections 30 also have an elongated length in the first direction, similar to the gate trench section 40. The tips of the dummy trench sections 30 may be connected by tip sections 31, similar to the gate trench section 40. However, the arrangement pattern and shape of the trench sections are not limited to the example in Figure 2.

[0059] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are positioned to overlap with the well region 11 in a top view. If tip portions 41 and 31 are provided, they may be positioned to overlap with the well region 11 in a top view. In other words, at the Y-axis end of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0060] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in a first direction (Y-axis direction). In this example, the mesa portion sandwiched between the gate trench portion 40 or the gate trench portion 40 and the dummy trench portion 30 is defined as the active mesa portion 60, and the mesa portion sandwiched between the dummy trench portion 30 is defined as the dummy mesa portion 61. In other words, the mesa portion that is in contact with at least the gate trench portion 40 is the active mesa portion 60, and the mesa portion that is in contact only with the dummy trench portion 30 is the dummy mesa portion 61. In this specification, when the term "mesa section" is used, it refers to the active mesa section 60 and the dummy mesa section 61, respectively.

[0061] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0062] The active mesa portion 60 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The active mesa portion 60 may also have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0063] In this example, the contact region 15 and emitter region 12 of the active mesa section 60 are provided from one trench section to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the active mesa section 60 are arranged alternately along the first direction (Y-axis direction). By providing the contact region 15, holes are extracted during turn-off, and latch-up can be suppressed.

[0064] In other examples, the contact region 15 and emitter region 12 of the active mesa portion 60 may be arranged in a stripe pattern along the first direction. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0065] The dummy mesa portion 61 may or may not have an emitter region 12. The dummy mesa portion 61 may or may not have a contact region 15. In this example, the dummy mesa portion 61 has emitter regions 12 and contact regions 15 arranged alternately along the first direction. The arrangement of the emitter regions 12 and contact regions 15 of the dummy mesa portion 61 may be the same as the arrangement of the emitter regions 12 and contact regions 15 of the active mesa portion 60. By providing the contact region 15, holes are extracted during turn-off, and latch-up can be suppressed.

[0066] A contact hole 54 is provided above the active mesa portion 60. The contact hole 54 is located in the region overlapping with the base region 14-e and in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the base region 14-e, the contact region 15, and the emitter region 12. The base region 14-e, the contact region 15, and the emitter region 12 are connected to the emitter electrode via the contact hole 54 on the upper surface of the semiconductor substrate 10. The contact hole 54 is not provided in the region corresponding to the well region 11. The contact hole 54 may be located in the center of the active mesa portion 60 in the second direction (X-axis direction).

[0067] Let Y1 be the end of the contact hole 54 of the dummy trench portion 30 in the first direction. Let Y2 be the end of the contact hole 54 of the active mesa portion 60 in the first direction. In this example, end Y1 is located inside end Y2. Inside may be the side closer to the center in the longitudinal direction of the trench portion, and may be the side away from the active gate wiring 131 or the outer gate wiring 130. In Figure 2, inside is the negative side in the first direction.

[0068] The contact holes 54 of the dummy trench portion 30 do not need to be located outside the contact holes 54 of the active mesa portion 60 in the first direction. "Outside" may refer to the side closer to the end of the trench portion, or the side closer to the active gate wiring 131 or the outer peripheral gate wiring 130. The contact holes 54 of the dummy trench portion 30 may be located in a range that overlaps with the contact holes 54 of the active mesa portion 60 in the second direction. This allows for a larger area of ​​the active portion 160 compared to a comparative example where the contact holes 54 of the dummy trench portion 30 are located in a position overlapping with the well region 11, thereby improving the output current with the same area of ​​the semiconductor substrate 10. Alternatively, the area of ​​the semiconductor substrate 10 required to secure the same area of ​​the active portion 160 becomes smaller, thus reducing costs. In other words, the contact holes 54 of the dummy trench portion 30 may be located in the active portion 160. If there are multiple contact holes 54 in the active mesa portion 60, the first contact hole does not need to be located outside the second contact hole, which is located on the outermost side. In this example, the end of the active portion 160 is the end of the outermost contact region 15.

[0069] The contact holes 54 of the dummy trench portion 30 do not need to be located in a position that overlaps with the well region 11 when viewed from above. The contact holes 54 of the dummy trench portion 30 may be located inside the well region 11 when viewed from above. Also, the contact holes 54 of the dummy trench portion 30 do not need to be located outside the outermost emitter region 12 of the active mesa portion 60 in the first direction. The contact holes 54 of the dummy trench portion 30 may be located inside the emitter region 12 in the first direction. Inside the emitter region 12 means inside the outer edge of the emitter region 12 in the first direction. This makes it possible to increase the area of ​​the active portion 160.

[0070] When a contact area 15 is provided in the active mesa portion 60, the contact holes 54 of the dummy trench portion 30 do not need to be located outside the outermost contact area 15 of the active mesa portion 60 in the first direction. The contact holes 54 of the dummy trench portion 30 may be located inside the contact area 15 in the first direction. Inside the contact area 15 means inside the outer edge of the contact area 15 in the first direction. This also allows for a larger area of ​​the active portion 160. Multiple dummy trench portions 30 may have the above-described arrangement of contact holes 54, and all dummy trench portions 30 of the semiconductor device 100 may have the above-described arrangement of contact holes 54.

[0071] Let D1 be the distance in the first direction between the tip of the dummy trench portion 30 and the end of the contact hole 54 of the active mesa portion 60. The distance D1 may be 20 μm or less. By arranging the contact hole 54 in this example, the distance D1 can be reduced, and the area of ​​the active portion 160 can be increased. The distance D1 may be 2 μm or more.

[0072] Figure 3 is an enlarged view of region D of the semiconductor device 200 in the comparative example. In the semiconductor device 200 of the comparative example, end Y1 is located outside of end Y2. That is, the contact hole 54 of the dummy trench portion 30 is located outside of the contact hole 54 of the active mesa portion 60 in the first direction. Furthermore, the contact hole 54 of the dummy trench portion 30 is located in a position that overlaps with the well region 11, and is located outside of the outermost emitter region 12 of the active mesa portion 60 in the first direction, and outside of the outermost contact region 15 of the active mesa portion 60 in the first direction. As a result, the distance from the tip portion 31 of the dummy trench portion 30 to the emitter region 12 of the active portion 160 becomes longer, and the area of ​​the active portion 160 becomes smaller. In other words, the contact hole 54 of the dummy trench portion 30 is located outside of the active portion 160. In the comparative example semiconductor device 200, a connection portion made of impurity-doped polysilicon may be provided near the contact hole 54 between the emitter electrode 52 and the dummy trench portion 30.

[0073] Figure 4 shows a modified example of region D in Figure 1. This example differs from the example in Figure 2 in that a gate polysilicon layer 133 is not provided above the upper surface of the semiconductor substrate 10. In other words, the active gate wiring 131 in this example is directly connected to the gate trench portion 40. This eliminates the step between the gate polysilicon layer 133 and the aforementioned connection portion, and allows for a larger area of ​​the active portion 160.

[0074] Figure 5 is an enlarged view of the dummy mesa section 61 and the active mesa section 60 in Figure 2. Figure 5 shows the vicinity of the ends of the dummy mesa section 61 and the two active mesa sections 60 that are positioned flanking the dummy mesa section 61 in the second direction. In this example, the dummy trench section 30 on the positive side in the second direction shown in Figure 5 is referred to as the first dummy trench section 30-1. The gate trench section 40 positioned alongside the first dummy trench section 30-1 on the positive side in the second direction is referred to as the first gate trench section 40.

[0075] On the opposite side of the first gate trench section 40-1, a dummy trench section 30 arranged in the second direction alongside the first dummy trench section 30-1 is designated as the second dummy trench section 30-2. Also, on the opposite side of the first dummy trench section 30-1, a gate trench section 40 arranged in the second direction alongside the second dummy trench section 30-2 is designated as the second gate trench section 40-2.

[0076] The active mesa portion 60 in contact with the first gate trench portion 40-1 is designated as the first active mesa portion 60-1, and the active mesa portion 60 in contact with the second gate trench portion 40-2 is designated as the second active mesa portion 60-2. In this example, the dummy mesa portion 61 is a mesa portion sandwiched between the first dummy trench portion 30-1 and the second dummy trench portion 30-2. The width of each mesa portion may be equal.

[0077] In this example, the first active mesa portion 60-1 is a mesa portion sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1. However, the first active mesa portion 60-1 is not in contact with the first dummy trench portion 30-1, and other trench portions may be provided between the first dummy trench portion 30-1 and the first gate trench portion 40-1. For example, the mesa portion sandwiched between the gate trench portion 40 shown in Figure 2 may be the first active mesa portion 60-1. Similarly, the second active mesa portion 60-2 may have other trench portions provided between the second dummy trench portion 30-2 and the second gate trench portion 40-2. Furthermore, the first dummy trench portion 30-1 may be any dummy trench portion 30 provided on the semiconductor substrate 10. The second dummy trench section 30-2 is not required, and other dummy trench sections 30 may be provided between the first dummy trench section 30-1 and the second dummy trench section 30-2.

[0078] In this example, the contact hole 54 provided in the first dummy trench section 30-1 is designated as the first contact hole 54-1. The contact hole 54 provided in the first active mesa section 60-1 is designated as the second contact hole 54-2. The contact hole 54 provided in the second dummy trench section 30-2 is designated as the third contact hole 54-3. The contact hole 54 provided in the second active mesa section 60-2 is designated as the fourth contact hole 54-4. The contact hole 54 provided in the dummy mesa section 61 is designated as the fifth contact hole 54-5. The width of each contact hole 54 may be equal.

[0079] The emitter region 12 provided in the first active mesa section 60-1 is designated as the first emitter region 12-1, and the contact region 15 provided in the first active mesa section 60-1 is designated as the first contact region 15-1. In this example, the first emitter region 12-1 and the first contact region 15-1 are arranged alternately along the first direction. Furthermore, the emitter region 12 provided in the second active mesa section 60-2 is designated as the second emitter region 12-2, and the contact region 15 provided in the second active mesa section 60-2 is designated as the second contact region 15-2. In this example, the second emitter region 12-2 and the second contact region 15-2 are arranged alternately along the first direction. Furthermore, the emitter region 12 provided in the dummy mesa section 61 is designated as the third emitter region 12-3, and the contact region 15 provided in the dummy mesa section 61 is designated as the third contact region 15-3. In this example, the third emitter region 12-3 and the third contact region 15-3 are arranged alternately along the first direction.

[0080] At least a portion of the first contact hole 54-1 may face the first emitter region 12-1 of the first active mesa portion 60-1 in the second direction. Let We1 be the length of the portion of the first contact hole 54-1 that faces the first emitter region 12-1 in the second direction. Let Wc1 be the length of the portion of the first contact hole 54-1 that faces the first contact region 15-1 in the second direction. In this example, since the first contact hole 54-1 faces the first contact region 15-1 in two places, the sum of the respective lengths Wc11 and Wc21 is Wc1.

[0081] Length We1 may be greater than length Wc1. When the first contact hole 54-1 is provided in the active portion 160, the contact holes 54 will be densely clustered in the vicinity of the first contact hole 54-1. In this example, the density of contact holes increases in the second direction. In that case, the etching amount may be insufficient, resulting in shallow etching of the contact holes 54, which may lead to poor contact between the emitter electrode 52 and the semiconductor substrate 10. As the semiconductor device 100 is miniaturized, the mesa portion becomes narrower, increasing the likelihood of shallow etching. If shallow etching occurs in the second contact hole 54-2, and it occurs above the first contact region 15-1, the hole may not be extracted when the semiconductor device 100 is turned off, increasing the risk of reduced latch-up tolerance. On the other hand, even if shallow etching occurs above the first emitter region 12-1, only a localized current flow is interrupted, and the risk of reduced latch-up tolerance is small. With the above arrangement, the area where shallow drilling occurs can be placed above the first emitter region 12-1, thereby reducing the risk of reduced latch-up tolerance due to the provision of the first contact hole 54-1 in the active portion 160.

[0082] The length We1 may be 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more of the length Wc1. This further suppresses poor contact between the first contact region 15-1 and the emitter electrode 52. The same relationship may also hold for the third emitter region 12-3 and the third contact region 15-3 of the dummy mesa portion 61.

[0083] Similarly, with respect to the third contact hole 54-3, at least a portion of the third contact hole 54-3 may face the second emitter region 12-2 of the second active mesa portion 60-2 in the second direction. Let We3 be the length of the portion of the third contact hole 54-3 that faces the second emitter region 12-2 in the second direction. Let Wc3 be the length of the portion of the third contact hole 54-3 that faces the second contact region 15-2 in the second direction. In this example, since the third contact hole 54-3 faces the second contact region 15-2 in two places, the sum of the respective lengths Wc13 and Wc23 is Wc3.

[0084] Length We3 may be greater than length Wc3. Length We3 may be 1.5 times or more, 2 times or more, 5 times or more, or 10 times or more of length Wc3. This further suppresses poor contact between the second contact region 15-2 and the emitter electrode 52. The same relationship may also hold for the third emitter region 12-3 and the third contact region 15-3 of the dummy mesa portion 61.

[0085] In the first direction, multiple first contact holes 54-1 may be discretely arranged. If the above-mentioned shallow drilling occurs in the first contact hole 54-1, the first dummy trench portion 30-1 will become floating potential, which poses a risk of switching waveform abnormalities or failure starting points. By providing multiple first contact holes 54-1, even if shallow drilling occurs in one first contact hole 54-1, the connection between the dummy trench portion 30-1 and the emitter electrode 52 can be ensured in the other first contact holes 54-1. Multiple first contact holes 54-1 may be provided for one first dummy trench portion 30-1. Each first contact hole 54-1 may have the above-mentioned length relationship. Similarly, for the third contact holes 54-3, multiple third contact holes 54-3 may be discretely arranged in the first direction, and each third contact hole 54-3 may have the above-mentioned length relationship.

[0086] In the first direction, the length L1 of the first contact hole 54-1 may be smaller than the length L2 of the second contact hole 54-2. If multiple first contact holes 54-1 are provided, the length L1 of each first contact hole 54-1 may be smaller than the length L2 of the second contact hole 54-2. In the first direction, the length L3 of the third contact hole 54-3 may be smaller than the length L4 of the fourth contact hole 54-4. If multiple third contact holes 54-3 are provided, the length L3 of each third contact hole 54-3 may be smaller than the length L4 of the fourth contact hole 54-4.

[0087] The first contact hole 54-1 and the third contact hole 54-3 may be positioned opposite each other in the second direction. In other words, at least a portion of the first contact hole 54-1 and at least a portion of the third contact hole 54-3 may overlap in the second direction. In that case, another contact hole 54 may be positioned between the first contact hole 54-1 and the third contact hole 54-3. In this example, a fifth contact hole 54-5 is positioned between them.

[0088] Figure 6 is an enlarged view showing a modified example of the dummy mesa portion 61 and the active mesa portion 60 in Figure 2. In this example, the length L1 of the first contact hole 54-1 and the length L3 of the third contact hole 54-3 differ from the example shown in Figure 5. Other aspects are the same as the example in Figure 5.

[0089] In this example, the entire first contact hole 54-1 faces the first emitter region 12-1 in the second direction. In other words, the first contact hole 54-1 does not face the first contact region 15-1 in the second direction. This further suppresses poor contact between the first contact region 15-1 and the emitter electrode 52. Also in this example, the entire first contact hole 54-1 faces the third emitter region 12-3 in the second direction. In the first direction, the length L1 of the first contact hole 54-1 may be shorter than the first emitter region 12-1 or the third emitter region 12-3.

[0090] Similarly, the entire third contact hole 54-3 may face the second emitter region 12-2 in the second direction. The entire third contact hole 54-3 may face the third emitter region 12-3 in the second direction. In the first direction, the length L3 of the third contact hole 54-3 may be shorter than the second emitter region 12-2 or the third emitter region 12-3. The above relationship may hold for each of the first contact holes 54-1 and the third contact hole 54-3. This example also shows a case where the contact hole 54 of the dummy trench portion 30 is not located outside the outermost emitter region 12 of the active mesa portion 60 in the first direction, but is located inside the emitter region 12.

[0091] Figure 7 is an enlarged view showing another modified example of the dummy mesa portion 61 and active mesa portion 60 in Figure 2. In this example, the widths of the second contact hole 54-1 and the fourth contact hole 54-4 differ from the example shown in Figure 5. Other aspects are the same as the example in Figure 5.

[0092] In the second contact hole 54-2, the width in the second direction of the portion facing the first contact hole 54-1 is denoted as W1, and the width in the second direction of the portion not facing the first contact hole 54-1 is denoted as W2. In this example, width W1 is smaller than width W2. If shallow erosion occurs slightly in the second contact hole 54-2 as described above, the above relationship may occur. Even in this case, by using the arrangement shown in Figure 5, most of width W1 overlaps with the emitter region 12-1, so contact between the first contact region 15-1 and the emitter electrode 52 is ensured.

[0093] Similarly, in the fourth contact hole 54-4, the width in the second direction of the portion facing the third contact hole 54-3 is defined as W3, and the width in the second direction of the portion not facing the third contact hole 54-3 is defined as W4. In this example, width W3 is smaller than width W4.

[0094] Similarly, in the fifth contact hole 54-5, the width in the second direction of the portion facing the first contact hole 54-1 or the third contact hole 54-3 is defined as W5, and the width in the second direction of the portion not facing the first contact hole 54-1 or the third contact hole 54-3 is defined as W6. In this example, width W5 is smaller than width W6. Note that the relationship shown in Figure 7 may also hold in the modified example shown in Figure 6.

[0095] Figure 8 is an enlarged view showing another modified example of the dummy mesa portion 61 and active mesa portion 60 in Figure 2. In this example, the shapes of the first contact hole 54-1 and the third contact hole 54-3 differ from the example shown in Figure 5. Other aspects are the same as the example in Figure 5.

[0096] In this example, the first contact hole 54-1 and the third contact hole 54-3 are connected in the second direction via the fifth contact hole 54-5. Because the contact holes 54 are densely packed, rather than being shallowly drilled as described above, the shape shown in this example can occur if the interlayer insulating film between the contact holes 54 is also eroded. Even in this case, since all of these contact holes 54 are contact holes 54 that connect the semiconductor substrate 10 and the emitter electrode 52, there is no problem with the operation of the semiconductor device 100. The shape in this example can also occur in the modified example shown in Figure 6, and can also occur in the modified example shown in Figure 7.

[0097] Figure 9 is an enlarged view showing another modified example of the dummy mesa portion 61 and active mesa portion 60 in Figure 2. In this example, the positions of the second contact hole 54-2 and the fourth contact hole 54-4 in the second direction differ from the example shown in Figure 5. Other aspects are the same as the example in Figure 5.

[0098] Let Xm1 be the central position of the first active mesa portion 60-1 in the second direction. Let Xc2 be the central position of the second contact hole 54-2 in the second direction. Position Xc2 may be closer to the first dummy trench portion 30-1 than position Xm1. This makes it possible to prevent the emitter electrode 52 and the gate trench portion 40 from short-circuiting due to the miniaturization of the semiconductor device 100, by the second contact hole 54-2. On the other hand, since the first contact hole 54-1 and the second contact hole 54-2 are closer together, the above-mentioned shallow drilling is more likely to occur, but by arranging them as in each embodiment or modified example, contact between the first contact region 15-1 and the emitter electrode 52 is ensured.

[0099] Let Xm2 be the central position of the second active mesa portion 60-2 in the second direction. Let Xc4 be the central position of the fourth contact hole 54-4 in the second direction. Position Xc4 may be closer to the second dummy trench portion 30-2 than position Xm2.

[0100] Figure 10 is an enlarged view showing another modified example of the dummy mesa portion 61 and active mesa portion 60 in Figure 2. In this example, the width of the first contact hole 54-1 and the third contact hole 54-3 in the second direction differs from the example shown in Figure 5. Other aspects are the same as the example in Figure 5.

[0101] Let W7 be the width of the second contact hole 54-2 in the second direction. Let W8 be the width of the first contact hole 54-1 in the second direction. In this example, width W8 is smaller than width W7. This reduces the occurrence rate of shape abnormalities such as shallow drilling. On the other hand, if the width W8 is small, it may become difficult to connect the emitter electrode 52 and the first dummy trench portion 30-1, but by providing multiple first contact holes 54-1, the connection can be ensured.

[0102] Let W9 be the width of the fourth contact hole 54-4 in the second direction. Let W10 be the width of the third contact hole 54-3 in the second direction. In this example, width W10 is smaller than width w9. Also, let W11 be the width of the fifth contact hole 54-5 in the second direction. Width W8 may be smaller than width W11. Width W10 may be smaller than width W11.

[0103] Figure 11 shows an example of the arrangement of the first contact hole 54-1 and the third contact hole 54-3 in a top view. Figure 11 shows one end, the center, and the vicinity of the other end of the first dummy trench section 30-1 and the second dummy trench section 30-2, with the sections between one end and the center and between the other end and the center omitted. The first dummy trench section 30-1 and the second dummy trench section 30-2 are connected to each other by the tip section 31. The mesa sections in Figure 11 are also the first active mesa section 60-1, the second active mesa section 60-2, and the dummy mesa section 61, but their reference numerals have been omitted.

[0104] Point C in the figure indicates the central position of the first dummy trench section 30-1 and the second dummy trench section 30-2 in the first direction, respectively. The first dummy trench section 30-1 has a central region 140 including the center C, and an outer region 142 provided outside the central region 140 in the first direction. In Figure 11, two outer regions 142 are shown on the positive and negative sides of the first direction.

[0105] The density of first contact holes 54-1 in the outer region 142 may be higher than that in the central region 140. If the density of contact holes 54 is higher due to the first contact holes 54-1, the interlayer insulating film will be damaged. In the vicinity of the center of the first dummy trench portion 30-1, the interlayer insulating film is subjected to load due to wire bonding, etc., so the damaged interlayer insulating film may break or crack. With the arrangement in this example, it is possible to suppress the breakdown or cracking of the interlayer insulating film due to wire bonding, etc. The density of first contact holes 54-1 in the outer region 142 may be 1.5 times or more, 2 times or more, or 4 times or more than the density of first contact holes 54-1 in the central region 140.

[0106] The semiconductor device 100 may be provided with connecting wiring 148 connected to the emitter electrode 52. The connecting wiring 148 is, for example, a wire or a lead frame. In Figure 11, the connecting wiring 148 is schematically shown as a line. In a top view, the area to which the connecting wiring 148 is connected is defined as the connection area 146. The connection area 146 may include the center C. The density of the first contact holes 54-1 in the area overlapping with the connection area 146 may be lower than the density of the first contact holes 54-1 in the area not overlapping with the connection area 146. This can suppress the destruction or cracking of the interlayer insulating film due to wire bonding, etc. The density of the first contact holes 54-1 in the area overlapping with the connection area 146 may be two-thirds or less, half or one-quarter or less of the density of the first contact holes 54-1 in the area not overlapping with the connection area 146.

[0107] Similarly, in the second dummy trench section 30-2, the density of third contact holes 54-3 may be higher in the outer region 142 than in the central region 140. Also, the density of third contact holes 54-3 in the area overlapping with the connection region 146 may be lower than the density of third contact holes 54-3 in the area not overlapping with the connection region 146.

[0108] Figure 12 shows another arrangement example of the first contact hole 54-1 and the third contact hole 54-3 in a top view. In addition to the area shown in Figure 11, Figure 12 also shows the active side gate wiring 131 and the outer peripheral gate wiring 130. Figure 12 shows a part of the active portion 160, and for example, as shown in Figure 1, the first dummy trench portion 30-1 and the first gate trench portion 40-1 may be provided on the positive Y-axis side, sandwiching the active side gate wiring 131. In that case, the active side gate wiring 131 may be sandwiched in the first direction by the first active mesa portion 60-1, the dummy mesa portion 61, or the first dummy trench portion 30-1, etc. Also, the outer peripheral gate wiring 130 may surround the first dummy trench portion 30-1 and the first gate trench portion 40-1.

[0109] Point E in the figure is a point in the first dummy trench section 30-1 or the third dummy trench section 30-3 where the distance from the outer gate wiring 130 to the active gate wiring 131 is equal in the first direction. In this example, the first dummy trench section 30-1 has a central region 152 including point E and an inner region 154 located on the side of the active gate wiring 131 that is closer to the active gate wiring 131 than the central region 152 in the first direction.

[0110] The density of the first contact holes 54-1 in the inner region 154 may be higher than in the central region 152. In the central region 152, the interlayer insulating film is subjected to load due to wire bonding, etc., so the damaged interlayer insulating film may break or crack. With the arrangement in this example, it is possible to suppress the breakdown or cracking of the interlayer insulating film due to wire bonding, etc.

[0111] The density of the first contact holes 54-1 in the inner region 154 may be 1.5 times or more, 2 times or more, or 4 times or more, than the density of the first contact holes 54-1 in the central region 152. Similarly, in the second dummy trench portion 30-2, the density of the third contact holes 54-3 in the inner region 154 may be higher than that in the central region 152.

[0112] Figure 13 shows another example of the arrangement of the first contact hole 54-1 and the third contact hole 54-3 in a top view. At least a portion of the third contact hole 54-3 may be located in a position that does not face the first contact hole 54-1 in the second direction. In this example, the first contact hole 54-1 and the third contact hole 54-3 are arranged in a staggered pattern. This reduces the density of the contact holes 54 and mitigates the risk of shape abnormalities in the contact holes 54. The entire third contact hole 54-3 may be located in a position that does not face the first contact hole 54-1 in the second direction.

[0113] Figure 14A shows an example of the A-A' cross section in Figure 2. The A-A' cross section is the XZ plane passing through the contact region 15. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0114] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0115] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0116] The semiconductor substrate 10 has an N-type or N-type drift region 18. The active mesa portion 60 has a P+-type contact region 15 and a P--type base region 14, arranged sequentially from the upper surface 21 side of the semiconductor substrate 10. The drift region 18 is provided below the base region 14. The active mesa portion 60 may also have an N+-type storage region 16. The storage region 16 is located between the base region 14 and the drift region 18.

[0117] The contact area 15 is exposed on the upper surface 21 of the semiconductor substrate 10. The contact area 15 may be in contact with the gate trench portion 40. The contact area 15 may be in contact with the trench portions on both sides of the active mesa portion 60.

[0118] The base region 14 is located below the contact region 15. In this example, the base region 14 is located in contact with the contact region 15. The base region 14 may be in contact with the trenches on both sides of the active mesa region 60.

[0119] The storage region 16 is located below the base region 14. The storage region 16 is an N+ type region with a higher doping concentration than the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each active mesa section 60. The configuration of the dummy mesa section 61 may be the same as that of the active mesa section 60.

[0120] An N+ type buffer region 20 may be provided below the drift region 18. The doping concentration in the buffer region 20 is higher than that in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22.

[0121] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0122] The collector region 22 is exposed to the lower surface 23 of the semiconductor substrate 10 and is connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0123] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Two gate trenches 40 and two dummy trenches 30 are provided in the A-A' section. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trenches. Even when doping regions are formed between the trenches after the trenches have been formed, the trenches are still considered to penetrate the doping regions.

[0124] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0125] The gate conductive portion 44 may be provided to be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the outer peripheral gate wiring 130 or the active side gate wiring 131. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in contact with the gate trench portion 40 in the base region 14.

[0126] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in that cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. In another cross-section, the dummy conductive portion 34 is electrically connected to the emitter electrode 52 via a contact hole 54. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0127] The gate trench portion 40 and the dummy trench portion 30 in the cross-section are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0128] Figure 14B shows an example of the B-B' cross section in Figure 2. The B-B' cross section is the XZ plane passing through the emitter region 12. In the B-B' cross section, the contact region 15 of the A-A' cross section becomes the emitter region 12. In addition, a contact hole 54 is provided above the dummy trench portion 30 to connect the dummy conductive portion 34 and the emitter electrode 52. Other aspects are the same as in the A-A' cross section.

[0129] Figure 15 shows the case where a shape abnormality of the contact hole 54 occurs in the B-B' section in Figure 2. In this example, shallow erosion 56 occurs in the active mesa section 60 and dummy mesa section 61 that sandwich the dummy trench section 30, which has a contact hole 54 above it. When shallow erosion 56 occurs, the contact hole 54 either does not penetrate the interlayer insulating film 38 completely or its width becomes narrower, resulting in poor contact between the emitter electrode 52 and the semiconductor substrate 10. However, in this embodiment, since shape abnormalities such as shallow erosion 56 are more likely to occur above the emitter region 12, contact between the emitter electrode 52 and the contact region 15-1 is ensured, and the risk of a decrease in latch-up tolerance can be reduced.

[0130] Figure 16A shows another example of the A-A' section in Figure 2. The contact hole 54 in this example is a trench contact. That is, the contact hole 54 is provided inward beyond the upper surface 21 of the semiconductor substrate 10.

[0131] Figure 16B shows another example of the B-B' cross section in Figure 2. In this example, the contact holes 54 are trench contacts. The contact holes 54 above the dummy trench section 30 may also be trench contacts. This makes it easier to ensure contact between the emitter electrode 52 and the semiconductor substrate 10 even when the contact holes 54 are densely packed.

[0132] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0133] 10... Semiconductor substrate, 11... Well region, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 18... Drift region, 20... Buffer region, 21... Top surface, 22... Collector region, 23... Bottom surface, 24... Collector electrode, 30... Dummy trench section, 31... Tip section, 32... Dummy insulating film, 34... Dummy conductive section, 38... Interlayer insulating film, 40... Gate trench section, 41... Tip section, 42... Gate insulating film, 44... Gate conductive section, 52... Emitter electrode, 54... Contact Hole, 56... Shallow drilling, 60... Active mesa section, 61... Dummy mesa section, 64... Contact hole, 70... Transistor section, 80... Diode section, 90... Edge termination structure section, 100... Semiconductor device, 130... Outer gate wiring, 131... Active side gate wiring, 133... Gate polysilicon layer, 140... Central region, 142... Outer region, 146... Connection region, 148... Connection wiring, 152... Central region, 154... Inner region, 160... Active section, 162... Edge, 164... Gate pad, 200... Semiconductor device

Claims

1. A semiconductor substrate having an upper surface and a lower surface; an emitter electrode provided above the upper surface of the semiconductor substrate; and an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode, wherein the semiconductor substrate has a drift region of a first conductivity type; a first dummy trench portion having a longitudinal direction and connected to the emitter electrode by a first contact hole provided in the interlayer insulating film; a first gate trench portion having a longitudinal direction and arranged alongside the first dummy trench portion in a second direction intersecting the first direction, to which a gate voltage is applied; and a first active mesa portion in contact with the first gate trench portion, wherein the first active mesa portion includes a first emitter region of a first conductivity type on the upper surface of the semiconductor substrate, connected to the emitter electrode by a second contact hole provided in the interlayer insulating film, and in the first direction, the end of the first contact hole is located inward from the end of the second contact hole. A semiconductor device wherein the first contact hole is not located outside the second contact hole in the first direction, and is located within the range overlapping with the second contact hole in the second direction.

2. The semiconductor device according to claim 1, wherein the first contact hole is not located in a range outside the outermost first emitter region of the first active mesa in the first direction, but is located in a range inside it.

3. The semiconductor device according to claim 1, wherein the first active mesa portion includes a first contact region of a second conductivity type connected to the emitter electrode by a second contact hole provided in the interlayer insulating film on the upper surface of the semiconductor substrate, and the first contact hole is not provided in a range outside the outermost first contact region of the first active mesa portion in a first direction, but is provided in a range inside the first contact region.

4. The semiconductor device according to claim 1, wherein the semiconductor substrate has a second conductivity type well region located at a position overlapping with the first dummy trench portion and the first gate trench portion in the first direction when viewed from above, and the first contact hole is not located at a position overlapping with the well region when viewed from above, but is located inside the well region.

5. The semiconductor device according to claim 1, wherein at least a portion of the first contact hole faces the first emitter region of the first active mesa in the second direction.

6. The semiconductor device according to claim 5, wherein the first active mesa portion includes a first contact region of a second conductivity type connected to the emitter electrode by a second contact hole provided in the interlayer insulating film on the upper surface of the semiconductor substrate, the first emitter region and the first contact region are arranged alternately along the first direction, the first active mesa portion is a mesa portion sandwiched between the first dummy trench portion and the first gate trench portion, and the portion of the first contact hole facing the first emitter region is longer in the first direction than the portion facing the first contact region.

7. The semiconductor device according to claim 6, wherein the entirety of the first contact hole faces the first emitter region in the second direction.

8. The semiconductor device according to claim 1, wherein a plurality of the first contact holes are discretely arranged in the first direction.

9. The semiconductor device according to claim 1, wherein in the first direction, the first contact hole is shorter than the second contact hole.

10. The semiconductor device according to claim 1, wherein the first dummy trench portion includes a central region including the center of the first dummy trench portion in the first direction, and an outer region provided outside the central region in the first direction, and having a higher density of first contact holes than the central region.

11. The semiconductor device according to claim 10, comprising connecting wiring connected to the emitter electrode, wherein, in a top view, the density of the first contact holes in the area overlapping with the connection region to which the connecting wiring is connected is lower than the density of the first contact holes in the area not overlapping with the connection region.

12. A semiconductor device according to claim 1, comprising: an outer peripheral gate wiring provided above the upper surface of the semiconductor substrate along the edge of the semiconductor substrate and surrounding the first dummy trench portion and the first gate trench portion; and an active side gate wiring provided above the upper surface, branching from the outer peripheral gate wiring and extending in the second direction, sandwiched in the first direction by the first active mesa portion and electrically connected to the first gate trench portion, wherein the first dummy trench portion comprises a central region including a point where the distance from the outer peripheral gate wiring and the active side gate wiring in the first direction are equal, and an inner region provided on the side of the active side gate wiring that is closer to the central region than the central region and where the density of the first contact holes is higher than that of the central region.

13. The semiconductor device according to claim 1, wherein, in the second direction, the width of the portion of the second contact hole facing the first contact hole is smaller than the width of the portion of the second contact hole not facing the first contact hole.

14. The semiconductor substrate has: a second dummy trench portion arranged in the second direction opposite to the first gate trench portion and adjacent to the first dummy trench portion, and connected to the emitter electrode by a third contact hole provided in the interlayer insulating film; a second gate trench portion arranged in the second direction opposite to the first dummy trench portion and adjacent to the second dummy trench portion; and a second active mesa portion in contact with the second gate trench portion. The second active mesa portion includes, on the upper surface of the semiconductor substrate, a second emitter region of a first conductivity type and a second contact region of a second conductivity type, connected to the emitter electrode by a fourth contact hole provided in the interlayer insulating film; the third contact hole is not provided outside the fourth contact hole in the first direction, and is provided in a range overlapping with the fourth contact hole in the second direction; and the second emitter region and the second contact region are arranged alternately along the first direction. The semiconductor device according to any one of claims 1 to 13, wherein the third contact hole has a longer length in the first direction in the portion facing the second emitter region than in the portion facing the second contact region in the second direction.

15. The semiconductor device according to claim 14, wherein the first contact hole and the third contact hole are arranged facing each other in the second direction.

16. The semiconductor device according to claim 14, wherein at least a portion of the third contact hole is provided in a position that does not face the first contact hole in the second direction.

17. The semiconductor device according to claim 14, wherein the semiconductor substrate has a dummy mesa portion sandwiched between the first dummy trench portion and the second dummy trench portion, and the dummy mesa portion includes a third emitter region of a first conductivity type and a third contact region of a second conductivity type, on the upper surface of the semiconductor substrate, connected to the emitter electrode by a fifth contact hole provided in the interlayer insulating film, and the third emitter region and the third contact region are alternately arranged along the first direction.

18. The semiconductor device according to claim 17, wherein the first contact hole and the third contact hole are connected in the second direction via the fifth contact hole.

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