Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate which has a first main surface. The silicon carbide substrate includes a silicon carbide single crystal substrate which has a first conductivity type, a first semiconductor region which is provided on the silicon carbide single crystal substrate and has the first conductivity type, a second semiconductor region which is provided on the first semiconductor region and has the first conductivity type, and a third semiconductor region which is provided on the first semiconductor region and has a second conductivity type that is different from the first conductivity type. The second semiconductor region and the third semiconductor region are alternately arranged along a first axis that is parallel to the first main surface, the third semiconductor region extends along a second axis that is parallel to the first main surface and is perpendicular to the first axis, and the second semiconductor region contains nitrogen or phosphorus.

Description

Silicon carbide semiconductor equipment

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority under Japanese application No. 2024-194289, filed on November 6, 2024, and incorporates all the provisions contained herein.

[0003] A silicon carbide semiconductor device is disclosed, in which an n-type drift region is provided on a silicon carbide single crystal substrate, and p-type regions are arranged in a staggered pattern within the n-type drift region.

[0004] Japanese Patent Application Publication No. 2021-64723

[0005] The silicon carbide semiconductor device of the present disclosure comprises a silicon carbide substrate having a first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a first semiconductor region provided on the silicon carbide single crystal substrate having the first conductivity type, a second semiconductor region provided on the first semiconductor region having the first conductivity type, and a third semiconductor region provided on the first semiconductor region having a second conductivity type different from the first conductivity type, wherein the second semiconductor region and the third semiconductor region are alternately arranged along a first axis parallel to the first main surface, the third semiconductor region extends along a second axis parallel to the first main surface and perpendicular to the first axis, and the second semiconductor region contains nitrogen or phosphorus.

[0006] Figure 1 is a diagram showing a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. Figure 3 is a diagram showing the concentration distribution of impurities at a position along arrow III in Figure 2. Figure 4 is a cross-sectional view (1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 5 is a cross-sectional view (2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 6 is a cross-sectional view (3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 7 is a cross-sectional view (4) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 8 is a cross-sectional view (5) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 9 is a cross-sectional view (6) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figure 10 is a cross-sectional view (7) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0007] Silicon carbide single crystal substrates may contain basal plane dislocations. When current flows through the drift region during operation of a silicon carbide semiconductor device, stacking faults originating from the basal plane dislocations may expand into the drift region. These stacking faults degrade the forward characteristics.

[0008] This disclosure aims to provide a silicon carbide semiconductor device that can reduce the degradation of forward characteristics.

[0009] According to this disclosure, a silicon carbide semiconductor device can be provided that can reduce the degradation of forward characteristics.

[0010] The implementation methods are described below.

[0011] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions herein, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Negative crystallographic exponents are usually indicated by a "-" (bar) above the number, but in this disclosure, the negative sign is placed before the number. In the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the silicon carbide semiconductor device. The XY plane view is referred to as the plan view, and from any point, the +Z direction may be referred to as upward, upper side, or up, and the -Z direction may be referred to as downward, lower side, or down.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a first semiconductor region provided on the silicon carbide single crystal substrate having the first conductivity type, a second semiconductor region provided on the first semiconductor region having the first conductivity type, and a third semiconductor region provided on the first semiconductor region having a second conductivity type different from the first conductivity type, wherein the second semiconductor region and the third semiconductor region are aligned along a first axis parallel to the first main surface, the third semiconductor region extends along a second axis parallel to the first main surface and perpendicular to the first axis, and the second semiconductor region contains nitrogen or phosphorus. When a hole reaches the silicon carbide single crystal substrate during operation of the silicon carbide semiconductor device, a stacking fault is generated from a basal plane dislocation in the silicon carbide single crystal substrate. When the second semiconductor region contains nitrogen or phosphorus, the minority carrier lifetime in the second semiconductor region is shortened, making it easier for holes to disappear within the second semiconductor region. This reduces the number of holes reaching the silicon carbide single crystal substrate. As a result, the expansion of stacking faults from basal plane dislocations in the silicon carbide single crystal substrate is reduced, thereby reducing the degradation of forward properties caused by stacking faults.

[0013] [2] In [1], the second semiconductor region may contain nitrogen and phosphorus. In this case, the minority carrier lifetime of the second semiconductor region tends to be shortened.

[0014] [3] In [1] or [2], the silicon carbide substrate is provided between the silicon carbide single crystal substrate in the first semiconductor region and the third semiconductor region, and has a fourth semiconductor region having the first conductivity type, and the effective concentration of impurities of the first conductivity type in the fourth semiconductor region may be lower than the effective concentration of the first conductivity type in the first semiconductor region. In this case, holes moving from the third semiconductor region toward the silicon carbide single crystal substrate tend to disappear within the fourth semiconductor region. Therefore, the number of holes reaching the silicon carbide single crystal substrate can be reduced. As a result, the expansion of stacking faults from basal plane dislocations in the silicon carbide single crystal substrate is reduced, and the deterioration of forward characteristics caused by stacking faults can be reduced.

[0015] [4] In [3], the fourth semiconductor region includes the first conductivity type impurity and the second conductivity type impurity, wherein the first conductivity type impurity is nitrogen or phosphorus, and the second conductivity type impurity may be boron or aluminum. In this case, the minority carrier lifetime of the fourth semiconductor region is shortened, so holes are more likely to disappear within the fourth semiconductor region.

[0016] [5] In [3] or [4], the thickness of the fourth semiconductor region may be 0.3 μm or more. In this case, the distance of the fourth semiconductor region through which the holes pass becomes longer, so the holes are more likely to disappear within the fourth semiconductor region.

[0017] [6] In any of [3] to [5], the fourth semiconductor region may be in contact with the third semiconductor region. In this case, it is easier to reduce the amount of holes that reach the silicon carbide single crystal substrate from the third semiconductor region.

[0018] [7] In any of [3] to [6], the fourth semiconductor region may be in contact with the silicon carbide single crystal substrate. In this case, it is easier to reduce the number of holes that reach the silicon carbide single crystal substrate from the third semiconductor region.

[0019] [8] In any of [1] to [7], the silicon carbide single crystal substrate may contain basal plane dislocations. In this case, the expansion of stacking faults from basal plane dislocations in the silicon carbide single crystal substrate can be reduced.

[0020] Embodiments of this disclosure relate to a so-called vertical MOS (metal oxide semiconductor) type field-effect transistor (FET) using silicon carbide. A MOS type FET is an example of a silicon carbide semiconductor device.

[0021] Figure 1 is a diagram showing a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0022] As shown in Figures 1 and 2, the silicon carbide semiconductor device 100 according to the embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

[0023] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The first main surface 1 is on the silicon carbide epitaxial layer 40, and the second main surface 2 is on the silicon carbide single crystal substrate 50. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are formed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity type (first conductivity type).

[0024] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. The first main surface 1 may also be the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The first main surface 1 may also be the (0001) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction is the direction along the X-axis. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0025] The silicon carbide substrate 10 includes a basal plane dislocation 101 and stacking faults 102. The basal plane dislocation 101 is located within the silicon carbide single crystal substrate 50. The basal plane dislocation 101 is located closer to the second principal plane 2 than the stacking faults 102. The basal plane dislocation 101 extends along the X-axis. There may be one or more basal plane dislocations 101. The stacking faults 102 are located, for example, within the buffer region 15. Part of the stacking faults 102 may be located within the drift region 11 or the field relaxation region 14. The stacking faults 102 include faults that have extended from the basal plane dislocation 101. There may be one or more stacking faults 102.

[0026] The silicon carbide epitaxial layer 40 has a drift region 11, a body region 12, a source region 13, an electric field relaxation region 14, a buffer region 15, a carrier killer region 16, and a contact region 18.

[0027] The drift region 11 contains nitrogen or phosphorus (P) and has an n-type conductivity. The drift region 11 may contain nitrogen and phosphorus. The drift region 11 is provided on a silicon carbide single crystal substrate 50. The drift region 11 is an example of a second semiconductor region.

[0028] The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity. The body region 12 is located on top of the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0029] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The source region 13 is located on top of the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. A portion of the first main surface 1 is located in the source region 13.

[0030] A plurality of gate trenches 5 are provided on the first main surface 1, defined by a side surface 3 and a bottom surface 4. Each gate trench 5 has a side surface 3 and a bottom surface 4. The gate trenches 5 extend, for example, along the X-axis. A plurality of gate trenches 5 are provided at regular intervals along the Y-axis. The side surface 3 penetrates the source region 13, the body region 12, and a part of the drift region 11, reaching the drift region 11. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the X-axis, the angle of the side surface 3 with respect to the plane containing the bottom surface 4 is, for example, 45° or more and 65° or less. In a cross-sectional view perpendicular to the X-axis, the angle of the side surface 3 with respect to the plane containing the bottom surface 4 may be 90°. The side surface 3 has, for example, a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0031] The contact region 18 contains p-type impurities such as aluminum and has a p-type conductivity. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. A portion of the first main surface 1 is located in the contact region 18. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the Y-axis. Between two adjacent gate trenches 5 along the Y-axis, the contact region 18 and the source region 13 may be alternately provided along the X-axis. Between two adjacent gate trenches 5 along the Y-axis, the contact region 18 may be provided intermittently along the X-axis.

[0032] Multiple gate trenches 5 may be arranged at regular intervals along the X-axis. If multiple gate trenches 5 are arranged at regular intervals along the X-axis, a portion of the contact area 18 may be located between adjacent gate trenches 5 along the X-axis. Multiple gate trenches 5 may be arranged in an array.

[0033] The electric field relaxation region 14 contains p-type impurities such as aluminum and has a p-type conductivity type. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 is between adjacent gate trenches 5 along the Y-axis. The electric field relaxation region 14 is away from the gate trench 5. The body region 12 is exposed on the side surface 3 of the gate trench 5. The electric field relaxation region 14 is farther from the gate trench 5 than the body region 12 along the Y-axis. The electric field relaxation region 14 is between the body region 12 and the second main surface 2 and contacts the body region 12. In a plan view perpendicular to the first main surface 1, the electric field relaxation region 14 may overlap with the contact region 18. The electric field relaxation region 14 may contact the body region 12 and the contact region 18. The electric field relaxation region 14 extends along the X-axis. A plurality of electric field relaxation regions 14 are arranged side by side at a certain interval along the Y-axis. The plurality of electric field relaxation regions 14 may be provided in a stripe shape. The lower end surface of the electric field relaxation region 14 is closer to the second main surface 2 than the bottom surface 4. The contact region 18, the body region 12, and the electric field relaxation region 14 are electrically connected to each other. The drift region 11 is exposed on the side surface 3 and contacts the body region 12 and the electric field relaxation region 14. The drift region 11 and the electric field relaxation region 14 may be arranged alternately along the Y-axis. The electric field relaxation region 14 is an example of a third semiconductor region.

[0034] The buffer region 15 contains n-type impurities such as nitrogen and has an n-type conductivity type. The buffer region 15 is between the silicon carbide single crystal substrate 50 and the drift region 11 and contacts the drift region 11. The buffer region 15 is between the silicon carbide single crystal substrate 50 and the electric field relaxation region 14 and contacts the electric field relaxation region 14. The buffer region 15 is an example of a first semiconductor region.

[0035] The carrier killer region 16 contains n-type impurities such as nitrogen and has an n-type conductivity. The carrier killer region 16 may contain two or more types of n-type impurities. The carrier killer region 16 may contain p-type impurities such as aluminum. The concentration of p-type impurities contained in the carrier killer region 16 is lower than the concentration of n-type impurities contained in the carrier killer region 16. The carrier killer region 16 may contain impurities that form deep energy levels, such as vanadium. The carrier killer region 16 is provided within the buffer region 15. In a plan view perpendicular to the first main surface 1, the carrier killer region 16 is located between adjacent gate trenches 5 along the Y-axis. The carrier killer region 16 is located between the field relaxation region 14 and the silicon carbide single crystal substrate 50. The carrier killer region 16 may be in contact with the field relaxation region 14. The carrier killer region 16 may be in contact with the silicon carbide single crystal substrate 50. The carrier killer region 16 overlaps the field relaxation region 14 in a plan view perpendicular to the first main surface 1. The carrier killer region 16 extends along the X-axis. Multiple carrier killer regions 16 are arranged at regular intervals along the Y-axis. Multiple carrier killer regions 16 may be arranged in a stripe pattern. The thickness of the carrier killer region 16 may be 0.3 μm or more. The width W1 of the carrier killer region 16 is, for example, the same as the width W2 of the field relaxation region 14. In this case, ion implantation for forming the carrier killer region 16 can be performed using the same mask as when forming the field relaxation region 14. The width W1 of the carrier killer region 16 may be wider than the width W2 of the field relaxation region 14. The width W1 of the carrier killer region 16 may be narrower than the width W2 of the field relaxation region 14. The carrier killer region 16 is an example of a fourth semiconductor region.

[0036] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contains, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12 and the drift region 11 at the side surface 3.

[0037] The gate electrode 82 is provided on the gate insulating film 81 so as to sandwich the gate insulating film 81 between the gate electrode 82 and the silicon carbide substrate 10. The gate electrode 82 includes, for example, polycrystalline silicon containing a conductive impurity. The gate electrode 82 is provided inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A part of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the X axis.

[0038] The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 includes, for example, silicon dioxide. The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 contacts the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface with a continuously changing curvature. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5. The upper surface of the interlayer insulating film 83 may be flat.

[0039] Contact holes 90 are formed in the interlayer insulating film 83 at regular intervals along the Y axis. The contact holes 90 are arranged such that the gate trench 5 is positioned between adjacent contact holes 90 along the Y axis. The contact holes 90 extend along the X axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83.

[0040] The source electrode 60 contacts the first main surface 1. The source electrode 60 includes a contact electrode 61 that contacts the source region 13 and the contact region 18, and a source wiring 62 that contacts the contact electrode 61. The contact electrode 61 includes, for example, nickel silicide (NiSi). The contact electrode 61 may include titanium (Ti), aluminum, and silicon. The contact electrode 61 makes an ohmic contact with the source region 13 and the contact region 18.

[0041] The source wiring 62 covers the upper surface and the side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 contains, for example, aluminum.

[0042] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 contains, for example, nickel silicide. The drain electrode 70 may contain titanium, aluminum, and silicon. The drain electrode 70 makes an ohmic contact with the silicon carbide single crystal substrate 50.

[0043] The effective concentration of the p-type impurity in the contact region 18 may be higher than the effective concentration of the p-type impurity in the body region 12. For example, the effective concentration of the p-type impurity in the contact region 18 is, for example, 1×10 －３ , －３ , , １８ , １６ ,

[0045] cm －３ or more and 1×10 ２０ cm －３ or less, and the effective concentration of the p-type impurity in the body region 12 is 5×10 １７ cm －３ or more and 1×10 １８ cm －３ or less.

[0044] The effective concentration of the n-type impurity in the source region 13 may be higher than the effective concentration of the p-type impurity in the body region 12. The effective concentration of the n-type impurity in the source region 13 is, for example, 1×10 １９ cm －３ or so. The effective concentration of the n-type impurity in the drift region 11 is, for example, 1×10 １６ cm －３ or more and 5×10 １７ [[ID=3?]] cm －３ or less.

[0045] The effective concentration of the n-type impurity in the buffer region 15 may be higher than the effective concentration of the n-type impurity in the drift region 11. The effective concentration of the n-type impurity in the buffer region 15 is, for example, 1×10 １６ cm －３ or more and 1×10 １８ cm－３ The following applies:

[0046] The effective concentration of n-type impurities in the carrier killer region 16 may be lower than the effective concentration of n-type impurities in the buffer region 15. For example, the effective concentration of n-type impurities in the carrier killer region 16 may be 5 × 10⁻⁶. １５ cm －３ The above 5 x 10 １７ cm －３ The following applies:

[0047] Figure 3 shows the concentration distribution of impurities in the direction along arrow III in Figure 2. In Figure 3, depth D0 is the position of the upper surface of the electric field relaxation region 14, depth D1 is the position of the interface between the electric field relaxation region 14 and the carrier killer region 16, and depth D2 is the position of the interface between the carrier killer region 16 and the silicon carbide single crystal substrate 50. In Figure 3, the thick solid line shows the aluminum concentration, the thin solid line shows the nitrogen concentration, and the dashed line shows a concentration of 1 / 10 of the nitrogen concentration.

[0048] As shown in Figure 3, the carrier killer region 16 has a nitrogen concentration higher than the aluminum concentration. The aluminum concentration in the carrier killer region 16 may also be higher than 1 / 10 of the nitrogen concentration.

[0049] In this disclosure, the effective concentration of the first conductivity type impurity is the concentration obtained by subtracting the concentration of the second conductivity type impurity from the concentration of the first conductivity type impurity. The effective concentration of the second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentration can be measured, for example, using a scanning capacitance microscope (SCM). The effective concentration of impurities contained in each region is the average value of the effective concentrations of impurities contained in that region.

[0050] In the silicon carbide semiconductor device 100, when a hole reaches the silicon carbide single crystal substrate 50 during operation, a stacking fault 102 is generated from a basal plane dislocation 101 on the silicon carbide single crystal substrate 50. If the drift region 11 contains nitrogen or phosphorus, the minority carrier lifetime of the drift region 11 is shortened, making it easier for holes to disappear within the drift region 11. Therefore, the number of holes reaching the silicon carbide single crystal substrate 50 can be reduced. As a result, the expansion of stacking faults 102 from basal plane dislocations 101 on the silicon carbide single crystal substrate 50 is reduced, and the degradation of forward characteristics caused by stacking faults 102 can be reduced.

[0051] When the drift region 11 contains nitrogen and phosphorus, the minority carrier lifetime of the drift region 11 tends to be shortened.

[0052] When a carrier killer region 16 is provided between the silicon carbide single crystal substrate 50 and the electric field relaxation region 14 within the buffer region 15, holes moving from the electric field relaxation region 14 toward the silicon carbide single crystal substrate 50 are more likely to disappear within the carrier killer region 16. Therefore, the number of holes reaching the silicon carbide single crystal substrate 50 can be reduced. As a result, the expansion of stacking faults 102 from basal plane dislocations 101 in the silicon carbide single crystal substrate 50 is reduced, and the deterioration of forward characteristics caused by stacking faults 102 can be reduced.

[0053] When the carrier killer region 16 contains p-type impurities, the minority carrier lifetime of the carrier killer region 16 is shortened, making it easier for holes to disappear within the carrier killer region 16.

[0054] When the thickness of the carrier killer region 16 is 0.3 μm or more, the distance that holes pass through the carrier killer region 16 becomes longer, making it easier for holes to disappear within the carrier killer region 16.

[0055] When the carrier killer region 16 is in contact with the electric field relaxation region 14, it is easier to reduce the number of holes that reach the silicon carbide single crystal substrate 50 from the electric field relaxation region 14.

[0056] When the carrier killer region 16 is in contact with the silicon carbide single crystal substrate 50, it is easier to reduce the number of holes that reach the silicon carbide single crystal substrate 50 from the electric field relaxation region 14.

[0057] If the silicon carbide single crystal substrate 50 contains basal plane dislocations 101, the expansion of stacking faults 102 from the basal plane dislocations 101 in the silicon carbide single crystal substrate 50 can be reduced.

[0058] Next, a method for manufacturing the silicon carbide semiconductor device 100 will be described. Figures 4 to 10 are cross-sectional views showing a method for manufacturing the silicon carbide semiconductor device 100 according to an embodiment.

[0059] First, a silicon carbide single crystal substrate 50 is prepared as shown in Figure 4.

[0060] Next, as shown in Figure 5, a buffer region 15 and a silicon carbide epitaxial layer 41 are formed on the silicon carbide single crystal substrate 50 in this order. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type conductivity. The buffer region 15 and the silicon carbide epitaxial layer 41 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0061] Next, as shown in Figure 6, ion implantation is performed into the silicon carbide epitaxial layer 41 to form the silicon carbide epitaxial layer 42. In ion implantation, n-type impurities such as phosphorus are implanted.

[0062] Next, as shown in Figure 7, ion implantation is performed into the silicon carbide epitaxial layer 42 to form an implantation region 43. In the ion implantation to form the implantation region 43, p-type impurities such as aluminum are implanted. Next, ion implantation is performed into the buffer region 15 to form a carrier killer region 16. In the ion implantation to form the carrier killer region 16, p-type impurities such as aluminum are implanted. Channeling ion implantation may be used in the ion implantation to form the carrier killer region 16. Using channeling ion implantation makes it easier to implant ions at deeper locations.

[0063] Next, as shown in Figure 8, ion implantation is performed into the silicon carbide epitaxial layer 42 to form a body region 12, a source region 13, and a contact region 18. In the ion implantation to form the body region 12 and the contact region 18, p-type impurities such as aluminum are implanted. In the ion implantation to form the source region 13, n-type impurities such as phosphorus are implanted. Of the remainder of the silicon carbide epitaxial layer 42, the implanted region 43 becomes the electric field relaxation region 14, and the region other than the implanted region 43 becomes the drift region 11. In this way, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained. Next, activation annealing is performed to activate the impurity ions implanted in the silicon carbide substrate 10. The activation annealing temperature may be between 1500°C and 1900°C, for example, around 1700°C. The activation annealing time is, for example, around 30 minutes. The atmosphere for activation annealing may be an inert gas atmosphere, such as an argon (Ar) atmosphere.

[0064] Next, as shown in Figure 9, a gate trench 5 is formed on the first main surface 1. Then, a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 are formed. Next, contact holes 90 are formed in the gate insulating film 81 and the interlayer insulating film 83.

[0065] Next, as shown in Figure 10, the contact electrode 61, source wiring 62, and drain electrode 70 are formed. In this way, the silicon carbide semiconductor device 100 according to the embodiment can be manufactured.

[0066] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims.

[0067] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region (second semiconductor region) 12 Body region 13 Source region 14 Field relaxation region (third semiconductor region) 15 Buffer region (first semiconductor region) 16 Carrier killer region (fourth semiconductor region) 18 Contact region 40 Silicon carbide epitaxial layer 41 Silicon carbide epitaxial layer 42 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 90 Contact hole 100 Silicon carbide semiconductor device 101 Basal plane dislocation 102 Stacking fault D0 Depth D1 Depth D2 Depth W1 Width W2 Width

Claims

1. A silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface, wherein the silicon carbide substrate comprises: a silicon carbide single crystal substrate having a first conductivity type; a first semiconductor region provided on the silicon carbide single crystal substrate and having the first conductivity type; a second semiconductor region provided on the first semiconductor region and having the first conductivity type; and a third semiconductor region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, wherein the second semiconductor region and the third semiconductor region are alternately arranged along a first axis parallel to the first main surface, the third semiconductor region extends along a second axis parallel to the first main surface and perpendicular to the first axis, and the second semiconductor region contains nitrogen or phosphorus.

2. The silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region comprises nitrogen and phosphorus.

3. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the silicon carbide substrate is provided between the silicon carbide single crystal substrate and the third semiconductor region within the first semiconductor region and has a fourth semiconductor region having the first conductivity type, and the effective concentration of the impurity of the first conductivity type in the fourth semiconductor region is lower than the effective concentration of the first conductivity type in the first semiconductor region.

4. The silicon carbide semiconductor device according to claim 3, wherein the fourth semiconductor region comprises an impurity of the first conductivity type and an impurity of the second conductivity type, the impurity of the first conductivity type being nitrogen or phosphorus, and the impurity of the second conductivity type being boron or aluminum.

5. The silicon carbide semiconductor device according to claim 3 or claim 4, wherein the thickness of the fourth semiconductor region is 0.3 μm or more.

6. The silicon carbide semiconductor device according to any one of claims 3 to 5, wherein the fourth semiconductor region is in contact with the third semiconductor region.

7. The silicon carbide semiconductor device according to any one of claims 3 to 6, wherein the fourth semiconductor region is in contact with the silicon carbide single crystal substrate.

8. The silicon carbide single crystal substrate includes basal plane dislocations, as described in any one of claims 1 to 7, the silicon carbide semiconductor device according to claim 1 to 7.

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