Light detection device

Abstract

[Problem] To provide a light detection device that can suppress a dark current that is generated due to various factors. [Solution] This light detection device comprises: a photoelectric conversion region that stores a charge corresponding to the quantity of incident light; a first transistor that has a first gate controlling whether to transfer the charge; a floating diffusion region that holds the charge which was transferred via the first transistor; a second transistor that is positioned adjacent to the first transistor and has a second gate; a region separation layer that is positioned between the first gate and the second gate and extends in the thickness direction of the photoelectric conversion region; and a first insulation layer that is positioned above the region separation layer and has a first surface facing a second gate-side side surface of the first gate, a second surface facing a first gate-side side surface of the second gate, a third surface in contact with an upper surface of the first gate, and a fourth surface in contact with an upper surface of the second gate.

Description

Optical detection device

[0001] The present disclosure relates to an optical detection device.

[0002] With the miniaturization of image sensors, the dark current may increase, and various techniques for reducing the dark current have been proposed (see Patent Documents 1 and 2).

[0003] Japanese Patent Application Laid-Open No. 2016-92203, Japanese Patent Application Laid-Open No. 2013-21352

[0004] When performing etch-back using anisotropic dry etching when forming the sidewalls of the gates of pixel transistors, the surface of the semiconductor substrate may be damaged by the etch-back, resulting in crystal defects and an increase in dark current. Therefore, in Patent Documents 1 and 2, sidewalls are not provided for the gates of pixel transistors arranged above the photoelectric conversion region to suppress the generation of dark current.

[0005] The factors causing the generation of dark current are not limited to the above-described etch-back. With miniaturization, the width of the element isolation region that separates pixels becomes narrow, and pixel transistors and transfer transistors are arranged in close proximity. The PN junction region formed near the interface between the element isolation region and the photoelectric conversion region may become depleted by capacitive coupling when the gate of the nearby pixel transistor becomes high potential, resulting in an increase in dark current.

[0006] In addition, in a pixel configuration where a single floating diffusion region (floating diffusion) is shared by a plurality of pixels, with miniaturization, a plurality of transfer transistors are arranged in close proximity around the floating diffusion region. As a result, when transferring the accumulated charges of a plurality of photoelectric conversion regions sharing a single floating diffusion region to the floating diffusion region via the corresponding transfer transistors, the electric field between the floating diffusion region and each transfer transistor becomes large, resulting in an increase in dark current. Also, by arranging a plurality of transfer transistors in close proximity, there is a risk of an increase in dark current due to GIDL (Gate Induced Drain Leakage current).

[0007] Therefore, the present disclosure provides an optical detection device capable of suppressing dark current generated by various factors.

[0008] To solve the above problems, the present disclosure provides a photodetector comprising: a photoelectric conversion region that stores a charge corresponding to the amount of incident light; a first transistor having a first gate that controls whether or not to transfer the charge; a floating diffusion region that holds the charge transferred via the first transistor; a second transistor having a second gate and arranged adjacent to the first transistor; a region separation layer arranged between the first gate and the second gate and extending in the depth direction of the photoelectric conversion region; and a first insulating layer arranged above the region separation layer and having a first surface facing the side of the first gate on the second gate side, a second surface facing the side of the second gate on the first gate side, a third surface in contact with the upper surface of the first gate, and a fourth surface in contact with the upper surface of the second gate.

[0009] The first insulating layer may be arranged to cover the region between the first gate and the second gate, the upper surface of the first gate, and the upper surface of the second gate.

[0010] The device comprises a third transistor having a third gate positioned at a distance from the first transistor that is greater than the distance from the second transistor, and which controls the reading of the charge held in the floating diffusion region; and a second insulating layer having a curved cross-section at a portion facing the side surface of the third gate, wherein the cross-sectional shape of the first insulating layer at the portion facing the side surface of the first gate and the side surface of the second gate may be rectangular.

[0011] The first transistor is a transfer transistor, and the second and third transistors may be pixel transistors.

[0012] The second transistor may also be an amplifying transistor.

[0013] A diffusion region may be provided along the end face of the region separation layer on the first gate side, where the impurity concentration is higher than that of the region separation layer.

[0014] The aforementioned diffusion region may be a P-type diffusion region.

[0015] The second gate is positioned to cover a portion of the region separation layer, and the area near the end face of the region separation layer on the second gate side may have the same impurity concentration as the region separation layer.

[0016] The diffusion region may suppress the dark current while the charge is being accumulated in the photoelectric conversion region.

[0017] The diffusion region may suppress the dark current that occurs when a high potential is applied to the second gate while the charge is being accumulated in the photoelectric conversion region.

[0018] The diffusion region may mitigate depletion that occurs when a high potential is applied to the second gate while the charge is accumulating in the photoelectric conversion region.

[0019] A first gate group having a plurality of the first gates arranged along a first direction, and a second gate group having a plurality of the second gates arranged along the first direction, wherein the first gate group and the second gate group are arranged at a distance apart in a second direction intersecting the first direction, and the distance between the first gate group and the second gate group may be shorter than the distance between two adjacent first gates in the first direction and shorter than the distance between two adjacent second gates in the first direction.

[0020] The floating diffusion region is shared by a plurality of photoelectric conversion regions and a plurality of transfer transistors, and the plurality of transfer transistors include a first transistor and a second transistor, and the second transistor may control whether or not to transfer charge accumulated in a photoelectric conversion region different from the photoelectric conversion region to which the first transistor transfers to the floating diffusion region.

[0021] The system may include a diffusion region located around the floating diffusion region between the first gate and the second gate, with a higher impurity concentration than the region separation layer.

[0022] The aforementioned diffusion region may be an N-type diffusion region or a P-type diffusion region.

[0023] The diffusion region may relax the electric field of the floating diffusion region when the charge has been transferred from the plurality of photoelectric conversion regions to the floating diffusion region.

[0024] The diffusion region may reduce the GIDL (Gate Induced Drain Leakage current) of the first and second transistors.

[0025] A block diagram showing the schematic configuration of the photodetector according to the first embodiment. A circuit diagram showing an example of a pixel and pixel circuit according to the first embodiment. A plan view of a part of the pixel array section. A cross-sectional view in the direction of line A-A' in Figure 3. A process diagram showing a part of the process sequence of the photodetector according to the first embodiment. A process diagram following Figure 5A. A process diagram following Figure 5B. A process diagram following Figure 5C. A process diagram following Figure 5D. A process diagram following Figure 5E. A process diagram following Figure 5F. A process diagram showing a part of the process sequence of the photodetector according to one modified example of the first embodiment. A process diagram following Figure 5A. A process diagram following Figure 5B. A process diagram following Figure 5C. A process diagram following Figure 5D. A cross-sectional view showing the impurity ion implantation process in a photodetector according to one comparative example. A plan view showing the arrangement of the four transfer gates of the photodetector according to the second embodiment. A cross-sectional view in the direction of line A-A' in Figure 8. A cross-sectional view in the direction of line B-B' in Figure 8. A cross-sectional view of one modified example in the direction of line B-B' in Figure 8. A block diagram showing an example of the schematic configuration of the vehicle control system. An explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0026] The embodiments of the photodetector will be described below with reference to the drawings. While the main components of the photodetector will be described below, there may be components and functions not shown or described in the drawings. The following description does not exclude any components or functions not shown or described.

[0027] (First Embodiment) Figure 1 is a block diagram showing the schematic configuration of a photodetector according to the first embodiment. The photodetector 1 in Figure 1 is composed of a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section around it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like. The photodetector 1 in Figure 1 may be arranged on a single substrate, or it may be arranged on multiple substrates. When it is arranged on multiple substrates, miniaturization can be achieved by creating a laminated structure in which each substrate is joined to the others by Cu-Cu junctions, vias, or bumps.

[0028] Pixel 2 has a photodiode PD, which is a photoelectric conversion element, and a transfer transistor TR. Pixel 2 is connected to a pixel circuit not shown in Figure 1. The pixel circuit has multiple pixel transistors, etc. These multiple pixel transistors are composed of multiple MOS (Metal Oxide Semiconductor) transistors, such as a selection transistor, a reset transistor, and an amplification transistor.

[0029] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the light detection device 1. In other words, based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0030] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive line L1, supplies a pulse signal to the selected pixel drive line L1 to drive the pixel 2, and drives the pixel 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a pixel signal based on the signal charge generated in the photodiode PD of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line VSL.

[0031] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and analog-to-digital (AD) conversion to remove pixel-specific fixed pattern noise.

[0032] The horizontal drive circuit 6, for example, has a shift register and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line L2.

[0033] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line L2 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 9 exchanges signals with the outside.

[0034] The light detection device 1 configured as described above is a CMOS (Complementary Metal Oxide Semiconductor) image sensor called a column AD type, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each pixel row.

[0035] The light detection device 1 is a back-illuminated type that directs light onto the back side of the substrate. Pixel transistors or logic circuits are arranged on the front side of the substrate.

[0036] Figure 2 is a circuit diagram showing an example of a pixel 2 and pixel circuit 11 according to the first embodiment, showing an example in which four pixels 2 share one pixel circuit 11. Here, "sharing" means that the four pixels 10 are electrically connected to a common pixel circuit 11, that is, the outputs of the four pixels 10 are input to the common pixel circuit 11.

[0037] Each pixel 10 has a common configuration. Specifically, each pixel 10 has, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. These pixels 10 share a floating diffusion region FD electrically connected to each transfer transistor TR. Here, "shared" means that each individual photodiode PD of each pixel 10 is electrically connected to the floating diffusion region FD. The photodiode PD, transfer transistor TR, floating diffusion region FD, etc., are provided, for example, on the same substrate.

[0038] A photodiode PD performs photoelectric conversion to generate an electric charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of a transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). A photodiode PD is an example of a photoelectric conversion element.

[0039] The drain of the transfer transistor TR is electrically connected to the floating diffusion region FD, and the transfer gate TG of the transfer transistor TR is electrically connected to the pixel drive line L1 (see Figure 1). The transfer transistor TR is, for example, a CMOS transistor.

[0040] The floating diffusion region FD is electrically connected to four transfer transistors TR in four pixels 2. The floating diffusion region FD temporarily holds the charge output from the photodiode PD via the transfer transistors TR. The floating diffusion region FD is an example of a floating diffusion layer.

[0041] The pixel circuit 11 has, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and an FD transfer transistor FDG. The reset transistor RST, the selection transistor SEL, the amplification transistor AMP, and the FD transfer transistor FDG may be arranged on the same substrate as the pixel 2, or may be arranged on different substrates. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the FD transfer transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the FD transfer transistor FDG may be omitted as necessary.

[0042] The source of the FD transfer transistor FDG (the input terminal of the pixel circuit 11) is electrically connected to the floating diffusion region FD, and the drain of the FD transfer transistor FDG is electrically connected to the source of the reset transistor RST. The gate of the FD transfer transistor FDG is electrically connected to the pixel drive line L1 (see FIG. 1).

[0043] The drain of the reset transistor RST is electrically connected to the power supply line VDD. The gate of the reset transistor RST is electrically connected to the pixel drive line L1 (see FIG. 1).

[0044] The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the drain of the amplification transistor AMP is electrically connected to the power supply line VDD. The gate of the amplification transistor AMP is electrically connected to the source of the FD transfer transistor FDG.

[0045] The drain of the selection transistor SEL (the output terminal of the pixel circuit 11) is electrically connected to the vertical signal line VSL (VSL in FIG. 2), and the gate of the selection transistor SEL is electrically connected to the pixel drive line L1 (see FIG. 1).

[0046] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion region FD.

[0047] The reset transistor RST resets the potential of the floating diffusion region FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion region FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 11.

[0048] The amplification transistor (AMP) generates a pixel signal with a voltage corresponding to the level of charge held in the floating diffusion region (FD). The amplification transistor (AMP) constitutes a source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated by the photodiode (PD).

[0049] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to that potential to the column signal processing circuit 5 (see Figure 1) via the vertical signal line VSL.

[0050] The FD transfer transistor FDG is used to switch the conversion efficiency. Generally, when shooting in dark places, the pixel signal is small. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion region FD (hereinafter referred to as FD capacitance) is large, the V obtained when converted to voltage by the amplification transistor AMP will be small. On the other hand, in bright places, the pixel signal is large, so if the FD capacitance is not large enough, the floating diffusion region FD cannot accept the charge of the photodiode PD. Furthermore, the FD capacitance needs to be large so that the V obtained when converted to voltage by the amplification transistor AMP does not become too large (in other words, to keep it small).

[0051] In other words, when the FD transfer transistor FDG is turned on, the gate capacitance increases by the amount of the FD transfer transistor FDG, so the overall FD capacitance increases. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance decreases. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance can be made variable and the conversion efficiency can be switched.

[0052] Figure 3 is a plan view of a part of the pixel array 3. As shown in Figure 3, two transfer transistor groups 12G, each consisting of multiple transfer transistors TR arranged along the first direction X, are positioned close to each other in the second direction Y. In addition, two pixel transistor groups 13G, each including a selection transistor SEL, an amplification transistor AMP, a reset transistor RST, and an FD transfer transistor FDG, are positioned close to the transfer transistor groups 12G in the second direction Y. The distance between the transfer transistor groups 12G and the pixel transistor groups 13G in the second direction Y is shorter than the distance between two adjacent transfer gates TG in the first direction X, and shorter than the distance between the gates of two adjacent pixel transistors 13 in the first direction X.

[0053] The four dashed boxes 14 shown in Figure 3 represent four photoelectric conversion regions 15 that share a single pixel circuit 11. One transfer transistor TR is positioned in association with each photoelectric conversion region 15.

[0054] Figure 4 is a cross-sectional view taken along the line A-A' in Figure 3. As shown in Figure 4, the amplification transistor AMP and the transfer transistor TR are arranged with an element isolation region 16 in between. In this specification, the element isolation region 16 may be referred to as the region isolation region. Below the gate of the transfer transistor TR (hereinafter referred to as the transfer gate TG) is a photoelectric conversion region 15. The photoelectric conversion region 15 is an N-type semiconductor region. Below the gate of the amplification transistor AMP (hereinafter referred to as the AMP gate) is a P-type semiconductor region 17.

[0055] More specifically, the element isolation region 16 is located between the photoelectric conversion region 15 below the transfer gate TG and the P-type semiconductor region 17 below the AMP gate AMPG. The element isolation region 16 is formed by filling the interior of a trench extending in the depth direction from the surface of the semiconductor substrate in which the photoelectric conversion region 15 and the P-type semiconductor region 17 are formed with multiple materials. For example, the element isolation region 16 has a layered structure of a P-type diffusion region 18, a first insulating region 19, and a second insulating region 20. A P-type high-impurity region 21 is provided on the surface side of the P-type diffusion region 18, as will be described later. The P-type diffusion region 18 and the high-impurity region 21 contain P-type impurity ions such as boron. The first insulating region 19 is, for example, SiO２ The second insulating region 20 is formed of an insulating material such as SiN. The second insulating region 20 may also be formed of a metallic material such as polysilicon or tungsten, in which case it becomes a conductive region.

[0056] As shown in Figure 4, the AMP gate AMPG is positioned to cover a portion of the upper surface of the element isolation region 16. The transfer gate TG is positioned above the element isolation region 16 along its end face. The high-impurity region 21 described above is positioned along the end face of the element isolation region 16 on the transfer gate TG side. No high-impurity region is provided on the end face of the element isolation region 16 on the AMP gate AMPG side.

[0057] Near the interface between the element isolation region 16 and the photoelectric conversion region 15, a PN junction region 23 is formed by the aforementioned P-type diffusion region 18 and the N-type diffusion region 22 on the photoelectric conversion region 15 side. While the photoelectric conversion region 15 is accumulating charge due to incident light, if the gate of the pixel transistor 13 located near the transfer transistor TR (for example, the AMP gate AMPG of the amplification transistor AMP) becomes high potential, the potential of the N-type diffusion region 22 near the PN junction region 23 rises due to capacitive coupling, and the PN junction region 23 becomes depleted. When the PN junction region 23 becomes depleted, the amount of P-type impurity ions in the P-type diffusion region 18 decreases, which may increase the dark current. To suppress the dark current, it is effective to increase the amount of P-type impurity ions in the P-type diffusion region 18.

[0058] Therefore, in this embodiment, P-type impurity ions are implanted into at least the surface side of the P-type diffusion region 18 formed near the interface between the element isolation region 16 and the photoelectric conversion region 15 to form a high-impurity region 21. As a result, even if the gate of the pixel transistor 13 located near the transfer transistor TR becomes high potential while the photoelectric conversion region 15 is accumulating charge due to photoelectric conversion, the PN junction region 23 formed near the interface between the element isolation region 16 and the photoelectric conversion region 15 will not become depleted, and dark current can be suppressed.

[0059] In the photodetector 1 according to the first embodiment, no curved sidewall insulating layer is formed on the side surface of the transfer gate TG and the side surface of the AMP gate AMPG. Instead, a first insulating layer 30 is provided, having a first surface facing the side surface of the transfer gate TG, a second surface facing the side surface of the AMP gate AMPG, a third surface facing the upper surface of the transfer gate TG, and a fourth surface facing the upper surface of the AMP gate AMPG. This first insulating layer 30 is made of, for example, SiO ２ It is formed of insulating material such as the above. In this way, the first insulating layer 30 is arranged to cover the region between the transfer gate TG and the AMP gate AMPG, and the upper surface of the two transfer gates TG.

[0060] Thus, in the photodetector 1 according to the first embodiment, since there is no sidewall insulating layer on the side surface of the transfer gate TG and the side surface of the gate of the pixel transistor 13 (for example, the AMP gate AMPG), when impurity ions are injected from above the element isolation region 16 and the transfer transistor TR, the impurity ions can be injected into the P-type diffusion region 18, and the high-impurity region 21 described above can be formed. On the other hand, a sidewall insulating layer is provided on the gate of the pixel transistor 13 that is not located near the transfer gate TG. Therefore, the cross-sectional shape between the gate of the pixel transistor 13 located near the transfer gate TG and the transfer gate TG is rectangular, while the cross-sectional shape of the gate sidewall of the pixel transistor 13 that is not located near the transfer gate TG is curved.

[0061] Although not shown in Figure 4, a pixel separation region, a color filter, and an on-chip lens are arranged below Figure 4. Light is incident through the on-chip lens. Thus, the light detection device 1 according to the first embodiment is a back-illuminated image sensor. Also, although not shown in Figure 4, a wiring layer is arranged above Figure 4, and another substrate on which logic circuits are arranged may be bonded thereto by Cu-Cu junctions or the like.

[0062] Figures 5A to 5G are process diagrams showing a partial process sequence of the photodetector 1 according to the first embodiment. Figure 5A shows a state in which an element isolation region 16 is formed between the photoelectric conversion region 15 and the P-type semiconductor region 17, a transfer gate TG is formed above the photoelectric conversion region 15 via an insulating layer 24, and an AMP gate AMPG is formed above the P-type semiconductor region 17 via an insulating layer 24. Following the process in Figure 5A, as shown in Figure 5B, an insulating layer 25 is formed over the entire upper surface, for example, using a sputtering apparatus. This insulating layer 25 is made of, for example, SiO or SiO ２ And so on.

[0063] Next, as shown in Figure 5C, an insulating layer 26 is formed over the entire upper surface. This insulating layer 26 is made of, for example, SiN.

[0064] Next, the insulating layer 26 is etched back by dry etching or the like to form a sidewall insulating layer 27 on the sides of the transfer gate TG and the AMP gate AMPG. The material of this sidewall insulating layer 27 is, for example, SiN.

[0065] Next, a process to form ohmic contacts and the like is carried out, but this is omitted from the illustration.

[0066] Next, as shown in Figure 5E, the transfer gate TG and the AMP gate AMPG are covered with resist 28. At this time, the area above the side wall insulating layer 27 is not covered with resist 28.

[0067] Next, as shown in Figure 5F, the resist 28 is used as a mask to remove the sidewall insulating layer 27 by etching, and then the resist 28 is removed.

[0068] Next, as shown in Figure 5G, the resist 29 is used to cover only the area above the gate of the pixel transistor 13 adjacent to the transfer transistor TR, and impurity ions are implanted from above the transfer gate TG and the element isolation region 16 using the resist 29 as a mask. The impurity ions to be implanted are P-type. As a result, a high-impurity region 21 is formed on the surface side of the P-type diffusion region 18 provided on the side surface of the element isolation region 16.

[0069] Figures 6A to 6E are process diagrams showing a partial sequence of steps for a photodetector 1 according to one modified example of the first embodiment. Figure 6A has the same cross-sectional structure as Figure 5A. Next, as shown in Figure 6B, an insulating layer 25 is formed on the upper surface, for example, using a sputtering apparatus. At this time, the insulating layer 25 is formed so as to cover the side surface of the transfer gate TG, the side surface of the AMP gate AMPG, the upper surface of the transfer gate TG, and the upper surface of the AMP gate AMPG. In one modified example, there is no step of forming a side wall insulating layer 27 on the side surfaces of the transfer gate TG and the AMP gate AMPG.

[0070] Next, as shown in Figure 6C, the transfer gate TG and the AMP gate AMPG are covered with resist 28. At this time, the insulating layer 25 between the transfer gate TG and the AMP gate AMPG is not covered with resist 28.

[0071] Next, as shown in Figure 6D, the insulating layer between the transfer gate TG and the AMP gate AMPG is removed by etching using the resist 28 as a mask, and then the resist 28 is removed.

[0072] Next, as shown in Figure 6E, only the area above the gate of the pixel transistor 13 adjacent to the transfer gate TG is covered with resist 29, and P-type impurity ions are implanted from above the element isolation region 16 and the transfer gate TG. As a result, a high-impurity region 21 is formed on the surface side of the P-type diffusion region 18.

[0073] Figure 7 is a cross-sectional view showing the impurity ion implantation process in a photodetector 1 according to one comparative example. In the photodetector 1 according to one comparative example, sidewall insulating layers 27 are formed on each side surface of the transfer gate TG and the AMP gate AMPG, and impurity ions are implanted from above the element isolation region 16 and the transfer gate TG with the top of the AMP gate AMPG covered with a resist. In this case, because the sidewall insulating layer 27 is formed on the side surface of the transfer gate TG, it is not possible to implant impurity ions near the interface between the element isolation region 16 and the photoelectric conversion region 15. Therefore, it is not possible to form a high-impurity region 21 on the surface side of the P-type diffusion region 18 located near the interface between the element isolation region 16 and the photoelectric conversion region 15. As a result, when the gate of the pixel transistor 13 adjacent to the transfer transistor TR becomes high potential while charge is accumulating in the photoelectric conversion region 15, the PN junction region 23 formed near the interface between the element isolation region 16 and the photoelectric conversion region 15 becomes depleted, and the dark current increases.

[0074] Thus, in the first embodiment, after removing the gate of the pixel transistor 13 adjacent to the transfer gate TG (for example, the AMP gate AMPG) and the side wall insulating layer 27 of the side of the transfer gate TG, impurity ions are injected from above the element isolation region 16 and the transfer gate TG, thereby forming a high-impurity region 21 on the surface side of the P-type diffusion region 18 located near the interface between the element isolation region 16 and the photoelectric conversion region 15.

[0075] As a result, even if the gate of the pixel transistor 13 adjacent to the transfer gate TG becomes high potential during the period when charge is accumulating in the photoelectric conversion region 15, and the potential of the N-type semiconductor region within the photoelectric conversion region 15 near the interface between the element isolation region 16 and the photoelectric conversion region 15 rises due to capacitive coupling, there is no risk of depletion of the PN junction region 23 formed near the P-type diffusion region 18, and dark current can be suppressed.

[0076] (Second Embodiment) The photodetector 1 according to the second embodiment has a block configuration similar to that in Figure 1 and a pixel configuration similar to that in Figure 2. That is, in the photodetector 1 according to the second embodiment, four pixels 10 share one pixel circuit 11. The accumulated charge of the four pixels 10 is transferred to a floating diffusion region FD via four corresponding transfer transistors TR.

[0077] Figure 8 is a plan view showing the arrangement of four transfer gates TG in the photodetector 1 according to the second embodiment. The four transfer gates TG in the four pixels 10 that share one pixel circuit 11 are arranged in pairs in the first direction X and the second direction Y. A floating diffusion region FD is located at the center of the four transfer gates TG. A diffusion layer 31 and the gates of the pixel transistors 13 are arranged around the transfer gates.

[0078] Figure 9A is a cross-sectional view in the direction of line A-A' in Figure 8, Figure 9B is a cross-sectional view in the direction of line B-B' in Figure 8, and Figure 9C is a cross-sectional view relating to a modified example in the direction of line B-B' in Figure 8. Below the floating diffusion region FD located between the two transfer gates TG, an element isolation region 16 is located. The sides of the two transfer gates TG do not have sidewall insulating layers; instead, a first insulating layer 30 is provided, having first and second surfaces facing the sides of the two transfer gates TG and third and fourth surfaces in contact with the upper surfaces of the two transfer gates TG. In this way, the first insulating layer 30 is arranged to cover the region between the two transfer gates TG and the upper surfaces of the two transfer gates TG.

[0079] Impurity ions are implanted in the region between the sides of the two transfer gates TG to form an LDD (Lightly Doped Drain) region 21a. The LDD region 21a is, for example, an N-type impurity region. The P-type diffusion region 18 and the first insulating region 19 may be arranged at the same height as the element isolation region 16 in Figure 9A, as shown in Figure 9B, or they may be arranged in a direction inclined toward the light incident surface from the upper surface of the element isolation region 16 in Figure 9A, as shown in Figure 9C.

[0080] When multiple pixels 10 share a single floating diffusion region FD, the charge converted photoelectrically by each pixel 10 is transferred to the floating diffusion region FD via the corresponding transfer transistor TR. A P-type semiconductor region 17 is provided around the floating diffusion region FD. The floating diffusion region FD is an N-type semiconductor region, and a PN junction region 23 is provided near the interface between the floating diffusion region FD and the P-type semiconductor region 17.

[0081] If the surrounding electric field of the floating diffusion region FD is high, the junction leakage current increases during charge transfer from the photoelectric conversion region (PD) 15 to the floating diffusion region FD, making it easier for highly visible defects to occur at the pixel level that shares the floating diffusion region FD.

[0082] Therefore, in this embodiment, N-type impurity ions are implanted around the floating diffusion region FD between two adjacent transfer gates TG. This forms an N-type LDD region 21a between the two adjacent transfer gates TG, and the electric field near the floating diffusion region FD can be relaxed when charge is transferred from each pixel 2 to the floating diffusion region FD. In addition, it may be possible to implant P-type impurity ions instead of N-type impurity ions to suppress the dark current due to GIDL between the transfer gates TG.

[0083] In the second embodiment, similar to Figure 5, a sidewall insulating layer 27 is formed on the sides of the two transfer gates TG by etch-back, then the sidewall insulating layer 27 is removed, and then the two transfer gates TG are covered with resist, and impurity ions are implanted around the floating diffusion region FD between the two transfer gates TG to form the LDD region 21a. Alternatively, similar to Figure 6, an insulating layer 25 may be formed between the two transfer gates TG, then this insulating layer 25 may be removed and impurity ions may be implanted to form the LDD region 21a.

[0084] Thus, in the second embodiment, N-type impurity ions are implanted on the sides of two adjacent transfer gates TG without providing a sidewall insulating layer, thereby forming an N-type LDD region 21a. This makes it possible to suppress dark current caused by the electric field near the floating diffusion region FD.

[0085] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0086] Figure 10 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0087] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 10, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0088] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0089] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0090] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0091] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0092] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0093] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0094] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0095] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0096] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 10, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0097] Figure 11 shows an example of the installation position of the imaging unit 12031.

[0098] In Figure 11, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0099] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0100] Figure 11 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0101] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0102] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0103] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0104] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0105] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031, among the configurations described above. Specifically, by applying the technology described herein to the imaging unit 12031, it is possible to obtain clearer images, thereby reducing driver fatigue.

[0106] The technology can take the following configurations: (1) A photodetector comprising: a photoelectric conversion region that stores charge according to the amount of incident light; a first transistor having a first gate that controls whether or not to transfer the charge; a floating diffusion region that holds the charge transferred via the first transistor; a second transistor having a second gate and positioned adjacent to the first transistor; a region separation layer positioned between the first gate and the second gate and extending in the depth direction of the photoelectric conversion region; and a first insulating layer positioned above the region separation layer and having a first surface facing the side of the first gate on the second gate side, a second surface facing the side of the second gate on the first gate side, a third surface in contact with the upper surface of the first gate, and a fourth surface in contact with the upper surface of the second gate. (2) The photodetector according to (1), wherein the first insulating layer is positioned to cover the region between the first gate and the second gate, the upper surface of the first gate, and the upper surface of the second gate. (3) The photodetector according to (1) or (2), comprising: a third transistor having a third gate that controls the reading of the charge held in the floating diffusion region, and positioned at a distance from the first transistor that is longer than the distance from the second transistor; and a second insulating layer having a curved cross-section at a portion facing the side surface of the third gate, wherein the cross-sectional shape of the first insulating layer at the portion facing the side surface of the first gate and the side surface of the second gate is rectangular. (4) The photodetector according to (3), wherein the first transistor is a transfer transistor, and the second and third transistors are pixel transistors. (5) The photodetector according to any one of (1) to (4), wherein the second transistor is an amplification transistor. (6) The photodetector according to any one of (1) to (5), comprising: a third transistor positioned along the end face of the region separation layer on the first gate side, and comprising a diffusion region with a higher impurity concentration than the region separation layer. (7) The photodetector according to (6), wherein the diffusion region is a P-type diffusion region.(8) The photodetector according to (6) or (7), wherein the second gate is arranged to cover a portion of the region separation layer, and the area near the end face of the region separation layer on the second gate side has the same impurity concentration as the region separation layer. (9) The photodetector according to any one of (6) to (8), wherein the diffusion region suppresses dark current while the charge is being stored in the photoelectric conversion region. (10) The photodetector according to (9), wherein the diffusion region suppresses dark current when a high potential is applied to the second gate while the charge is being stored in the photoelectric conversion region. (11) The photodetector according to (10), wherein the diffusion region mitigates depletion that occurs when a high potential is applied to the second gate while the charge is being stored in the photoelectric conversion region. (12) The photodetector according to any one of (1) to (11), comprising: (12) a first gate group having a plurality of first gates arranged along a first direction; a second gate group having a plurality of second gates arranged along the first direction; the first gate group and the second gate group being spaced apart in a second direction intersecting the first direction, the distance between the first gate group and the second gate group being shorter than the distance between two adjacent first gates in the first direction and shorter than the distance between two adjacent second gates in the first direction; (13) The photodetector according to (1) or (2), wherein the floating diffusion region is shared by a plurality of photoelectric conversion regions and a plurality of transfer transistors, the plurality of transfer transistors having a first transistor and a second transistor, and the second transistor controls whether or not to transfer charge accumulated in a photoelectric conversion region different from the photoelectric conversion region to which the first transistor transfers to the floating diffusion region; (14) The photodetector according to (13), further comprising a diffusion region disposed around the floating diffusion region between the first gate and the second gate, wherein the diffusion region has a higher impurity concentration than the region separation layer. (15) The photodetector according to (14), wherein the diffusion region is an N-type diffusion region or a P-type diffusion region. (16) The photodetector according to (14) or (15), wherein the diffusion region mitigates the electric field of the floating diffusion region when the charge has been transferred from the plurality of photoelectric conversion regions to the floating diffusion region.(17) The photodetector according to any one of (14) to (16), wherein the diffusion region reduces the GIDL (Gate Induced Drain Leakage current) of the first transistor and the second transistor.

[0107] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0108] 1. Photodetector, 2. Pixel, 3. Pixel array section, 4. Vertical drive circuit, 5. Column signal processing circuit, 6. Horizontal drive circuit, 7. Output circuit, 8. Control circuit, 9. Input / output terminals, 10. Pixel, 11. Pixel circuit, 12. G transfer transistor group, 13. Pixel transistor, 13G pixel transistor group, 14. Dashed frame, 15. Photoelectric conversion region, 16. Element isolation region, 17. P-type semiconductor region, 18. P-type diffusion region, 19. First insulating region, 20. Second insulating region, 21. High impurity region, 21a. LDD region, 22. N-type diffusion region, 23. PN junction region, 24. Insulating layer, 25. Insulating layer, 26. Insulating layer, 27. Sidewall insulating layer, 28. Resist, 29. Resist, 30. First insulating layer, 31. Diffusion layer

Claims

1. A photodetector comprising: a photoelectric conversion region that accumulates charge in proportion to the amount of incident light; a first transistor having a first gate that controls whether or not to transfer the charge; a floating diffusion region that holds the charge transferred via the first transistor; a second transistor having a second gate and positioned adjacent to the first transistor; a region separation layer positioned between the first gate and the second gate and extending in the depth direction of the photoelectric conversion region; and a first insulating layer positioned above the region separation layer and having a first surface facing the side of the first gate on the second gate side, a second surface facing the side of the second gate on the first gate side, a third surface in contact with the upper surface of the first gate, and a fourth surface in contact with the upper surface of the second gate.

2. The photodetector according to claim 1, wherein the first insulating layer is arranged to cover the region between the first gate and the second gate, the upper surface of the first gate, and the upper surface of the second gate.

3. The photodetector according to claim 1, comprising: a third transistor having a third gate positioned at a distance from the first transistor that is longer than the distance from the second transistor, for controlling the reading of the charge held in the floating diffusion region; and a second insulating layer having a curved cross-section at a portion facing the side surface of the third gate, wherein the cross-sectional shape of the first insulating layer at the portion facing the side surface of the first gate and the side surface of the second gate is rectangular.

4. The photodetector according to claim 3, wherein the first transistor is a transfer transistor, and the second and third transistors are pixel transistors.

5. The photodetector according to claim 1, wherein the second transistor is an amplifying transistor.

6. The photodetector according to claim 1, comprising a diffusion region arranged along the end face of the region separation layer on the first gate side, wherein the impurity concentration is higher than that of the region separation layer.

7. The photodetector according to claim 6, wherein the diffusion region is a P-type diffusion region.

8. The photodetector according to claim 6, wherein the second gate is arranged to cover a portion of the region separation layer, and the area near the end face of the region separation layer on the second gate side has the same impurity concentration as the region separation layer.

9. The photodetector according to claim 6, wherein the diffusion region suppresses the dark current while the charge is being accumulated in the photoelectric conversion region.

10. The photodetector according to claim 9, wherein the diffusion region suppresses dark current when a high potential is applied to the second gate while the charge is being accumulated in the photoelectric conversion region.

11. The photodetector according to claim 10, wherein the diffusion region mitigates depletion that occurs when a high potential is applied to the second gate while the charge is being accumulated in the photoelectric conversion region.

12. The photodetector according to claim 1, comprising: a first gate group having a plurality of first gates arranged along a first direction; a second gate group having a plurality of second gates arranged along the first direction; the first gate group and the second gate group being spaced apart in a second direction intersecting the first direction, wherein the distance between the first gate group and the second gate group is shorter than the distance between two adjacent first gates in the first direction and shorter than the distance between two adjacent second gates in the first direction.

13. The photodetector according to claim 1, wherein the floating diffusion region is shared by a plurality of photoelectric conversion regions and a plurality of transfer transistors, the plurality of transfer transistors comprises a first transistor and a second transistor, and the second transistor controls whether or not to transfer charge accumulated in a photoelectric conversion region different from the photoelectric conversion region to which the first transistor transfers charge to the floating diffusion region.

14. The photodetector according to claim 13, comprising a diffusion region disposed around the floating diffusion region between the first gate and the second gate, wherein the impurity concentration is higher than that of the region separation layer.

15. The photodetector according to claim 14, wherein the diffusion region is an N-type diffusion region or a P-type diffusion region.

16. The photodetector according to claim 14, wherein the diffusion region mitigates the electric field of the floating diffusion region when the charge has been transferred from the plurality of photoelectric conversion regions to the floating diffusion region.

17. The photodetector according to claim 14, wherein the diffusion region reduces the GIDL (Gate Induced Drain Leakage current) of the first transistor and the second transistor.

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