Light detection device and electronic apparatus

Abstract

An imaging device comprises a semiconductor substrate a first pixel. The first pixel comprises a first photoelectric conversion region disposed in the semiconductor substrate, a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view, a first floating diffusion region disposed in the semiconductor substrate, a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region, and a second transistor coupled to the second photoelectric conversion region and the first floating diffusion region. In the plan view, the second transistor may be adjacent to the first transistor and have a different size than the first transistor. The imaging device may be included in an electronic apparatus and / or a control vehicle for a system that comprises a signal processing circuit.

Description

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2024-194015 filed November 5, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a light detection device and an electronic apparatus.

[0003] A solid-state imaging device in which a plurality of photoelectric conversion units is provided in one pixel to detect an image plane phase difference and adjust the focus has been known. In this type of pixel, in the case where one photoelectric conversion unit is saturated, excess charges overflowed from the photoelectric conversion unit are transferred to another photoelectric conversion unit to prevent the image quality from deteriorating.

[0004] Patent Literature 1 discloses a structure that prevents charges overflowed from each of the photoelectric conversion units of the two pixels that detect an image plane phase difference from flowing into a floating diffusion (referred to also as a floating diffusion region).

[0005] Japanese Patent Application Laid-open No. 2016-225597Summary

[0006] However, the solid-state imaging device disclosed in Patent Literature 1 cannot perform focus adjustment in a wide illuminance range because no measures have been taken to increase the amount of charges that can be accumulated in the photoelectric conversion unit in the pixel. Meanwhile, a solid-state imaging device having a function of switching the conversion efficiency of photoelectric conversion has also been proposed. However, since the S / N ratio changes significantly when switching the conversion efficiency, there is a possibility that the image quality of the captured image deteriorates. In this regard, the present disclosure provides a light detection device and an electronic apparatus that are capable of performing focus adjustment in a wide illuminance range with high accuracy and improving the image quality of the captured image.

[0007] An imaging device comprises a semiconductor substrate a first pixel. The first pixel comprises a first photoelectric conversion region disposed in the semiconductor substrate, a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view, a first floating diffusion region disposed in the semiconductor substrate, a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region, and a second transistor coupled to the second photoelectric conversion region and the first floating diffusion region. In the plan view, the second transistor may be adjacent to the first transistor and have a different size than the first transistor. The imaging device may be included in an electronic apparatus and / or a control vehicle for a system that comprises a signal processing circuit. The imaging device may include an insulating layer on the semiconductor substrate, where at least a first portion of the first transistor and at least a second portion of the second transistor are disposed in the insulating layer. A second portion of the first transistor and a second portion of the second transistor may be disposed in the semiconductor substrate. The imaging device may further comprise an isolation region disposed in the semiconductor substrate between the second portion of the first transistor and the second portion the second transistor. In the plan view, a gate of the first transistor may be at a first edge of the first photoelectric conversion region and a gate of the second transistor may be a first edge of the second photoelectric conversion region. In the plan view, a gate of the first transistor may overlap with a central region of the first photoelectric conversion region and a gate of the second transistor may overlap with a central region of the second photoelectric conversion region. The imaging device may further comprise a second floating diffusion region, and a third transistor coupled between the first floating diffusion region and the second floating diffusion region. The imaging device may further comprise a capacitance coupled to the second floating diffusion region. The imaging device may further comprise a third floating diffusion region, and a fourth transistor coupled between the second floating diffusion region and the third floating diffusion region. The imaging device may further comprise a capacitance coupled to the third floating diffusion region. The imaging device may further comprise a semiconductor region of a first conductivity type disposed in the semiconductor substrate between the first photoelectric conversion region and the second photoelectric conversion region. The first and second photoelectric conversion regions may be of the first conductivity type, and the semiconductor region may have a lower impurity concentration than the first and second photoelectric conversion regions. The imaging device may further comprise a first semiconductor region disposed in the semiconductor substrate, where, in the plan view, a gate of the first transistor overlaps the first semiconductor region; and a second semiconductor region disposed in the semiconductor substrate, where, in the plan view, a gate of the second transistor overlaps the second semiconductor region, and where the first and second semiconductor regions are of a conductivity type opposite to a conductivity type of the first and second photoelectric conversion regions. In the plan view a space between a source or a drain of the first transistor and the gate of the first transistor may be greater than a space between a source or a drain of the second transistor and the gate of the second transistor. A size of the first semiconductor region may be greater than a size of the second semiconductor region. The imaging device may further comprise a second pixel adjacent to the first pixel, and a full trench isolation region disposed in the semiconductor substrate between the first pixel and the second pixel.

[0008] Fig. 1 is a block diagram showing a configuration of an electronic apparatus according to a first embodiment.Fig. 2 is a block diagram showing a configuration of a light detection device according to the first embodiment.Fig. 3A is a diagram showing a first example of a stacked structure of an image processing system.Fig. 3B is a diagram showing a second example of the stacked structure of the image processing system.Fig. 4 is a circuit diagram showing configurations of a large pixel and a pixel circuit according to the first embodiment.Fig. 5 is a plan view showing a layout of the large pixel and the pixel circuit according to the first embodiment.Fig. 6 is a cross-sectional view of a transfer transistor according to the first embodiment.Fig. 7 is a diagram showing a potential barrier of the large pixel according to the first embodiment.Fig. 8 is a plan view of a layout of a large pixel and a pixel circuit according to a second embodiment.Fig. 9 is a diagram showing a potential barrier of the large pixel according to the second embodiment.Fig. 10 is a waveform diagram showing a relationship between the signal level and S / N of a pixel signal in the light detection device.Fig. 11A is a cross-sectional view of a first transfer transistor according to a third embodiment.Fig. 11B is a cross-sectional view of a second transfer transistor according to the third embodiment.Fig. 12 is a circuit diagram showing configurations of a large pixel and a pixel circuit according to a fourth embodiment.Fig. 13 is a plan view showing a layout of the large pixel and the pixel circuit according to the fourth embodiment.Fig. 14 is a plan view showing a layout of a large pixel and a pixel circuit according to a fifth embodiment.Fig. 15 is a plan view showing a layout of a large pixel and a pixel circuit according to a sixth embodiment.Fig. 16 is a cross-sectional view of two transfer transistors according to the sixth embodiment.Fig. 17 is a plan view showing a layout of a large pixel and a pixel circuit according to the seventh embodiment.Fig. 18 is a cross-sectional view of two transfer transistors according to the seventh embodiment.Fig. 19 is a plan view showing a layout of a large pixel and a pixel circuit according to the eighth embodiment.Fig. 20 is a cross-sectional view of the large pixel and the pixel circuit according to the eighth embodiment.Fig. 21 is a plan view showing a layout of a large pixel and a pixel circuit according to a ninth embodiment.Fig. 22 is a cross-sectional view of the large pixel and the pixel circuit according to the ninth embodiment.Fig. 23 is a plan view showing a layout of a large pixel and a pixel circuit according to a tenth embodiment.Fig. 24 is a cross-sectional view of the large pixel and the pixel circuit according to the tenth embodiment.Fig. 25 is a circuit diagram showing configurations of a large pixel and a pixel circuit according to an eleventh embodiment.Fig. 26 is a plan view showing a layout of the large pixel and the pixel circuit according to the eleventh embodiment.Fig. 27 is a cross-sectional view of the large pixel and the pixel circuit according to the eleventh embodiment.Fig. 28 is a diagram showing a potential barrier of the large pixel according to the eleventh embodiment.Fig. 29 is a circuit diagram showing configurations of a large pixel and a pixel circuit according to a twelfth embodiment.Fig. 30 is a plan view showing a layout of the large pixel and the pixel circuit according to the twelfth embodiment.Fig. 31 is a cross-sectional view showing the large pixel and the pixel circuit according to the twelfth embodiment.Fig. 32 is a diagram showing a potential barrier of the large pixel according to the twelfth embodiment.Fig. 33 is a circuit diagram showing configurations of a large pixel and a pixel circuit according to a thirteenth embodiment.Fig. 34 is a plan view showing a layout of the large pixel and the pixel circuit according to the thirteenth embodiment.Fig. 35A is a first cross-sectional view of the large pixel and the pixel circuit according to the thirteenth embodiment.Fig. 35B is a second cross-sectional view of the large pixel and the pixel circuit according to the thirteenth embodiment.Fig. 36 is a plan view showing a layout of a large pixel and a pixel circuit according to a fourteenth embodiment.Fig. 37A is a plan view showing a first layer of a large pixel and a pixel circuit according to a fifteenth embodiment.Fig. 37B is a plan view showing a second layer of the large pixel and the pixel circuit according to the fifteenth embodiment.Fig. 38 is a cross-sectional view showing the large pixel and the pixel circuit according to fifteenth embodiment.Fig. 39A is a plan view showing a first layer of a large pixel and a pixel circuit according to a sixteenth embodiment.Fig. 39B is a plan view showing a second layer of the large pixel and the pixel circuit according to the sixteenth embodiment.Fig. 40 is a cross-sectional view showing the large pixel and the pixel circuit according to the sixteenth embodiment.Fig. 41 is a cross-sectional view showing a large pixel and a pixel circuit according to a seventeenth embodiment.Fig. 42 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 43 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section.

[0009] A light detection device (also called at and an electronic apparatus according to an embodiment will be described below with reference to the drawings. Although the main components of the light detection device and the electronic apparatus will be mainly described below, the light detection device and the electronic apparatus can include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0010] (First embodiment) Fig. 1 is a block diagram showing a configuration of an electronic apparatus 1 that includes a light detection device 10 (also called a light detecting device) according to a first embodiment of the present disclosure. The electronic apparatus 1 is an apparatus (e.g., solid-state imaging device) that generates image data based on the amount of incident light and includes a light detection device 10, an imaging lens 2, a recording unit 3, and a control unit 4. The electronic apparatus 1 may include, for example, a sensing apparatus, a camera mounted on an industrial robot, or an in-vehicle camera, but the specific application and configuration of the electronic apparatus 1 are arbitrary.

[0011] The light detection device 10 performs photoelectric conversion on incident light to generate image data having gradation information. The light detection device 10 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor.

[0012] The light detection device 10 is capable of detecting a phase difference (image plane phase difference) of incident light between a plurality of light-receiving positions. The light detection device 10 may have a function of bringing the plurality of light-receiving positions into a focused state where the phases of incident light match by adjusting the phase difference of incident light. In the present specification, the above focusing method is referred to also as image plane phase difference autofocus (ZAF).

[0013] The imaging lens 2 collects incident light and guides the collected light into the light detection device 10. The recording unit 3 records the image data input from the light detection device 10 via a transmission line 5. The recording unit 3 may be disposed in a server connected via a network, or the like. The control unit 4 controls the imaging timing of the light detection device 10, and the like via a control line 6. The electronic apparatus 1 may have a configuration including a signal processing unit 7 that performs image processing, machine learning processing, or the like on the image data output from the light detection device 10.

[0014] Fig. 2 is a block diagram showing a configuration of the light detection device 10 according to the first embodiment of the present disclosure. The light detection device 10 includes a pixel array unit 11, a row drive circuit 12, a control circuit 13, and a column signal processing circuit 14.

[0015] The pixel array unit 11 includes a plurality of large pixels 20 arranged in the first direction X and the second direction Y. In the present specification, the right-left (horizontal) direction in Fig. 2 is referred to as the first direction X, and the up-and-down (vertical) direction in Fig. 2 is referred to as the second direction Y. A group of large pixels 20 arranged along the first direction X is referred to as a pixel row, and a group of large pixels 20 arranged along the second direction is referred to as a pixel column.

[0016] The large pixel 20 includes a plurality of photoelectric conversion devices that each generates charges corresponding to the amount of incident light. Further, the large pixel 20 (also referred to as a pixel) includes a plurality of small pixels that each includes a photoelectric conversion device. The plurality of small pixels in one large pixel 20 shares one pixel circuit. The pixel circuit generates a pixel signal Vimg on the basis of the charges of the plurality of photoelectric conversion devices. Note that the illustration of the small pixel and the pixel circuit is omitted in Fig. 2.

[0017] The row drive circuit 12 includes a shift register, an address decoder, and the like. The row drive circuit 12 drives each large pixel 20 of the pixel array unit 11 simultaneously or in units of pixel rows. The row drive circuit 12 resets and reads the signal for each large pixel 20 and the pixel circuit.

[0018] In a reset operation, unnecessary charges are discharged from the plurality of photoelectric conversion devices of the large pixel 20. This allows the plurality of photoelectric conversion devices in the large pixel 20 to start new exposure. The operation of discharging the charges of the plurality of photoelectric conversion devices and starting new exposure (starting charge accumulation) is also called an electronic shutter operation. The light detection device 10 may perform a global shutter operation in which the electronic shutter operation is performed simultaneously in all large pixels. The global shutter operation has the feature that timings of exposure for each large pixel or small pixel match.

[0019] In the signal reading, the pixel signal Vimg based on the charges accumulated in the plurality of photoelectric conversion devices in the large pixel 20 are read from the pixel circuit. The period from the electronic shutter operation to the signal reading is referred to also as an exposure period. In the signal reading, the pixel signal Vimg corresponding to the amount of light that has entered the large pixel 20 during the exposure period is read from the pixel circuit.

[0020] The control circuit 13 includes a timing generator that generates various timing signals, and the like. The control circuit 13 performs control of the reading and resetting timings of the row drive circuit 12, and drive control of the column signal processing circuit 14, and the like on the basis of the various timing signals.

[0021] The column signal processing circuit 14 is supplied with the pixel signal Vimg from each large pixel 20 in the pixel array unit 11 and the pixel circuit. The column signal processing circuit 14 performs predetermined signal processing on the pixel signal Vimg. Examples of the predetermined signal processing include analog-to-digital conversion of the pixel signal Vimg and processing of removing noise superimposed on the pixel signal Vimg. As the noise removal processing on the pixel signal Vimg, for example, correlated double sampling (CDS) is used.

[0022] The light detection device 10 may be configured using, for example, a stacked chip in which a plurality of chips is stacked. Fig. 3A is a diagram showing a first example of the stacked structure of the light detection device 10. The light detection device 10 in Fig. 3A has a two-layer structure in which a pixel chip b1 and a logic chip b2 are bonded together in this order. These chips are bonded together by a via or the like. Note that the pixel chip b1 and the logic chip b2 may be bonded together by Cu-Cu bonding or a bump instead of the via.

[0023] In the pixel chip b1, for example, the plurality of large pixels 20 in the pixel array unit 11 and the pixel circuit are disposed. In the logic chip b2, for example, the row drive circuit 12, the control circuit 13, and the column signal processing circuit 14 are disposed.

[0024] Fig. 3B is a diagram showing a second example of the stacked structure of the light detection device 10. A light detection device 10a in Fig. 3B has a three-layer structure in which a first pixel chip b3, a second pixel chip b4, and the logic chip b2 are bonded together in this order. In the first pixel chip b3, for example, the plurality of large pixels 20 is arranged. In the second pixel chip b4, the pixel circuit is disposed. By disposing the pixel circuit in the second pixel chip b4, the light detection device 10a is capable of increasing the ratio of the area of the photoelectric conversion devices to the chip area, improving the sensitivity, and miniaturizing the chip.

[0025] Note that the components disposed in each chip are not limited to the above-mentioned components. Further, the light detection device 10 may include a stacked chip of four or more layers or may include a single flat chip.

[0026] Fig. 4 is a circuit diagram showing configurations of the large pixel 20 and a pixel circuit 21 according to the first embodiment of the present disclosure. Fig. 5 is a plan view showing the layout of the large pixel 20 and the pixel circuit 21 according to the first embodiment of the present disclosure. The large pixel 20 includes a plurality of photoelectric conversion devices PD (also called photoelectric conversion regions), a plurality of transfer transistors (transfer circuit) TG, a floating diffusion region (first floating diffusion region) FD1, a transfer region (first semiconductor region) TRN, a conversion efficiency transistor (third transistor) FDG, and a floating diffusion region (second floating diffusion region) FD2. Further, a capacitor Cp connected to the floating diffusion region FD2 is also illustrated in Fig. 4.

[0027] The plurality of photoelectric conversion devices PD includes a photoelectric conversion device (first photoelectric conversion device) PD1 and a photoelectric conversion device (second photoelectric conversion device) PD2 arranged to be adjacent to each other. The plurality of transfer transistors TG includes a transfer transistor (first transistor) TG1 corresponding to the photoelectric conversion device PD1 and a transfer transistor (second transistor) TG2 corresponding to the photoelectric conversion device PD2. Further, the large pixel 20 includes a small pixel 22a including the photoelectric conversion device PD1 and the transfer transistor TG1 and a small pixel 22b including the photoelectric conversion device PD2 and the transfer transistor TG2.

[0028] The pixel circuit 21 includes a discharge transistor RST, an amplifier transistor AMP, and a selection transistor SEL. The pixel circuit 21 outputs the pixel signal Vimg to the column signal processing circuit 14 via the vertical signal line VSL.

[0029] The components in Fig. 4 may be arbitrarily disposed in either the large pixel 20 or the pixel circuit 21. At least some (e.g., the amplifier transistor AMP) of the above components of the pixel circuit 21 may be included in the large pixel 20. Further, at least some (e.g., the conversion efficiency transistor FDG and the floating diffusion region FD2) of the components of the large pixel 20 may be included in the pixel circuit 21. The capacitor Cp may be included in the large pixel 20 or may be included in the pixel circuit 21.

[0030] The transfer transistors TG1 and TG2, the conversion efficiency transistor FDG, the discharge transistor RST, the discharge transistor RST, the amplifier transistor AMP, and the selection transistor SEL in Fig. 4 are, for example, N channel metal-oxide-semiconductor (NMOS) transistors. Note that some or all of these transistors may be P channel metal-oxide-semiconductor (PMOS) transistors. As described above, the polarity of the transistors described in the present specification is arbitrary.

[0031] The photoelectric conversion devices PD1 and PD2 are, for example, photodiodes and each accumulate charges corresponding to the amount of incident light. The photoelectric conversion devices PD1 and PD2 each include an anode and a cathode. One of the anode and the cathode of the photoelectric conversion device PD1 (e.g., cathode) is connected to the source of the transfer transistor TG1, and the other (e.g., anode) is connected to a predetermined reference voltage node VSS such as a ground voltage. One of the anode and the cathode of the photoelectric conversion device PD2 (e.g., cathode) is connected to the source of the transfer transistor TG2, and the other (e.g., anode) is connected to the reference voltage node VSS.

[0032] The drains of the transfer transistors TG1 and TG2 are connected to the floating diffusion region FD1. The transfer transistor TG1 is turned on when a predetermined voltage is applied to the gate thereof, and transfers the charges accumulated in the photoelectric conversion device PD1 to the floating diffusion region FD1. The transfer transistor TG2 is turned on when a predetermined voltage is applied to the gate thereof, and transfers the charges accumulated in the photoelectric conversion device PD2 to the floating diffusion region FD1. As shown in Fig. 5, the transfer transistors TG1 and TG2 according to the first embodiment of the present disclosure have substantially the same surface area (size).

[0033] The floating diffusion region FD1 is shared by the plurality of photoelectric conversion devices PD, and holds the charges transferred from the plurality of photoelectric conversion devices PD (the photoelectric conversion devices PD1 and PD2 in Fig. 4). The floating diffusion region FD1 is connected to the gate of the amplifier transistor AMP and the source of the conversion efficiency transistor FDG.

[0034] The photoelectric conversion devices PD1 and PD2 and the floating diffusion region FD1 are semiconductor regions in which an impurity of a first conductivity type (e.g., N-type) is injected. Further, a device isolation region ISO (also called an isolation region) is disposed between the photoelectric conversion devices PD1 and PD2 and the floating diffusion region FD1. The device isolation region ISO has, for example, shallow trench isolation (STI) including an insulation region. The device isolation region ISO may have a configuration having a semiconductor region in which an impurity of a second conductivity type (e.g., P-type) is injected.

[0035] As shown in Fig. 5, the transfer region TRN is disposed between the photoelectric conversion devices PD1 and PD2. The transfer region TRN transfers the charges overflowed from one of the photoelectric conversion devices PD1 and PD2 (hereinafter, referred to also as overflow charges) to the other.

[0036] The transfer region TRN may be, for example, a semiconductor region in which an impurity of a first conductivity type is injected, with the semiconductor region having an impurity concentration lower than those of the photoelectric conversion devices PD1 and PD2. Alternatively, the transfer region TRN may be a region in which an impurity of a second conductivity type is injected, with the region having an impurity concentration lower than that of the semiconductor region of the second conductivity type in the device isolation region ISO.

[0037] The drain of the conversion efficiency transistor FDG is connected to the floating diffusion region FD2. The conversion efficiency transistor FDG is turned on when a predetermined voltage is applied to the gate thereof, and transfers the charges overflowed from the plurality of photoelectric conversion devices PD to the floating diffusion region FD2.

[0038] The floating diffusion region FD2 holds the charges overflowed from the plurality of photoelectric conversion devices PD. Further, the floating diffusion region FD2 is connected to the source of the discharge transistor RST.

[0039] The capacitor Cp holds at least some of the charges held in the floating diffusion region FD2. One end of the capacitor Cp is connected to the floating diffusion region FD2, and the other end is connected to a predetermined high-voltage node MIMVDD such as a power supply voltage.

[0040] The capacitor Cp is, for example, a lateral overflow integration capacitor (LOFIC). The capacitor Cp has, for example, a metal-insulator-metal (MIM) capacitance. The capacitor Cp may have a metal-oxide semiconductor (MOS) capacitance. Since the capacitor Cp has a large capacitance, more charges than the floating diffusion region FD1 can be held in the floating diffusion region FD2 and the capacitor Cp.

[0041] The discharge transistor RST controls the discharging of charges in the large pixel 20 and the pixel circuit 21. The drain of the discharge transistor RST is connected to a predetermined high-voltage node VDD such as a power supply voltage. The discharge transistor RST is turned on when a predetermined voltage is applied to the gate thereof, and discharges the charges of the large pixel 20 and the pixel circuit 21 to the high-voltage node VDD.

[0042] The amplifier transistor AMP is used as an input unit of a source-follower circuit. The source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL, and the drain of the amplifier transistor AMP is connected to the high-voltage node VDD. Further, the voltage of the floating diffusion region FD1 is applied to the gate of the amplifier transistor AMP. The amplifier transistor AMP supplies the current based on the voltage of the floating diffusion region FD1 to the selection transistor SEL.

[0043] The source of the selection transistor SEL is connected to the vertical signal line VSL. The selection transistor SEL is turned on when a predetermined voltage is applied to the gate thereof, and outputs the pixel signal Vimg based on the voltage of the floating diffusion region FD1 to the column signal processing circuit 14 in Fig. 2 via the vertical signal line VSL.

[0044] Fig. 5 illustrates a path (first transfer path) Ps1 through which charges are transferred from the photoelectric conversion device PD1 to the floating diffusion region FD1 via the transfer transistor TG1. Further, Fig. 5 illustrates a path (second transfer path) Ps2 through which charges are transferred from the photoelectric conversion device PD2 to the floating diffusion region FD1 via the transfer transistor TG2. Further, Fig. 5 shows a path Ps3 through which charges are transferred between the photoelectric conversion device PD1 and the photoelectric conversion device PD2 via the transfer region TRN.

[0045] The device isolation region ISO in Fig. 5 includes a device isolation region (second semiconductor region or insulation region) ISOa disposed between the transfer transistors TG1 and TG2 and the floating diffusion region FD1. the device isolation region ISOa separates the paths Ps1 and Ps2 from each other.

[0046] Fig. 6 is a cross-sectional view of the transfer transistor TG1 according to the first embodiment of the present disclosure. Fig. 6 illustrates the cross section taken along the line A-A’ in Fig. 5. Further, Fig. 6 illustrates a semiconductor layer 30 in which the plurality of photoelectric conversion devices PD is arranged. The transfer transistor TG1 includes an electrode 31 disposed on the surface of the semiconductor layer 30 and a semiconductor region 32 disposed in the semiconductor layer 30. The electrode 31 is the gate electrode (also called a gate) of the transfer transistor TG1. The semiconductor region 32 is either the drain region or source region (e.g., drain region) of the transfer transistor TG1. Note that in Fig. 6, illustration of the other of the drain region and source region is omitted. Further, in the semiconductor layer 30, a semiconductor region 33 is disposed to face the electrode 31.

[0047] The semiconductor layer 30 contains, for example, silicon (Si). The semiconductor region 32 is a region in which an impurity of a first conductivity type is injected. Further, charges are transferred from the photoelectric conversion device PD1 to the semiconductor region 32 when a predetermined voltage is applied to the electrode 31. The semiconductor region 32 may be formed integrally with the floating diffusion region FD1.

[0048] The semiconductor region 33 is a region in which an impurity of a second conductivity type is injected, and is disposed to be separated from the semiconductor region 32. The semiconductor region 33 is used to form the potential barrier of the transfer transistor TG1. Increasing the impurity concentration of the semiconductor region 33 allows the potential barrier of the transfer transistor TG1 to increase. In the present specification, the semiconductor region 33 is referred to also as a back gate region.

[0049] The cross-sectional structure of the transfer transistor TG2 is similar to that in Fig. 6.

[0050] Fig. 7 is a diagram showing the potential barrier of the large pixel 20 according to the first embodiment of the present disclosure. Fig. 7 illustrates the potential barrier when the transfer transistors TG1 and TG2 are off. There is a potential barrier of the transfer transistor TG1 (i.e., the path Ps1) between the photoelectric conversion device PD1 and the floating diffusion region FD1. There is a potential barrier of the transfer transistor TG2 (i.e., the path Ps2) between the photoelectric conversion device PD2 and the floating diffusion region FD1. There is a potential barrier of the transfer region TRN(i.e., the path Ps3) between the photoelectric conversion devices PD1 and PD2.

[0051] In the example of Fig. 7, the transfer transistors TG1 and TG2 have substantially the same potential barrier when they are in the off-state. Note that the transfer transistors TG1 and TG2 may have different potential barriers when they are in the off-state. Further, the potential barrier of the transfer region TRN is lower than the potential barriers of the transfer transistors TG1 and TG2 when they are in the off-state.

[0052] The operations of the large pixel 20 and the pixel circuit 21 in Fig. 4 will be described below. The transfer transistors TG1 and TG2, the conversion efficiency transistor FDG, the discharge transistor RST, the amplifier transistor AMP, and the selection transistor SEL are controlled when, for example, a predetermined voltage is applied to the corresponding gate from the row drive circuit 12 in Fig. 2.

[0053] During the exposure period, the photoelectric conversion devices PD1 and PD2 accumulate charges corresponding to the amount of incident light. During the exposure period, the transfer transistors TG1 and TG2 are off, and the charges accumulated in the photoelectric conversion devices PD1 and PD2 are not transferred to the floating diffusion region FD1.

[0054] During the exposure period, the discharge transistor RST and the selection transistor SEL are off. Further, during the exposure period, the conversion efficiency transistor FDG is on.

[0055] When the illuminance of incident light is high, the photoelectric conversion device PD1 or PD2 (e.g., the photoelectric conversion device PD1) is saturated. The potential barrier of the transfer region TRN is lower than the potential barriers of the transfer transistors TG1 and TG2 in the off-state. For this reason, the overflow charges of the saturated photoelectric conversion device PD1 overflow to the photoelectric conversion device PD2 beyond the potential barrier of the transfer region TRN.

[0056] When both the photoelectric conversion devices PD1 and PD2 are saturated, the overflow charges flow to the floating diffusion region FD1 beyond the potential barriers of the transfer transistors TG1 and TG2. Further, the conversion efficiency transistor FDG transfers the overflow charges to the floating diffusion region FD2 and the capacitor Cp.

[0057] That is, the floating diffusion region FD2 and the capacitor Cp are capable of holding the overflow charges overflowed from the photoelectric conversion devices PD1 and PD2 during the exposure period.

[0058] After the exposure period ends, the reading period in which charges are read from the large pixel 20 and the pixel circuit 21 starts.

[0059] In the reading period, the pixel circuit 21 is capable of collecting and reading the charges obtained by photoelectric conversion by the plurality of photoelectric conversion devices PD in the large pixel 20. Alternatively, the pixel circuit 21 is also capable of separately reading the charges obtained by photoelectric conversion by the plurality of photoelectric conversion devices PD or separately reading the charges accumulated in some photoelectric conversion devices PD and the charges accumulated in the other photoelectric conversion devices PD.

[0060] First, a case where the charges of the plurality of photoelectric conversion devices PD are collected and read will be described. The pixel circuit 21 is capable of outputting the pixel signal Vimg at the reset level before transferring the charges accumulated in the photoelectric conversion device PD to the floating diffusion region FD1, by turning off the conversion efficiency transistor FDG and turning on the selection transistor SEL. The pixel signal Vimg before transferring charges can be used for CDS on the pixel signal Vimg with high conversion efficiency(HCG) described later.

[0061] Subsequently, the pixel circuit 21 is capable of transferring the charges accumulated in the photoelectric conversion devices PD1 and PD2 to the floating diffusion region FD1, by turning on the transfer transistors TG1 and TG2 while the conversion efficiency transistor FDG is in the off-state. The pixel circuit 21 is capable of outputting the pixel signal Vimg at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2, by turning the selection transistor SEL.

[0062] In the present specification, the pixel signal Vimg corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2 is referred to also as the pixel signal Vimg with high conversion efficiency (HCG).

[0063] Further, by turning on the conversion efficiency transistor FDG and the transfer transistors TG1 and TG2, the charges accumulated in the photoelectric conversion devices PD1 and PD2 and the overflow charges held in the floating diffusion region FD2 and the capacitor Cp are transferred to the floating diffusion region FD1. The pixel circuit 21 is capable of outputting the pixel signal Vimg at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2 and the overflow charges overflowed from the photoelectric conversion devices PD1 and PD2, by turning on the selection transistor SEL.

[0064] In the present specification, the pixel signal Vimg corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2 and the overflow charges is referred to also as the pixel signal Vimg with low conversion efficiency (SLCG).

[0065] The pixel circuit 21 is capable of discharging the charges from the large pixel 20 and the pixel circuit 21 by turning on the discharge transistor RST and of resetting the voltages of the photoelectric conversion devices PD1 and PD2 to the voltage level before exposure. The pixel circuit 21 is capable of outputting the pixel signal Vimg at the reset level after the discharge of charges, by turning on the selection transistor SEL. The pixel signal Vimg at the reset level after the discharge of charges can be used for CDS on the pixel signal Vimg with low conversion efficiency (SLCG).

[0066] As described above, by turning on the conversion efficiency transistor FDG, the charges transferred to the floating diffusion region FD1 and the overflow charges held in the floating diffusion region FD2 and the capacitor Cp can be read. By reading the charges and overflow charges of the plurality of photoelectric conversion devices PD, the pixel circuit 21 is capable of reading charges of the saturation charge amount of the plurality of photoelectric conversion devices PD or more. This allows the dynamic range of the pixel signal Vimg to be expanded. In the present specification, the above drive is referred to also as LOFIC drive.

[0067] The pixel circuit 21 is capable of collecting the charges of the plurality of photoelectric conversion devices PD by turning on the plurality of transfer transistors TG simultaneously. This method can be used for the above LOFIC drive. In addition, even if the light amount of incident light is small and the charges accumulated in each of the plurality of photoelectric conversion devices PD are few, the pixel circuit 21 is capable of collecting and reading the charges.

[0068] Subsequently, a case of separately reading the charges of the plurality of photoelectric conversion devices PD will be described. The pixel circuit 21 is capable of transferring the charges of the photoelectric conversion device PD1 to the floating diffusion region FD1, by turning on the transfer transistor TG1 while the conversion efficiency transistor FDG and the transfer transistor TG2 are in the off-state. The pixel circuit 21 is capable of outputting the pixel signal Vimg at the signal level corresponding to the charges accumulated in the photoelectric conversion device PD1, by turning on the selection transistor SEL.

[0069] Subsequently, by turning on the transfer transistor TG2 and the selection transistor SEL while the conversion efficiency transistor FDG and the transfer transistor TG1 are in the off-state, the pixel signal Vimg at the signal level corresponding to the charges accumulated in the photoelectric conversion device PD2 can be output.

[0070] As described above, the pixel circuit 21 is capable of separately reading the charges obtained by photoelectric conversion by the plurality of photoelectric conversion devices PD, by turning on some of the plurality of transfer transistors TG and turning on the others. As a result, the pixel circuit 21 is capable of outputting the pixel signal Vimg for each of a plurality of small pixels and acquiring gradation information for each small pixel.

[0071] Further, in the case where the photoelectric conversion devices PD1 and PD2 are not saturated, the light detection device 10 is capable of acquiring the phase difference of incident light received by the photoelectric conversion devices PD1 and PD2, by comparing the pixel signal Vimg corresponding to the charges accumulated in the photoelectric conversion device PD1 and the pixel signal Vimg corresponding to the charges accumulated in the photoelectric conversion device PD2.

[0072] The light detection device 10 is capable of determining whether or not the photoelectric conversion devices PD1 and PD2 are in the focused state, by determining whether or not there is a phase difference between incident light of the photoelectric conversion devices PD1 and PD2. By adjusting the phase difference between the photoelectric conversion devices PD1 and PD2, the light detection device 10 is capable of realizing autofocus.

[0073] As described above, the light detection device 10 according to the first embodiment of the present disclosure includes the plurality of photoelectric conversion devices PD, the transfer transistor TG disposed for each photoelectric conversion device PD, and the floating diffusion regions FD1 and FD2 and the capacitor Cp shared by the plurality of photoelectric conversion devices PD.

[0074] In the light detection device 10, by controlling the plurality of transfer transistors TG, it is possible to switch between collecting and reading the charges of the plurality of photoelectric conversion devices PD or separately reading them.

[0075] In the case of collecting and reading charges, even if the amount of incident light is small, the pixel signal Vimg can be amplified to output clear image data. Further, in the case where the amount of incident light is large, by holding overflow charges in the capacitor Cp, the saturated signal amount (Qs) can be expanded. As a result, the light detection device 10 is capable of expanding the dynamic range.

[0076] In the case of separating reading charges, the pixel signal Vimg can be output for each small pixel to generate image data with high accuracy. Further, autofocus by detecting the image plane phase difference can be realized.

[0077] That is, the light detection device 10 is capable of performing focus adjustment with high accuracy in a wide illuminance range and improving the image quality of the captured image.

[0078] (Second embodiment) In second embodiment of the present disclosure, a method of further expanding the saturated signal amount will be described. Fig. 8 is a plan view showing the layout of a large pixel 20a and a pixel circuit 21a according to the second embodiment of the present disclosure. Fig. 9 is a diagram showing the potential barrier of the large pixel 20a according to the second embodiment of the present disclosure. The circuit diagram of the large pixel 20a and the pixel circuit 21a is similar to the circuit diagram in Fig. 4. The large pixel 20a according to the second embodiment of the present disclosure includes transfer transistors TG1a and TG2a respectively corresponding to the transfer transistors TG1 and TG2 in Fig. 5.

[0079] As shown in Fig. 9, the potential barrier of the transfer transistor TG2a in the off-state is larger than that of the transfer transistor TG2 in Fig. 7. The potential barrier of the transfer transistor TG2a can be realized by strengthening the negative bias of the transfer transistor TG2a in the off-state or injecting an impurity at a higher concentration to the back gate region of the transfer transistor TG2a (i.e., the semiconductor region 33 in Fig. 6).

[0080] The transfer transistor TG2a has a large potential barrier. Meanwhile, the potential barrier of the transfer transistor TG1a in the off-state is smaller than that of the transfer transistor TG2a in the off-state. For this reason, in the case where the photoelectric conversion device PD2 is saturated, the overflow charges are transferred to the floating diffusion region FD1 via the transfer region TRN (path Ps3), the photoelectric conversion device PD1, and the transfer transistor TG1a (path Ps1).

[0081] As described above, the large pixel 20a in Fig. 8 is different from the large pixel 20 in Fig. 5 in that the path Ps2 in Fig. 5 is not used to transfer overflow charges.

[0082] Further, as shown in Fig. 8, the transfer transistor TG1a has a larger size (e.g., surface area) than the transfer transistor TG2a. By increasing the size of the transfer transistor TG1a, the back gate region of the transfer transistor TG1a (i.e., the semiconductor region 33 in Fig. 6) can be enlarged. As a result, in the transfer transistor TG1a, it is possible to suppress the potential variation caused by the discrete dopant effect.

[0083] In the large pixel 20a, the overflow charges can be transferred using not the path Ps2 having a large potential variation but the path Ps1 having a small potential variation. In the large pixel 20a, the transfer of overflow charges can be limited by the potential of the transfer transistor TG1a. As a result, it is possible to make the saturated signal amount of the photoelectric conversion device PD larger than that of the large pixel 20 in Fig. 5.

[0084] Fig. 10 is a waveform diagram showing the relationship between the signal level and signal-to-noise ratio (hereinafter, referred to also as S / N) of the pixel signal Vimg in the light detection device 10. The horizontal axis in Fig. 10 indicates the signal level of the pixel signal Vimg, and the vertical axis indicates the signal-to-noise ratio of the pixel signal Vimg. Further, Fig. 10 illustrates a waveform WHCGindicating the pixel signal Vimg with high conversion efficiency and a waveform SLCG indicating the pixel signal Vimg with low conversion efficiency.

[0085] The S / N of the pixel signal Vimg with high conversion efficiency increases monotonically in accordance with the increase in signal level until the photoelectric conversion device PD is saturated. However, when the photoelectric conversion device PD is saturated, the S / N of the pixel signal Vimg with high conversion efficiency no longer increases even if the signal level increases. In this regard, the light detection device 10 acquires the pixel signal Vimg with low conversion efficiency in at the signal level where the photoelectric conversion device PD is saturated (connection part in Fig. 10).

[0086] In the present specification, the degree of decrease from the S / N of the pixel signal Vimg with high conversion efficiency to the S / N of the pixel signal Vimg with low conversion efficiency at the connection part in Fig. 10 is referred to also as a connection S / N step. In the light detection device 10, in the case where the connection S / N step is large, the image quality of image data deteriorates.

[0087] In the large pixel 20a in Fig. 8, the overflow charges of the photoelectric conversion devices PD1 and PD2 are transferred to the floating diffusion region FD1 through the path Ps1 having a small potential variation. As a result, it is possible to improve the S / N of the pixel signal Vimg with low conversion efficiency and reduce the connection S / N step. That is, in the light detection device 10 using the large pixel 20a in Fig. 8, it is possible to improve the image quality of image data.

[0088] As another method, it is conceivable to increase the sizes of both the transfer transistors TG1 and TG2 without making a difference between the potential barriers of the transfer transistors TG1 and TG2. It is possible to reduce the potential variation, similarly to the large pixel 20a in Fig. 8.

[0089] However, this method has the problem that increasing the sizes of the plurality of transfer transistors TG makes it difficult to provide a sufficient size for the photoelectric conversion device PD and the saturation charge amount of the photoelectric conversion device PD becomes smaller.

[0090] On the other hand, in the large pixel 20a in Fig. 8, it is unnecessary to increase the size of the transfer transistor TG2, and thus, it is possible to provide a sufficient size for the photoelectric conversion device PD as compared with the above method.

[0091] In the large pixel 20a in Fig. 8 and Fig. 9, the size of the transfer transistor TG1a is increased and the potential barrier of the transfer transistor TG2a is increased. However, the present disclosure is not limited thereto, and the size of the transfer transistor TG2a may be increased and the potential barrier of the transfer transistor TG1a may be increased.

[0092] The large pixel 20a in Fig. 8 may include three or more photoelectric conversion devices PD and three or more transfer transistors TG. In this case, by increasing the size of any one of transfer transistor TG of the plurality of transfer transistors TG and increasing the potential barrier of another transfer transistors TG, it is possible to increase the saturated signal amount of the photoelectric conversion device PD, similarly to the above.

[0093] As described above, in the large pixel 20a according to the second embodiment of the present disclosure, the size of one of the plurality of transfer transistors TG is increased and the potential barrier of another transfer transistor TG is increased. As a result, it is possible to transfer overflow charges through a path having a small potential variation, increase the saturated signal amount as compared with the large pixel 20 according to the first embodiment, and improve the image quality of image data.

[0094] Further, in the large pixel 20a according to the second embodiment, it is unnecessary to increase the size of the plurality of transfer transistors TG and it only needs to increase the size of one transfer transistor TG. For this reason, in the large pixel 20a, it is possible to provide a sufficient size for the photoelectric conversion device PD and increase the saturated signal amount of the photoelectric conversion device PD.

[0095] (Third embodiment) A plurality of methos is conceivable as a method of reducing the potential variation of the transfer transistor TG. Fig. 11A is a cross-sectional view of a transfer transistor TG1b according to the third embodiment of the present disclosure. Fig. 11B is a cross-sectional view of a transfer transistor TG2b according to the third embodiment of the present disclosure. The transfer transistors TG1b and TG2b in Fig. 11A and Fig. 11B respectively correspond to the transfer transistors TG1 and TG2 in Fig. 5.

[0096] The transfer transistor TG1b in Fig. 11A is different from the transfer transistor TG1 in Fig. 6 in that the distance between the electrode 31 and the semiconductor region 32 is larger. As a result, in the transfer transistor TG1b, the size of a semiconductor region 33a that is a back gate region can be made larger than that of the semiconductor region 33 in Fig. 6. In the transfer transistor TG1b in Fig. 11A, by increasing the size of the semiconductor region 33a, it is possible to suppress the potential variation caused by the discrete dopant effect.

[0097] The cross-sectional structure of the transfer transistor TG2b according to the third embodiment of the present disclosure is similar to that in Fig. 6. That is, in the transfer transistor TG1b, the distance between the electrode 31 and the semiconductor region 32 is larger than that in the transfer transistor TG2b. Further, the size of the semiconductor region 33a is larger than that of a semiconductor region 33b that is a back gate region of the transfer transistor TG2b.

[0098] In the third embodiment of the present disclosure, by increasing the potential barrier of the transfer transistor TG2b in the off-state similarly to the second embodiment, it is possible to increase the saturated signal amount, reduce the connection S / N step, and improve the image quality of image data. The semiconductor region 33b in Fig. 11B has an impurity concentration higher than that of the semiconductor region 33a in Fig. 11A, for example.

[0099] Further, the size of the transfer transistor TG1b may be larger than or substantially the same as that of the transfer transistor TG2b.

[0100] As described above, in the third embodiment of the present disclosure, by disposing the semiconductor region 32 at a position farther away from the electrode 31, it is possible to suppress the potential variation of the transfer transistor TG1b.

[0101] (Fourth embodiment) Fig. 12 is a circuit diagram showing configurations of a large pixel 20b and a pixel circuit 21b according to the fourth embodiment of the present disclosure. Fig. 13 is a plan view showing the layout of the large pixel 20b and the pixel circuit 21b according to the fourth embodiment of the present disclosure. The pixel circuit 21b (or the large pixel 20b) in Fig. 12 is different from the pixel circuit 21 (or the large pixel 20) in Fig. 4 in that it further includes a floating diffusion region (second floating diffusion region) FD3 and a conversion efficiency transistor (fourth transistor) FCG.

[0102] The source of the conversion efficiency transistor (third transistor) FDG in Fig. 12 is connected to the floating diffusion region (first floating diffusion region) FD1, and the drain thereof is connected to the floating diffusion region (third floating diffusion region) FD2. When the conversion efficiency transistor FDG is in the on-state, it transfers at least some of the charges held in the floating diffusion region FD1 to the floating diffusion region FD2.

[0103] The floating diffusion region FD2 holds at least some of the overflow charges overflowed from the plurality of photoelectric conversion devices PD during the exposure period.

[0104] The source of the conversion efficiency transistor FCG in Fig. 12 is connected to the floating diffusion region FD2, and the drain thereof is connected to the floating diffusion region FD3. When the conversion efficiency transistor FCG is in the on-state, it transfers at least some of the charges held in the floating diffusion region FD2 to the floating diffusion region FD3. The conversion efficiency transistor FCG is, for example, an NMOS transistor. The conversion efficiency transistor FCG is controlled when a predetermined voltage is applied to the gate thereof from the row drive circuit 12.

[0105] The floating diffusion region FD3 holds overflow charges during the exposure period. The floating diffusion region FD3 is connected to the source of the discharge transistor RST and one end of the capacitor Cp. More charges than the floating diffusion regions FD1 and FD2 can be held in the floating diffusion region FD3 and the capacitor Cp.

[0106] The operations of the large pixel 20b and the pixel circuit 21b in Fig. 12 will be described below. During the exposure period, the transfer transistors TG1a and TG2a, the discharge transistor RST, and the selection transistor SEL are off and the conversion efficiency transistors FDG and FCG are on. As a result, overflow charges are transferred to the floating diffusion regions FD2 and FD3 and the capacitor Cp.

[0107] During the reading period, the pixel circuit 21b is capable of detecting an image plane phase difference or performing LOFIC drive. First, an example of the detection of an image plane phase difference will be described. First, in the reading of charges of the photoelectric conversion device PD1, the conversion efficiency transistor FDG and the transfer transistor TG1a are turned on while the conversion efficiency transistor FCG and the transfer transistor TG2a are off. As a result, the charges of the photoelectric conversion device PD1 can be read into the floating diffusion regions FD1 and FD2. By turning on the selection transistor SEL, the pixel signal Vimg having information of the phase of incident light of the photoelectric conversion device PD1 can be output.

[0108] In the reading of the charges of the photoelectric conversion device PD2, similarly, by turning on the conversion efficiency transistor FDG, the transfer transistor TG2a, and the selection transistor SEL while the conversion efficiency transistor FCG and the transfer transistor TG1a are off, the pixel signal Vimg having information of the phase of incident light of the photoelectric conversion device PD2 can be output.

[0109] By comparing the pixel signals Vimg having information of the phase of incident light of the photoelectric conversion devices PD1 and PD2, it is possible to detect an image plane phase difference. Although an example in which charges are read in the order of the photoelectric conversion devices PD1 and PD2 has been described above, the charges may be read in the reverse order.

[0110] Subsequently, an example of the LOFIC drive will be described. First, by turning on the conversion efficiency transistor FDG and the selection transistor SEL while the conversion efficiency transistor FCG and the transfer transistors TG1a and TG2a are off, it is possible to read the potentials of the floating diffusion regions FD1 and FD2 at the reset level. This allows the pixel signal Vimg at the reset level used for CDS on the pixel signal Vimg of medium conversion efficiency (MCG) described later to be output.

[0111] By turning on the selection transistor SEL while the conversion efficiency transistors FCG and FDG and the transfer transistors TG1a and TG2a are off, it is possible to read the potential of the floating diffusion region FD1 at the reset level. This allows the pixel signal Vimg at the reset level corresponding to the pixel signal Vimg with high conversion efficiency (HCG).

[0112] By turning on the transfer transistors TG1a and TG2a while the conversion efficiency transistors FCG and FDG are off, it is possible to transfer the charges accumulated in the photoelectric conversion devices PD1 and PD2 to the floating diffusion region FD1. By turning on the selection transistor SEL, it is possible to read the charges from the floating diffusion region FD1 and output the pixel signal Vimg with high conversion efficiency (HCG) at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2.

[0113] By turning on the conversion efficiency transistor FDG and the transfer transistors TG1a and TG2a while the conversion efficiency transistor FCG is off, it is possible to transfer the charges accumulated in the photoelectric conversion devices PD1 and PD2 to the floating diffusion regions FD1 and FD2. By turning on the selection transistor SEL, it is possible to output the pixel signal Vimg with medium conversion efficiency (MCG) at the signal level corresponding to the charges held in the floating diffusion regions FD1 and FD2.

[0114] By turning on the conversion efficiency transistors FCG and FDG, the transfer transistors TG1a and TG2a, and the selection transistor SEL, it is possible to output the pixel signal Vimg with low conversion efficiency (SLCG) at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2 and the overflow charges.

[0115] By turning on the discharge transistor RST, the charges can be discharged from the large pixel 20b and the pixel circuit 21b. By turning on the selection transistor SEL after the discharge of charges, it is possible to output the pixel signal Vimg at the reset level corresponding to the pixel signal Vimg with low conversion efficiency (SLCG).

[0116] The large pixel 20 and the pixel circuit 21 in Fig. 4 are capable of outputting two types of pixel signals Vimg with different conversion efficiencies (i.e., HCG and SLCG). Meanwhile, the large pixel 20b and the pixel circuit 21b in Fig. 12 are capable of outputting three types of pixel signals Vimg with different conversion efficiencies (i.e., HCG, MCG, and SLCG). In the present specification, the driving of the large pixel 20 and the pixel circuit 21 in Fig. 4 is referred to also as two-stage conversion efficiency switching drive. Further, the driving of the large pixel 20b and the pixel circuit 21b in Fig. 12 is referred to also as three-stage conversion efficiency switching drive.

[0117] In the two-stage conversion efficiency switching drive, there is a problem that increasing the conversion efficiency of the pixel signal Vimg with high conversion efficiency (HCG) deteriorates the connection S / N step. Meanwhile, in the three-stage conversion efficiency switching drive, by providing the pixel signal Vimg with medium conversion efficiency (MCG), it is possible to increase the conversion efficiency of the pixel signal Vimg with high conversion efficiency (HCG) without deteriorating the connection S / N step. As a result, the large pixel 20b and the pixel circuit 21b in Fig. 12 is capable of improving low illuminance properties.

[0118] Fig. 13 shows an example in which the size of the transfer transistor TG1a is made larger than the size of the transfer transistor TG2a, similarly to the large pixel 20a according to the second embodiment. The present disclosure is not limited thereto, and the sizes of the transfer transistors TG1a and TG2a may be substantially the same. The configuration of the three-stage conversion efficiency switching drive according to the fourth embodiment of the present disclosure can be applied to any of the first to third embodiments.

[0119] (Fifth embodiment) Fig. 14 is a plan view showing the layout of a large pixel 20c and a pixel circuit 21c according to a fifth embodiment of the present disclosure. The large pixel 20c in Fig. 14 includes transfer transistors TG1c and TG2c respectively corresponding to the transfer transistors TG1a and TG2a in Fig. 13. The transfer transistors TG1c and TG2c in Fig. 14 is different from the transfer transistors TG1a and TG2a in Fig. 13 in terms of the disposed positions and shapes.

[0120] In Fig. 14, the plurality of photoelectric conversion devices PD (i.e., the photoelectric conversion devices PD1 and PD2) is arranged in a plurality of rectangular regions in a plan view. Further, the plurality of transfer transistors TG (i.e., the transfer transistors TG1c and TG2c) is arranged to overlap with corner portions of the above plurality of rectangular regions in a plan view. The transfer transistors TG1c and TG2c each have, for example, a substantially trapezoidal shape.

[0121] More specifically, of a plurality of corner portions of the rectangular region in which the photoelectric conversion device PD is disposed, the transfer transistor TG is disposed in the corner portion in the vicinity of another photoelectric conversion device PD and the floating diffusion region FD1. In the large pixel 20c in Fig. 14, the transfer transistor TG can be disposed at a position closer to the floating diffusion region FD1 as compared with the layout in Fig. 13 and the like.

[0122] In the large pixel 20c in Fig. 14, it is possible to make the size of the floating diffusion region FD1 smaller. As a result, it is possible to improve the conversion efficiency of the charges held in the floating diffusion region FD1 and improve the low illuminance properties.

[0123] Further, in the large pixel 20c in Fig. 14, the device isolation region ISOa shown in Fig. 13 and the like is not provided. That is, the transfer transistors TG1c and TG2c and the floating diffusion region FD1 are not separated by the device isolation region ISO. For this reason, the charges of the photoelectric conversion devices PD1 and PD2 are transferred through a common path (third transfer path) Ps4.

[0124] As shown in Fig. 14, one end of the path Ps4 is provided with the transfer transistors TG1c and TG2c and the other end is provided with the floating diffusion region FD1. The path Ps4 includes, for example, an impurity of the same conductivity type as those of the photoelectric conversion devices PD1 and PD2 and the floating diffusion region FD1.

[0125] Fig. 14 shows an example in which the size of the transfer transistor TG1c is made larger than the size of the transfer transistor TG2c in order to suppress the potential variation. Note that the present disclosure is not limited thereto, and the transfer transistors TG1c and TG2c may have substantially the same size.

[0126] As described above, in the fifth embodiment of the present disclosure, by disposing the transfer transistor TG in the corner portion of the rectangular region in which the photoelectric conversion device PD is provided, the disposed positions of the floating diffusion region FD1 and the plurality of transfer transistors TG can be made closer. As a result, it is possible to make the size of the floating diffusion region FD1 smaller and improve the low illuminance properties. The layout according to the fifth embodiment can be applied to any of the first to fourth embodiments.

[0127] (Sixth embodiment) Fig. 15 is a plan view showing the layout of a large pixel 20d and a pixel circuit 21d according to a sixth embodiment of the present disclosure. Fig. 16 is a cross-sectional view of transfer transistors TG1d and TG2c according to the sixth embodiment of the present disclosure. Fig. 16 illustrates the cross section taken along the line B-B’ in Fig. 15. The transfer transistor TG1d corresponds to the transfer transistor TG1c in Fig. 14.

[0128] As shown in Fig. 16, the transfer transistor TG1d includes an electrode (first gate) 31a including a projecting portion that extends in the depth direction of the semiconductor layer 30. In the present specification, a transistor having the above projecting portion is referred to also as a longitudinal transistor. The projecting portion of the electrode 31a extends to a position deeper than the bottom portion of the device isolation region ISO that separates the transfer transistors TG1d and TG2c, for example.

[0129] The transfer transistor TG2c does not include the above projecting portion, i.e., is not a longitudinal transistor. Note that in Fig. 16, illustration of the drain regions, source regions, and back gate regions of the transfer transistors TG1d and TG2c is omitted.

[0130] By making the transfer transistor TG1d a longitudinal transistor, it is possible to suppress the potential variation and increase the saturated signal amount. In this method, as shown in Fig. 15, it is possible to suppress the potential variation without increasing the size of the transfer transistor TG1d. As a result, it is possible to reduce the size of the large pixel 20d as compared with the large pixel 20c in Fig. 14. Further, by not making the transfer transistor TG2c a longitudinal transistor, it is possible to prevent the control line capacitance connected to the transfer transistor TG2c from increasing and suppress the decrease in drive speed of the large pixel 20d. The transfer transistor TG1d according to the sixth embodiment can be applied to any of the first to fifth embodiments.

[0131] (Seventh embodiment) Fig. 17 is a plan view showing the layout of a large pixel 20e and a pixel circuit 21e according to a seventh embodiment of the present disclosure. Fig. 18 is a cross-sectional view of the transfer transistor TG1d and a transfer transistor TG2d according to the seventh embodiment of the present disclosure. Fig. 18 illustrates the cross section taken along the line B-B’ in Fig. 17. The transfer transistor TG2d corresponds to the transfer transistor TG2c in Fig. 14.

[0132] As shown in Fig. 18, the transfer transistor TG2d includes an electrode (second gate) 31b including a projecting portion that extends in the depth direction of the semiconductor layer 30. That is, the transfer transistor TG2d is a longitudinal transistor. The length of the projecting portion (gate length) of the electrode 31b is longer than the length of the projecting portion of the electrode 31a.

[0133] By making the transfer transistor TG2d a longitudinal transistor, it is possible to improve the charge transfer capability between the photoelectric conversion device PD2 and the floating diffusion region FD1. Further, the projecting portion of the electrode 31b extends to a shallower position than the projecting portion of the electrode 31a. As a result, it is possible to make the control line capacitance connected to the transfer transistor TG2d smaller than the control line capacitance connected to the transfer transistor TG1d. That is, it is possible to prevent the control line capacitance of the transfer transistor TG2d from increasing and suppress the decrease in drive speed of the large pixel 20e.

[0134] (Eighth embodiment) Fig. 19 is a plan view showing the layout of a large pixel 40 and a pixel circuit 41 according to an eighth embodiment of the present disclosure. Fig. 20 is a cross-sectional view of the large pixel 40 and the pixel circuit 41 according to the eighth embodiment of the present disclosure. Fig. 20 illustrates the cross section taken along the line C-C’ in Fig. 10.

[0135] The large pixel 40 in Fig. 20 is different from the large pixel 20 in Fig. 5 in that the plurality of photoelectric conversion devices PD has a structure embedded in a semiconductor substrate (i.e., the semiconductor layer 30). In the present specification, the structure of the large pixel 40 is referred to also as an embedded PD structure. Note that the circuit diagram of the large pixel 40 and the pixel circuit 41 is similar to that in Fig. 12.

[0136] In the large pixel 40, light enters from the lower side in Fig. 20. A lens (On Chip Lens) OCL and a color filter CF are disposed on the light-incident surface side of the semiconductor layer 30. The lens OCL collects incident light on the plurality of photoelectric conversion devices PD in the semiconductor layer 30.

[0137] The color filter CF causes light of a predetermined wavelength, of the incident light on the large pixel 40, to be transmitted therethrough or blocks the light. As the color filter CF, for example, a color filter that causes visible light to be transmitted therethrough or an infrared (IR) pass filter that causes infrared rays (near-infrared rays) to be transmitted can be used. By changing the color filter CF disposed in the large pixel 40, the application of the large pixel 40 can be changed.

[0138] The floating diffusion region FD1 and the like are disposed on the surface of the semiconductor layer 30 opposite to the light-incident surface. Further, the plurality of transfer transistors TG are arranged along the surface opposite to the light-incident surface. Further, the capacitor Cp is disposed to be separated from the surface of the semiconductor layer 30 opposite to the light incident surface, for example. As shown, the capacitor Cp may be disposed in an insulating layer along with gates of TG1 and TG2 (insulating layer unlabeled in Fig. 20 but corresponding to the layer including TG1, TG2 and Cp with the same or similar unlabeled insulating layer shown in at least Figs. 22, 24, 38, 40, 41, and with the same or similar insulating layer not shown but understood to exist in at least Figs. 16, 18, 27, 31, and 35A-B).

[0139] The plurality of photoelectric conversion devices PD and the transfer region TRN are arranged inwardly of the surface of the semiconductor layer 30 opposite to the light-incident surface.

[0140] The adjacent large pixels 40 can be separated by disposing full trench isolation (FFTI) (also called a full trench isolation region) in the semiconductor layer 30. Further, Fig. 20 illustrates the device isolation region ISOa disposed between the photoelectric conversion devices PD1 and PD2 and the floating diffusion region FD1. Note that in Fig. 19, illustration of the device isolation region ISOa is omitted.

[0141] In the large pixel 40 according to the eighth embodiment of the present disclosure, it is possible to reduce the size of the large pixel 40 by embedding the photoelectric conversion device PD and the transfer region TRN in the semiconductor layer 30.

[0142] Further, in the large pixel 40 in Fig. 19, the size of the transfer transistor TG1 is larger than the size of the transfer transistor TG2. As a result, as shown in Fig. 20, a distance d1 between the photoelectric conversion device PD1 and the floating diffusion region FD1 on the surface of the semiconductor layer 30 opposite to the light-incident surface can be made larger than a distance d2 between the photoelectric conversion device PD2 and the floating diffusion region FD1. As a result, it is possible to suppress the potential variation of the transfer transistor TG1 and increase the saturated signal amount of the photoelectric conversion device PD, similarly to the large pixel 20a in Fig. 8.

[0143] (Ninth embodiment) Fig. 21 is a plan view showing the layout of a large pixel 40a and a pixel circuit 41a according to a ninth embodiment of the present disclosure. Fig. 22 is a cross-sectional view of the large pixel 40a and the pixel circuit 41a according to the ninth embodiment of the present disclosure. Fig. 22 illustrates the cross section taken along the line D-D’ in Fig. 21. In the large pixel 40a in Fig. 21, the transfer transistors TG1 and TG2 are disposed to be adjacent to each other at positions closer to each other than the large pixel 40 in Fig. 19.

[0144] Further, the large pixel 40a in Fig. 22 does not include the device isolation region ISOa shown in Fig. 20. That is, the transfer transistors TG1 and TG2 and the floating diffusion region FD1 are not separated by the device isolation region ISO. For this reason, the charges of the photoelectric conversion devices PD1 and PD2 are transferred through a common path Ps4. As shown in Fig. 21, one end of the path Ps4 is provided with the transfer transistors TG1 and TG2, and the other end is provided with the floating diffusion region FD1. More specifically, one end of the path Ps4 is provided with the drain regions or source regions of the transfer transistors TG1 and TG2.

[0145] In the large pixel 40a in Fig. 21, since the transfer transistors TG1 and TG2 can be disposed at positions closer to the floating diffusion region FD1, it is possible to reduce the size of the floating diffusion region FD1. As a result, it is possible to improve the conversion efficiency of the charges held in the floating diffusion region FD1 and improve the low illuminance properties.

[0146] The large pixel 40a in Fig. 21 includes the floating diffusion region FD3 and the conversion efficiency transistor FCG. That is, the large pixel 40a has the configuration of the three-stage conversion efficiency switching drive. Note that the floating diffusion region FD3 and the conversion efficiency transistor FCG may be omitted from the large pixel 40a, and the configuration of the two-stage conversion efficiency switching drive may also be used.

[0147] Note that in the example of Fig. 22, the transfer transistor TG2 and the photoelectric conversion device PD2 are disposed on the left side of Fig. 22, and the transfer transistor TG1 and the photoelectric conversion device PD1 are disposed on the right side of Fig. 22. The photoelectric conversion device PD2 is disposed at a position closer to the floating diffusion region FD3, as compared with the photoelectric conversion device PD1.

[0148] As described above, in the large pixel 40a according to the ninth embodiment of the present disclosure, the device isolation region ISOa is omitted and the transfer transistors TG1 and TG2 are disposed at positions close to each other. As a result, it is possible to reduce the size of the floating diffusion region FD1 and improve the low illuminance properties.

[0149] (Tenth embodiment) Fig. 23 is a plan view showing the layout of a large pixel 40b and a pixel circuit 41b according to a tenth embodiment of the present disclosure. Fig. 24 is a cross-sectional view of the large pixel 40b and the pixel circuit 41b according to the tenth embodiment of the present disclosure.

[0150] The large pixel 40b in Fig. 23 is different from the large pixel 40a in Fig. 21 in that the size of the transfer transistor TG1a is larger than the size of the transfer transistor TG2a. As a result, similarly to the large pixel 40 in Fig. 19, it is possible to suppress the potential variation of the transfer transistor TG1a and increase the saturated signal amount of the photoelectric conversion device PD.

[0151] Further, in the large pixel 40b in Fig. 23, the size of the floating diffusion region FD1 can be made smaller than that in the large pixel 40 in Fig. 19. As a result, it is possible to improve the low illuminance properties.

[0152] (Eleventh embodiment) Fig. 25 is a circuit diagram showing configurations of a large pixel 40c and a pixel circuit 41c according to an eleventh embodiment of the present disclosure. Fig. 26 is a plan view showing the layout of the large pixel 40c and the pixel circuit 41c according to the eleventh embodiment of the present disclosure. Fig. 27 is a cross-sectional view of the large pixel 40c and the pixel circuit 41c according to the eleventh embodiment of the present disclosure. Fig. 28 is a diagram showing the potential barrier of the large pixel 40c according to the eleventh embodiment of the present disclosure.

[0153] The large pixel 40c and the pixel circuit 41c in Fig. 25 and Fig. 27 are different from the large pixel 20 and the pixel circuit 21 in Fig. 4 in that they further include a transfer region (third semiconductor region) TRNa, the floating diffusion region (second floating diffusion region) FD3, and the conversion efficiency transistor (fourth transistor) FCG. The transfer region TRNa and the floating diffusion region FD3 are disposed in, for example, the large pixel 40c. The conversion efficiency transistor FCG is disposed in, for example, the pixel circuit 41c.

[0154] The floating diffusion region FD3 holds overflow charges during the exposure period. The floating diffusion region FD3 is connected to the drain of the conversion efficiency transistor FCG and one end of the capacitor Cp. More charges than the floating diffusion regions FD1 and FD2 can be held in the floating diffusion region FD3 and the capacitor Cp.

[0155] The transfer region TRNa directly transfers the overflow charges overflowed from the photoelectric conversion device PD (in Fig. 25, the photoelectric conversion device PD1) to the floating diffusion region FD3.

[0156] The source of the conversion efficiency transistor FCG in Fig. 25 is connected to the floating diffusion region FD2. When the conversion efficiency transistor FCG is in the on-state, it transfers the charges held in the floating diffusion region FD3 to the floating diffusion region FD2. The conversion efficiency transistor FCG is, for example, an NMOS transistor. The conversion efficiency transistor FCG is controlled when a predetermined voltage is applied to the gate thereof from the row drive circuit 12.

[0157] The source of the conversion efficiency transistor (third transistor) FDG in Fig. 25 is connected to the floating diffusion region (first floating diffusion region) FD1, and the drain thereof is connected to the floating diffusion region (third floating diffusion region) FD2. When the conversion efficiency transistor FDG is in the on-state, it transfers at least some of the charges held in the floating diffusion region FD2 to the floating diffusion region FD1.

[0158] During the exposure period, the floating diffusion region FD2 holds at least some of the overflow charges overflowed from the plurality of photoelectric conversion devices PD. Further, the floating diffusion region FD2 is connected to the source of the discharge transistor RST.

[0159] The transfer region TRNa is disposed between the floating diffusion region FD3 and the photoelectric conversion device PD1. More specifically, as shown in Fig. 27, the large pixel 40c has the embedded PD structure. Further, the transfer region TRNa is disposed inward of the surface of the semiconductor layer 30 opposite to the light-incident surface. Note that in the example of Fig. 27, the photoelectric conversion device PD1 is disposed at a position closer to the floating diffusion region FD3, as compared with the photoelectric conversion device PD2.

[0160] The transfer region TRNa may be, for example, a semiconductor region in which an impurity of a first conductivity type (e.g., N-type) is injected, the semiconductor region having an impurity concentration lower than the transfer region TRN. Alternatively, the transfer region TRNa may be a region in which an impurity of a second conductivity type (e.g., P-type) is injected, the region having an impurity concentration higher than the transfer region TRN.

[0161] As shown in Fig. 28, the potential barrier of the transfer region TRNa is larger than the potential barrier of the transfer region TRN and smaller than the potential barrier of the transfer transistor TG2 (and the transfer transistor TG1) in the off-state. As a result, the overflow charges of the plurality of photoelectric conversion devices PD are transferred to the floating diffusion region FD3 via the transfer region TRNa.

[0162] Fig. 27 illustrates a path (fourth transfer path) Ps5 that transfers the charges overflowed from the plurality of photoelectric conversion devices PD to the floating diffusion region FD3. The transfer region TRNa includes at least part of the path Ps5.

[0163] The operations of the large pixel 40c and the pixel circuit 41c in Fig. 25 will be described below. During the exposure period, the transfer transistors TG1 and TG2, the discharge transistor RST, and the selection transistor SEL are off. During the exposure period, overflow charges are transferred to the floating diffusion region FD3 and the capacitor Cp by the transfer region TRNa.

[0164] During the reading period, an image plane phase difference can be detected by turning on the plurality of transfer transistors TG at a plurality of timings.

[0165] Subsequently, an example of the LOFIC drive will be described. First, while turning on the conversion efficiency transistor FDG and the selection transistor SEL while the conversion efficiency transistor FCG and the transfer transistors TG1 and TG2 are off, it is possible to output the pixel signal Vimg at the reset level used for CDS on the pixel signal Vimg with medium conversion efficiency (MCG). Further, by turning on the selection transistor SEL while the conversion efficiency transistors FCG and FDG and the transfer transistors TG1 and TG2 are off, it is possible to output the pixel signal Vimg at the reset level corresponding to the pixel signal Vimg with high conversion efficiency (HCG).

[0166] By turning on the transfer transistors TG1 and TG2 while the conversion efficiency transistors FCG and FDG are off, it is possible to transfer the charges accumulated in the photoelectric conversion devices PD1 and PD2 to the floating diffusion region FD1. By selecting the selection transistor SEL, it is possible to read the charges from the floating diffusion region FD1 and output the pixel signal Vimg with high conversion efficiency (HCG) at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2.

[0167] By turning on the conversion efficiency transistor FDG and the transfer transistors TG1 and TG2 while the conversion efficiency transistor FCG is off, it is possible to transfer the charges accumulated in the photoelectric conversion devices PD1 and PD2 to the floating diffusion regions FD1 and FD2. By selecting the selection transistor SEL, it is possible to output the pixel signal Vimg with medium conversion efficiency (MCG) at the signal level corresponding the charges held in the floating diffusion regions FD1 and FD2.

[0168] By turning on the conversion efficiency transistors FCG and FDG, the transfer transistors TG1 and TG2, and the selection transistor SEL, it is possible to output the pixel signal Vimg with low conversion efficiency (SLCG) at the signal level corresponding to the charges accumulated in the photoelectric conversion devices PD1 and PD2 and the overflow charges accumulated in the capacitor Cp.

[0169] By turning on the discharge transistor RST, it is possible to discharge the charges from the large pixel 40c and the pixel circuit 41c. By turning on the selection transistor SEL after the discharge of charges, it is possible to output the pixel signal Vimg at the reset level corresponding to the pixel signal Vimg with low conversion efficiency (SLCG).

[0170] In the large pixel 40c in Fig. 25, it is unnecessary to transfer the overflow charges of the plurality of photoelectric conversion devices PD to the floating diffusion region FD1 via the transfer transistor TG in the off-state. For this reason, it is possible to simplify the design of the transfer transistor TG.

[0171] (Twelfth embodiment) Fig. 29 is a circuit diagram showing configurations of a large pixel 40d and a pixel circuit 41d according to a twelfth embodiment of the present disclosure. Fig. 30 is a plan view showing the layout of the large pixel 40d and the pixel circuit 41d according to the twelfth embodiment of the present disclosure. Fig. 31 is a cross-sectional view of the large pixel 40d and the pixel circuit 41d according to the twelfth embodiment of the present disclosure. Fig. 32 is a diagram showing the potential barrier of the large pixel 40d according to the twelfth embodiment of the present disclosure.

[0172] The large pixel 40d and the pixel circuit 41d in Fig. 29 are different from the large pixel 40c and the pixel circuit 41c in Fig. 25 in that an overflow gate transistor (fifth transistor) OFG is provided instead of the transfer region TRNa.

[0173] The overflow gate transistor OFG transfers the overflow charges of the plurality of photoelectric conversion devices PD to the floating diffusion region FD3 without passing through the floating diffusion region FD1. The overflow gate transistor OFG is, for example, an NMOS transistor. The source of the overflow gate transistor OFG is connected to either the anode or the cathode (e.g., cathode) of the photoelectric conversion device PD1, and the drain thereof is connected to the floating diffusion region FD3.

[0174] By applying a predetermined bias voltage to the gate of the overflow gate transistor OFG, a transfer region TRNb can be formed between the floating diffusion region FD3 and the photoelectric conversion device PD1. The transfer region TRNb is, for example, a channel region of the overflow gate transistor OFG. Fig. 31 illustrates the formed transfer region TRNb.

[0175] As shown in Fig. 32, the potential barrier of the transfer region TRNb is set to be larger than the potential barrier of the transfer region TRN and smaller than the potential barrier of the transfer transistor TG2 (and the transfer transistor TG1) in the off-state. As a result, the overflow charges of the plurality of photoelectric conversion devices PD are transferred to the floating diffusion region FD3 via the transfer region TRNb.

[0176] The potential barrier of the transfer region TRNb can be controlled by the bias voltage to be applied to the gate of the overflow gate transistor OFG. Note that the potential barrier of the transfer region TRNb may be controlled by adjusting the impurity concentration of the back gate region of the overflow gate transistor OFG.

[0177] The operations of the large pixel 40d and the pixel circuit 41d are similar to those of the large pixel 40c and the pixel circuit 41c in Fig. 25.

[0178] In the large pixel 40d in Fig. 29, the potential barrier of the transfer region TRNb is controlled by the overflow gate transistor OFG. As a result, it is possible to suppress the potential variation of the transfer region TRNb and increase the saturated signal amount.

[0179] (Thirteenth embodiment) Fig. 33 is a circuit diagram showing configurations of a large pixel 40e and a pixel circuit 41e according to a thirteenth embodiment of the present disclosure. Fig. 34 is a plan view showing the layout of the large pixel 40e and the pixel circuit 41e according to the thirteenth embodiment of the present disclosure.

[0180] The large pixel 40e in Fig. 33 includes four small pixels 22a, 22b, 22c, and 22d. The four small pixels 22a to 22d respectively include photoelectric conversion devices PD1, PD2, PD3, and PD4. Further, the small pixels 22a to 22d respectively include transfer transistors TG1, TG2, TG3, and TG4.

[0181] As shown in Fig. 34, the four small pixels 22a to 22d are arranged in the lateral direction and the longitudinal direction in Fig. 34. Each of the four small pixels 22a to 22d includes the lens OCL. In the present specification, the structure of the large pixel 40e in Fig. 34 is referred to also as a 2 × 2 OCL structure.

[0182] The transfer transistors TG1 to TG4 are arranged to face each other at the corner portions of the rectangular regions in which the photoelectric conversion device PD1 to PD4 are arranged in a plan view, for example. As a result, it is possible to reduce the size of the floating diffusion region FD1 and improve the conversion efficiency of the charges held in the floating diffusion region FD1.

[0183] The photoelectric conversion devices PD1 and PD2 are adjacent to each other in the lateral direction in Fig. 34. The photoelectric conversion devices PD3 and PD4 are adjacent to each other in the lateral direction in Fig. 34. The photoelectric conversion devices PD1 and PD4 are adjacent to each other in the longitudinal direction in Fig. 34. The photoelectric conversion devices PD2 and PD3 are adjacent to each other in the longitudinal direction in Fig. 34.

[0184] Between the two photoelectric conversion devices PD adjacent to each other in the lateral direction or longitudinal direction in Fig. 34, the transfer region TRN is disposed. That is, the large pixel 40e includes four transfer regions TRN. The potential barrier of the transfer region TRN in Fig. 34 is similar to that in Fig. 7.

[0185] Fig. 35A and Fig. 35B are each a cross-sectional view of the large pixel 40d and the pixel circuit 41d according to the thirteenth embodiment of the present disclosure. Fig. 35A shows the cross section taken along the line E-E’ in Fig. 34. Fig. 35A illustrates the photoelectric conversion devices PD1 and PD4, the transfer transistors TG1 and TG4, and the amplifier transistor AMP. Further, Fig. 35A illustrates rear deep trench isolation (RDTI) that separates the two adjacent large pixels 40e. Fig. 35B illustrates the photoelectric conversion devices PD1 and PD4 and the transfer region TRN.

[0186] The large pixel 40e is capable of detecting an image plane phase difference in the lateral direction in Fig. 34 and an image plane phase difference in the longitudinal direction. In the detection of an image plane phase difference in the lateral direction, first, the transfer transistors TG1 and TG4 are turned on simultaneously to read the charges of the photoelectric conversion devices PD1 and PD4 simultaneously. Subsequently, the transfer transistors TG2 and TG3 are turned on simultaneously to read the charges of the photoelectric conversion devices PD2 and PD3 simultaneously. By comparing the pixel signal Vimg based on the charges of the photoelectric conversion devices PD1 and PD4 and the pixel signal Vimg based on the charges of the photoelectric conversion devices PD2 and PD3, it is possible to detect the image plane phase difference in the lateral direction.

[0187] In the detection of an image plane phase difference in the longitudinal direction, first, the transfer transistors TG1 and TG2 are turned on simultaneously to read the charges of the photoelectric conversion devices PD1 and PD2 simultaneously. Subsequently, the transfer transistors TG3 and TG4 are turned on simultaneously to read the charges of the photoelectric conversion devices PD3 and PD4 simultaneously. By comparing the pixel signal Vimg based on the charges of the photoelectric conversion devices PD1 and PD2 and the pixel signal Vimg based on the charges of the photoelectric conversion devices PD3 and PD4, it is possible to detect the image plane phase difference in the longitudinal direction.

[0188] The reading of charges may be performed in the reverse order of the above. Further, the large pixel 40e is capable of performing the LOFIC drive similarly to the large pixel 20 in Fig. 4 and the large pixel 20b in Fig. 12, and expanding the saturated signal amount.

[0189] (Fourteenth embodiment) Fig. 36 is a plan view showing the layout of a large pixel 40f and a pixel circuit 41f according to a fourteenth embodiment of the present disclosure. The large pixel 40f in Fig. 36 includes the transfer transistor TG1d that is a longitudinal transistor. The structure of the transfer transistor TG1d is similar to that in Fig. 16. As a result, it is possible to suppress the potential variation without increasing the size of the transfer transistor TG1d.

[0190] Fig. 36 shows an example in which one transfer transistor TG1d of the four transfer transistors TG included in the large pixel 40f is a longitudinal transistor. The present disclosure is not limited thereto, and the large pixel 40f may include a plurality of longitudinal transistors. For example, two transfer transistors TG disposed diagonally relative to each other (e.g., the transfer transistors TG1d and TG3) may be longitudinal transistor.

[0191] Further, similarly to Fig. 18, some of the four transfer transistors TG may be longitudinal transistors having long gate length and the others may be longitudinal transistors having short gate lengths.

[0192] (Fifteenth embodiment) The large pixel, and the photoelectric conversion device PD, the transistor, the floating diffusion region, and the like in the pixel circuit may be disposed in a plurality of layers. Fig. 37A is a plan view showing the layout of a first layer (first substrate) L1 of a large pixel 40g and a pixel circuit 41g according to a fifteenth embodiment of the present disclosure. Fig. 37B is a plan view showing the layout of a second layer (second substrate) L2 of the large pixel 40g and the pixel circuit 41g according to the fifteenth embodiment of the present disclosure. Fig. 38 is a cross-sectional view of the large pixel 40g and the pixel circuit 41g according to the fifteenth embodiment of the present disclosure. Fig. 38 illustrates the cross section taken along the line G-G’ in Fig. 37A and Fig. 37B.

[0193] The first layer L1 and the second layer L2 are stacked in this order from the light-incident surface side of the light detection device 10. In the present specification, the configuration of the large pixel 40g is referred to also as a two-stage pixel configuration.

[0194] In the first layer L1 in Fig. 37A, for example, the plurality of transfer transistors TG, the conversion efficiency transistor FDG, and the floating diffusion regions FD1 and FD2 are disposed. Further, in the first layer L1, the photoelectric conversion devices PD1 and PD2 (not shown in Fig. 37A) are disposed. As the plurality of transfer transistors TG, for example, the transfer transistor TG1a having a large size and the transfer transistor TG2a having a small size are disposed.

[0195] The floating diffusion regions FD1 and FD2 are separated by STI, and the photoelectric conversion devices PD1 and PD2 are separated by STI. Note that a semiconductor region in which an impurity of a second conductivity type (e.g., P-typed) is injected may be disposed instead of STI.

[0196] For example, the discharge transistor RST, the amplifier transistor AMP, the selection transistor SEL, the conversion efficiency transistor FCG, and the floating diffusion region FD3 are disposed in the second layer L2 in Fig. 37B. Note that the capacitor Cp (not shown in 37B and Fig. 38) may be disposed in the second layer L2.

[0197] For example, an insulation film such as a silicon oxide film (SiO2) is disposed between the transfer transistor TG of the first layer L1 and the transistor on the second layer L2. Further, for example, a charge transfer path formed of silicon (Si) is disposed between the transistors on the second layer L2.

[0198] In the large pixel 40g and the pixel circuit 41g, by disposing the components in the first layer L1 and the second layer L2, it is possible to reduce the pixel size.

[0199] Further, by causing the region (fourth semiconductor region) of a first conductivity type (e.g., N-type) having a high concentration, which is disposed in the first layer L1, to include only the plurality of photoelectric conversion devices PD (and the transfer region TRN) and the floating diffusion regions FD1 and FD2, it is possible to limit the transfer destination of the overflow charges of the photoelectric conversion device PD to the floating diffusion regions FD1 and FD2. For this reason, even if the potential barrier of the transfer transistor TG1 is increased, there is no risk of overflow charges overflowing to regions other than the floating diffusion regions FD1 and FD2. As a result, it is possible to increase the saturated signal amount.

[0200] The above layout of the first layer L1 can be realized by, for example, injecting an impurity of a first conductivity type at a high concentration into the plurality of photoelectric conversion devices PD and the floating diffusion regions FD1 and FD2; and injecting an impurity of a second conductivity type into the other regions of the first layer L1, making the other regions insulation regions, or injecting an impurity of a first conductivity type at a low concentration into the other regions.

[0201] (Sixteenth embodiment) In the two-stage pixel configuration, the longitudinal transistor shown in Fig. 16 may be disposed. Fig. 39A is a plan view showing the layout of the first layer L1 of a large pixel 40h and a pixel circuit 41h according to a sixteenth embodiment of the present disclosure. Fig. 39B is a plan view showing the layout of the second layer L2 of the large pixel 40h and the pixel circuit 41h according to the sixteenth embodiment of the present disclosure. Fig. 40 is a cross-sectional view of the large pixel 40h and the pixel circuit 41h according to the sixteenth embodiment according to the present disclosure.

[0202] As the transfer transistor TG in Fig. 39A, the transfer transistor TG1d that is a longitudinal transistor and the transfer transistor TG2 that is not a longitudinal transistor are disposed. Note that the transfer transistor TG2 may include a longitudinal transistor having a short gate, similarly to Fig. 18. As a result, it is possible to suppress the potential variation without increasing the size of the transfer transistor TG1d.

[0203] (Seventeenth embodiment) The large pixel and the pixel circuit may include three or more layers. Fig. 41 is a cross-sectional view of a large pixel 40i and a pixel circuit 41i according to a seventeenth embodiment of the present disclosure. The large pixel 40i and the pixel circuit 41i have a three-stage pixel configuration including the first layer L1, the second layer L2, and a third layer (third substrate) L3. The first layer L1, the second layer L2, and the third layer L3 are stacked in this order from the light-incident surface side.

[0204] In the third layer L3, for example, one or more logic transistors LTr are disposed. Fig. 41 illustrates a junction (e.g., Cu-Cu boding) disposed between the first layer L1 and the second layer L2.

[0205] As described above, in the three-stage pixel configuration, the logic transistor LTr forming a logic circuit or the like can be mounted.

[0206] (Application examples) The technology according to the present disclosure is applicable to various products. For example, the technology according to the present disclosure may be realized as an apparatus installed in any kind of moving object such as automobiles, electric cars, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, robots, construction equipment, and agricultural machinery (tractors).

[0207] Fig. 42 is a block diagram depicting an example of schematic configuration of a vehicle control system 7000 as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. In the example depicted in Fig. 42, the vehicle control system 7000 includes a driving system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detecting unit 7400, an in-vehicle information detecting unit 7500, and an integrated control unit 7600. The communication network 7010 connecting the plurality of control units to each other may, for example, be a vehicle-mounted communication network compliant with an arbitrary standard such as controller area network (CAN), local interconnect network (LIN), local area network (LAN), FlexRay (registered trademark), or the like.

[0208] Each of the control units includes: a microcomputer that performs arithmetic processing according to various kinds of programs; a storage section that stores the programs executed by the microcomputer, parameters used for various kinds of operations, or the like; and a driving circuit that drives various kinds of control target devices. Each of the control units further includes: a network interface (I / F) for performing communication with other control units via the communication network 7010; and a communication I / F for performing communication with a device, a sensor, or the like within and without the vehicle by wire communication or radio communication. A functional configuration of the integrated control unit 7600 illustrated in Fig. 42 includes a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning section 7640, a beacon receiving section 7650, an in-vehicle device I / F 7660, a sound / image output section 7670, a vehicle-mounted network I / F 7680, and a storage section 7690. The other control units similarly include a microcomputer, a communication I / F, a storage section, and the like.

[0209] The driving system control unit 7100 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 7100 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like. The driving system control unit 7100 may have a function as a control device of an antilock brake system (ABS), electronic stability control (ESC), or the like.

[0210] The driving system control unit 7100 is connected with a vehicle state detecting section 7110. The vehicle state detecting section 7110, for example, includes at least one of a gyro sensor that detects the angular velocity of axial rotational movement of a vehicle body, an acceleration sensor that detects the acceleration of the vehicle, and sensors for detecting an amount of operation of an accelerator pedal, an amount of operation of a brake pedal, the steering angle of a steering wheel, an engine speed or the rotational speed of wheels, and the like. The driving system control unit 7100 performs arithmetic processing using a signal input from the vehicle state detecting section 7110, and controls the internal combustion engine, the driving motor, an electric power steering device, the brake device, and the like.

[0211] The body system control unit 7200 controls the operation of various kinds of devices provided to the vehicle body in accordance with various kinds of programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 7200. The body system control unit 7200 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0212] The battery control unit 7300 controls a secondary battery 7310, which is a power supply source for the driving motor, in accordance with various kinds of programs. For example, the battery control unit 7300 is supplied with information about a battery temperature, a battery output voltage, an amount of charge remaining in the battery, or the like from a battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and performs control for regulating the temperature of the secondary battery 7310 or controls a cooling device provided to the battery device or the like.

[0213] The outside-vehicle information detecting unit 7400 detects information about the outside of the vehicle including the vehicle control system 7000. For example, the outside-vehicle information detecting unit 7400 is connected with at least one of an imaging section 7410 and an outside-vehicle information detecting section 7420. The imaging section 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside-vehicle information detecting section 7420, for example, includes at least one of an environmental sensor for detecting current atmospheric conditions or weather conditions and a peripheral information detecting sensor for detecting another vehicle, an obstacle, a pedestrian, or the like on the periphery of the vehicle including the vehicle control system 7000.

[0214] The environmental sensor, for example, may be at least one of a rain drop sensor detecting rain, a fog sensor detecting a fog, a sunshine sensor detecting a degree of sunshine, and a snow sensor detecting a snowfall. The peripheral information detecting sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR device (Light detection and Ranging device, or Laser imaging detection and ranging device). Each of the imaging section 7410 and the outside-vehicle information detecting section 7420 may be provided as an independent sensor or device, or may be provided as a device in which a plurality of sensors or devices are integrated.

[0215] Fig. 43 depicts an example of installation positions of the imaging section 7410 and the outside-vehicle information detecting section 7420. Imaging sections 7910, 7912, 7914, 7916, and 7918 are, for example, disposed at at least one of positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 7900 and a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 7910 provided to the front nose and the imaging section 7918 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 7900. The imaging sections 7912 and 7914 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 7900. The imaging section 7916 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 7900. The imaging section 7918 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0216] Incidentally, Fig. 43 depicts an example of photographing ranges of the respective imaging sections 7910, 7912, 7914, and 7916. An imaging range a represents the imaging range of the imaging section 7910 provided to the front nose. Imaging ranges b and c respectively represent the imaging ranges of the imaging sections 7912 and 7914 provided to the sideview mirrors. An imaging range d represents the imaging range of the imaging section 7916 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 7900 as viewed from above can be obtained by superimposing image data imaged by the imaging sections 7910, 7912, 7914, and 7916, for example.

[0217] Outside-vehicle information detecting sections 7920, 7922, 7924, 7926, 7928, and 7930 provided to the front, rear, sides, and corners of the vehicle 7900 and the upper portion of the windshield within the interior of the vehicle may be, for example, an ultrasonic sensor or a radar device. The outside-vehicle information detecting sections 7920, 7926, and 7930 provided to the front nose of the vehicle 7900, the rear bumper, the back door of the vehicle 7900, and the upper portion of the windshield within the interior of the vehicle may be a LIDAR device, for example. These outside-vehicle information detecting sections 7920 to 7930 are used mainly to detect a preceding vehicle, a pedestrian, an obstacle, or the like.

[0218] Returning to Fig. 42, the description will be continued. The outside-vehicle information detecting unit 7400 makes the imaging section 7410 image an image of the outside of the vehicle, and receives imaged image data. In addition, the outside-vehicle information detecting unit 7400 receives detection information from the outside-vehicle information detecting section 7420 connected to the outside-vehicle information detecting unit 7400. In a case where the outside-vehicle information detecting section 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detecting unit 7400 transmits an ultrasonic wave, an electromagnetic wave, or the like, and receives information of a received reflected wave. On the basis of the received information, the outside-vehicle information detecting unit 7400 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto. The outside-vehicle information detecting unit 7400 may perform environment recognition processing of recognizing a rainfall, a fog, road surface conditions, or the like on the basis of the received information. The outside-vehicle information detecting unit 7400 may calculate a distance to an object outside the vehicle on the basis of the received information.

[0219] In addition, on the basis of the received image data, the outside-vehicle information detecting unit 7400 may perform image recognition processing of recognizing a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto. The outside-vehicle information detecting unit 7400 may subject the received image data to processing such as distortion correction, alignment, or the like, and combine the image data imaged by a plurality of different imaging sections 7410 to generate a bird’s-eye image or a panoramic image. The outside-vehicle information detecting unit 7400 may perform viewpoint conversion processing using the image data imaged by the imaging section 7410 including the different imaging parts.

[0220] The in-vehicle information detecting unit 7500 detects information about the inside of the vehicle. The in-vehicle information detecting unit 7500 is, for example, connected with a driver state detecting section 7510 that detects the state of a driver. The driver state detecting section 7510 may include a camera that images the driver, a biosensor that detects biological information of the driver, a microphone that collects sound within the interior of the vehicle, or the like. The biosensor is, for example, disposed in a seat surface, the steering wheel, or the like, and detects biological information of an occupant sitting in a seat or the driver holding the steering wheel. On the basis of detection information input from the driver state detecting section 7510, the in-vehicle information detecting unit 7500 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing. The in-vehicle information detecting unit 7500 may subject an audio signal obtained by the collection of the sound to processing such as noise canceling processing or the like.

[0221] The integrated control unit 7600 controls general operation within the vehicle control system 7000 in accordance with various kinds of programs. The integrated control unit 7600 is connected with an input section 7800. The input section 7800 is implemented by a device capable of input operation by an occupant, such, for example, as a touch panel, a button, a microphone, a switch, a lever, or the like. The integrated control unit 7600 may be supplied with data obtained by voice recognition of voice input through the microphone. The input section 7800 may, for example, be a remote control device using infrared rays or other radio waves, or an external connecting device such as a mobile telephone, a personal digital assistant (PDA), or the like that supports operation of the vehicle control system 7000. The input section 7800 may be, for example, a camera. In that case, an occupant can input information by gesture. Alternatively, data may be input which is obtained by detecting the movement of a wearable device that an occupant wears. Further, the input section 7800 may, for example, include an input control circuit or the like that generates an input signal on the basis of information input by an occupant or the like using the above-described input section 7800, and which outputs the generated input signal to the integrated control unit 7600. An occupant or the like inputs various kinds of data or gives an instruction for processing operation to the vehicle control system 7000 by operating the input section 7800.

[0222] The storage section 7690 may include a read only memory (ROM) that stores various kinds of programs executed by the microcomputer and a random access memory (RAM) that stores various kinds of parameters, operation results, sensor values, or the like. In addition, the storage section 7690 may be implemented by a magnetic storage device such as a hard disc drive (HDD) or the like, a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0223] The general-purpose communication I / F 7620 is a communication I / F used widely, which communication I / F mediates communication with various apparatuses present in an external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as global system for mobile communications (GSM (registered trademark)), worldwide interoperability for microwave access (WiMAX (registered trademark)), long term evolution (LTE (registered trademark)), LTE-advanced (LTE-A), or the like, or another wireless communication protocol such as wireless LAN (referred to also as wireless fidelity (Wi-Fi (registered trademark)), Bluetooth (registered trademark), or the like. The general-purpose communication I / F 7620 may, for example, connect to an apparatus (for example, an application server or a control server) present on an external network (for example, the Internet, a cloud network, or a company-specific network) via a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal present in the vicinity of the vehicle (which terminal is, for example, a terminal of the driver, a pedestrian, or a store, or a machine type communication (MTC) terminal) using a peer to peer (P2P) technology, for example.

[0224] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol developed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such, for example, as wireless access in vehicle environment (WAVE), which is a combination of institute of electrical and electronic engineers (IEEE) 802.11p as a lower layer and IEEE 1609 as a higher layer, dedicated short range communications (DSRC), or a cellular communication protocol. The dedicated communication I / F 7630 typically carries out V2X communication as a concept including one or more of communication between a vehicle and a vehicle (Vehicle to Vehicle), communication between a road and a vehicle (Vehicle to Infrastructure), communication between a vehicle and a home (Vehicle to Home), and communication between a pedestrian and a vehicle (Vehicle to Pedestrian).

[0225] The positioning section 7640, for example, performs positioning by receiving a global navigation satellite system (GNSS) signal from a GNSS satellite (for example, a GPS signal from a global positioning system (GPS) satellite), and generates positional information including the latitude, longitude, and altitude of the vehicle. Incidentally, the positioning section 7640 may identify a current position by exchanging signals with a wireless access point, or may obtain the positional information from a terminal such as a mobile telephone, a personal handyphone system (PHS), or a smart phone that has a positioning function.

[0226] The beacon receiving section 7650, for example, receives a radio wave or an electromagnetic wave transmitted from a radio station installed on a road or the like, and thereby obtains information about the current position, congestion, a closed road, a necessary time, or the like. Incidentally, the function of the beacon receiving section 7650 may be included in the dedicated communication I / F 7630 described above.

[0227] The in-vehicle device I / F 7660 is a communication interface that mediates connection between the microcomputer 7610 and various in-vehicle devices 7760 present within the vehicle. The in-vehicle device I / F 7660 may establish wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or wireless universal serial bus (WUSB). In addition, the in-vehicle device I / F 7660 may establish wired connection by universal serial bus (USB), high-definition multimedia interface (HDMI (registered trademark)), mobile high-definition link (MHL), or the like via a connection terminal (and a cable if necessary) not depicted in the figures. The in-vehicle devices 7760 may, for example, include at least one of a mobile device and a wearable device possessed by an occupant and an information device carried into or attached to the vehicle. The in-vehicle devices 7760 may also include a navigation device that searches for a path to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0228] The vehicle-mounted network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The vehicle-mounted network I / F 7680 transmits and receives signals or the like in conformity with a predetermined protocol supported by the communication network 7010.

[0229] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various kinds of programs on the basis of information obtained via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning section 7640, the beacon receiving section 7650, the in-vehicle device I / F 7660, and the vehicle-mounted network I / F 7680. For example, the microcomputer 7610 may calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the obtained information about the inside and outside of the vehicle, and output a control command to the driving system control unit 7100. For example, the microcomputer 7610 may perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like. In addition, the microcomputer 7610 may perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the obtained information about the surroundings of the vehicle.

[0230] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and an object such as a surrounding structure, a person, or the like, and generate local map information including information about the surroundings of the current position of the vehicle, on the basis of information obtained via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning section 7640, the beacon receiving section 7650, the in-vehicle device I / F 7660, and the vehicle-mounted network I / F 7680. In addition, the microcomputer 7610 may predict danger such as collision of the vehicle, approaching of a pedestrian or the like, an entry to a closed road, or the like on the basis of the obtained information, and generate a warning signal. The warning signal may, for example, be a signal for producing a warning sound or lighting a warning lamp.

[0231] The sound / image output section 7670 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 42, an audio speaker 7710, a display section 7720, and an instrument panel 7730 are illustrated as the output device. The display section 7720 may, for example, include at least one of an on-board display and a head-up display. The display section 7720 may have an augmented reality (AR) display function. The output device may be other than these devices, and may be another device such as headphones, a wearable device such as an eyeglass type display worn by an occupant or the like, a projector, a lamp, or the like. In a case where the output device is a display device, the display device visually displays results obtained by various kinds of processing performed by the microcomputer 7610 or information received from another control unit in various forms such as text, an image, a table, a graph, or the like. In addition, in a case where the output device is an audio output device, the audio output device converts an audio signal constituted of reproduced audio data or sound data or the like into an analog signal, and auditorily outputs the analog signal.

[0232] Incidentally, at least two control units connected to each other via the communication network 7010 in the example depicted in Fig. 42 may be integrated into one control unit. Alternatively, each individual control unit may include a plurality of control units. Further, the vehicle control system 7000 may include another control unit not depicted in the figures. In addition, part or the whole of the functions performed by one of the control units in the above description may be assigned to another control unit. That is, predetermined arithmetic processing may be performed by any of the control units as long as information is transmitted and received via the communication network 7010. Similarly, a sensor or a device connected to one of the control units may be connected to another control unit, and a plurality of control units may mutually transmit and receive detection information via the communication network 7010.

[0233] In the vehicle control system 7000, the light detection device 10 according to this embodiment described with reference to Fig. 2 is applicable to the imaging section 7410 in the application example shown in Fig. 42. This allows the dynamic range to be expanded and clear image data to be generated even in dark places while realizing the function of the imaging section 7410.

[0234] Note that the present technology may also take the following configurations. (1)　A light detection device, including: a plurality of photoelectric conversion devices that each accumulates charges corresponding to an amount of incident light; a first floating diffusion region that is shared by the plurality of photoelectric conversion devices and holds the charges transferred from the plurality of photoelectric conversion devices; a plurality of transfer circuits that transfers the charges accumulated in the plurality of photoelectric conversion devices to the first floating diffusion region; a first semiconductor region that is disposed between two adjacent photoelectric conversion devices of the plurality of photoelectric conversion devices and transfers the charges overflowed from one of the two photoelectric conversion devices to another of the two photoelectric conversion devices; a second floating diffusion region and a capacitor that hold the charges overflowed from the plurality of photoelectric conversion devices; and a pixel circuit that reads the charges held in the first floating diffusion region and the second floating diffusion region or separately reads the charges accumulated in some of the plurality of photoelectric conversion devices and the charges accumulated in the other photoelectric conversion devices. (2)　The light detection device according to (1), further including a plurality of pixels that includes corresponding photoelectric conversion devices and transfer circuits of the plurality of photoelectric conversion devices and the plurality of transfer circuits and shares the pixel circuit, the pixel circuit switching between collecting and reading the charges obtained by photoelectric conversion by the plurality of photoelectric conversion devices in the plurality of pixels, separately reading the charges obtained by photoelectric conversion by the plurality of photoelectric conversion devices, and separately reading the charges accumulated in some of the plurality of photoelectric conversion devices and the charges accumulated in the other photoelectric conversion devices. (3)　The light detection device according to (1) or (2), in which the plurality of photoelectric conversion devices includes a first photoelectric conversion device and a second photoelectric conversion device disposed adjacent to the first photoelectric conversion device, the plurality of transfer circuits includes a first transistor that transfers the charges of the first photoelectric conversion device to the first floating diffusion region and a second transistor that transfers the charges of the second photoelectric conversion device to the first floating diffusion region, and the first semiconductor region is disposed between the first photoelectric conversion device and the second photoelectric conversion device and transfers the charges overflowed from one of the first photoelectric conversion device and the second photoelectric conversion device to the other. (4)　The light detection device according to (3), in which the first transistor has a potential barrier smaller than that of the second transistor, and the first transistor has a potential variation smaller than that of the second transistor. (5)　The light detection device according to (3) or (4), in which the first transistor has substantially the same size as the second transistor. (6)　The light detection device according to (3) or (4), in which the first transistor has a larger size than the second transistor. (7)　The light detection device according to any one of (3) to (6), in which a distance between a gate electrode and a source region or a drain region of the first transistor is larger than a distance between a gate electrode and a source region or a drain region of the second transistor. (8)　The light detection device according to any one of (3) to (7), in which the plurality of photoelectric conversion devices is arranged in a plurality of rectangular regions in a plan view, and the plurality of transfer circuits is arranged to overlap with corner portions of the plurality of rectangular regions in a plan view. (9)　The light detection device according to any one of (3) to (8), further including a semiconductor layer in which the plurality of photoelectric conversion devices is arranged, the first transistor including a first gate extending in a depth direction of the semiconductor layer. (10) The light detection device according to (9), in which the second transistor includes a second gate extending in the depth direction of the semiconductor layer, and a gate length of the first gate in the depth direction of the semiconductor layer is longer than a gate length of the second gate. (11) The light detection device according to any one of (3) to (10), further including a semiconductor layer in which the plurality of transfer circuits is arranged along a surface opposite to a light-incident surface, the plurality of photoelectric conversion devices and the first semiconductor region being arranged inwardly of the opposite surface. (12) The light detection device according to any one of (3) to (11), further including: a first transfer path that transfers charges from the first photoelectric conversion device to the first floating diffusion region; a second transfer path that transfer charges from the second photoelectric conversion device to the first floating diffusion region; and a second semiconductor region or an insulation region that separates the first transfer path and the second transfer path from each other, the second semiconductor region having the same conductive type as the first semiconductor region and having a lower impurity concentration than the first semiconductor region or being of a conductive type opposite to that of the first semiconductor region. (13) The light detection device according to any one of (3) to (11), further including a third transfer path that transfers charges from the first photoelectric conversion device to the first floating diffusion region and transfers charges from the second photoelectric conversion device to the first floating diffusion region, the first transistor and the second transistor being disposed on one end of the third transfer path, the first floating diffusion region being disposed on another end of the third transfer path. (14) The light detection device according to any one of (3) to (13), further including a third transistor that transfers the charges overflowed from the plurality of photoelectric conversion devices and the first floating diffusion region to the second floating diffusion region. (15) The light detection device according to any one of (3) to (13), further including: a third floating diffusion region that holds at least some of the charges overflowed from the plurality of photoelectric conversion devices; a third transistor that transfers at least some of the charges held in the second floating diffusion region to the first floating diffusion region; and a fourth transistor that transfers at least some of the charges held in the third floating diffusion region to the second floating diffusion region. (16) The light detection device according to any one of (3) to (13), further including: a third floating diffusion region that holds at least some of the charges overflowed from the plurality of photoelectric conversion devices; a third transistor that transfers at least some of the charges held in the third floating diffusion region to the first floating diffusion region; a fourth transistor that transfers at least some of the charges held in the second floating diffusion region to the third floating diffusion region; and a fifth transistor that transfers the charges overflowed from the plurality of photoelectric conversion devices to the second floating diffusion region without passing through the first floating diffusion region. (17) The light detection device according to any one of (3) to (13), further including: a third floating diffusion region that holds at least some of the charges overflowed from the plurality of photoelectric conversion devices; a third transistor that transfers at least some of the charges held in the third floating diffusion region to the first floating diffusion region; a fourth transistor that transfers at least some of the charges held in the second floating diffusion region to the third floating diffusion region; and a fourth transfer path that transfers at least some of the charges overflowing form the plurality of photoelectric conversion devices to the second floating diffusion region without passing through the first floating diffusion region. (18) The light detection device according to (17), in which the fourth transfer path has a third semiconductor region that is disposed between at least one of the plurality of photoelectric conversion devices and the second floating diffusion region and has a potential barrier lower than those of the first transistor and the second transistor. (19) The light detection device according to any one of (1) to (18), further including: a first substrate that has a fourth semiconductor region in which the plurality of photoelectric conversion devices, the first floating diffusion region, and the first semiconductor region are disposed; and a second substrate that is stacked on the first substrate, the second floating diffusion region being disposed in the second substrate, the fourth semiconductor region of the first substrate including an impurity of a first conductive type, regions of the first substrate other than the fourth semiconductor region including at least one of an impurity of a second conductive type, an impurity of the first conductive type at a concentration lower than that of the fourth semiconductor region, or an insulation region. (20) An electronic apparatus, including: the light detection device according to any one of (1) to (19) that outputs image data; and a signal processing unit that performs signal processing on the image data. (21) An imaging device, comprising: a semiconductor substrate; and a first pixel comprising: a first photoelectric conversion region disposed in the semiconductor substrate; a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view; a first floating diffusion region disposed in the semiconductor substrate; a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; and a second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor. (22) The imaging device of (21), further comprising: an insulating layer on the semiconductor substrate, wherein at least a first portion of the first transistor and at least a second portion of the second transistor are disposed in the insulating layer. (23) The imaging device of one or more of (21) to (22), wherein a second portion of the first transistor and a second portion of the second transistor are disposed in the semiconductor substrate. (24) The imaging device of one or more of (21) to (23), further comprising: an isolation region disposed in the semiconductor substrate between the second portion of the first transistor and the second portion the second transistor. (25) The imaging device of one or more of (21) to (24), wherein, in the plan view, a gate of the first transistor is at a first edge of the first photoelectric conversion region and a gate of the second transistor is a first edge of the second photoelectric conversion region. (26) The imaging device of one or more of (21) to (25), wherein, in the plan view, a gate of the first transistor overlaps with a central region of the first photoelectric conversion region and a gate of the second transistor overlaps with a central region of the second photoelectric conversion region. (27) The imaging device of one or more of (21) to (26), further comprising: a second floating diffusion region; and a third transistor coupled between the first floating diffusion region and the second floating diffusion region. (28) The imaging device of one or more of (21) to (27), further comprising a capacitance coupled to the second floating diffusion region. (29) The imaging device of one or more of (21) to (28), further comprising: a third floating diffusion region; and a fourth transistor coupled between the second floating diffusion region and the third floating diffusion region. (30) The imaging device of one or more of (21) to (29), further comprising a capacitance coupled to the third floating diffusion region. (31) The imaging device of one or more of (21) to (30), further comprising: a semiconductor region of a first conductivity type disposed in the semiconductor substrate between the first photoelectric conversion region and the second photoelectric conversion region. (32) The imaging device of one or more of (21) to (31), wherein the first and second photoelectric conversion regions are of the first conductivity type. (33) The imaging device of one or more of (21) to (32), wherein the semiconductor region has a lower impurity concentration than the first and second photoelectric conversion regions. (34) The imaging device of one or more of (21) to (33), further comprising: a first semiconductor region disposed in the semiconductor substrate, wherein, in the plan view, a gate of the first transistor overlaps the first semiconductor region; and a second semiconductor region disposed in the semiconductor substrate, wherein, in the plan view, a gate of the second transistor overlaps the second semiconductor region, and wherein the first and second semiconductor regions are of a conductivity type opposite to a conductivity type of the first and second photoelectric conversion regions. (35) The imaging device of one or more of (21) to (34), wherein, in the plan view a space between a source or a drain of the first transistor and the gate of the first transistor is greater than a space between a source or a drain of the second transistor and the gate of the second transistor. (36) The imaging device of one or more of (21) to (35), wherein a size of the first semiconductor region is greater than a size of the second semiconductor region. (37) The imaging device of one or more of (21) to (36), further comprising: a second pixel adjacent to the first pixel; and a full trench isolation region disposed in the semiconductor substrate between the first pixel and the second pixel. (38) An electronic apparatus, comprising: a signal processing circuit; and an imaging device, comprising: a semiconductor substrate; and a first pixel comprising: a first photoelectric conversion region disposed in the semiconductor substrate; a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view; a first floating diffusion region disposed in the semiconductor substrate; a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; and a second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor. (39) The electronic apparatus of (38), further comprising: an insulating layer on the semiconductor substrate; a second floating diffusion region; and a third transistor coupled between the first floating diffusion region and the second floating diffusion region; and a capacitance coupled to the second floating diffusion region, wherein the capacitance and gates of the first and second transistors are disposed in the insulating layer. (40) A control system for a vehicle, comprising: a signal processing circuit; and an imaging device, comprising: a semiconductor substrate; and a first pixel comprising: a first photoelectric conversion region disposed in the semiconductor substrate; a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view; a first floating diffusion region disposed in the semiconductor substrate; a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; and a second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor.

[0235] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments and include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned content. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and essence of the present disclosure derived from the content defined in the claims and their equivalents.

[0236] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0237] 1 electronic apparatus 2 imaging lens 3 recording unit 4 control unit 5 transmission line 6 control line 7 signal processing unit 10, 10a light detection device 11 pixel array unit 12 row drive circuit 13 control circuit 14 column signal processing circuit 20, 20a, 20b, 20c, 20d, 20e, 40, 40a, 40b, 40c, 40d, 40e, 40f, 40g, 40h, 40i large pixel 21, 21a, 21b, 21c, 21d, 21e, 41, 41a, 41b, 41c, 41d, 41e, 41f, 41g, 41h, 41i pixel circuit 22a, 22b, 22c, 22d small pixel 30 semiconductor layer 31, 31a, 31b electrode 32, 33, 33a, 33b semiconductor region

Claims

An imaging device, comprising:a semiconductor substrate; anda first pixel comprising:a first photoelectric conversion region disposed in the semiconductor substrate;a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view;a first floating diffusion region disposed in the semiconductor substrate;a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; anda second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor.The imaging device of claim 1, further comprising:an insulating layer on the semiconductor substrate, wherein at least a first portion of the first transistor and at least a second portion of the second transistor are disposed in the insulating layer.The imaging device of claim 2, wherein a second portion of the first transistor and a second portion of the second transistor are disposed in the semiconductor substrate.The imaging device of claim 3, further comprising:an isolation region disposed in the semiconductor substrate between the second portion of the first transistor and the second portion the second transistor.The imaging device of claim 1, wherein, in the plan view, a gate of the first transistor is at a first edge of the first photoelectric conversion region and a gate of the second transistor is a first edge of the second photoelectric conversion region.The imaging device of claim 1, wherein, in the plan view, a gate of the first transistor overlaps with a central region of the first photoelectric conversion region and a gate of the second transistor overlaps with a central region of the second photoelectric conversion region.The imaging device of claim 1, further comprising:a second floating diffusion region; anda third transistor coupled between the first floating diffusion region and the second floating diffusion region.The imaging device of claim 7, further comprising a capacitance coupled to the second floating diffusion region.The imaging device of claim 7, further comprising:a third floating diffusion region; anda fourth transistor coupled between the second floating diffusion region and the third floating diffusion region.The imaging device of claim 9, further comprising a capacitance coupled to the third floating diffusion region.The imaging device of claim 1, further comprising:a semiconductor region of a first conductivity type disposed in the semiconductor substrate between the first photoelectric conversion region and the second photoelectric conversion region.The imaging device of claim 11, wherein the first and second photoelectric conversion regions are of the first conductivity type.The imaging device of claim 12, wherein the semiconductor region has a lower impurity concentration than the first and second photoelectric conversion regions.The imaging device of claim 1, further comprising:a first semiconductor region disposed in the semiconductor substrate, wherein, in the plan view, a gate of the first transistor overlaps the first semiconductor region; anda second semiconductor region disposed in the semiconductor substrate, wherein, in the plan view, a gate of the second transistor overlaps the second semiconductor region, and wherein the first and second semiconductor regions are of a conductivity type opposite to a conductivity type of the first and second photoelectric conversion regions.The imaging device of claim 14, wherein, in the plan view a space between a source or a drain of the first transistor and the gate of the first transistor is greater than a space between a source or a drain of the second transistor and the gate of the second transistor.The imaging device of claim 15, wherein a size of the first semiconductor region is greater than a size of the second semiconductor region.The imaging device of claim 1, further comprising:a second pixel adjacent to the first pixel; anda full trench isolation region disposed in the semiconductor substrate between the first pixel and the second pixel.An electronic apparatus, comprising:a signal processing circuit; andan imaging device, comprising:a semiconductor substrate; anda first pixel comprising:a first photoelectric conversion region disposed in the semiconductor substrate;a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view;a first floating diffusion region disposed in the semiconductor substrate;a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; anda second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor.The electronic apparatus of claim 18, further comprising:an insulating layer on the semiconductor substrate;a second floating diffusion region; anda third transistor coupled between the first floating diffusion region and the second floating diffusion region; anda capacitance coupled to the second floating diffusion region, wherein the capacitance and gates of the first and second transistors are disposed in the insulating layer.A control system for a vehicle, comprising:a signal processing circuit; andan imaging device, comprising:a semiconductor substrate; anda first pixel comprising:a first photoelectric conversion region disposed in the semiconductor substrate;a second photoelectric conversion region disposed in the semiconductor substrate adjacent to the first photoelectric conversion region in a plan view;a first floating diffusion region disposed in the semiconductor substrate;a first transistor coupled to the first photoelectric conversion region and the first floating diffusion region; anda second transistor coupled to the second photoelectric conversion region and the first floating diffusion region, wherein, in the plan view, the second transistor is adjacent to the first transistor and has a different size than the first transistor.

Images