Semiconductor package

Abstract

This semiconductor package has an open portion formed on one end of a conductor track on a base plate and has a connection conductor connected, through direct contact, to a connection pad placed within the open portion, thereby improving the stability of signal transmission for a semiconductor chip group. As the one end of the semiconductor package is open to allow direct contact between the connection pad and the connection conductor, the present invention has a shorter electrical path between the connection pad and an external circuit and thus has the effects of reducing electrical loss during signal transmission and significantly enhancing the stability of signal transmission. The present invention ensures signal quality by minimizing electrical interference when processing high-frequency signals.

Description

semiconductor package

[0001] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package capable of improving the stability of signal transmission of a semiconductor chip group by opening one end of a conductor track formed on a base plate to form an opening, and connecting a connecting conductor by directly contacting it to a connecting pad disposed within the opening.

[0002] Power control semiconductors used in automobiles are critical electronic components responsible for the conversion, distribution, and control of power within the vehicle. These power control semiconductors can be used to ensure a stable power supply to the vehicle's drive system, electronic control units, and various electrical and electronic devices.

[0003] The power control semiconductor is equipped with multiple semiconductor chips, and can receive control signals from an external device to control each semiconductor chip.

[0004] Conventional power control semiconductors partially open the inner side of a conductor track to place a connection pad inside, and connect it to an external connection conductor through a wire, and receive a control signal by connecting the connection pad to a control terminal of a semiconductor chip with a wire.

[0005] These conventional power control semiconductors have a problem in that the connection pads are located inside the conductor track and connected to the connecting conductor via wires, which increases electrical loss and can degrade the stability of signal transmission. In addition, conventional power control semiconductors have a problem in that they are structurally complex because they must form an opening inside the conductor track and attach the wire to the connecting conductor, making the manufacturing process difficult and increasing production costs.

[0006] Conventional power control semiconductors have the problem of reduced semiconductor design flexibility and lower space efficiency due to the limited placement of connection pads.

[0007] The present invention aims to provide a semiconductor package capable of improving the stability of signal transmission of a semiconductor chip group by opening one end of a conductor track formed on a base plate to form an opening, and connecting a connecting conductor by directly contacting it to a connecting pad disposed within the opening.

[0008] A semiconductor package according to the features of the present invention for achieving the above objective comprises: a base plate; first, second, and third conductor tracks formed on the upper portion of the base plate and spaced apart from each other; a fourth conductor track positioned surrounded by the first conductor track; a fifth conductor track positioned surrounded by the second conductor track; first and second connection pads, at least a portion of which is surrounded by the second conductor track; a first semiconductor chip group comprising a plurality of semiconductor chips coupled to the first conductor track; a second semiconductor chip group comprising a plurality of semiconductor chips coupled to the second conductor track; a first input / output connection portion electrically connecting the first semiconductor chip group and the second conductor track; a second input / output connection portion electrically connecting the second semiconductor chip group and the third conductor track; a first bonding wire connecting the fourth conductor track and the first connection pad; a second bonding wire connecting the fifth conductor track and the second connection pad; and one end of which is coupled to the first connection pad and the other end extending to the outside of the base plate. It includes an extended first connecting conductor and a second connecting conductor, one end of which is coupled to the second connecting pad and the other end of which extends to the outside of the base plate, wherein the second conductor track forms first and second openings in an inwardly recessed shape, and the first connecting conductor may be located in the first opening and the second connecting conductor may be located in the second opening.

[0009] With the above-described configuration, when the present invention is configured such that one end of a semiconductor package is opened to directly contact a connection pad and a connection conductor, the electrical path between the connection pad and the external circuit is shortened, thereby reducing electrical loss during signal transmission and significantly improving the stability of signal transmission.

[0010] The present invention has the effect of minimizing electrical interference when processing high-frequency signals, thereby ensuring signal quality.

[0011] The present invention simplifies the structure and facilitates the manufacturing process by forming a connecting pad at an opening at one end of a conductor track, thereby reducing production costs and increasing manufacturing efficiency.

[0012] The present invention simplifies the position of the opening at one end of the conductor track and the arrangement of the connection pad, thereby maximizing space efficiency and increasing the flexibility of semiconductor design; consequently, it has an advantageous effect for the miniaturization and high integration of semiconductor packages.

[0013] FIG. 1 is a diagram showing the configuration of a semiconductor package according to a first embodiment of the present invention.

[0014] FIG. 2 is a drawing showing an enlarged view of region A in a semiconductor package according to the first embodiment of the present invention.

[0015] FIG. 3 is a drawing showing an enlarged view of region B in a semiconductor package according to the first embodiment of the present invention.

[0016] FIG. 4 is a drawing showing an enlarged view of region C in a semiconductor package according to the first embodiment of the present invention.

[0017] FIG. 5 is a diagram showing the configuration of a semiconductor package according to a second embodiment of the present invention.

[0018] FIG. 6 is a drawing showing an enlarged view of region A in a semiconductor package according to a second embodiment of the present invention.

[0019] FIG. 7 is a drawing showing an enlarged view of region B in a semiconductor package according to a second embodiment of the present invention.

[0020] FIG. 8 is a drawing showing an enlarged view of region C in a semiconductor package according to a second embodiment of the present invention.

[0021] FIG. 9 is a diagram showing the configuration of an input / output connection portion in the form of a wire in a semiconductor package according to the first embodiment of the present invention.

[0022] FIG. 10 is a diagram showing the configuration of an input / output connection portion in the form of a clip in a semiconductor package according to a second embodiment of the present invention.

[0023] The present invention is susceptible to various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the invention to specific embodiments, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0024] Terms such as first, second, A, B, etc., may be used to describe various components, but said components shall not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0025] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0026] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0027] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0028] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In order to facilitate an overall understanding of the present invention, the same reference numerals are used for identical components in the drawings, and redundant descriptions of identical components are omitted.

[0029] Hereinafter, the semiconductor package of the present invention will be described with reference to the attached drawings.

[0030] FIG. 1 is a diagram showing the configuration of a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a diagram showing an enlarged view of region A in a semiconductor package according to a first embodiment of the present invention, FIG. 3 is a diagram showing an enlarged view of region B in a semiconductor package according to a first embodiment of the present invention, and FIG. 4 is a diagram showing an enlarged view of region C in a semiconductor package according to a first embodiment of the present invention.

[0031] The semiconductor package (100) of the present invention relates to an electrical connection structure comprising a plurality of conductor tracks formed on a base plate (101), a plurality of semiconductor chip groups connected to the conductor tracks, and connection pads. This structure can enable efficient electrical connection between semiconductor chips and stable connection with an external circuit.

[0032] A semiconductor package (100) according to an embodiment of the present invention may include a base plate (101), a first conductor track (110), a second conductor track (111), a third conductor track (114), a fourth conductor track (115), a fifth conductor track (116), a first connection pad (120), a second connection pad (123), a first semiconductor chip group (140), a second semiconductor chip group (150), a first connection conductor (130), and a second connection conductor (133).

[0033] The base plate (101) can form a first conductor track (110), a second conductor track (111), and a third conductor track (114) spaced apart from each other on its upper surface.

[0034] The first conductor track (110) is formed in a rectangular shape, and the first semiconductor chip group (140) can be configured on the upper surface. The first semiconductor chip group (140) can perform data processing and signal control functions. Each semiconductor chip operates individually and cooperates with others to process signals, thereby enabling smooth data transmission and reception through the control terminal.

[0035] The first semiconductor chip group (140) may include first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d).

[0036] The first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) are inserted into the first chip mounting area (142) and can be arranged in a 2×2 matrix array.

[0037] The first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) are arranged in adjacent positions, thereby maximizing space efficiency and optimizing the transmission of electrical signals.

[0038] The first semiconductor chip group (140) may have a fourth conductor track (115) disposed in the center and may form internal control terminals (147, 148) connected to each semiconductor chip (141a, 141b, 141c, 141d).

[0039] The fourth conductor track (115) may include a fourth-1 conductor track (115a) and a fourth-2 conductor track (115b).

[0040] The 4-1 conductor track (115a) is connected to the 1st, 2nd, 3rd, and 4th semiconductor chips (141a, 141b, 141c, 141d), respectively, and can transmit electrical signals to the chips or provide control signals.

[0041] The 4-1 conductor track (115a) is rectangular in shape and may include a plurality of first internal control terminals (147) and first external control terminals (145a). The first internal control terminals (147) are connected to each semiconductor chip (141a, 141b, 141c, 141d), and the first external control terminals (145a) are connected to an external circuit to transmit electrical signals.

[0042] The 4-2 conductor track (115b) can be formed at a position spaced apart from the 4-1 conductor track (115a) to form a closed-loop structure surrounding the 4-1 conductor track (115a). This closed-loop structure can minimize interference in signal transmission.

[0043] The 4-2 conductor track (115b) is connected to the 1st, 2nd, 3rd, and 4th semiconductor chips (141a, 141b, 141c, 141d), respectively, and can transmit electrical signals to the chips or provide control signals.

[0044] The 4-2 conductor track (115b) is in the shape of a rectangle and may include a plurality of second internal control terminals (148) and second external control terminals (145b). The second internal control terminals (148) are connected to each semiconductor chip (141a, 141b, 141c, 141d), and the second external control terminals (145b) are connected to an external circuit to transmit electrical signals.

[0045] The structure of the first semiconductor chip group (140) can provide high data processing speed and signal transmission stability, and the arrangement of conductor tracks is optimized to prevent electrical interference and maintain signal quality.

[0046] When a specific signal is input to the 4-1 conductor track (115a) through the 1st and 2nd external control terminals (145a, 145b), the signal can be transmitted from the 1st and 2nd internal control terminals (147, 148) to the 1st, 2nd, 3rd, and 4th semiconductor chips (141a, 141b, 141c, 141d) through the 1st and 2nd internal control terminals (147, 148) and the 1st and 2nd external control terminals (145a, 145b). After the 1st, 2nd, 3rd, and 4th semiconductor chips (141a, 141b, 141c, 141d) process the signal, the result data can be output to an external circuit through the 1st and 2nd internal control terminals (147, 148) and the 1st and 2nd external control terminals (145a, 145b).

[0047] The first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) each include a pair of first input / output terminals (143), and the first input / output terminals (143) of the first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) are connected using a first input / output connection part (144).

[0048] A second conductor track (111) has a second semiconductor chip group (150) configured on its upper surface and is spaced apart from the first conductor track (110) and faces each other across two surfaces of the first conductor track (110). It can be formed in the shape of '

[0049] The second conductor track (111) may include a horizontal conductor track (122) electrically connected to the first semiconductor chip group (140) of the first conductor track (110) by a first input / output connection part (144), and a vertical conductor track extending from the horizontal conductor track (122) toward the third conductor track (114), arranging the second semiconductor chip group (150) parallel to the first semiconductor chip group (140), and electrically connecting the second semiconductor chip group (150) to the third conductor track (114) by a second input / output connection part (154).

[0050] The second semiconductor chip group (150) may be formed by arranging the first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) in a 2×2 matrix array.

[0051] The first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) are inserted into the second chip mounting area (152) and can be arranged in a 2×2 matrix array.

[0052] The first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) are arranged in adjacent positions, thereby maximizing space efficiency and optimizing the transmission of electrical signals.

[0053] The second semiconductor chip group (150) may have a fifth conductor track (116) disposed in the center and may form a third internal control terminal (157) connected to each semiconductor chip (151a, 151b, 151c, 151d).

[0054] The fifth conductor track (116) may include the fifth-1 conductor track (116a) and the fifth-2 conductor track (116b).

[0055] The 5-1 conductor track (116a) is connected to the 1st, 2nd, 3rd, and 4th semiconductor chips (151a, 151b, 151c, 151d), respectively, and can transmit electrical signals to the chips or provide control signals.

[0056] The 5-1 conductor track (116a) is rectangular in shape and may include a plurality of first internal control terminals (147) and third external control terminals (155a). The third internal control terminals (157) are connected to each semiconductor chip (151a, 151b, 151c, 151d), and the third external control terminals (155a) are connected to an external circuit to transmit electrical signals.

[0057] The 5-2 conductor track (116b) can be formed at a position spaced apart from the 5-1 conductor track (116a) to form a closed-loop structure surrounding the 5-1 conductor track (116a). This closed-loop structure can minimize interference in signal transmission.

[0058] The 5-2 conductor track (116b) is connected to the 1st, 2nd, 3rd, and 4th semiconductor chips (151a, 151b, 151c, 151d), respectively, and can transmit electrical signals to the chips or provide control signals.

[0059] The 5-2 conductor track (116b) is rectangular in shape and may include a plurality of fourth internal control terminals (158) and a fourth external control terminal (155b). The fourth internal control terminal (158) is connected to each semiconductor chip (151a, 151b, 151c, 151d), and the fourth external control terminal (155b) is connected to an external circuit to transmit an electrical signal.

[0060] The structure of the second semiconductor chip group (150) can provide high data processing speed and signal transmission stability, and the arrangement of conductor tracks is optimized to prevent electrical interference and maintain signal quality.

[0061] When a specific signal is input to the 5-1 conductor track (116a) through the 3rd and 4th external control terminals (155a, 155b), the signal can be transmitted from the 3rd and 4th internal control terminals (157, 158) to the 1st, 2nd, 3rd, and 4th semiconductor chips (151a, 151b, 151c, 151d) through the 2nd bonding wire (156). After the 1st, 2nd, 3rd, and 4th semiconductor chips (151a, 151b, 151c, 151d) process the signal, the result data can be output to an external circuit through the 3rd and 4th internal control terminals (157, 158) and the 3rd and 4th external control terminals (155a, 155b).

[0062] The first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) each include a pair of second input / output terminals (153), and the second input / output terminals (153) of the first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) are connected using a second input / output connection part (154).

[0063] The first connection pad (120) can be electrically connected to the first semiconductor chip group (140) of the first conductor track (110) by the first input / output connection part (144).

[0064] At least one first connecting pad (120) may be formed in a first opening (112a) that is opened to a certain size from one end of the horizontal conductor track (122).

[0065] The second connection pad (123) can be electrically connected to the second semiconductor chip group (150) of the second conductor track (111) and the second input / output connection part (154).

[0066] At least one second connecting pad (123) may be formed in a second opening (113a) that is opened to a certain size from one end of the horizontal conductor track (122), which is located at a certain distance from the first opening (112a) in the horizontal conductor track (122). The first opening (112a) and the second opening (113a) are located at one end of the second conductor track (111) formed on the upper part of the base plate (101), and each is opened to a certain size to provide a structure that accommodates a connecting pad and a connecting conductor. The connecting conductor may extend outward along the longitudinal direction while one end contacts the connecting pad.

[0067] The first opening (112a) and the second opening (113a) are formed in a rectangular shape and can be formed at one end of the horizontal conductor track (122) of the second conductor track (111).

[0068] The first opening (112a) may be opened to a certain size at one end of the horizontal conductor track (122). The first opening (112a) provides space to accommodate a first connecting pad (120) inside, and the first connecting pad (120) may be arranged at a predetermined interval inside the first opening (112a).

[0069] The first connecting pad (120) may further include a first-1 connecting pad (121) and a first-2 connecting pad (122) arranged at a predetermined interval within the first opening (112a) in a rectangular shape.

[0070] The first-1 connecting pad (121) and the first-2 connecting pad (122) can be connected to the first-1 connecting conductor (131) and the first-2 connecting conductor (132), which respectively extend outward along the longitudinal direction while in contact at one side.

[0071] The second opening (113a) is positioned parallel to the first opening (112a) and can be opened to a certain size from one end of the horizontal conductor track (122).

[0072] The second opening (113a) provides space to accommodate a second connecting pad (123) inside, and the second connecting pad (123) can be placed inside the second opening (113a) at a predetermined distance.

[0073] The second connecting pad (123) may further include a second-1 connecting pad (124) and a second-2 connecting pad (125) arranged at a predetermined interval within the second opening (113a) in a rectangular shape.

[0074] The second-1 connecting pad (124) and the second-2 connecting pad (125) can be connected to the second-1 connecting conductor (134) and the second-2 connecting conductor (135), which respectively extend outward along the longitudinal direction while one side is in contact.

[0075] The third conductor track (114) is formed in a rectangular shape and is smaller than the first conductor track (110), and one side is spaced apart from and opposite the first conductor track (110), and the other side is spaced apart from and opposite the third conductor track (114).

[0076] The first input / output pad (160) further includes one or more first lead frames (161), the second input / output pad (162) further includes one or more second lead frames (163), and the third input / output pad (164) further includes one or more third lead frames (165).

[0077] The first input / output pad (160), the second input / output pad (162), and the third input / output pad (164) can perform the function of efficiently transmitting power delivered from an external power source to the first, second, and third conductor tracks (110, 111, 114) using the first, second, and third lead frames (161, 163, 165). The first, second, and third lead frames (161, 163, 165) are composed of a conductive metal and can provide an electrical connection between the internal circuit and the external circuit of the semiconductor package (100).

[0078] The first input / output pad (160) connects the first lead frame (161) to the first conductor track (110) and is connected to an external power source to provide power to the first conductor track (110).

[0079] The second input / output pad (162) connects the second lead frame (163) to the second conductor track (111) and is connected to an external power source to provide power to the second conductor track (111).

[0080] The third input / output pad (164) connects the third lead frame (165) to the third conductor track (114) and is connected to an external power source to provide power to the third conductor track (114).

[0081] The first, second, and third lead frames (161, 163, 165) are made of a metal material with high rigidity and durability, and in some cases, multiple lead frames may be used, thereby enabling independent power supply to the first and second semiconductor chip groups (140, 150), respectively. For example, it can be designed so that one lead frame supplies high voltage power and another lead frame supplies low voltage power.

[0082] FIG. 5 is a diagram showing the configuration of a semiconductor package according to a second embodiment of the present invention, FIG. 6 is a diagram showing an enlarged view of region A in a semiconductor package according to a second embodiment of the present invention, FIG. 7 is a diagram showing an enlarged view of region B in a semiconductor package according to a second embodiment of the present invention, and FIG. 8 is a diagram showing an enlarged view of region C in a semiconductor package according to a second embodiment of the present invention.

[0083] The second embodiment includes structurally identical components to the first embodiment of FIGS. 1 to 4 described above, and therefore the same reference numerals are applied to identical components. Accordingly, the description of redundant components in the second embodiment is omitted, and only the differences are described. The second embodiment differs in that the input / output connection is configured in the form of a clip, while the remaining components include the same configuration.

[0084] FIG. 9 is a diagram showing the configuration of an input / output connection portion in the form of a wire in a semiconductor package according to the first embodiment of the present invention.

[0085] The first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) each include a pair of first input / output terminals (143), and the first input / output terminals (143) of the first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) are connected to each other using a first input / output connection part (144). Here, the first input / output connection part (144) can be configured in the form of a wire.

[0086] The second semiconductor chip (141b) can be connected to the first power terminal (117a) of the second conductor track (111) through the first input / output connection (144).

[0087] The fourth semiconductor chip (141d) can be connected to the second power terminal (117b) of the second conductor track (111) through the first input / output connection (144).

[0088] The first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) each include a pair of second input / output terminals (153), and the second input / output terminals (153) of the first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) are connected to each other using a second input / output connection part (154). Here, the second input / output connection part (154) can be configured in the form of a wire.

[0089] The first semiconductor chip (151a) can be connected to the third power terminal (114a) of the third conductor track (114) through the second input / output connection (154).

[0090] The third semiconductor chip (151c) can be connected to the fourth power terminal (114b) of the third conductor track (114) through the second input / output connection (154).

[0091] FIG. 10 is a diagram showing the configuration of an input / output connection portion in the form of a clip in a semiconductor package according to a second embodiment of the present invention.

[0092] The first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) each include a pair of first input / output terminals (143), and the first input / output terminals (143) of the first, second, third, and fourth semiconductor chips (141a, 141b, 141c, 141d) are connected using a clip (200).

[0093] The first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) each include a pair of second input / output terminals (153), and the second input / output terminals (153) of the first, second, third, and fourth semiconductor chips (151a, 151b, 151c, 151d) are connected using a clip (200). The clip (200) can simultaneously perform electrical signal transmission and physical coupling.

[0094] The clip (200) may include a connecting part, a spring part, and a fixing part, and the connecting part may directly contact the semiconductor chip to transmit an electrical signal. The spring part provides elasticity so that it can be firmly fixed to the semiconductor chip and the conductor track, and performs the function of reducing external vibrations or shocks. The fixing part performs the function of fixing to the semiconductor package through soldering or mechanical joining.

[0095] The technical features disclosed in each embodiment of the present invention are not limited to that embodiment only, and as long as they are not mutually incompatible, the technical features disclosed in each embodiment may be combined and applied to different embodiments.

[0096] Therefore, in each embodiment, the technical features are described primarily, but as long as the technical features are not mutually incompatible, they may be combined and applied together.

[0097] The present invention is not limited to the embodiments described above and the attached drawings, and various modifications and variations may be possible from the perspective of those skilled in the art to which the present invention belongs. Accordingly, the scope of the present invention should be defined not only by the claims of this specification but also by equivalents thereof.

Claims

1. Base plate; First, second, and third conductor tracks formed on the upper part of the base plate and spaced apart from each other; A fourth conductor track located surrounded by the first conductor track; A fifth conductor track located surrounded by the second conductor track; First and second connecting pads, at least a portion of which is surrounded by the second conductor track; A first semiconductor chip group comprising a plurality of semiconductor chips coupled to the first conductor track; A second semiconductor chip group comprising a plurality of semiconductor chips coupled to the second conductor track; A first input / output connection unit that electrically connects the first semiconductor chip group and the second conductor track; A second input / output connection unit that electrically connects the second semiconductor chip group and the third conductor track; A first bonding wire connecting the above-mentioned fourth conductor track and the above-mentioned first connecting pad; A second bonding wire connecting the fifth conductor track and the second connecting pad; A first connecting conductor having one end coupled to the first connecting pad and the other end extending to the outside of the base plate; and It includes a second connecting conductor, one end of which is coupled to the second connecting pad and the other end of which extends to the outside of the base plate, and The second conductor track above forms first and second openings in an inwardly recessed shape, and The first connecting conductor is located in the first opening, and The second connecting conductor is located in the second opening. Semiconductor package.

2. In Paragraph 1, The first conductor track is configured with the first semiconductor chip group on its upper surface in a rectangular shape, and The second conductor track has the second semiconductor chip group configured on its upper surface and is spaced apart from the first conductor track and faces each other across two surfaces of the first conductor track. Formed in the shape of ', The third conductor track is formed in a rectangular shape, smaller than the first conductor track, with one side facing the first conductor track at a distance and the other side facing the third conductor track at a distance. Semiconductor package.

3. In Paragraph 2, The above second conductor track is, A horizontal conductor track electrically connected to a first semiconductor chip group of the above-mentioned spaced-apart first conductor track and a first input / output connection part; and A vertical conductor track extending from the horizontal conductor track toward the third conductor track, arranging the second semiconductor chip group parallel to the first semiconductor chip group, and electrically connecting the second semiconductor chip group to the third conductor track by a second input / output connection. A semiconductor package including 4. In Paragraph 3, A first connecting pad formed at least one in a first opening of a certain size from one end of the horizontal conductor track; A second connecting pad, at least one formed in a second opening of a certain size at one end of the horizontal conductor track located at a certain distance from the first opening in the horizontal conductor track; A first connecting conductor extending outward along the longitudinal direction while one end contacts the first connecting pad; and A second connecting conductor extending outward along the longitudinal direction, with one end in contact with the second connecting pad. A semiconductor package including 5. In Paragraph 3, The first opening is opened to a certain size at one end of the horizontal conductor track, and The first connecting pad further comprises a first-1 connecting pad and a first-2 connecting pad arranged at a predetermined interval within the first opening in a rectangular shape, and the first-1 connecting pad and the first-2 connecting pad each have a first-1 connecting conductor and a first-2 connecting conductor that extend outward along the longitudinal direction while one side of each contacts. A semiconductor package including additional 6. In Paragraph 3, The second opening is spaced horizontally from the first opening and is opened to a certain size at one end of the horizontal conductor track, The second connecting pad further comprises a second-1 connecting pad and a second-2 connecting pad arranged at a predetermined interval within the second opening in a rectangular shape, and the second-1 connecting pad and the second-2 connecting pad each have a second-1 connecting conductor and a second-2 connecting conductor that extend outward along the longitudinal direction while one side of each contacts. A semiconductor package including additional 7. In Paragraph 5, The above-mentioned first semiconductor chip group is, The first, second, third, and fourth semiconductor chips are formed in a 2×2 matrix array, and the fourth conductor track is placed in the center between the first, second, third, and fourth semiconductor chips. The above-mentioned fourth conductor track is, A plurality of first internal control terminals each connected to the first, second, third, and fourth semiconductor chips, and a 4-1 conductor track of a certain shape constituting a first external control terminal; and It includes a 4-2 conductor track of a certain shape that forms a closed loop surrounding the 4-1 conductor track spaced apart from it, and comprises a plurality of 2nd internal control terminals each connected to the 1st, 2nd, 3rd, and 4th semiconductor chips, and a 2nd external control terminal, wherein the 1-1 connection pad is connected to the 1st external control terminal through a 1st bonding wire, and the 1-2 connection pad is connected to the 2nd external control terminal through a 2nd bonding wire. Semiconductor package.

8. In Paragraph 6, The above second semiconductor chip group is, The first, second, third, and fourth semiconductor chips, each connected to the first, second, third, and fourth semiconductor chips, are formed in a 2×2 matrix array, and the fifth conductor track is formed in the center between the first, second, third, and fourth semiconductor chips. The above-mentioned fifth conductor track is, A plurality of third internal control terminals each connected to the first, second, third, and fourth semiconductor chips, and a 5-1 conductor track of a certain shape constituting a third external control terminal; and It includes a plurality of fourth internal control terminals each connected to the first, second, third, and fourth semiconductor chips, and a fifth-second conductor track of a certain shape constituting a fourth external control terminal, wherein the second-first connection pad is connected to the first external control terminal through a first bonding wire, and the first-second connection pad is connected to the second external control terminal through a second bonding wire. Semiconductor package.

9. In Paragraph 1, Connecting the respective input / output terminals of the first, second, third, and fourth semiconductor chips, and the semiconductor chip and the second conductor track with a wire Semiconductor package.

10. In Paragraph 1, Connecting the respective input / output terminals of the first, second, third, and fourth semiconductor chips, and the semiconductor chip and the second conductor track, with a clip that simultaneously performs electrical signal transmission and physical coupling. Semiconductor package.

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