Smart IC substrate, smart IC module, and IC card comprising same

Abstract

A smart IC substrate according to an embodiment comprises: a substrate; an upper bonding layer disposed on the substrate; an upper conductive pattern part disposed on the upper bonding layer; and a lower bonding layer disposed under the substrate, wherein the upper bonding layer and the lower bonding layer include mutually different materials.

Description

Smart IC substrate, smart IC module, and IC card including the same

[0001] The embodiment relates to a smart IC substrate, a smart IC module, and an IC card including the same.

[0002] An IC card is a plastic card embedded with an integrated circuit chip capable of storing and processing information. An IC containing the necessary information is mounted on the card, and this information is transmitted to a reader in the form of electrical signals. Such IC cards are manufactured by inserting a smart IC module into the main body of the card.

[0003] Smart IC modules are classified into single type or dual type depending on the arrangement of the metal layers. In the single type, an electrode pattern is provided on only one side of the substrate. In addition, in the dual type, an electrode pattern is provided on each side of the substrate.

[0004] Furthermore, smart IC modules are classified into contact, contactless, hybrid, and combi cards depending on the method of card usage. Contact cards transmit and receive information through physical contact. Additionally, contactless cards transmit and receive information without physical contact. Moreover, hybrid and combi cards include both contact and contactless functions.

[0005] Contact-type smart IC modules transmit and receive information via physical contact. Contactless smart IC modules transmit and receive information without physical contact using wireless communication functions (e.g., NFC: Near Field Communication). Combi-smart IC modules and hybrid smart IC modules include both physical contact functions and wireless communication functions without physical contact.

[0006] Smart IC cards in these smart IC card modules are widely used in various fields, such as credit cards, SIM cards, security cards, and identification cards. The smart IC card module applied to these smart IC cards is attached to an adhesive placed on the card body.

[0007] However, smart IC cards are used in various environments (e.g., high temperature, low temperature, high humidity, etc.). In such cases, a problem may arise where the adhesion between the smart IC card module and the adhesive on the card body deteriorates. Furthermore, if the adhesion between the smart IC card module and the adhesive on the card body deteriorates, reliability issues may occur where the smart IC card module separates from the card body during the bonding test process between the module and the card body, and / or in the usage environment of the smart IC card.

[0008] (Patent Document 1) KR 10-2002-0011361 A

[0009] An embodiment provides a smart IC substrate with improved adhesion to a card body, a smart IC module, and an IC card including the same.

[0010] In addition, the embodiment provides a smart IC substrate with improved mechanical durability, a smart IC module, and an IC card including the same.

[0011] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below.

[0012] A smart IC substrate according to an embodiment comprises a substrate; an upper bonding layer disposed on the substrate; an upper conductive pattern portion disposed on the upper bonding layer; and a lower bonding layer disposed below the substrate, wherein the upper bonding layer and the lower bonding layer comprise different materials.

[0013] In addition, the lower bonding layer comprises epoxy resin and polyimide.

[0014] In addition, the above epoxy resin includes novolak epoxy resin.

[0015] In addition, the polyimide satisfies 15% to 30% by weight of the total weight of the lower bonding layer.

[0016] In addition, the polyimide has a molecular weight of 5,000 to 20,000.

[0017] In addition, the upper bonding layer and the lower bonding layer have different thicknesses.

[0018] In addition, the thickness of the lower bonding layer has a range of 18㎛ to 25㎛.

[0019] In addition, the lower surface of the lower bonding layer has an arithmetic mean roughness in the range of 1 μm to 10.21 μm.

[0020] In addition, the smart IC substrate of the embodiment further includes a lower conductive pattern portion disposed under the lower bonding layer.

[0021] Additionally, the upper conductive pattern portion comprises a metal layer and a buffer layer disposed between the metal layer and the upper bonding layer, and the buffer layer and the metal layer comprise different metal materials.

[0022] Additionally, the buffer layer comprises a first plating layer disposed on the lower surface of the metal layer and a second plating layer disposed on the lower surface of the first plating layer, and the first plating layer and the second plating layer comprise different metal materials.

[0023] Additionally, the upper conductive pattern portion further includes an upper cover layer disposed on the metal layer, and the upper cover layer includes TiNx, TaNx, TiCN, TiAlN, TiO, TiO2, or TiOx.

[0024] Additionally, the buffer layer comprises a bonding metal bonded to the lower surface of the metal layer, and the upper conductive pattern portion further comprises a diffusion layer disposed between the metal layer and the bonding metal, wherein a portion of the metal layer diffuses into the bonding metal layer or a portion of the bonding metal diffuses into the metal layer.

[0025] Meanwhile, a smart IC module according to an embodiment includes a smart IC substrate; a chip attached to the smart IC substrate; and a connecting member connecting a terminal of the chip to a second cover layer of the smart IC substrate, wherein the chip is disposed under a lower bonding layer of the smart IC substrate.

[0026] Additionally, the smart IC module further includes a molding layer for molding the chip, and at least a portion of the molding layer covers at least a portion of the lower bonding layer of the smart IC substrate.

[0027] Meanwhile, an IC card according to an embodiment includes a main body portion including a receiving space; a protective layer disposed on the main body portion; and a smart IC module disposed within the receiving portion.

[0028] Additionally, the IC card further comprises an adhesive disposed on the main body, the adhesive contacts the lower bonding layer of the smart IC module, and each of the lower bonding layer and the adhesive comprises polyimide.

[0029] The smart IC substrate of the embodiment includes a substrate and a lower bonding layer disposed on the lower surface of the substrate. The lower bonding layer may include a material having excellent bonding strength with the hot melt adhesive of the card body. For example, the lower bonding layer may include epoxy resin and polyimide. Accordingly, the embodiment includes polyimide, which is a hot melt component, in a certain amount in the lower bonding layer, thereby further improving the bonding strength between the smart IC substrate and the card body. Through this, the embodiment can further improve product reliability. Furthermore, the embodiment can further improve the bending reliability of the IC card, thereby enabling the IC card to operate more stably in various environments.

[0030] In addition, the embodiment determines the content and thickness of the polyimide in the lower bonding layer, taking into account adhesion and modulus, based on the condition where bending reliability is best. Through this, the embodiment can further improve the bending reliability of the smart IC substrate, thereby further improving product satisfaction.

[0031] Furthermore, the polyimide in the lower bonding layer is configured to have a molecular weight above a certain level. At this time, the molecular weight of the polyimide can affect miscibility, compatibility, coating properties, and adhesion. Accordingly, the embodiment configures the molecular weight of the polyimide added to the lower bonding layer to be in the range of 5,000 to 20,000. Through this, the embodiment can improve the miscibility, compatibility, coating properties, adhesion, and bending reliability between the polyimide in the lower bonding layer and the epoxy resin.

[0032] FIG. 1 is a plan view of one side of a smart IC substrate according to a first embodiment.

[0033] FIG. 2 is a plan view of the other side of a smart IC substrate according to the first embodiment.

[0034] FIG. 3a is a cross-sectional view cut along the AA' direction of FIG. 2 according to the first embodiment.

[0035] FIG. 3b is a cross-sectional view cut along the AA' direction of FIG. 2 according to a second embodiment.

[0036] FIGS. 4a to 4e are drawings for explaining the physical properties of the lower adhesive layer according to an embodiment.

[0037] FIG. 5 is a plan view of the other side of a smart IC substrate according to the third embodiment.

[0038] Figure 6 is a cross-sectional view cut along the BB' direction of Figure 5.

[0039] FIG. 7 is a cross-sectional view cut along the AA' direction of FIG. 2 according to the fourth embodiment.

[0040] FIG. 8 is a cross-sectional view cut along the AA' direction of FIG. 2 according to the fifth embodiment.

[0041] FIG. 9 is a cross-sectional view cut along the AA' direction of FIG. 2 according to the 6th embodiment.

[0042] FIG. 10 is a cross-sectional view cut along the AA' direction of FIG. 2 according to the 7th embodiment.

[0043] FIG. 11 is a plan view showing a smart IC module according to one embodiment.

[0044] FIG. 12 is a cross-sectional view showing a smart IC module according to an embodiment.

[0045] FIG. 13 is a perspective view showing a smart IC card according to an embodiment.

[0046] FIG. 14 is a schematic cross-sectional view of the smart IC card of FIG. 9.

[0047] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0048] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0049] Furthermore, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “A and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0050] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0051] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0052] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0053] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0054]

[0055] Hereinafter, a smart IC substrate, a smart IC module, and a smart IC card including the same according to an embodiment are described with reference to the drawings.

[0056]

[0057] FIG. 1 is a plan view of one side of a smart IC substrate according to a first embodiment, FIG. 2 is a plan view of the other side of a smart IC substrate according to a first embodiment, FIG. 3a is a cross-sectional view cut along the AA' direction of FIG. 2 according to a first embodiment, FIG. 3b is a cross-sectional view cut along the AA' direction of FIG. 2 according to a second embodiment, FIG. 4a to 4e are drawings for explaining the physical properties of a lower adhesive layer according to an embodiment, FIG. 4 is a cross-sectional view cut along the AA' direction of FIG. 2 according to a second embodiment, FIG. 5 is a plan view of the other side of a smart IC substrate according to a third embodiment, FIG. 6 is a cross-sectional view cut along the BB' direction of FIG. 5, FIG. 7 is a cross-sectional view cut along the AA' direction of FIG. 2 according to a fourth embodiment, FIG. 8 is a cross-sectional view cut along the AA' direction of FIG. 2 according to a fifth embodiment, and FIG. 9 is FIG. 2 according to a sixth embodiment FIG. 10 is a cross-sectional view cut along the AA' direction, and FIG. 2 is a cross-sectional view cut along the AA' direction according to the 7th embodiment.

[0058] Referring to FIGS. 1 and 2, the smart IC substrate (100) includes a substrate (110) and a conductive pattern portion (120).

[0059] At this time, the conductive pattern portion (120) of the smart IC substrate (100) in the first embodiment may be a single type disposed only on one side of the substrate (110).

[0060] The substrate (110) includes a first surface (110S1) and a second surface (110S2) opposite to the first surface (110S1). And, a conductive pattern portion (120) is disposed on the first surface (110S1) of the substrate (110).

[0061] Here, being placed on the first surface (110S1) is not understood only as a configuration in which the conductive pattern portion (120) is in direct contact with the first surface (110S1) of the substrate (110), but can also be understood as having other configurations between the first surface (110S1) of the substrate (110) and the conductive pattern portion (120).

[0062] The first surface (110S1) of the substrate (110) and the second surface (110S2) of the substrate (110) represent opposite surfaces. The first surface (110S1) of the substrate (110) may be defined as a contact surface. For example, the first surface (110S1) of the substrate (110) may represent a surface capable of recognizing information of a smart IC module through direct or indirect contact. Additionally, the second surface (110S2) of the substrate (110) may be defined as a bonding surface. For example, the second surface (110S2) of the substrate (110) may represent a surface for bonding with a mounted chip (described later) while the chip is mounted.

[0063] The substrate (110) includes a resin material. The substrate (110) may have a certain strength. The substrate (110) may be provided with a reinforcing member. For example, the substrate (110) may be provided as a prepreg having a reinforcing member such as glass fiber. Specifically, the substrate (110) may be provided with glass fiber and a silicone-based filler (Si filler) dispersed within an epoxy resin.

[0064] The substrate (110) may be rigid or flexible. For example, the substrate (110) may include glass or plastic. For example, the substrate (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (110) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0065] The substrate (110) may include a photoisotropic film. For example, the substrate (110) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA).

[0066] Alternatively, the above-mentioned substrate (110) may be bent while having a partially curved surface. That is, the substrate (110) may be bent while having a partially flat surface and a partially curved surface. Specifically, the end of the substrate (110) may be bent while having a curved surface. Alternatively, the substrate (110) may be bent while having a random curvature.

[0067] The substrate (110) may have a thickness within a set range. For example, the thickness of the substrate (110) may be 80 µm to 150 µm, 90 µm to 140 µm, or 100 µm to 120 µm. If the thickness of the substrate (110) is less than 80 µm, the supporting force and / or rigidity of the substrate (110) may be reduced, and thereby it may be difficult to stably place the conductive pattern portion (120). If the thickness of the substrate (110) exceeds 150 µm, the thickness of the smart IC substrate may increase, and thereby, the thickness of the smart IC card including the smart IC substrate (100) may increase, making it difficult to thin.

[0068] The substrate (110) has insulating properties. For example, the substrate (110) may be provided to support the conductive pattern portion (120) and to provide insulation between a plurality of electrode patterns constituting the conductive pattern portion (120). For example, the substrate (110) may prevent short circuits between the plurality of electrode patterns.

[0069] The substrate (110) may be provided with through holes. For example, the substrate (110) may include a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) spaced apart from each other along the horizontal direction. In this case, although the drawing shows that the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in eight numbers, this is not limited thereto. For example, depending on the type of chip mounted on the smart IC substrate (100), the number of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may increase or decrease. For example, the number of terminals of a chip mounted on a smart IC substrate (100) may be less than 8 or more than 8, and accordingly, the number of multiple through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) provided in the substrate (110) may be less than 8 or more than 8.

[0070] A plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be areas for electrically connecting a conductive pattern portion (120) disposed on a first surface (110S1) of a substrate (110) and a terminal of a chip. Preferably, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be areas for wire bonding between the terminal of the chip and the conductive pattern portion (120).

[0071] Each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) has a width (W1) of a set range. The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may refer to the diameter of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Alternatively, the width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be defined as the minimum distance between the inner walls of the through holes passing through the horizontal central axis of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0072] The width (W1) of each of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be 500 µm to 1000 µm, 600 µm to 900 µm, or 700 µm to 800 µm. If the width (W1) of at least one of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) is less than 500 µm, it may be difficult to secure a wire bonding space, and this may degrade the process characteristics in the wire bonding process. In addition, if the width (W1) of at least one of the multiple through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) exceeds 1000 μm, the planar area of ​​the substrate (110) is reduced, and consequently, the rigidity of the substrate (110) is reduced, or it may be difficult to stably place the conductive pattern portion (120) on the substrate (110).

[0073] The conductive pattern portion (120) may be disposed on the first surface (110S1) of the substrate (110). Preferably, the conductive pattern portion (120) may be in direct contact with the first surface (110S1) of the substrate (110). For example, in the first embodiment, the smart IC substrate (100) may not have any additional configuration interposed between the first surface (110S1) of the substrate (110) and the lower surface of the conductive pattern portion (120).

[0074] That is, the metal layer (e.g., a copper foil layer) constituting the conductive pattern portion (120) can be directly attached to the substrate (110). For example, a resin laminate can be provided in which the metal layer constituting the conductive pattern portion (120) is directly attached to the substrate (110) through a direct bonding method, and the smart IC substrate of the embodiment can be manufactured using the resin laminate described above. As another example, the substrate (110) may be a prepreg, and the prepreg may be directly molded onto the metal layer constituting the conductive pattern portion (120). In this case, the resin laminate described above may be a CCL (Copper Clad Laminate).

[0075] The conductive pattern portion (120) may refer to a pattern placed on the contact surface of the substrate (110).

[0076] The conductive pattern portion (120) may include a plurality of electrode patterns. For example, the conductive pattern portion (120) may have a plurality of pads spaced apart from each other along the horizontal direction. For example, the conductive pattern portion (120) may include a plurality of pads. In this case, the number of the plurality of pads of the conductive pattern portion (120) may correspond to the number of a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be eight, and accordingly, the conductive pattern portion (120) may include first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) spaced apart from each other along the horizontal direction. One side of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a contact surface that contacts or does not contact an external terminal to transmit information of the smart IC substrate (100) to the outside. Additionally, the other side of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a bonding surface that is wire-bonded with a terminal of a chip mounted on the smart IC substrate (100). The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may also be referred to as upper pads.

[0077] Each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be provided with a plurality of layers. The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may have the same layer structure.

[0078] Referring to FIG. 3a, each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may include a metal layer (120a) disposed on one side of the substrate (110) and a cover layer covering the exposed surface of the metal layer (120a). In this case, the cover layer may also be referred to as a surface treatment layer disposed on the surface of the metal layer (120a). Depending on the location, the cover layer may include a first cover layer (120b) and a second cover layer (120c).

[0079] A metal layer (120a) is disposed on a first surface (110S1) of a substrate (110). The metal layer (120a) may include at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the metal layer (120a) may be a copper foil layer attached to the substrate (110), and thus may include copper.

[0080] The metal layer (120a) may have a thickness within a set range. For example, the thickness of the metal layer (120a) may be 20㎛ to 75㎛, 22㎛ to 65㎛, or 25㎛ to 60㎛. If the thickness of the metal layer (120a) is less than 20㎛, the resistance of the metal layer (120a) may increase, and consequently, the resistance of the conductive pattern portion (120) may increase, thereby degrading signal characteristics. If the thickness of the metal layer (120a) is greater than 75㎛, the thickness of the smart IC substrate may increase, and the thickness of the smart IC card may increase. Furthermore, if the thickness of the metal layer (120a) is greater than 75㎛, the time required to form the conductive pattern portion (120) may increase, and consequently, process efficiency may decrease and product yield may decrease. For example, the conductive pattern portion (120) can be manufactured by patterning a metal layer (120a) having a certain thickness placed on a substrate (110) using an etching method. And, as the thickness of the metal layer (120a) increases, the etching time of the metal layer (120a) may increase, and the manufacturing time may increase accordingly.

[0081] The first cover layer (120b) and the second cover layer (120c) may be disposed on the surface of the patterned metal layer (120a) described above. That is, a portion of the surface of the metal layer (120a) may not be covered by the substrate (110). And, the first cover layer (120b) and the second cover layer (120c) may be provided to cover the surface of the metal layer (120a) that is not covered by the substrate (110).

[0082] Additionally, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to satisfy a certain level of required characteristics. For example, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to have corrosion resistance, oxidation resistance, wear resistance, hardness, gloss, and wire bonding properties above a certain level.

[0083] Different characteristics may be required for the contact surface and the bonding surface of the conductive pattern portion (120). The contact surface of the conductive pattern portion (120) may be a surface exposed to the outside, and accordingly, a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness may be required for continuous connection with an external device. In addition, the bonding surface of the conductive pattern portion (120) may be a surface electrically connected to the terminal of the chip, and accordingly, a certain level of wire bonding ability may be required.

[0084] The first cover layer (120b) may be disposed on the surface of the metal layer (120a) corresponding to the contact surface of the conductive pattern portion (120). The first cover layer (120b) may satisfy the required characteristics that the contact surface of the conductive pattern portion (120) must have. For example, the first cover layer (120b) may have corrosion resistance, oxidation resistance, wear resistance, and hardness at a certain level or higher. At this time, the metal layer (120a) may be disposed on the upper surface corresponding to the first surface (110S1) of the substrate (110). Accordingly, the first cover layer (120b) may cover the upper surface of the metal layer (120a). Furthermore, the first cover layer (120b) may not be provided on the side of the metal layer (120a) that is not substantially used as a contact surface. However, the embodiment is not limited thereto. According to the embodiment, the first cover layer (120b) may extend from the upper surface of the metal layer (120a) and cover at least a portion of the side surface of the metal layer (120a).

[0085] In one embodiment, the first cover layer may include gold (Au). Gold (Au) may have corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level. Accordingly, in one embodiment, surface treatment of the contact surface of the conductive pattern portion (120) can be performed using gold (Au).

[0086] In another embodiment, the first cover layer (120b) may be a nitride. Preferably, the first cover layer (120b) may be a nitride having corrosion resistance, oxidation resistance, wear resistance, and hardness at a certain level or higher. For example, the first cover layer (120b) may have a hardness greater than that of gold (Au). In this case, if the first cover layer (120b) only has a hardness greater than that of gold (Au), the design satisfaction of the smart IC substrate may be reduced.

[0087] For example, the aforementioned contact surface is a surface exposed to the outside of the final product, the smart IC card, and can serve as a factor in determining the design satisfaction of the smart IC card. In this case, if the contact surface is composed of a plating layer containing gold (Au), a gold-colored terminal portion corresponding to the plating layer containing gold (Au) is exposed to the outside, which makes it possible to provide a more luxurious smart IC card while improving the design satisfaction of the smart IC card. Therefore, if the first cover layer (120b) has a color other than gold, the design satisfaction may be reduced, and consequently, the product satisfaction may be reduced.

[0088] Accordingly, the embodiment may provide a first cover layer (120b) using a nitride containing a metal material having a gold color and a hardness greater than that of gold (Au).

[0089] That is, the first cover layer (120b) may include at least one of titanium nitride (TiNx) and tantalum nitride (TaNx). For example, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color. Therefore, if the first cover layer (120b) is provided with at least one of titanium nitride (TiNx) and tantalum nitride (TaNx), mechanical resistance can be improved compared to a cover layer using gold (Au), and design satisfaction can be enhanced while reducing product unit costs.

[0090] That is, titanium nitride (TiNx) and tantalum nitride (TaNx) can have a hardness in the range of 2000 to 2500 HV, which is 20 times the hardness of gold (Au). Through this, when the first cover layer (120b) is provided using titanium nitride (TiNx) and tantalum nitride (TaNx) in the embodiment, the mechanical resistance of the contact surface of the conductive pattern portion (120) can be improved to a level of more than 20 times that of the existing one.

[0091] Furthermore, titanium nitride (TiNx) and tantalum nitride (TaNx) are relatively cheaper than gold (Au), and accordingly, if the first cover layer (120b) is provided using titanium nitride (TiNx) and tantalum nitride (TaNx), the product unit cost can be lowered and product satisfaction can be improved.

[0092] In addition, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color, and accordingly, it is possible to provide a product that meets the design satisfaction of a contact surface containing gold (Au) at a relatively low unit price.

[0093] Additionally, the first cover layer (120b) can be implemented in various colors depending on the degree of nitridation. For example, the first cover layer (120b) can be provided in gold, blue, purple, etc., depending on the degree of nitridation. Accordingly, the embodiment can provide a smart IC card having a contact surface of various colors by adjusting the degree of nitridation of the first cover layer (120b), thereby further improving product satisfaction and further improving design freedom.

[0094] In addition, with the recent advancement of smart ICs, the required colors for the first cover layer (120b) are becoming more diverse. As described above, the first cover layer (120b) may be required to be gold, blue, purple, etc., and may be required to be black. Accordingly, the first cover layer (120b) may be Ti(X1)N or Ti(X2).

[0095] At this time, X1 may include C or Al. For example, the first cover layer (120b) may be TiCN or TiAlN. If the first cover layer (120b) is TiCN, the first cover layer (120b) may be provided in a black or gray color. Additionally, if the first cover layer (120b) is TiAlN, the first cover layer (120b) may be provided in purple.

[0096] Additionally, X2 may be O, O2, or Ox. For example, the first cover layer may be TiO, TiO2, or TiOx (where x is a positive number). If the first cover layer (120b) is TiO, TiO2, or TiOx, the first cover layer (120b) may be provided in a black, gray, or brown color. Additionally, if the thickness of the first cover layer (120b) is thin while the first cover layer (120b) is provided as TiO, TiO2, or TiOx, a rainbow color may be provided due to thickness non-uniformity.

[0097] That is, the first cover layer (120b) may be TiCN, TiAlN, TiO, TiO2, or TiOx, and in this case, the hardness of the first cover layer (120b) can be further increased, and the mechanical resistance of the contact surface of the conductive pattern portion (120) can be further improved accordingly. For example, the hardness of TiCN is about 3000 HV, and the hardness of TiAlN is about 3200 HV.

[0098] Accordingly, the embodiment may provide a first cover layer (120b) using any one of TiNx, TaNx, TiCN, TiAlN, TiO, TiO2, or TiOx, and the color of the first cover layer (120b) may be varied accordingly.

[0099] The second cover layer (120c) may be placed at a location different from where the first cover layer (120b) is placed. For example, the second cover layer (120c) may be provided on the bonding surface of the metal layer (120a) that is not covered by the first cover layer (120b). The second cover layer (120c) may be placed on the lower surface of the metal layer (120a).

[0100] That is, at least a portion of the lower surface of the metal layer (120a) of each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may overlap along the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Accordingly, the area of ​​the lower surface of the metal layer (120a) that overlaps in the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may not be covered by the first cover layer (120b) and the substrate (110). And, the second cover layer (120c) can be placed on the lower surface of the metal layer (120a) which is superimposed in a vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0101] That is, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to cover the lower surface of the metal layer (120a).

[0102] In this case, the second cover layer (120c) in one embodiment may include a metal material different from the metal material constituting the first cover layer (120b). For example, if the first cover layer (120b) includes a nitride, the second cover layer (120c) and the first cover layer (120b) may include different metal materials. In this case, the second cover layer (120c) may include a metal material having a hardness different from the hardness of the metal material constituting the first cover layer (120b). For example, the second cover layer (120c) may include a first layer (120c1) and a second layer (120c2).

[0103] The first layer (120c1) and the second layer (120c2) of the second cover layer (120c) are disposed on the lower surface of the metal layer (120a), thereby providing a wire bonding capability of a certain level or higher required on the bonding surface of the conductive pattern portion (120).

[0104] The first layer (120c1) of the second cover layer (120c) may be disposed on the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may be in direct contact with the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may include nickel. The first layer (120c1) of the second cover layer (120c) may represent a seed layer for forming the second layer (120c2). The first layer (120c1) of the second cover layer (120c) may be a barrier layer that prevents the metal material constituting the metal layer (120a) from diffusing into the second layer (120c2). Additionally, the first layer (120c1) of the second cover layer (120c) may be an anti-oxidation layer that prevents oxidation of the metal layer (120a).

[0105] The second layer (120c2) of the second cover layer (120c) may be disposed on the lower surface of the first layer (120c1) of the second cover layer (120c). The second layer (120c2) of the second cover layer (120c) may provide wire bonding properties of a certain level or higher required on the bonding surface of the conductive pattern portion (120). The second layer (120c2) of the second cover layer (120c) may include at least one of gold (Au) and silver (Ag).

[0106] A dummy pattern portion (DP) may be further provided on the first surface (110S1) of the substrate (110). The dummy pattern portion (DP) may include the same material as the conductive pattern portion (120) and, preferably, may have the same layer structure as the conductive pattern portion (120). The dummy pattern portion (DP) may be electrically separated from the conductive pattern portion (120), thereby improving the rigidity of the smart IC substrate (100). Additionally, the dummy pattern portion (DP) may be provided in the corner area of ​​the first surface (110S1) of the substrate (110) to improve process characteristics during the assembly process of the smart IC substrate (100). For example, the dummy pattern portion (DP) may include first to fourth dummy patterns (DP1, DP2, DP3, DP4) respectively provided in the corner area of ​​the first surface (110S1) of the substrate (110).

[0107] Meanwhile, referring to FIG. 3b, the smart IC substrate according to the second embodiment may further include an upper bonding layer (140). The upper bonding layer (140) may be disposed between the first surface (110S1) of the substrate (110) and the conductive pattern portion (120). For example, the upper bonding layer (140) may be disposed between one surface of the substrate (110) and the lower surface of the metal layer (120a).

[0108] At this time, unlike the lower bonding layer (150), the upper bonding layer (140) may be provided for bonding strength between the conductive pattern portion (120) and the substrate (110). The upper bonding layer (140) may be a bonding sheet. The upper bonding layer (140) may be provided to bond a copper foil layer (not shown), which is a metal layer prior to implementing a circuit such as the conductive pattern portion (120), onto the first surface (110S1) of the substrate (110).

[0109] For example, as in the first embodiment, a conductive pattern portion (120) can be placed directly on one surface of the substrate (110) without an upper bonding layer (140). However, to further improve the adhesion between the substrate (110) and the conductive pattern portion (120), an upper bonding layer (140) may be additionally placed between the substrate (110) and the conductive pattern portion (120).

[0110] The upper bonding layer (140) comprises a resin material. For example, the upper bonding layer (140) may comprise at least one of epoxy resin, acrylic resin, and polyimide resin. Additionally, the upper bonding layer (140) may comprise at least one additive selected from natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the upper bonding layer (140) may be improved.

[0111] The upper bonding layer (140) may have a thickness (T1) within a set range. For example, the thickness (T1) of the upper bonding layer (140) may be 8 µm to 35 µm, 10 µm to 30 µm, or 12 µm to 25 µm. If the thickness (T1) of the upper bonding layer (140) is less than 8 µm, the adhesive strength of the upper bonding layer (140) may be reduced, and thereby, the conductive pattern portion (120) may be separated from the upper bonding layer (140). Additionally, if the thickness (T1) of the upper bonding layer (140) exceeds 35 µm, the thickness of the smart IC substrate may increase or the thickness of the smart IC card may increase.

[0112] At this time, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the substrate (110) and the upper bonding layer (140). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate from one side of the upper bonding layer (140) to the second side (110S2) of the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be formed through a process such as punching while the upper bonding layer (140) is placed on the substrate (110), thereby penetrating the substrate (110) and the upper bonding layer (140) in common.

[0113] The planar area of ​​the upper bonding layer (140) can correspond to the planar area of ​​the substrate (110). For example, the upper bonding layer (140) can completely cover the first surface (110S1) of the substrate (110). Thus, the rigidity of the substrate (110) can be further improved.

[0114] At this time, when the smart IC substrate includes an upper bonding layer (140), through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the upper bonding layer (140) together with the substrate (110). For example, in the case of the second embodiment, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first part penetrating the substrate (110), and a second part penetrating the upper bonding layer (140) while being connected to the first part described above.

[0115] According to the second embodiment, an upper bonding layer (140) is additionally disposed between the substrate (110) and the conductive pattern portion (120) to further improve the adhesion between the substrate (110) and the conductive pattern portion (120). Accordingly, the physical reliability and / or electrical reliability of the smart IC substrate can be further improved.

[0116] Additionally, referring to FIGS. 3a and 3b, a lower bonding layer (150) may be disposed on the second surface (110S2) of the substrate (110). In this case, the lower bonding layer (150) in the first and second embodiments may function to improve adhesion with an adhesive layer (described later) provided on the card body when the smart IC substrate is attached to the card body. In this case, the lower bonding layer (150) in the embodiment may include a material that has excellent adhesion with a hot melt adhesive provided on the card body. Additionally, the lower bonding layer (150) may function to improve adhesion with a chip attached to the smart IC substrate.

[0117] Recently, smart IC cards are widely used in various application fields such as electronic payment, identity verification, and access control. Consequently, there is a growing need to enhance the security and reliability of smart IC cards that store personal information. In particular, a certain level of adhesion is required between the smart IC substrate containing the IC chip and the card body, and bending reliability is especially required.

[0118] At this time, conventionally, the adhesion between the smart IC substrate and the card body is not secured, and consequently, a problem occurs where the smart IC substrate separates from the card body during bending reliability evaluation.

[0119] Accordingly, the embodiment places a lower bonding layer (150) on the second surface (110S2) of the substrate (110). Furthermore, the lower bonding layer (150) may include a material having excellent adhesion properties with the hot melt adhesive of the card body.

[0120] In particular, the lower bonding layer (150) may include a hot melt component with excellent bonding strength with the hot melt adhesive, thereby increasing the chemical bonding strength with the hot melt adhesive.

[0121] To this end, the embodiment selects candidate materials for a lower bonding layer (150) that have excellent bonding strength with the hot melt adhesive of the card body, and determines the material with the best bonding strength with the hot melt adhesive among the selected candidate materials. In addition, the embodiment places the lower bonding layer (150) containing the determined material on the second surface (110S2) of the substrate (110). Through this, the embodiment can improve the bonding strength between the hot melt adhesive of the card body and the smart IC substrate, thereby further improving the bending reliability of the smart IC card.

[0122] The embodiment can select a candidate composition of a lower bonding layer (150) that has excellent bonding strength with the hot melt adhesive of the card body. Through this, the embodiment can select a candidate composition of a lower bonding layer (150) that has excellent adhesion strength with the hot melt adhesive of the card body both before and after moisture absorption.

[0123] At this time, adhesion can be measured by performing a bending test. Specifically, a test card can be manufactured by joining the card body and the smart IC substrate by thermal compression using a hot melt adhesive, and the adhesion can be evaluated by performing a bending test on the manufactured test card. For example, a primary dynamic bending test (ISO / IEC 10373-1) can be performed after exposing the test card to a temperature of 50°C and a humidity of 93% for 48 hours, and the separation between the card body and the smart IC substrate can be tested accordingly. Furthermore, a secondary bending test can be performed after the test card, upon completion of the primary dynamic bending test, is exposed again to a temperature of 50°C and a humidity of 93% for 48 hours.

[0124] Here, the embodiment may conduct a bending test as described above on the candidate composition of the lower bonding layer (150), and accordingly, select three final candidate compositions.

[0125] In particular, the lower bonding layer (150) may include polyimide, which is a hot melt material, in the epoxy resin, and the polyimide may be included in the lower bonding layer (150) with a certain level of content. Among these, the bending test described above is performed according to the content of polyimide in the lower bonding layer (150), and accordingly, three candidate compositions with excellent adhesion based on the bending test results can be selected. Preferably, the lower bonding layer (150) may have a certain level or more of polyimide added to the novolac epoxy resin.

[0126] Specifically, referring to FIG. 4a, the embodiment may perform a bending test according to the content of polyimide in the lower bonding layer (150). At this time, the reference material (Ref.) in FIG. 3a refers to a bonding layer containing only novolak epoxy resin, R-1 refers to a bonding layer with polyimide added in an amount of 5% to 15% by weight, R-2 refers to a bonding layer with polyimide added in an amount of 15% to 30% by weight, R-3 refers to a bonding layer with polyimide added in an amount of 30% to 45% by weight, R-4 refers to a bonding layer with polyimide added in an amount of 45% to 55% by weight, R-5 refers to a bonding layer with polyimide added in an amount of 55% to 65% by weight, and R-6 refers to a bonding layer with polyimide added in an amount of 65% to 75% by weight.

[0127] At this time, as shown in FIG. 4a, it can be confirmed that the adhesion strength before and after moisture absorption differs depending on the content of polyimide in the bonding layer. Here, the bonding layers having a higher adhesion strength compared to the adhesion strength of the bonding layer of the reference material (Ref.) are R-2, R-3, and R-4, and accordingly, the embodiment can select R-2, R-3, and R-4 as candidate compositions for the lower bonding layer (150).

[0128] Subsequently, the embodiment can select a final composition of the lower bonding layer (150) that has excellent bonding strength with the hot melt adhesive among the selected candidate compositions. To this end, the embodiment can select a final composition of the lower bonding layer (150) that has excellent bonding strength with the hot melt adhesive based on the elastic load method.

[0129] For example, as shown in FIG. 4b, it can be seen that the load P received by the smart IC substrate and the modulus E of the lower bonding layer (150) are in a mutually proportional relationship. And, it can be seen that the lower the modulus E, the less the stress caused by bending.

[0130] Specifically, the elastic load method can be determined by the following Equation 1.

[0131] [Equation 1]

[0132]

[0133] θ in Equation 1 max represents the maximum curvature, I represents the secondary moment, L represents the length of the smart IC substrate, E represents the modulus, and P may represent the load.

[0134] Accordingly, according to Equation 1, P (load) and E (modulus) of the lower bonding layer (150) may have the following relationship.

[0135]

[0136] Here, the E (modulus) of the bonding layer of the reference material (Ref.) is about 2.0 GPa. Furthermore, as shown in FIG. 4c, the E (modulus) of R-2 selected as a candidate composition is about 1.8 GPa, the E (modulus) of R-3 selected as a candidate composition is about 2.4 GPa, and the E (modulus) of R-4 selected as a candidate composition is about 2.0 GPa.

[0137] In other words, among the three bonding layers selected as candidate compositions, the E (modulus) of the bonding layer of R-2 is the lowest, and the E (modulus) of the bonding layer of R-3 is the highest. Furthermore, as a result of conducting bending tests according to each E (modulus), it was confirmed that R-2, which has the lowest E (modulus), has the highest reliability, and in particular, it was confirmed that it withstood the longest in dynamic bending tests.

[0138] Accordingly, the embodiment finally provides a lower bonding layer (150) comprising novolak epoxy resin and polyimide, and the content of polyimide in the lower bonding layer (150) is in the range of 15% by weight to 30% by weight.

[0139] In addition, the polyimide in the lower bonding layer (150) is configured to have a molecular weight above a certain level. At this time, the molecular weight of the polyimide can affect mixability, compatibility, coating properties, and adhesion. Accordingly, the embodiment is configured so that the molecular weight of the polyimide added to the lower bonding layer (150) is in the range of 5,000 to 20,000. At this time, if the molecular weight of the polyimide is less than 5,000, the adhesion may decrease. Also, if the molecular weight of the polyimide exceeds 20,000, compatibility is reduced and the modulus decreases, which may reduce reliability during the bending test. Therefore, the embodiment is configured so that the molecular weight of the polyimide added to the lower bonding layer (150) is in the range of 5,000 to 20,000, thereby improving the mixability, compatibility, coating properties, adhesion, and bending reliability with the epoxy resin.

[0140] At this time, the lower bonding layer (150) may have a certain thickness (T2). Here, the thickness (T2) of the lower bonding layer (150) may affect the results of the bending test evaluation of the lower bonding layer (150). For example, as illustrated in FIG. 4d, the results of the bending test evaluation may differ depending on the thickness of the lower bonding layer (150). Specifically, it was confirmed that as the thickness of the lower bonding layer (150) decreases from 35 μm to 0 μm, the stress applied to the smart IC substrate decreases by 4% in the long axis direction and by 7% in the short axis direction.

[0141] In particular, it was confirmed that the lower the thickness (T2) of the lower bonding layer (150), the higher the reliability. However, if the thickness (T2) of the lower bonding layer (150) is reduced below a certain level, there is a problem that it cannot withstand process conditions or the process is impossible. Therefore, the embodiment determines the thickness (T2) of the lower bonding layer (150) within a range that can withstand process conditions and has excellent results in the bending test evaluation.

[0142] The bending test results according to the thickness (T2) of the lower bonding layer (150) are as shown in Table 1 below.

[0143] Sorting Bending Test (Pass Quantity / Input Quantity) 1 cycle 2 cycle 3 cycle 4 cycle 5 cycleRef. 25㎛ 10 / 10 10 / 10 Fail 9 / 10 --R- 218㎛ 10 / 10 10 / 10 10 / 10 10 / 10 10 / 10 R- 225㎛ 10 / 10 10 / 10 10 / 10 Fail 9 / 10 10 / 10

[0144] Referring to Table 1, the bonding layer of the reference material (Ref.) passed the 2-cycle bending test at a thickness of 25 μm, but a defect occurred in the 3rd cycle.

[0145] Furthermore, it was confirmed that the bonding layer of the R-2 composition selected as the final candidate passed the bending test for up to 5 cycles at a thickness of 18㎛.

[0146] In addition, the bonding layer of the R-2 composition selected as the final candidate failed after 4 cycles when the thickness exceeded 25㎛.

[0147] According to this, it was confirmed that the bonding strength with the hot melt adhesive is affected by the thickness of the lower bonding layer (150), and furthermore, it was confirmed that it also affects the modulus.

[0148] Accordingly, the embodiment is configured such that the thickness (T2) of the lower bonding layer (150) ranges from 18 μm to 25 μm. If the thickness (T2) of the lower bonding layer (150) is less than 18 μm, the bonding strength between the smart IC substrate and the card body may be reduced. For example, a certain level of surface roughness may be applied to the upper surface of the lower conductive pattern portion or the lower surface of the substrate (110) to improve adhesion. In this case, if the thickness (T2) of the lower bonding layer (150) is less than 18 μm, a problem may occur in which the bonding strength is reduced because the lower bonding layer (150) fails to fill all the grooves of the surface roughness applied to the lower conductive pattern portion and / or the substrate (110). Additionally, if the thickness (T2) of the lower bonding layer (150) exceeds 25 μm, the bending reliability may be reduced.

[0149] Additionally, a certain level of surface roughness may be applied to the lower surface of the lower bonding layer (150). For example, an arithmetic mean roughness of 1 μm to 10.21 μm may be applied to the lower surface of the lower bonding layer (150). In this case, if the arithmetic mean roughness applied to the lower surface of the lower bonding layer (150) is less than 1 μm, the effect of improving adhesion with the hot melt adhesive of the card body may be insufficient. In addition, if the arithmetic mean roughness applied to the lower surface of the lower bonding layer (150) exceeds 10.21 μm, the thickness of the lower bonding layer (150) must be increased accordingly, which may reduce bending reliability.

[0150] The lower bonding layer (150) according to the embodiment may have a structure of Formula 1 (A1) as shown in FIG. 4e. In particular, the lower bonding layer (150) may be composed of epoxy chains provided in epoxy resin, with polyimide added thereto. Furthermore, the hot melt adhesive of the card body may have a structure of Formula 2 (A2) as shown in FIG. 4e. In this case, the hot melt adhesive of the card body may include polyimide chains. Accordingly, as polyimide is included in the lower bonding layer (150) in a certain amount, the bonding strength between the polyimide chains of the lower bonding layer (150) and the polyimide chains of the hot melt adhesive of the card body can be improved. Therefore, the embodiment can further improve bending reliability.

[0151]

[0152] Meanwhile, referring to FIGS. 5 and 6, the smart IC substrate may be provided as a dual type. For example, the smart IC substrate may have a structure in which a conductive pattern portion is provided on each side of the substrate (110). For example, the smart IC substrate may include a conductive pattern portion (120) that is disposed on the first surface (110S1) of the substrate (110) and described with reference to FIGS. 1, FIG. 2, FIG. 3a, and FIG. 3b. In this case, the conductive pattern portion (120) described with reference to FIGS. 1, FIG. 2, FIG. 3a, and FIG. 3b may be referred to as the first conductive pattern portion (120) or the upper conductive pattern portion (120) in the dual-type smart IC substrate.

[0153] Additionally, the smart IC substrate may further include a second conductive pattern portion (130, 135) or a lower conductive pattern portion (130, 135) disposed on the second surface (110S2) of the substrate (110). Hereinafter, this will be described as the second conductive pattern portion.

[0154] The second conductive pattern portion (130, 135) may be spaced apart from the first conductive pattern portion (120) with the substrate (110) in between. The second conductive pattern portion (130, 135) may be an antenna pad for an antenna function. For example, the second conductive pattern portion (130, 135) may be an antenna pad that electrically connects a chip mounted on a smart IC substrate (100) and an antenna pattern.

[0155] At this time, the second conductive pattern portion (130, 135) may be formed in a different way from the first conductive pattern portion (120). For example, the first conductive pattern portion (120) may be formed by etching the metal layer (120a) through an exposure and development process. For example, the first conductive pattern portion (120) may be formed through a photolithography process.

[0156] In contrast, the second conductive pattern portion (130, 135) can be attached to the second surface (110S2) of the substrate (110) in a pick and place manner. For example, the second conductive pattern portion (130, 135) can be attached to the second surface (110S2) of the substrate (110) after being formed on a separate structure.

[0157] A lower bonding layer (150) may be provided between the second surface (110S2) of the substrate (110) and the second conductive pattern portion (130, 135).

[0158] At this time, the lower bonding layer (150) has been described with reference to a previous embodiment, and accordingly, a detailed description thereof is omitted. Here, the lower bonding layer (150) in the previous embodiment is provided to improve the bonding strength with the hot melt adhesive of the card body. Furthermore, the lower bonding layer (150) in the embodiment of FIGS. 5 and 6 can provide bonding strength for attaching a second conductive pattern portion (130, 135) on the second surface (110S2) of the substrate (110) while improving the bonding strength with the hot melt adhesive of the card body.

[0159] In this way, the embodiment can form the first conductive pattern portion (120) and the second conductive pattern portion (130, 135) on the first surface (110S1) and the second surface (110S2) of the substrate (110) in different ways, respectively. Accordingly, the embodiment can resolve the problem that the manufacturing process of a double-sided wiring structure is complex and the manufacturing cost increases due to reduced product yield, which is a characteristic of the product structure of the smart IC substrate (100). That is, the embodiment can simplify the manufacturing process of the smart IC substrate (100) by forming an antenna pattern by attaching the pre-manufactured second conductive pattern portion (130, 135) to the substrate (110). Furthermore, the embodiment can easily adjust the attachment position of the second conductive pattern portion (130, 135) according to various product designs, can be applied to products of various designs, and can improve the degree of design freedom accordingly. Furthermore, the embodiment can reduce manufacturing costs by simplifying the process and further improve product yield.

[0160] Additionally, the lower bonding layer (150) may be larger than the thickness (T1) of the upper bonding layer (140). For example, the thickness (T2) of the lower bonding layer (150) may satisfy a range of 105% to 220%, or 110% to 210%, or 115% to 200% of the thickness (T1) of the upper bonding layer (140). That is, the embodiment makes the thickness (T2) of the lower bonding layer (150) larger than the thickness (T1) of the upper bonding layer (140), so that the second conductive pattern portion (130, 135) can be more stably attached to the second surface (110S2) of the substrate (110), and thus product reliability can be improved. Furthermore, the embodiment allows the thickness (T2) of the lower bonding layer (150) to be greater than the thickness (T1) of the upper bonding layer (140), thereby reducing the height difference between the terminals of the chip and the second conductive pattern portions (130, 135) by the difference in thicknesses (T1, T2) described above. Accordingly, the embodiment can improve process characteristics in the process of wire bonding the second conductive pattern portions (130, 135) and the terminals of the chip, and thus further improve wire bonding reliability. At this time, if the thickness (T2) of the lower bonding layer (150) is less than 105% of the thickness (T1) of the upper bonding layer (140), the bonding strength between the lower bonding layer (150) and the hot melt adhesive of the card body as described above may be reduced or the bending reliability may be reduced.

[0161] The second conductive pattern portion (130, 135) can be attached to the second surface (110S2) of the substrate (110) by means of an adhesive force provided through the lower bonding layer (150). The second conductive pattern portion (130, 135) may have a predetermined width (W2) and thickness (W3).

[0162] At this time, the embodiment can form a second conductive pattern portion (130, 135) by attaching a pre-manufactured conductive pattern as described above, and accordingly, the second conductive pattern portion (130, 135) can be formed without any constraint on the width (W2). To this end, the embodiment makes the width (W2) of the second conductive pattern portion (130, 135) larger than the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) may be larger than the width of the lower surface of the first conductive pattern portion (120) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the width (W2) of the second conductive pattern portion (130, 135) may be either the width in the longitudinal direction and / or the width in the width direction. The width (W2) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220%, or a range of 110% to 210%, or a range of 120% to 200% of the width (W1) of the through hole (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0163] In the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), thereby increasing the contact area between the second conductive pattern portion (130, 135) and the lower bonding layer (150) and increasing their bonding strength, which allows the second conductive pattern portion (130, 135) to be attached more stably to the second surface (110S2) of the substrate (110). Through this, the embodiment can further improve product reliability. Additionally, in the embodiment, the width (W2) of the second conductive pattern portion (130, 135) is made larger than the width (W2) of the first conductive pattern portion (120), which can increase the allowable current of the second conductive pattern portion (130, 135) and improve antenna characteristics accordingly.

[0164] At this time, if the width (W2) of the second conductive pattern portion (130, 135) is less than 105% of the width (W1) of the through hole (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the effect of improving product reliability and / or the effect of improving antenna characteristics as described above may be insufficient. Additionally, if the width (W2) of the second conductive pattern portion (130, 135) exceeds 220% of the width (W1) of the through hole (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), the thickness of the smart IC substrate (100) may increase.

[0165] Additionally, the thickness (T3) of the second conductive pattern portion (130, 135) may differ from the thickness of the first conductive pattern portion (120). Preferably, the thickness (T3) of the second conductive pattern portion (130, 135) may satisfy a range of 105% to 220% of the thickness of the first conductive pattern portion (120). At this time, the thickness of the first conductive pattern portion (120) may refer to the thickness of the metal layer (120a), or may refer to the sum of the thicknesses in the vertical direction of the metal layer (120a), the first conductive layer (120b), and the second conductive layer (120c). In the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is greater than the thickness of the first conductive pattern portion (120), thereby improving the allowable current of the second conductive pattern portion (130, 135) and further improving the antenna characteristics accordingly. In addition, in the embodiment, the thickness (T3) of the second conductive pattern portion (130, 135) is greater than the thickness of the first conductive pattern portion (120), thereby reducing the step difference between the second conductive pattern portion (130, 135) and the terminal of the chip, and thereby improving the wire bonding process characteristics. Therefore, the embodiment can improve the product reliability of the smart IC substrate (100).

[0166] At this time, the second conductive pattern portion (130, 135) may be provided as an alloy. For example, the second conductive pattern portion (130, 135) may be provided as a Cu / Sn / Ag alloy, an Fe / Ni / Ag alloy, or a Cu / Sn / Ag / Al / Ni alloy.

[0167] The second conductive pattern portion (130, 135) may include a plurality of pads electrically separated from each other. For example, the second conductive pattern portion (130, 135) may include a first antenna pad (130) and a second antenna pad (135) electrically separated from the first antenna pad (130). For example, the first antenna pad (130) may be a pad to which a power source of positive polarity is applied, and the second antenna pad (135) may be a pad to which a power source of negative polarity is applied.

[0168] The first antenna pad (130) and the second antenna pad (135) can each be divided into multiple parts. In this case, the first antenna pad (130) and the second antenna pad (135) can be described as lower pads disposed on the second surface (110S2) of the substrate (110).

[0169] The first antenna pad (130) may include a first portion (131) located closest to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping along the vertical direction with the through holes. The first portion (131) of the first antenna pad (130) may be a wire bonding area for electrically connecting to the terminals of the chip.

[0170] The first antenna pad (130) may include a second part (132) of the first antenna pad (130) located further from the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first part (131) of the first antenna pad (130). The second part (132) of the first antenna pad (130) may be the area closest to the edge of the second surface (110S2) of the substrate (110) in the first antenna pad (130). The second part (132) of the first antenna pad (130) may be a terminal area for connection with an antenna pattern (not shown).

[0171] The first antenna pad (130) may include a third part (133) connecting the first part (131) and the second part (132). The third part (133) of the first antenna pad (130) can electrically connect the first part (131) and the second part (132) of the first antenna pad (130) while keeping them spaced apart at a certain distance. For example, the third part (133) of the first antenna pad (130) can facilitate the electrical connection process with the chip in the first part (131) of the first antenna pad (130) and the connection process with the antenna pattern in the second part (132) of the first antenna pad (130) at a spaced-apart location, respectively.

[0172] The second antenna pad (135) may include a first portion (136) of the second antenna pad (135) located closest to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) without overlapping along the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). The first portion (136) of the second antenna pad (135) may be a wire bonding area for electrically connecting to the terminals of the chip.

[0173] The second antenna pad (135) may include a second part (137) of the second antenna pad (135) located further from the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) than the first part (136) of the second antenna pad (135). The second part (137) of the second antenna pad (135) may be the area closest to the edge of the second surface (110S2) of the substrate (110) on the second antenna pad (135). The second part (137) of the second antenna pad (135) may be a terminal area for connection with an antenna pattern (not shown).

[0174] The second antenna pad (136) may include a third part (138) of the second antenna pad (135) that connects the first part (136) of the second antenna pad (135) and the second part (137) of the second antenna pad (135). The third part (138) of the second antenna pad (135) can electrically connect the first part (136) of the second antenna pad (135) and the second part (137) of the second antenna pad (135) while keeping them spaced apart at a certain distance. For example, the third part (138) of the second antenna pad (135) can facilitate the electrical connection process with the chip in the first part (136) of the second antenna pad (135) and the connection process with the antenna pattern in the second part (137) of the second antenna pad (135) at a spaced-apart location, respectively.

[0175]

[0176] Hereinafter, smart IC substrates according to the 4th to 7th embodiments will be described with reference to FIGS. 7 to 10. At this time, the smart IC substrates of FIGS. 7 to 10 may differ from the smart IC substrates of FIGS. 1 to 6 in the material of the metal layer (120a) constituting the conductive pattern portion (120).

[0177] At this time, in the smart IC substrate according to the embodiment of FIGS. 7 to 10 described below, the upper bonding layer (140) is shown not to be disposed on the first surface (110S1) of the substrate (110), but is not limited thereto. Preferably, the upper bonding layer (140) described in the previous embodiment may be disposed between the first surface (110S1) of the substrate (110) and the conductive pattern portion (120) in FIGS. 7 to 10 described below, and preferably between the first surface (110S1) of the substrate (110) and the first buffer layer (161).

[0178] Referring to FIG. 7, the smart IC substrate according to the fourth embodiment includes a metal layer (120a) disposed on one side of the substrate (110).

[0179] At this time, the metal layer (120a) may include a binary alloy or a ternary alloy, unlike the metal layer of the first to third embodiments.

[0180] For example, the metal layer (120a) may include an alloy comprising nickel (Ni), iron (Fe), and chromium (Cr). For example, the metal layer (120a) may include a Monel-series alloy or an Inconel-series alloy. Specifically, the metal layer (120a) may be a nickel (Ni)-chromium (Cr)-iron (Fe) alloy comprising chromium and iron, with nickel as the main component. In the alloy, the meaning of the main component is defined as the metal having the largest weight percent among the plurality of metals constituting the alloy.

[0181] Alternatively, the metal layer (120a) may include a SUS-series alloy. Specifically, the metal layer (120a) may be an iron (Fe)-chromium (Cr)-nickel (Ni) alloy that has iron as the main component and includes chromium and nickel.

[0182] If the metal layer (120a) is provided with a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy as described above, a portion of the cover layer disposed on the metal layer (120a) may be omitted. For example, the metal layer (120a) comprising a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy may have corrosion resistance, wear resistance, oxidation resistance, and hardness above a certain level. Accordingly, if the metal layer (120a) comprises a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the first cover layer (120b) described in the previous embodiment may be omitted.

[0183] However, if the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy and the first cover layer (120b) is omitted, the contact surface of the conductive pattern portion (120) may not have a gold color. In this case, design satisfaction may be reduced, and user satisfaction may be reduced accordingly.

[0184] Accordingly, the embodiment may provide a first cover layer (120b) even if the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy. This improves design satisfaction and further enhances user satisfaction.

[0185] In this case, if the metal layer (120a) comprises a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the metal layer (120a) may be provided by a rolling process. In this case, the surface roughness of the metal layer (120a) may be reduced, thereby reducing the adhesion to the substrate (110).

[0186] Accordingly, a buffer layer (160) may be disposed between the first surface (110S1) of the substrate (110) and the metal layer (120a). The buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). The first buffer layer (161) may be disposed on the first surface (110S1) of the substrate (110). The second buffer layer (162) may be disposed on the first buffer layer (161). That is, the second buffer layer (162) is disposed between the first buffer layer (161) and the metal layer (120a).

[0187] The first buffer layer (161) may include a metal. For example, the first buffer layer (161) may include copper (Cu). The adhesion between the metal layer (120a) and the substrate (110) is enhanced by the first buffer layer (161).

[0188] Additionally, the second buffer layer (162) may include a metal. For example, the second buffer layer (162) may include nickel. The adhesion between the metal layer (120a) and the first buffer layer (161) can be improved by the second buffer layer (162).

[0189] The first buffer layer (161) may be divided into multiple regions along the thickness direction. For example, the first buffer layer (161) may be divided into an upper region adjacent to the second buffer layer (162) and a lower region adjacent to the first surface (110S1) of the substrate (110).

[0190] The upper region of the first buffer layer (161) may contain a metal. That is, the upper region of the first buffer layer (161) is a metal layer. For example, the upper region of the first buffer layer (161) may contain copper. The lower region of the first buffer layer (161) may contain a metal oxide. That is, the lower region of the first buffer layer (161) is a metal oxide layer. For example, the lower region of the first buffer layer (161) may contain copper oxide.

[0191] The lower region of the first buffer layer (161) may be formed by oxidizing a portion of the first buffer layer (161). The surface roughness of the lower region of the first buffer layer (161) may be increased by the oxidation process. That is, the surface roughness of the lower region of the first buffer layer (161) facing the first surface (110S1) of the substrate (110) may be greater than the surface roughness of the upper region of the first buffer layer (161). Specifically, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the metal layer (120a). Additionally, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the first buffer layer.

[0192] The thickness of the lower region of the first buffer layer (161) may be smaller than the thickness of the upper region of the first buffer layer (161). For example, the thickness of the lower region of the first buffer layer (161) may be 20% or less, 10% or less, or 5% or less of the total thickness of the first buffer layer (161). In addition, the adhesion between the first buffer layer (161) and the first surface (110S1) of the substrate (110) can be further improved by utilizing the lower region of the first buffer layer (161c).

[0193] At this time, the second buffer layer (162) can be said to be the first plating layer plated on one side of the metal layer (120a), and the first buffer layer (161) can be said to be the second plating layer plated on one side of the first plating layer.

[0194] At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) of the smart IC substrate of the fourth embodiment may further penetrate the buffer layer (160). For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first portion penetrating the substrate (110) and a second portion penetrating the buffer layer (160). According to the embodiment, a first adhesive layer may be further disposed between the buffer layer (160) and the substrate (110), and in this case, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first adhesive layer.

[0195] Additionally, the second cover layer (120c) of the smart IC substrate according to the fourth embodiment may be disposed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the buffer layer (160) and have a second part, and the second cover layer (120c) may be disposed within the second part of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0196] In this case, the first cover layer (120b) in one embodiment may be disposed only on the upper surface of the metal layer (120a). Alternatively, in another embodiment, the first cover layer (120b) may extend from the upper surface of the metal layer (120a) to cover at least a portion of the side surface of the metal layer (120a) and at least a portion of the side surface of the buffer layer (160).

[0197]

[0198] Referring to FIG. 8, the smart IC substrate of the fifth embodiment may differ from the smart IC substrate of the fourth embodiment in that through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are not provided in the buffer layer (160).

[0199] The lower surface of the buffer layer (160) in the smart IC substrate of the fifth embodiment may overlap along the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the buffer layer (160) in the area overlapping vertically with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may not be removed. In this case, a portion of the lower surface of the buffer layer (160) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be placed on the lower surface of the buffer layer (160) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0200] Referring to FIG. 9, the smart IC substrate of the 6th embodiment may differ from the smart IC substrate of the 4th embodiment in that through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in a part of the buffer layer (160).

[0201] The lower surface of the buffer layer (160) in the smart IC substrate of the sixth embodiment may overlap along the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, a portion of the buffer layer (160) in the area overlapping vertically with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be removed.

[0202] That is, the buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). And, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first buffer layer (161) but not penetrate the second buffer layer (162). In this case, a portion of the lower surface of the second buffer layer (162) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be placed on the lower surface of the second buffer layer (162) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0203] Referring to FIG. 10, the smart IC substrate of the 7th embodiment has through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) that penetrate the buffer layer (160) and penetrate at least a portion of the metal layer (120a) compared to the smart IC substrate of the 4th embodiment.

[0204] For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) can penetrate the first buffer layer (161) and the second buffer layer (162) together with the substrate (110).

[0205] Additionally, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate a portion of the metal layer (120a). For example, the metal layer (120a) may include a recess (not shown) provided in an area that overlaps along the vertical direction with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0206] And, the second cover layer (120c) can be placed within the recess of the metal layer (120a) which is superimposed vertically with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0207]

[0208] Meanwhile, according to another embodiment, the first buffer layer (161) may be bonded to one side of the metal layer (120a) by a rolling bonding method. Preferably, the first buffer layer (161) may be bonded to one side of the metal layer (120a) by a clad method. Accordingly, the first buffer layer (161) may be a bonded metal layer bonded to one side of the metal layer (120a) by a clad method. In this case, the second buffer layer (162) may be a mixed layer in which the metal material constituting the first buffer layer (161) and the metal material constituting the metal layer (120a) are mixed when bonding the metal layer (120a) and the first buffer layer (161) by a rolling bonding method. Preferably, the second buffer layer (162) may be a diffusion layer in which the metal layer (120a) diffuses toward the first buffer layer (161) or the first buffer layer (161) diffuses toward the metal layer (120a) as the metal layer (120a) and the first buffer layer (161) are bonded.

[0209]

[0210] FIG. 11 is a plan view showing a smart IC module according to one embodiment, and FIG. 12 is a cross-sectional view showing a smart IC module according to an embodiment. Preferably, FIG. 11 may show a plan view of the other side of the smart IC module in a state where the molding member (1300) is not placed.

[0211] Referring to FIGS. 11 and 12, the smart IC module (1000) may include a smart IC substrate having the plan view of FIGS. 1 and 2. However, the embodiment is not limited thereto, and the smart IC substrate provided in the smart IC module (1000) may include any one of the smart IC substrates selected in FIGS. 3 to 10.

[0212] The smart IC module (1000) may include a chip (1100) placed in a chip mounting area. Here, the chip mounting area may be an inner area of ​​a region surrounded by a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) on the second surface (110S2) of the substrate (110).

[0213] The chip (1100) can be attached to the lower bonding layer (150). Preferably, the lower bonding layer (150) can be further utilized for attaching the chip (1100).

[0214] The chip (1100) may include a plurality of terminals (not shown). For example, the chip (1100) may include first to eighth terminals.

[0215] Additionally, it may include a connecting member (1200) that connects the terminals of the chip (1100) and the pads of the smart IC substrate (100). The connecting member (1200) may be a wire, but is not limited thereto. The connecting member (1200) may include first to eighth connecting members. For example, the connecting member (1200) may include first to eighth connecting members that connect each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) exposed through a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to each of the first to eighth terminals of the chip (1100).

[0216] At this time, the smart IC module (1000) may further include a molding member (1200). The molding member (1200) can mold the chip (1100). Additionally, the molding member (1200) can mold the connecting member (1200). Accordingly, the molding member (1200) may be provided to cover the chip (1100) and the connecting member (1200) while filling the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0217] Additionally, the molding member (1200) can cover at least a portion of the lower bonding layer (150). This allows the bonding strength between the molding member (1200) and the lower bonding layer (150) to be further improved.

[0218]

[0219] FIG. 13 is a perspective view showing a smart IC card according to an embodiment, and FIG. 14 is a cross-sectional view schematically showing the smart IC card of FIG. 9.

[0220] Referring to FIGS. 13 and 14, a smart IC card (3000) according to an embodiment may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0221] The main body (3100) includes a receiving portion (3110). At this time, any one of the smart IC modules (2000) according to FIGS. 1 to 12 may be manufactured, and the manufactured smart IC module (2000) may be placed inside the receiving portion (3110).

[0222] The receiving portion (3110) may have a step. For example, the inner wall of the receiving portion (3110) may have a step. Preferably, the width of the receiving portion (3110) in the area corresponding to the upper part of the smart IC card (3000) may be greater than the width in the area corresponding to the lower part of the smart IC card (3000). Accordingly, the receiving portion (3110) may include a first portion having a first width and a second portion having a second width greater than the first width. Furthermore, the second portion of the receiving portion (3110) may accommodate a chip (1100) and a molding member (1200) provided in the smart IC module, and the first portion of the receiving portion (3110) may accommodate the remaining components of the smart IC module, excluding at least a portion of the chip (1100) and the molding member (1200). Accordingly, the embodiment can further drastically reduce the thickness of the smart IC card and allow the chip (1100) to be inserted more stably into the smart IC card.

[0223] At this time, the smart IC module (1000) may include a dual-type smart IC substrate according to FIGS. 5 and 6. In this case, an antenna pattern (not shown) may be disposed on the main body (3100). Specifically, the antenna pattern may be disposed in a coil shape on the edge of the main body (3100). The second portion (132, 137) of the antenna pads provided in the smart IC module (2000) may be connected to the antenna pattern disposed on the main body (3100) described above. An IC card including the smart IC module according to this is operated as a contactless card, a combination card, or a hybrid card.

[0224] The smart IC module (2000) is inserted into the interior of the receiving portion (3110). The smart IC module (2000) and the main body portion (3100) are bonded by an adhesive (3120). By this, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110). Preferably, the adhesive (3120) and the lower bonding layer (150) of the smart IC module (2000) can come into contact with each other, thereby further improving the bonding strength between the smart IC module (2000) and the main body portion (3100).

[0225] The first protective layer (3210) is disposed on the upper part of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed in at least one layer. That is, the first protective layer (3210) may include a plurality of layers.

[0226] The second protective layer (3220) is disposed on the lower part of the main body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed in at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0227]

[0228] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0229] Furthermore, although the above description has focused on the embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

Claims

1. Entry; An upper bonding layer disposed on the above-mentioned substrate; An upper conductive pattern portion disposed on the upper bonding layer; and It includes a lower bonding layer disposed under the above description, and A smart IC substrate comprising the upper bonding layer and the lower bonding layer, wherein the upper bonding layer and the lower bonding layer comprise different materials.

2. In Paragraph 1, The above lower bonding layer is a smart IC substrate comprising epoxy resin and polyimide.

3. In Paragraph 2, The above epoxy resin is a smart IC substrate including novolak epoxy resin.

4. In Paragraph 2 or 3, A smart IC substrate in which the above polyimide satisfies 15% to 30% by weight of the total weight of the lower bonding layer.

5. In Paragraph 2 or 3, The above polyimide is a smart IC substrate having a molecular weight of 5,000 to 20,000.

6. In any one of paragraphs 1 through 3, A smart IC substrate having the upper bonding layer and the lower bonding layer having different thicknesses.

7. In Paragraph 6, A smart IC substrate having a lower bonding layer thickness in the range of 18㎛ to 25㎛.

8. In any one of paragraphs 1 through 3, A smart IC substrate having a lower surface of the lower bonding layer having an arithmetic mean roughness in the range of 1 μm to 10.21 μm.

9. In any one of paragraphs 1 through 3, A smart IC substrate further comprising a lower conductive pattern portion disposed under the lower bonding layer.

10. In any one of paragraphs 1 through 3, The upper conductive pattern portion above is, It includes a metal layer and a buffer layer disposed between the metal layer and the upper bonding layer, A smart IC substrate comprising the above buffer layer and the above metal layer, wherein the above buffer layer and the above metal layer comprise different metal materials. 1*

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