Semiconductor package and manufacturing method thereof

Abstract

This semiconductor package comprises: a first package that includes a first redistribution structure, a first molding member disposed on the first redistribution structure, a second redistribution structure disposed on the first molding member, and a first vertical connection conductor electrically connecting the first redistribution structure and the second redistribution structure to each other; a second package that includes a third redistribution structure, a second molding member disposed on the third redistribution structure, a fourth redistribution structure disposed on the second molding member, and a second vertical connection conductor electrically connecting the third redistribution structure and the fourth redistribution structure to each other; a connection bump electrically connecting the second redistribution structure and the third redistribution structure; and a package cover layer including a first section, which surrounds the connection bump, and a second section, which extends from the first section and surrounds a side surface of the second package.

Description

Semiconductor package and method of manufacturing the same

[0001] The embodiments relate to semiconductor packages, and in particular to highly integrated semiconductor packages and methods for manufacturing the same.

[0002] Due to the increasing performance of various mobile devices, the number of input / output (I / O) terminals required in semiconductors is growing. Accordingly, Wafer Level Packaging (WLP) technology, which performs semiconductor packaging processes at the wafer level and separates the wafer-level semiconductor packages into individual units, is gaining attention.

[0003] Fan-Out Wafer Level Package (FOWLP) or Fan-Out Panel Level Package (FOPLP) is a technology that mounts semiconductor chips directly onto a wafer rather than on a circuit board (e.g., a PCB). For semiconductor packages manufactured using FOWLP and / or FOPLP, manufacturing costs can be lowered by eliminating the need for a circuit board, and it enables package miniaturization, improved heat dissipation, reduced power consumption, and enhanced frequency bandwidth.

[0004] FOWLP or FOPLP is manufactured by attaching individual dies to a carrier, molding them with a molding member, and subsequently performing processes such as forming a fan-out type redistribution layer (RDL) and bumping.

[0005] The aforementioned semiconductor packages require multifunctionality, high performance, miniaturization, and lightweighting, and consequently, high integration is required. Accordingly, research is being conducted on Package-on-Package (PFP) type semiconductor packages, in which a semiconductor package with different functions is stacked on top of a single semiconductor package, in order to provide multifunctional semiconductor packages.

[0006] However, conventional semiconductor packages have limitations in achieving high integration. Furthermore, in conventional semiconductor packages, stress may occur during the process of combining multiple packages, and electrical and / or mechanical reliability may be degraded by the aforementioned stress. For example, if stress is concentrated in the area where the terminals of semiconductor devices placed in each of the multiple packages are connected, the electrical and / or mechanical reliability of the semiconductor package may be degraded. Alternatively, if stress is concentrated in the area where multiple packages are connected to each other, electrical disconnection between the multiple packages may occur.

[0007] Therefore, there is a need for technology that enables high integration while improving electrical and / or mechanical reliability.

[0008] An embodiment provides a highly integrated semiconductor package and a method for manufacturing the same.

[0009] In addition, the embodiment provides a semiconductor package with improved electrical reliability and / or mechanical reliability and a method for manufacturing the same.

[0010] The problems of the present embodiment are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0011] A semiconductor package according to an embodiment comprises: a first package including a first redistribution structure, a first molding member disposed on the first redistribution structure, a second redistribution structure disposed on the first molding member, and a first vertical connecting conductor that penetrates the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other; a second package including a third redistribution structure, a second molding member disposed on the third redistribution structure, a fourth redistribution structure disposed on the second molding member, and a second vertical connecting conductor that penetrates the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other; and a connecting bump disposed between the first package and the second package and electrically connecting the second redistribution structure and the third redistribution structure. and includes a package cover layer comprising a first portion disposed between the first package and the second package and surrounding the connection bump, and a second portion extending from the first portion and surrounding the side of the second package.

[0012] Additionally, the first package further comprises a first semiconductor chip embedded within the first molding member and a second semiconductor chip disposed on the second redistribution structure, and the second package further comprises a third semiconductor chip embedded within the second molding member and a fourth semiconductor chip disposed on the fourth redistribution structure, wherein the second semiconductor chip is embedded within the first portion of the package cover layer.

[0013] Additionally, the second package further includes a second molding member disposed on the fourth redistribution structure and molding the fourth semiconductor chip, and the package cover layer is provided to cover the side of the second molding member of the second package.

[0014] In addition, the package cover layer further includes a third part that extends from the second part and molds the fourth semiconductor chip.

[0015] In addition, the second portion of the package cover layer has a first horizontal width and a second horizontal width that are different from each other along the perimeter direction of the side of the second package.

[0016] Additionally, each of the package cover layer and the second package includes a plurality of sides, and at least one of the plurality of sides of the second package is aligned along a vertical direction with at least one of the plurality of sides of the package cover layer, and the package cover layer does not come into contact with at least one of the aligned sides of the second package.

[0017] Additionally, the upper surface of the package cover layer is positioned lower than the upper surface of the second package, and at least some of the sides of the second molding member do not come into contact with the package cover layer.

[0018] Additionally, the upper surface of the package cover layer is positioned lower than the upper surface of the second package, and the second portion of the package cover layer is provided to cover the upper surface of the second molding member.

[0019] Additionally, the first redistribution structure and the second redistribution structure have a symmetrical structure centered on the first molding member, the third redistribution structure and the fourth redistribution structure have a symmetrical structure centered on the second molding member, and the first and second redistribution structures of the first package have a symmetrical structure with respect to the third and fourth redistribution structures of the second package centered on the first part of the package cover layer.

[0020] Additionally, the semiconductor package further comprises a third package disposed on the second package, wherein the third package comprises a fifth redistribution structure, a fourth molding member disposed on the fifth redistribution structure, a sixth redistribution structure disposed on the fourth molding member, and a third vertical connecting conductor that penetrates the fourth molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other.

[0021] Additionally, the outer width of the third package is smaller than the outer width of the first package and the outer width of the second package, and the package cover layer further includes a fourth part that extends from the third part toward the third package and surrounds the side of the third package.

[0022] Additionally, the package cover layer comprises a first package cover layer including the first part and the second part, and a second package cover layer disposed on the first package cover layer and including the third part and the fourth part.

[0023] The semiconductor package of the embodiment may include a first package and a second package that are electrically coupled to each other along a vertical direction. In this case, the first package and the second package may have a mutually symmetrical structure. Specifically, each of the first package and the second package may include a redistribution structure disposed on its upper and lower sides with a symmetrical structure, with a molding member in between.

[0024] That is, the first package may include first and second redistribution structures arranged in an up-and-down symmetrical structure with the first molding member in between. Additionally, the second package may include third and fourth redistribution structures arranged in an up-and-down symmetrical structure with the second molding member in between.

[0025] Through this, the embodiment may enable each of the first package and the second package to include a plurality of rewiring structures having an up-and-down symmetrical structure, thereby improving the integration density of the semiconductor package. Through this, the embodiment may make the semiconductor package slimmer or lighter.

[0026] In addition, the embodiment allows the first package and the second package to have an up-and-down symmetrical structure, thereby minimizing stress from thermal stress occurring in the operating environment of the semiconductor package. Furthermore, the embodiment can minimize bending occurring in the operating environment of the semiconductor package, and thereby enable the semiconductor chip to operate stably. Accordingly, the embodiment can improve the operational reliability of the semiconductor package.

[0027] In addition, the embodiment combines a first package and a second package manufactured individually using a connecting bump, thereby improving process efficiency, increasing product yield, and reducing manufacturing costs.

[0028] Additionally, the semiconductor package includes a package cover layer disposed to surround the side of the second package while filling the space between the first package and the second package. The package cover layer can prevent misalignment of the mounted semiconductor chip that occurs during the process of joining the first package and the second package using connection bumps. Accordingly, the embodiment can enable the semiconductor package to operate more stably, thereby further improving the electrical reliability and / or physical reliability of the semiconductor package. Furthermore, the embodiment can further improve the product reliability of the semiconductor package.

[0029] In addition, the embodiment can prevent the semiconductor package from bending due to stress occurring during the usage environment of the semiconductor package by using a package cover layer. Accordingly, the embodiment can improve the electrical reliability and / or mechanical reliability of the semiconductor package.

[0030] In addition, the embodiment may form a package cover layer having different widths along the periphery direction of the second package. By doing so, the embodiment can further improve the flatness of the semiconductor package by utilizing the different widths of the package cover layer.

[0031] For example, in a process for manufacturing a semiconductor package, a curing process may be performed after the package cover layer is formed. In this case, the bending of the semiconductor package after the curing process may occur not with the center of the semiconductor chip from a planar perspective as the reference axis, but with a point shifted in a specific horizontal direction as the reference axis. Accordingly, the embodiment allows the package cover layer to have different widths along the perimeter direction of the side of the second package, thereby further improving the flatness of the semiconductor package.

[0032] Through this, the embodiment can prevent and / or mitigate the bending of the semiconductor package in a specific direction. Accordingly, the embodiment can enable the semiconductor package to operate more stably, thereby further improving product reliability.

[0033] In addition, the outer surface of the semiconductor package may have a step, which can further alleviate stress generated during the operation of the semiconductor package.

[0034] FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0035] Figure 2 is a top view of the semiconductor package of Figure 1 as seen from the top direction.

[0036] FIGS. 3a to 3l are cross-sectional views showing the manufacturing method of a semiconductor package according to the first embodiment shown in FIGS. 1 and 2 in process order.

[0037] FIG. 4 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0038] Figure 5 is a top view of the semiconductor package of Figure 4 as seen from the top direction.

[0039] FIG. 6 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0040] FIGS. 7 and 8 are plan views of various embodiments of the semiconductor package of FIG. 6 viewed from the upper direction.

[0041] FIG. 9 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0042] FIG. 10 is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0043] FIG. 11 is a cross-sectional view showing a semiconductor package according to the 6th embodiment.

[0044] FIG. 12a is a cross-sectional view showing a semiconductor package according to the seventh embodiment.

[0045] FIG. 12b is a cross-sectional view showing a semiconductor package according to the eighth embodiment.

[0046] FIG. 13 is a cross-sectional view showing a semiconductor package according to the ninth embodiment.

[0047] FIG. 14 is a cross-sectional view showing a semiconductor package according to the 10th embodiment.

[0048] FIGS. 15a to 15j are cross-sectional views showing the manufacturing method of a semiconductor package illustrated in FIG. 14 in process order.

[0049] The purpose, means, and resulting effects of the present invention will become clearer through the following detailed description in conjunction with the attached drawings, and accordingly, a person skilled in the art to which the present invention pertains will be able to easily implement the technical concept of the present invention. Furthermore, in describing the present invention, if it is determined that a detailed description of known technology related to the present invention may unnecessarily obscure the essence of the present invention, such detailed description will be omitted.

[0050] The terms used in this specification are for describing embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form as appropriate unless specifically stated otherwise in the text. In this specification, terms such as "comprising," "providing," "arranging," or "having" do not exclude the presence or addition of one or more other components in addition to the components mentioned.

[0051] In this specification, terms such as "or", "at least one," etc., may indicate one of the words listed together or a combination of two or more. For example, "A or B", "at least one of A and B" may include only one of A or B, or may include both A and B.

[0052] In this specification, descriptions following "e.g." should not limit the embodiments of the invention according to various embodiments of the invention, such as variations including tolerances, measurement errors, limits of measurement accuracy, and other commonly known factors, as the information presented, such as cited characteristics, variables, or values, may not exactly match.

[0053] In this specification, where it is stated that a component is 'connected' or 'connected' to another component, it should be understood that it may be directly connected or connected to the other component, or that there may be other components in between. On the other hand, when it is mentioned that a component is 'directly connected' or 'directly connected' to another component, it should be understood that there are no other components in between.

[0054] In this specification, where a component is described as being 'on' or 'in contact' with another component, it should be understood that it may be in direct contact with or connected to the other component, but that another component may exist in between. On the other hand, where a component is described as being 'immediately above' or 'in direct contact' with another component, it should be understood that no other component exists in between. Other expressions describing the relationship between components, such as 'between' and 'directly between', may be interpreted in the same way.

[0055] In this specification, terms such as 'first', 'second', etc., may be used to describe various components, but such components should not be limited by the said terms. Furthermore, the said terms should not be interpreted as limiting the order of each component, but may be used for the purpose of distinguishing one component from another. For example, 'first component' may be named 'second component', and similarly, 'second component' may be named 'first component'.

[0056] Unless otherwise defined, all terms used herein may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0057] Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0058] A semiconductor package according to various embodiments of the present invention may be a wafer level package (WLP), a fan-out wafer level package (FOWLP), or a panel level package (PLP), but is not limited thereto.

[0059]

[0060] FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, and FIG. 2 is a plan view of the semiconductor package of FIG. 1 viewed from the upper direction.

[0061] Referring to FIGS. 1 and 2, a semiconductor package (1000) according to a first embodiment may include a first package (100), a second package (200), a connection bump (300), a package cover layer (400), and an external terminal bump (500).

[0062] The semiconductor package (1000) may have a package-on-package structure in which the first package (100) and the second package (200) are stacked along the vertical direction.

[0063] A connecting bump (300) is positioned between the first package (100) and the second package (200) and can electrically and / or physically connect the second package (200) to the first package (100).

[0064] The package cover layer (400) is disposed on the first package (100) and can cover the space between the first package (100) and the second package (200) and the second package (200).

[0065] An external terminal bump (500) is positioned at the bottom of the first package (100) to allow the semiconductor package (1000) to be connected to an external device.

[0066] To explain this in detail, the first package (100) includes a plurality of redistribution structures. For example, the first package (100) may have redistribution structures provided on the upper side and the lower side, respectively.

[0067] The first package (100) may include a first redistribution structure (110). The first redistribution structure (110) may be a lower redistribution structure located on the lower side of the first package (100).

[0068] The first rewiring structure (110) can electrically connect the first package (100) and the second package (200). Alternatively, the first rewiring structure (110) can electrically connect the first package (100) to an external device connected to an external terminal bump (500).

[0069] The first redistribution structure (110) may include a first redistribution insulating layer (111) and a first redistribution line. The first redistribution line refers to a signal line for transmitting an electrical signal, and for this purpose, may include a first redistribution pattern (112) and a first redistribution via (113).

[0070] The first redistribution insulating layer (111) may be provided in multiple layers depending on the type and number of semiconductor chips mounted on the first redistribution structure (110). The first redistribution insulating layer (111) may include a PID (Photo Imageable Dielectric) material. For example, the first redistribution insulating layer (111) may include a photosensitive polyimide (PSPI). That is, the first redistribution insulating layer (111) may include a photosensitive material capable of forming relatively fine wiring lines.

[0071] The first redistribution line includes a first redistribution pattern (112) and a first redistribution via (113). The first redistribution pattern (112) and the first redistribution via (113) of the first redistribution line may be disposed in the first redistribution insulating layer (111). The first redistribution pattern (112) may also be referred to as a redistribution circuit and may be provided extending along a horizontal direction on the surface of the first redistribution insulating layer (111). The first redistribution via (113) may extend penetrating at least a portion of the first redistribution insulating layer (111) along a vertical direction. The first redistribution via (113) may electrically connect the first redistribution patterns (112) provided in different layers.

[0072] The first redistribution pattern (112) and the first redistribution via (113) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc., or alloys thereof.

[0073] The width of the first redistribution via (113) in the horizontal direction may vary in one direction. For example, the width of the first redistribution via (113) in the horizontal direction may decrease from the upper surface of the first redistribution insulating layer (111) toward the lower surface. For example, the first redistribution structure (110) may be formed by performing a sequential redistribution process on a separate carrier member (not shown).

[0074] The first redistribution structure (110) may include a connection pad. The first redistribution connection pad may refer to a redistribution pattern formed on the outermost layer among the first redistribution patterns (112) provided in the first redistribution structure (110).

[0075] For example, the first redistribution structure (110) may include a lower connection pad. The lower connection pad may refer to a redistribution pattern positioned at the lowest side among the first redistribution patterns (112) of the first redistribution structure (110). The lower connection pad of the first redistribution structure (110) may be a pad to which an external terminal bump (500) is connected. The lower connection pad of the first redistribution structure (110) may be a pad that is electrically connected to an external device through the external terminal bump (500).

[0076] Additionally, the first redistribution structure (110) may include a first upper connection pad. The first upper connection pad may refer to a redistribution pattern positioned at the uppermost position among the first redistribution patterns (112) of the first redistribution structure (110). The first upper connection pad of the first redistribution structure (110) may be a pad connected to the first semiconductor chip (150). For example, the first upper connection pad of the first redistribution structure (110) may be a pad electrically connected to the terminals (155) of the first semiconductor chip (150).

[0077] Additionally, the first redistribution structure (110) may include a second upper connection pad. The second upper connection pad may refer to a redistribution pattern positioned at the uppermost position among the first redistribution patterns (112) of the first redistribution structure (110). The second upper connection pad of the first redistribution structure (110) may be a pad connected to the first vertical connection conductor (140). For example, the second upper connection pad of the first redistribution structure (110) may be a pad electrically connected to the second redistribution structure (120) of the first package (100) through the first vertical connection conductor (140).

[0078] The connection pads described above can penetrate at least a portion of the first redistribution insulation layer (111). For example, the connection pads may include a UBM layer.

[0079] The connection pads of the first redistribution structure (110) may include metals or alloys thereof such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. The connection pads of the first redistribution structure (110) may further include a UBM seed layer (not shown). In this case, the UBM seed layer is formed by performing a physical vapor deposition process, and the UBM layer of the connection pads may be formed through an electroplating process using the UBM seed layer.

[0080] Additionally, in exemplary embodiments, the connection pads may be provided with a wetting layer (such as a cover layer or a pre-metal layer) having excellent wettability to improve connection reliability. The wetting layer may be Au, Pd, Ni, Cu, Sn, and alloys thereof, or Ti, Cr, W, or Al.

[0081] A first semiconductor chip (150) may be disposed on the first redistribution structure (110). A terminal (155) of the first semiconductor chip (150) may be electrically connected to the first redistribution structure (110) through a first conductive bump (160). A plurality of first semiconductor chips (150) may be provided on the first redistribution structure (110) spaced apart along the horizontal direction. Although FIG. 1 shows two first semiconductor chips (150), it is not limited thereto.

[0082] The first semiconductor chip (150) may include a plurality of individual devices of various types. For example, the plurality of individual devices may include microelectronic devices, CMOS transistors (complementary metal insulator semiconductor transistors), MOSFETs (metal-oxide semiconductor field effect transistors), system LSIs (large scale integration), photoelectric devices such as CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), elastic wave filter devices, active devices, passive devices, etc., but are not limited thereto.

[0083] The first semiconductor chip (150) may include a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory semiconductor chip such as PRAM (Phase-change Random Access Memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory), but is not limited thereto.

[0084] Preferably, the first semiconductor chip (150) may include a logic chip. For example, the logic chip may be a CPU (Central Processor Unit), DSP (Digital Signal Processor), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), MCU (Micro Processor Unit), EPU (Encryption Processor Unit), or AP (Application Processor), but is not limited thereto.

[0085] The first semiconductor chip (150) may have an upper surface and a lower surface facing it. The first semiconductor chip (150) may have a terminal (155). The terminal (155) may also be referred to as a chip pad. The terminal (155) of the first semiconductor chip (150) may input and / or output a signal between the first semiconductor chip (150) and the first rewiring structure (110). The terminal (155) of the first semiconductor chip (150) may extend the function of the first semiconductor chip (150) externally by being electrically connected to the integrated circuit of the first semiconductor chip (150).

[0086] At this time, the terminal (155) of the first semiconductor chip (150) may be positioned to protrude from the first semiconductor chip (150) at a certain height. The terminal (155) of the first semiconductor chip (150) can function to improve the positional alignment between the first rewiring structure (110), thereby improving the electrical connection reliability between the first semiconductor chip (150) and the first rewiring structure (110).

[0087] A first conductive bump (160) may be disposed between the first redistribution structure (110) and the first semiconductor chip (150). The first conductive bump (160) can electrically connect the terminal (155) of the first redistribution structure (110) and the first semiconductor chip (150). The first conductive bump (160) may be formed using a solder ball, but is not limited thereto.

[0088] The first vertical connecting conductor (140) may be placed on the first redistribution structure (110). The first vertical connecting conductor (140) may be directly connected to the first redistribution line of the first redistribution structure (110). For example, the first vertical connecting conductor (140) may be directly connected to the second upper connecting pad placed on the top layer of the first redistribution pattern (112) of the first redistribution structure (110).

[0089] The first vertical connecting conductor (140) may protrude with a certain height on the first redistribution structure (110). The first vertical connecting conductor (140) may overlap with the first semiconductor chip (150) along the horizontal direction on the first redistribution structure (110). For example, a plurality of the first vertical connecting conductors (140) may be provided along the circumferential direction of the first semiconductor chip (150) at a position spaced apart from the first semiconductor chip (150) along the horizontal direction.

[0090] The first vertical connecting conductor (140) may be provided penetrating the first molding member (130) along the vertical direction. The upper surface of the first vertical connecting conductor (140) may be at the same vertical level as the upper surface of the first molding member (130).

[0091] The first vertical connecting conductor (140) can electrically connect the first redistribution structure (110) and the second redistribution structure (120). The first vertical connecting conductor (140) may include copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), palladium (Pd), or a combination thereof. In exemplary embodiments, the first vertical connecting conductor (140) may be a conductive post formed through a plating process and containing copper.

[0092] A first molding member (130) may be disposed on the first rewiring structure (110). The first molding member (130) may be disposed by embedding the first semiconductor chip (150). For example, the first molding member (130) may be provided to surround the side, bottom, and top of the first semiconductor chip (150). Additionally, the first molding member (130) may be provided to surround the first conductive bump (160). Additionally, the first molding member (130) may be provided to surround the first vertical connecting conductor (140).

[0093] The upper surface of the first molding member (130) may be at the same vertical level as the upper surface of the first vertical connecting conductor (140). Additionally, the upper surface of the first molding member (130) may be at the same vertical level as the lower surface of the second redistribution structure (120).

[0094] The first molding member (130) may include a non-conductive material and thereby mold the first vertical connecting conductor (140), the first conductive bump (150), and the first semiconductor chip (150). For example, the first molding member (130) can reliably protect the first semiconductor chip (150) from a harmful external environment.

[0095] The first molding member (130) may include various oxide or polymer materials, but is not limited thereto. However, the first molding member (130) may be provided with an EMC (Epoxy Mold Compound) to improve processability while lowering the manufacturing cost of the semiconductor package (1000).

[0096] The first package (100) may include a second redistribution structure (120). The second redistribution structure (120) may be placed on the first redistribution structure (110). The second redistribution structure (120) may be placed on the first molding member (130). Preferably, the second redistribution structure (120) may be placed on the first vertical connecting conductor (140).

[0097] The second redistribution structure (120) can be electrically connected to the first redistribution structure (110) through the first vertical connection conductor (140). The first package (100) as described above may have a structure in which the first redistribution structure (110) and the second redistribution structure (120) are arranged on both sides with the first molding member (130) that molds the second semiconductor chip (170) in between.

[0098] In this way, the embodiment can improve the integration density of the first package (100) as the first package (100) includes a first redistribution structure (110) and a second redistribution structure (120). In this way, the embodiment can make the semiconductor package (1000) slimmer or lighter.

[0099] Furthermore, the first package (100) may have a first redistribution structure (110) and a second redistribution structure (120) arranged symmetrically on both sides with the first molding member (130) in between. Accordingly, the embodiment can minimize stress from thermal stress occurring in the usage environment of the semiconductor package (1000). Furthermore, the embodiment can minimize bending occurring in the usage environment of the semiconductor package (1000), thereby enabling the semiconductor chip to operate stably. Accordingly, the embodiment can improve the operational reliability of the semiconductor package.

[0100] The second redistribution structure (120) may be an upper redistribution structure located above the first molding member (130) in the first package (100).

[0101] The second redistribution structure (120) may include a second redistribution insulating layer (121) and a second redistribution line. The second redistribution line refers to a signal line for transmitting an electrical signal, and for this purpose, it may include a second redistribution pattern (122) and a second redistribution via (123). At this time, the structure of the second redistribution structure (120) may correspond to or be similar to the first redistribution structure (110) described above, and accordingly, a detailed description thereof is omitted.

[0102] The second redistribution via (123L) positioned at the bottom of the second redistribution structure (120) can be directly connected to the first vertical connection conductor (140). For example, the width of the second redistribution via (123L) in the horizontal direction may decrease along the vertical direction. And, the bottom surface having the smallest width of the second redistribution via (123L) can be in direct contact with the top surface of the first vertical connection conductor (140).

[0103] The second rewiring structure (120) may include a first upper connection pad and a second upper connection pad corresponding to the first rewiring structure (110). The first upper connection pad of the second rewiring structure (120) may be a pad connected to the second semiconductor chip (170). For example, the first upper connection pad of the second rewiring structure (120) may be a pad electrically connected to the terminals (175) of the second semiconductor chip (170).

[0104] Additionally, the second redistribution structure (120) may include a second upper connection pad. The second upper connection pad may refer to a redistribution pattern positioned at the uppermost position among the second redistribution patterns (122) of the second redistribution structure (120). The second upper connection pad of the second redistribution structure (120) may be a pad connected to a connection bump (300). For example, the second upper connection pad of the second redistribution structure (120) may be a pad electrically connected to the second package (200) through the connection bump (300).

[0105] A second semiconductor chip (170) may be disposed on the second redistribution structure (120). A terminal (175) of the second semiconductor chip (170) may be electrically connected to the second redistribution structure (120) through a second conductive bump (180). Multiple second semiconductor chips (170) may be provided on the second redistribution structure (120) spaced apart along the horizontal direction.

[0106] The second semiconductor chip (170) may include a plurality of individual devices of various types corresponding to the first semiconductor chip (150). For example, the plurality of individual devices may include microelectronic devices, photoelectric devices such as CMOS transistors (complementary metal insulator semiconductor transistors), MOSFETs (metal-oxide semiconductor field effect transistors), system LSIs (large scale integration), CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), elastic wave filter devices, active devices, passive devices, etc., but are not limited thereto.

[0107] The second semiconductor chip (170) may include a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory semiconductor chip such as PRAM (Phase-change Random Access Memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory), but is not limited thereto.

[0108] Preferably, the second semiconductor chip (170) may include a logic chip. For example, the logic chip may be a CPU (Central Processor Unit), DSP (Digital Signal Processor), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), MCU (Micro Processor Unit), EPU (Encryption Processor Unit), or AP (Application Processor), but is not limited thereto.

[0109] A second conductive bump (180) may be disposed between the second redistribution structure (120) and the second semiconductor chip (170). The second conductive bump (180) can electrically connect the terminal (175) of the second redistribution structure (120) and the second semiconductor chip (170).

[0110] The second package (200) may be placed on the first package (100). For example, the first package (100) and the second package (200) may have a package-on-package structure.

[0111] The second package (200) may include a third redistribution structure (210). The third redistribution structure (210) may be placed on the first package (100). The third redistribution structure (210) may be placed on a connection bump (300). In particular, the third redistribution structure (210) may be electrically connected to the first package (100) through the connection bump (300). Specifically, the third redistribution structure (210) may be electrically connected to the second redistribution structure (120) of the first package (100).

[0112] The third redistribution structure (210) may be a lower redistribution structure located on the lower side of the second package (200). The third redistribution structure (210) may include a third redistribution insulating layer (211) and a third redistribution line. The third redistribution line refers to a signal line for transmitting an electrical signal, and for this purpose, it may include a third redistribution pattern (212) and a third redistribution via (213). At this time, the structure of the third redistribution structure (210) may correspond to or be similar to the first and second redistribution structures (110, 120) described above, and accordingly, a detailed description thereof is omitted.

[0113] The third redistribution structure (210) may include a lower connection pad, a first upper connection pad, and a second upper connection pad corresponding to the first redistribution structure (110).

[0114] The lower connection pad of the third rewiring structure (210) may be a pad connected to the connection bump (300). The first upper connection pad of the third rewiring structure (210) may be a pad connected to the third semiconductor chip (260). For example, the first upper connection pad of the third rewiring structure (210) may be a pad electrically connected to the terminals (265) of the third semiconductor chip (260).

[0115] Additionally, the second upper connection pad of the third redistribution structure (210) may be a pad connected to the second vertical connection conductor (240). For example, the second upper connection pad of the third redistribution structure (210) may be a pad electrically connected to the fourth redistribution structure (220) of the second package (200) through the second vertical connection conductor (240).

[0116] A third semiconductor chip (260) may be disposed on the third redistribution structure (210). A terminal (265) of the third semiconductor chip (260) may be electrically connected to the third redistribution structure (210) through a third conductive bump (270). Multiple third semiconductor chips (260) may be provided on the third redistribution structure (210) spaced apart along the horizontal direction.

[0117] The third semiconductor chip (260) may include a plurality of individual devices of various types. For example, the plurality of individual devices may include microelectronic devices, CMOS transistors (complementary metal insulator semiconductor transistors), MOSFETs (metal-oxide semiconductor field effect transistors), system LSIs (large scale integration), photoelectric devices such as CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), elastic wave filter devices, active devices, passive devices, etc., but are not limited thereto.

[0118] The third semiconductor chip (260) may include a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory semiconductor chip such as PRAM (Phase-change Random Access Memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory), but is not limited thereto.

[0119] Preferably, the third semiconductor chip (260) may include a logic chip. For example, the logic chip may be a CPU (Central Processor Unit), DSP (Digital Signal Processor), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), MCU (Micro Processor Unit), EPU (Encryption Processor Unit), or AP (Application Processor), but is not limited thereto.

[0120] A third conductive bump (270) may be disposed between the third redistribution structure (210) and the third semiconductor chip (260). The third conductive bump (270) may electrically connect the terminal (265) of the third redistribution structure (210) and the third semiconductor chip (260). The third conductive bump (270) may be formed using a solder ball, but is not limited thereto.

[0121] The second vertical connecting conductor (240) may be placed on the third redistribution structure (210). The second vertical connecting conductor (240) may be directly connected to the third redistribution line of the third redistribution structure (210). For example, the second vertical connecting conductor (240) may be directly connected to the second upper connecting pad placed on the top layer of the third redistribution pattern (212) of the third redistribution structure (210).

[0122] The second vertical connecting conductor (240) may protrude with a certain height on the third redistribution structure (210). The second vertical connecting conductor (240) may overlap with the third semiconductor chip (260) along the horizontal direction on the third redistribution structure (210). For example, a plurality of second vertical connecting conductors (240) may be provided along the circumferential direction of the third semiconductor chip (260) at a position spaced apart from the third semiconductor chip (260) along the horizontal direction.

[0123] The second vertical connecting conductor (240) may be provided penetrating the second molding member (230) along the vertical direction. The upper surface of the second vertical connecting conductor (240) may be at the same vertical level as the upper surface of the second molding member (230).

[0124] The second vertical connecting conductor (240) can electrically connect the third redistribution structure (210) and the second redistribution structure (120). The second vertical connecting conductor (240) may include copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), palladium (Pd), or a combination thereof. In exemplary embodiments, the second vertical connecting conductor (240) may be a conductive post formed through a plating process and containing copper.

[0125] A second molding member (230) may be disposed on the third rewiring structure (210). The second molding member (230) may be disposed by embedding the third semiconductor chip (260). For example, the second molding member (230) may be provided to surround the side, bottom, and top of the third semiconductor chip (260). Additionally, the second molding member (230) may be provided to surround the third conductive bump (270). Additionally, the second molding member (230) may be provided to surround the second vertical connecting conductor (240).

[0126] The upper surface of the second molding member (230) may be at the same vertical level as the upper surface of the second vertical connecting conductor (240). Additionally, the upper surface of the second molding member (230) may be at the same vertical level as the lower surface of the second redistribution structure (120).

[0127] The second molding member (230) may include a non-conductive material and thereby mold the second vertical connecting conductor (240), the third conductive bump (270), and the third semiconductor chip (260). For example, the second molding member (230) can reliably protect the third semiconductor chip (260) from an external harmful environment.

[0128] The second molding member (230) may include various oxide or polymer materials, but is not limited thereto. However, the second molding member (230) may be provided with an EMC (Epoxy Mold Compound) to improve processability while lowering the manufacturing cost of the semiconductor package (1000).

[0129] The second package (200) may include a fourth redistribution structure (220). The fourth redistribution structure (220) may be placed on the third redistribution structure (210). The fourth redistribution structure (220) may be placed on the second molding member (230). Preferably, the fourth redistribution structure (220) may be placed on the second vertical connection conductor (240).

[0130] The fourth redistribution structure (220) can be electrically connected to the third redistribution structure (210) through the second vertical connecting conductor (240). The second package (200) as described above may have a structure in which the third redistribution structure (210) and the fourth redistribution structure (220) are arranged on both sides with the second molding member (230) that molds the fourth semiconductor chip (280) in between.

[0131] In this way, the embodiment can improve the integration density of the second package (200) as the second package (200) includes a third redistribution structure (210) and a fourth redistribution structure (220). In this way, the embodiment can make the semiconductor package (1000) slimmer or lighter.

[0132] Furthermore, the second package (200) may have a third redistribution structure (210) and a fourth redistribution structure (220) arranged symmetrically on both sides with the second molding member (230) in between. Accordingly, the embodiment can minimize stress from thermal stress occurring in the usage environment of the semiconductor package (1000). Furthermore, the embodiment can minimize bending occurring in the usage environment of the semiconductor package (1000), thereby enabling the semiconductor chip to operate stably. Accordingly, the embodiment can improve the operational reliability of the semiconductor package.

[0133] The fourth redistribution structure (220) may be an upper redistribution structure located above the second molding member (230) in the second package (200).

[0134] The fourth redistribution structure (220) may include a fourth redistribution insulating layer (221) and a fourth redistribution line. The fourth redistribution line refers to a signal line for transmitting an electrical signal, and for this purpose, it may include a fourth redistribution pattern (222) and a fourth redistribution via (223). At this time, the structure of the fourth redistribution structure (220) may correspond to or be similar to the third redistribution structure (210) described above, and accordingly, a detailed description thereof is omitted.

[0135] The fourth redistribution via (223L) positioned at the bottom of the fourth redistribution structure (220) can be directly connected to the second vertical connection conductor (240). For example, the width of the fourth redistribution via (223L) in the horizontal direction may decrease along the vertical direction. And, the bottom surface having the smallest width of the second redistribution via (223L) can be in direct contact with the top surface of the second vertical connection conductor (240).

[0136] The fourth rewiring structure (220) may include a first upper connection pad and a second upper connection pad corresponding to the third rewiring structure (210). The first upper connection pad of the fourth rewiring structure (220) may be a pad connected to the fourth semiconductor chip (280). For example, the first upper connection pad of the fourth rewiring structure (220) may be a pad electrically connected to the terminals (285) of the fourth semiconductor chip (280).

[0137] A fourth semiconductor chip (280) may be disposed on the fourth redistribution structure (220). A terminal (285) of the fourth semiconductor chip (280) may be electrically connected to the fourth redistribution structure (220) through a fourth conductive bump (290). Multiple fourth semiconductor chips (280) may be provided on the fourth redistribution structure (220) spaced apart along the horizontal direction.

[0138] The fourth semiconductor chip (280) may include a plurality of individual devices of various types corresponding to the first to third semiconductor chips (150, 170, 260). For example, the plurality of individual devices may include microelectronic devices, photoelectric devices such as CMOS transistors (complementary metal insulator semiconductor transistors), MOSFETs (metal-oxide semiconductor field effect transistors), system LSIs (large scale integration), CIS (CMOS imaging sensors), MEMS (micro-electro-mechanical systems), elastic wave filter devices, active devices, passive devices, etc., but are not limited thereto.

[0139] The fourth semiconductor chip (280) may include a memory semiconductor chip. For example, the memory semiconductor chip may be a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory semiconductor chip such as PRAM (Phase-change Random Access Memory), MRAM (Magneto-resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory), but is not limited thereto.

[0140] Preferably, the fourth semiconductor chip (280) may include a logic chip. For example, the logic chip may be a CPU (Central Processor Unit), DSP (Digital Signal Processor), MPU (Micro Processor Unit), GPU (Graphic Processor Unit), MCU (Micro Processor Unit), EPU (Encryption Processor Unit), or AP (Application Processor), but is not limited thereto.

[0141] A fourth conductive bump (290) may be disposed between the fourth redistribution structure (220) and the fourth semiconductor chip (280). The fourth conductive bump (290) can electrically connect the terminal (285) of the fourth redistribution structure (220) and the fourth semiconductor chip (280).

[0142] Additionally, the semiconductor package (1000) may include a package cover layer (400). The package cover layer (400) may be disposed between the first package (100) and the second package (200).

[0143] The package cover layer (400) can mold the space between the first package (100) and the second package (200). For example, the package cover layer (400) can mold the connection bump (300). Additionally, the package cover layer (400) can mold the second semiconductor chip (170) disposed on the upper surface of the second redistribution structure (120) of the first package (100). By doing so, the embodiment can stably protect the second semiconductor chip (170) while ensuring that the first package (100) and the second package (200) are stably coupled to each other.

[0144] The outer width of the package cover layer (400) may correspond to the outer width of the first package (100). For example, the area of ​​the package cover layer (400) in a planar view may be the same as the area of ​​the first package (100) in a planar view. In contrast, the outer width of the second package (200) may be smaller than the outer width of the first package (100).

[0145] Preferably, the area of ​​the second package (200) in a planar view may be smaller than the area of ​​the first package (100) in a planar view. By doing so, the embodiment can improve process efficiency in the process of combining the first package (100) and the second package (200). Furthermore, the embodiment can enable the first package (100) and the second package (200) to be stably electrically coupled to each other.

[0146] That is, when electrically coupling the first package (100) and the second package (200), the connection pads of the first package (100) and the second package (200), respectively, which are coupled with the connection bump (300), may not be aligned, and positional misalignment may occur within a certain error range. Accordingly, the width in the horizontal direction of the first package (100) and / or the area in the planar view of the first package (100) may be larger than the width in the horizontal direction of the second package (200) and / or the area in the planar view of the second package (200). Therefore, the embodiment can improve process efficiency in the process of coupling the first package (100) and the second package (200) together, and furthermore, can improve product yield.

[0147] The first package (100) and the second package (200) are connected to each other through a connecting bump (300). At this time, the second package (200) may be laminated by directly performing the lamination process on the first package (100) without the connecting bump (300). However, in this case, productivity may be reduced. Furthermore, if a defect occurs during the lamination process, manufacturing costs may increase as both the first package (100) and the second package (200) must be disposed of.

[0148] Accordingly, the embodiment allows the first package (100) and the second package (200) to be manufactured individually and then electrically coupled to each other using a connecting bump (300). Thus, process efficiency can be improved, product yield can be increased, and manufacturing costs can be reduced.

[0149] In addition, in the embodiment, the first package (100) and the second package (200) may be arranged with an upper and lower symmetrical structure with the connecting bump (300) in between. Accordingly, bending of the semiconductor package (1000) that may occur due to the asymmetrical structure can be prevented.

[0150] Here, while performing the process of combining the first package (100) and the second package (200) using the connecting bump (300), a problem may occur with the physical and / or electrical reliability of the second conductive bump (180). That is, the connecting bump (300) is provided in a position that overlaps with the second conductive bump (180) along the horizontal direction. Accordingly, in the process of reflowing the connecting bump (300), the second conductive bump (180) may also be reflowed together. As a result, the second package (200) may become misaligned in the first phase.

[0151] Accordingly, the package cover layer (400) can ensure that the second package (200) is stably placed on the first package (100) while preventing the second package (200) from becoming distorted. For example, the package cover layer (400) may include a first portion disposed between the first package (100) and the second package (200), and a second portion extending from the first portion and overlapping with the second package (200) along a horizontal direction.

[0152] That is, the package cover layer (400) may come into contact with at least a portion of the side of the second package (200). The package cover layer (400) may be provided to surround the side of the second package (200). For example, the package cover layer (400) may be provided to surround the side of the third redistribution structure (210) of the second package (200). Alternatively, the package cover layer (400) may be provided to surround the side of the second molding member (230) of the second package (200). Alternatively, the package cover layer (400) may be provided to surround the side of the fourth redistribution structure (220) of the second package (200). Alternatively, the package cover layer (400) may be provided to surround the side of the third molding member (250) of the second package (200).

[0153] Through this, the package cover layer (400) can prevent the second package (200) from becoming misaligned and can stably place the second package (200) on the first package (100). Therefore, the semiconductor package (1000) can be made to operate stably, thereby greatly improving product reliability.

[0154] Additionally, the package cover layer (400) can prevent the semiconductor package (1000) from bending due to stress occurring during the use environment of the semiconductor package (1000). Accordingly, the embodiment can improve the electrical reliability and / or mechanical reliability of the semiconductor package (1000).

[0155] Meanwhile, referring to FIG. 2, the package cover layer (400) can cover the entire side of the second package (200). Preferably, the package cover layer (400) can be provided along the perimeter direction of the side of the second package (200).

[0156] That is, the side (200S) of the second package (200) may be located inward from a planar perspective than the side (400S) of the package cover layer (400). Additionally, the side (200S) of the second package (200) may be located inward from a planar perspective than the side (100S) of the first package (100). Furthermore, the side (100S) of the first package (100) and the side (400S) of the package cover layer (400) may be located on the same plane. That is, the side (100S) of the first package (100) and the side (400S) of the package cover layer (400) may be aligned on the same vertical line.

[0157] At this time, the package cover layer (400) may have a constant horizontal width (W1) along the perimeter direction of the side (200S) of the second package (200). For example, the package cover layer (400) may be provided on each of the four sides of the second package (200). The horizontal width (W1) of each part of the package cover layer (400) provided on each of the four sides of the second package (200) may be the same as each other. Accordingly, the embodiment can ensure that the second package (200) is uniformly protected along the perimeter direction of the second package (200) by the package cover layer (400).

[0158]

[0159] FIGS. 3a to 3l are cross-sectional views showing the manufacturing method of a semiconductor package according to the first embodiment shown in FIGS. 1 and 2 in process order.

[0160] The manufacturing process of a semiconductor package according to the first embodiment is divided into a process for manufacturing a first package, a process for manufacturing a second package, a process for combining the first package and the second package, and a process for forming a molding cover layer. At this time, the order of the process for manufacturing the first package and the process for manufacturing the second package may be optionally changed. For example, the second package may be manufactured preferentially over the first package, or the first package may be manufactured preferentially over the second package. An embodiment in which the first package is manufactured preferentially is described below.

[0161] Referring to FIG. 3a, the embodiment prepares a carrier member (CM) that serves as a basis for manufacturing a package (1000). The carrier member (CM) may have various shapes depending on the family of semiconductor packages.

[0162] The carrier member (CM) may have a flat plate shape. For example, from a planar perspective, the carrier member (CM) may be circular. As another example, the carrier member (CM) may be a polygon, such as a square, from a planar perspective. Specifically, the carrier member (CM) may be in the form of a wafer or a panel. The carrier member (CM) may be provided as a glass substrate, a ceramic substrate, or a plastic substrate.

[0163] Additionally, at least one side of the carrier member (CM) may be provided with a rigid member capable of offsetting bending that occurs during the manufacturing process of the semiconductor package. Subsequently, the embodiment may proceed with a first redistribution process to form a first redistribution structure (110) on the carrier member (CM). For example, the embodiment may repeat the process of stacking a first redistribution insulating layer (111) on the carrier member (CM), forming via holes in the first redistribution structure (110), and forming a first redistribution pattern (112) while forming a first redistribution via (113) that fills the via holes with a conductive material.

[0164] Next, referring to FIG. 3b, a process of forming a first vertical connection conductor (140) on the first redistribution structure (110) can be carried out. For example, the first vertical connection conductor (140) can be formed by carrying out a plating process on the second upper connection pattern of the first redistribution structure (110).

[0165] Next, referring to FIG. 3c, a process of mounting a first semiconductor chip (150) on a first redistribution structure (110) can be carried out. To this end, the embodiment may form a first conductive bump (160) on a first upper connection pad of the first redistribution structure (110). Subsequently, the embodiment may carry out a process of mounting a first semiconductor chip (150) on the first conductive bump (160).

[0166] Next, referring to FIG. 3d, a process of forming a first molding member (130) on a first redistribution structure (110) can be carried out. At this time, the first molding member (130) may be provided to cover the first semiconductor chip (150), the first conductive bump (160), and the first vertical connecting conductor (140). Subsequently, the embodiment may carry out a grinding process using a grinder (G). Through this, the upper surface of the first vertical connecting conductor (140) and the upper surface of the first molding member (130) may be located on the same plane.

[0167] Next, referring to FIG. 3e, a second rewiring process can be performed to form a second rewiring structure (120) on a first molding member (130). Subsequently, the embodiment can perform a process of mounting a second semiconductor chip (170) on the second rewiring structure (120). To do this, a second conductive bump (180) can be formed on the second rewiring structure (120), and a second semiconductor chip (170) can be mounted on the second conductive bump (180).

[0168] As described above, the first package (100) can be manufactured by carrying out the process illustrated in FIGS. 3a to 3e. Subsequently, the embodiment can carry out the process of manufacturing the second package (200).

[0169] Specifically, referring to FIG. 3f, a carrier member (CM) can be prepared, and a third redistribution process can be carried out to form a third redistribution structure (210) on the carrier member (CM). Additionally, the embodiment can carry out a process to form a second vertical connection conductor (240) on the third redistribution structure (210).

[0170] Next, referring to FIG. 3g, a process of forming a third conductive bump (270) on a third redistribution structure (210) and mounting a third semiconductor chip (260) on the third conductive bump (270) can be carried out. Subsequently, the embodiment can carry out a process of forming a second molding member (230) that molds the second vertical connecting conductor (240), the third conductive bump (270), and the third semiconductor chip (260).

[0171] Next, referring to FIG. 3h, a process of forming a fourth redistribution structure (220) on a second vertical connecting conductor (240) and a second molding member (230) can be carried out. Subsequently, the embodiment can carry out a process of forming a fourth conductive bump (290) on the fourth redistribution structure (220) and mounting a fourth semiconductor chip (280) on the fourth conductive bump (290). Subsequently, the embodiment can carry out a process of forming a third molding member (280) that molds the fourth semiconductor chip (280).

[0172] Next, referring to FIG. 3i, the embodiment can remove the carrier member (CM) placed at the bottom of the second package (200). Afterward, the embodiment can proceed with the process of forming a connection bump (300) on the bottom connection pad of the third redistribution structure (210).

[0173] Next, referring to FIG. 3j, a reflow process can be performed after placing a second package (200) including a connecting bump (300) on a first package (100) manufactured in the process described above. Through this, the first package (100) and the second package (200) can be electrically coupled to each other.

[0174] Next, referring to FIG. 3k, a process can be carried out to form a package cover layer (400) that extends along the side of the second package (200) while filling the space between the first package (100) and the second package (200). The package cover layer (400) can be provided to completely cover the side of the package cover layer (400).

[0175] Next, referring to FIG. 3L, the embodiment may proceed with a process of removing a carrier member (CM) disposed at the bottom of the first package (100). Afterward, the embodiment may proceed with a process of forming an external terminal bump (500) on the lower connection pad of the first redistribution structure (110) of the first package (100).

[0176]

[0177] A semiconductor package according to another embodiment is described below.

[0178] In the following, details identical to those already described in the first embodiment will be briefly explained or omitted. Furthermore, in the semiconductor package of the following embodiments, configurations that are substantially identical to and / or similar to the configuration of the semiconductor package of the previous embodiment will be given the same reference numerals.

[0179] FIG. 4 is a cross-sectional view showing a semiconductor package according to a second embodiment, and FIG. 5 is a plan view of the semiconductor package of FIG. 4 viewed from the upper direction.

[0180] Referring to FIGS. 4 and 5, the semiconductor package (1000A) of the second embodiment may have a different structure in the package cover layer (400) compared to the semiconductor package (1000) of the first embodiment.

[0181] For example, the package cover layer (400) in the first embodiment is arranged with the same horizontal width (W1) along the perimeter direction of the side of the second package (200).

[0182] In contrast, the package cover layer (400) in the second embodiment may have different horizontal widths along the perimeter direction of the side of the second package (200).

[0183] That is, the package cover layer (400) can be divided into a plurality of parts that contact different sides of the second package (200). And, at least one of the plurality of parts of the package cover layer (400) may have a horizontal width different from at least one other.

[0184] For example, the second package (200) may include a plurality of sides (200S1, 200S2, 200S3, 200S4). Additionally, the package cover layer (400) may include a plurality of sides (400S1, 400S2, 400S3, 400S4) that are in contact with the plurality of sides (200S1, 200S2, 200S3, 200S4) of the second package (200).

[0185] Additionally, the first package (100) may include a plurality of sides (100S1, 100S2, 100S3, 100S4). In this case, from a planar perspective, each of the plurality of sides (100S1, 100S2, 100S3, 100S4) of the first package (100) may be aligned along a vertical direction with each of the plurality of sides (400S1, 400S2, 400S3, 400S4) of the package cover layer (400).

[0186] Specifically, the second package (200) may include first to fourth sides (200S1, 200S2, 200S3, 200S4). Additionally, the package cover layer (400) may include first to fourth sides (400S1, 400S2, 400S3, 400S4) that are in contact with or face the first to fourth sides (200S1, 200S2, 200S3, 200S4) of the second package (200), respectively.

[0187] The first side (200S1) of the second package (200) and the first side (400S1) of the package cover layer (400) are arranged facing each other. The horizontal width between the first side (200S1) of the second package (200) and the first side (400S1) of the package cover layer (400) may have a first horizontal width (W2). Additionally, the second side (200S2) of the second package (200) and the second side (400S2) of the package cover layer (400) are arranged facing each other. The horizontal width between the second side (200S2) of the second package (200) and the second side (400S2) of the package cover layer (400) may have a second horizontal width (W3) that is different from the first horizontal width (W2).

[0188] For example, the first horizontal width (W2) may be larger than the second horizontal width (W3). For example, the first horizontal width (W2) between the first side (200S1) of the second package (200) and the first side (400S1) of the package cover layer (400) on one side of the vertical cross-section of the semiconductor package (1000A) may be larger than the second horizontal width (W3) between the second side (200S2) of the second package (200) and the second side (400S2) of the package cover layer (400) on the other side of the vertical cross-section of the semiconductor package (1000A).

[0189] As described above, the flatness of the semiconductor package (1000A) can be further improved by making the first horizontal width (W2) and the second horizontal width (W3) different from each other.

[0190] For example, in the process of manufacturing a semiconductor package (1000A), a curing process may be performed after the package cover layer (400) is formed. At this time, the bending of the semiconductor package (1000A) after the curing process may occur not with the center of the semiconductor chip (110) as the reference axis from a planar perspective, but with a point shifted in a specific horizontal direction as the reference axis. In this case, if the package cover layer (400) has the same horizontal width along the perimeter direction of the side of the second package (200), it may be difficult to alleviate the aforementioned bending. Therefore, the embodiment allows the package cover layer (400) to have different widths along the perimeter direction of the side of the second package (200), thereby further improving the flatness of the semiconductor package (1000A).

[0191] For example, when the semiconductor package (1000A) is bent into a smile shape, the first horizontal width (W2) can be made larger than the second horizontal width (W3), as shown in FIG. 4. Conversely, when the semiconductor package (1000A) is bent into a crying shape, the second horizontal width (W3) can be made larger than the first horizontal width (W2).

[0192] By doing so, the embodiment can prevent and / or mitigate the bending of the semiconductor package (1000A) in a specific direction. Accordingly, the embodiment can enable the semiconductor package (1000A) to operate more stably, thereby further improving product reliability.

[0193] Meanwhile, the horizontal width between the third side (200S3) of the second package (200) and the third side (400S3) of the package cover layer (400) may be the same as either the first horizontal width (W2) or the second horizontal width (W3), or may have a third horizontal width that is different from each of the first horizontal width (W2) and the second horizontal width (W3).

[0194] Additionally, the horizontal width between the fourth side (200S4) of the second package (200) and the fourth side (400S4) of the package cover layer (400) may be the same as any one of the first to third horizontal widths, or may have a fourth horizontal width that is different from each of the first to third horizontal widths.

[0195]

[0196] FIG. 6 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 7 and 8 are plan views of various embodiments of the semiconductor package of FIG. 6 viewed from an upward direction.

[0197] Referring to FIG. 6, the semiconductor package (1000B) of the third embodiment may have a different structure in the package cover layer (400) compared to the semiconductor packages (1000, 1000A) of the first and second embodiments.

[0198] For example, in the first embodiment, the package cover layer (400) is arranged with the same horizontal width (W1) along the perimeter direction of the side of the second package (200). Additionally, in the second embodiment, the package cover layer (400) may have different horizontal widths along the perimeter direction of the side of the second package (200).

[0199] Alternatively, in the third embodiment, the semiconductor package (1000B) may not have the package cover layer (400) in contact with at least one of the first to fourth sides (200S1, 200S2, 200S3, 200S4) of the second package (200). For example, at least one of the first to fourth sides (200S1, 200S2, 200S3, 200S4) of the second package (200) may not be covered by the package cover layer (400). Specifically, at least one of the first to fourth sides (200S1, 200S2, 200S3, 200S4) of the second package (200) may be aligned along a vertical direction with at least one side of the package cover layer (400) and at least one side of the first package (100).

[0200] Referring to FIG. 7, the first side (200S1) of the second package (200) may be misaligned along the vertical direction with the first side (100S1) of the first package (100) and the first side (400S1) of the package cover layer (400). The second side (200S2) of the second package (200) may be aligned along the vertical direction with the second side (100S2) of the first package (100) and the second side (400S2) of the package cover layer (400). The third side (200S3) of the second package (200) may be misaligned along the vertical direction with the third side (100S3) of the first package (100) and the third side (400S3) of the package cover layer (400). The fourth side (200S4) of the second package (200) may be misaligned along the vertical direction with the fourth side (100S4) of the first package (100) and the fourth side (400S4) of the package cover layer (400) without being aligned along the vertical direction.

[0201] Accordingly, the first side (200S1), the third side (200S3), and the fourth side (200S4) of the second package (200) can be covered with a package cover layer (400), and the second side (200S2) of the second package (200) can be covered with a package cover layer (400).

[0202] Referring to FIG. 8, the first side (200S1) of the second package (200) may be misaligned along the vertical direction with the first side (100S1) of the first package (100) and the first side (400S1) of the package cover layer (400). The second side (200S2) of the second package (200) may be aligned along the vertical direction with the second side (100S2) of the first package (100) and the second side (400S2) of the package cover layer (400). The third side (200S3) of the second package (200) may be aligned along the vertical direction with the third side (100S3) of the first package (100) and the third side (400S3) of the package cover layer (400). The fourth side (200S4) of the second package (200) may be misaligned along the vertical direction with the fourth side (100S4) of the first package (100) and the fourth side (400S4) of the package cover layer (400) without being aligned along the vertical direction.

[0203] Accordingly, the first side (200S1) and the fourth side (200S4) of the second package (200) can be covered with a package cover layer (400), and the second side (200S2) and the third side (200S3) of the second package (200) can be covered with a package cover layer (400).

[0204] By doing so, the embodiment can prevent and / or mitigate the bending of the semiconductor package (1000A) in a specific direction. Accordingly, the embodiment can enable the semiconductor package (1000A) to operate more stably, thereby further improving product reliability.

[0205]

[0206] FIG. 9 is a cross-sectional view showing a semiconductor package according to a fourth embodiment, FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment, FIG. 11 is a cross-sectional view showing a semiconductor package according to a sixth embodiment, FIG. 12a is a cross-sectional view showing a semiconductor package according to a seventh embodiment, FIG. 12b is a cross-sectional view showing a semiconductor package according to an eighth embodiment, and FIG. 13 is a cross-sectional view showing a semiconductor package according to a ninth embodiment.

[0207] Referring to FIG. 9, in the semiconductor package (1000C) according to the fourth embodiment, the upper surface of the package cover layer (400) may have a step difference with respect to the upper surface of the second package (200). For example, the upper surface of the package cover layer (400) may be positioned lower than the upper surface of the second package (200).

[0208] Accordingly, the outer surface of the semiconductor package (1000C) may have a step. For example, the outer surface of the semiconductor package (1000C) may be composed of a first outer surface of the second package (200) and a second outer surface of the package cover layer (400). In addition, the first outer surface and the second outer surface may have a step without being aligned along the vertical direction.

[0209] Accordingly, the embodiment can further relieve stress occurring during the operation of the semiconductor package (1000C).

[0210]

[0211] Additionally, referring to FIG. 10, the semiconductor package (1000D) according to the fifth embodiment may have a step difference between the upper surface of the package cover layer (400) and the upper surface of the second package (200). For example, the upper surface of the package cover layer (400) may be positioned higher than the upper surface of the second package (200).

[0212] Specifically, the upper surface of the package cover layer (400) may be provided to further cover the upper surface of the second package (200). For example, the package cover layer (400) may be provided to cover the upper surface of the third molding member (250) of the second package (200).

[0213] Accordingly, the embodiment can more stably protect the second package (200) using the package cover layer (400). Through this, the embodiment can enable the first package (100) and the second package (200) to be electrically coupled more stably.

[0214]

[0215] Additionally, referring to FIG. 11, the semiconductor package (1000E) according to the sixth embodiment may include a package cover layer (400), and the package cover layer (400) may further mold and provide a fourth semiconductor chip (280) provided in the second package (200).

[0216] For example, in the previous embodiment, the second package (200) is provided to cover the third molding member (250) that molds the fourth semiconductor chip (280).

[0217] Alternatively, according to the sixth embodiment, the process of forming the third molding member (250) can be omitted during the manufacturing process of the second package (200). In addition, during the process of forming the package cover layer (400), the process of molding the side of the second package (200) and the fourth semiconductor chip (280) on the second package (200) can be carried out while filling the space between the first package (100) and the second package (200).

[0218] Through this, the embodiment can simplify the manufacturing process of the semiconductor package (1000C) and reduce the manufacturing cost accordingly.

[0219]

[0220] Additionally, referring to FIG. 12a and FIG. 12b, the semiconductor package according to the seventh and eighth embodiments may further include a first package (100), a second package (200), and a third package (600). In this case, the third package (600) may have a structure corresponding to at least one of the first package (100) and the second package (200). For example, the third package (600) may include a fifth redistribution structure, a fourth molding member disposed on the fifth redistribution structure, a fifth semiconductor chip embedded in the fourth molding member, a sixth redistribution structure disposed on the fourth molding member, a third vertical connecting conductor penetrating the fourth molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other, and a sixth semiconductor chip disposed on the sixth redistribution structure. Additionally, the third package (600) may further include a fifth molding member for molding the sixth semiconductor chip.

[0221] At this time, the previous embodiment provided a semiconductor package having a structure including a first package (100) and a second package (200), but according to the seventh embodiment, a process of further stacking a third package (600) on the first package (100) and the second package (200) can be performed. However, the embodiment is not limited thereto. For example, the semiconductor package may have a structure in which an additional upper package is further stacked on the first package (100), the second package (200), and the third package (600).

[0222] Accordingly, a first connecting bump (300) may be placed between the first package (100) and the second package (200). Additionally, a second connecting bump (700) may be placed between the second package (200) and the third package (600).

[0223] At this time, the package cover layer (400) may be provided to fill the space between the first package (100) and the second package (200), and the space between the second package (200) and the third package (600).

[0224] For example, the package cover layer (400) may include a first portion disposed between the first package (100) and the second package (200), and a second portion provided between the second package (200) and the third package (600).

[0225] Additionally, the package cover layer (400) may further include a third part that surrounds the side of the second package (200) while being positioned between the first and second parts described above. Additionally, the package cover layer (400) may further include a fourth part that extends upward from the second part described above and surrounds the side of the third package (600).

[0226] Through this, the embodiment can increase the number of packages stacked along the vertical direction and further improve the circuit integration density accordingly.

[0227] At this time, as shown in FIG. 12a, the outer width of the third package (600) may be smaller than the outer width of the first package (100) and the second package (200). Alternatively, as shown in FIG. 12b, the outer width of the third package (600) may be smaller than the outer width of the first package (100) and equal to the outer width of the second package (200).

[0228]

[0229] Additionally, referring to FIG. 13, the semiconductor package according to the ninth embodiment may further include a first package (100), a second package (200), and a third package (600).

[0230] For example, the previous embodiment provided a semiconductor package having a structure including a first package (100) and a second package (200), but according to the seventh embodiment, a process of further stacking a third package (600) on the first package (100) and the second package (200) can be performed. However, the embodiment is not limited thereto. For example, the semiconductor package may have a structure in which an additional upper package is further stacked on the first package (100), the second package (200), and the third package (600).

[0231] Accordingly, a first connecting bump (300) may be placed between the first package (100) and the second package (200). Additionally, a second connecting bump (700) may be placed between the second package (200) and the third package (600).

[0232] At this time, the embodiment may include a plurality of package cover layers (400, 800).

[0233] The first package cover layer (400) may refer to the package cover layer (400) described in the previous embodiment. The first package cover layer (400) may include a first portion that fills the space between the first package (100) and the second package (200), and a second portion that surrounds the side of the second package (200). In this case, the vertical level of the upper surface of the first package cover layer (400) may be different from the vertical level of the upper surface of the second package (200). In an exemplary embodiment, the vertical level of the upper surface of the first package cover layer (400) may be lower than the vertical level of the upper surface of the second package (200).

[0234] Specifically, the first package cover layer (400) may be provided to surround a portion of the side of the second package (200). It may differ from the vertical level of the upper surface. For example, the vertical level of the upper surface of the first package cover layer (400) may be provided between the third molding member and the fourth redistribution structure of the second package (200).

[0235] Additionally, the second package cover layer (800) may be provided to fill the space between the second package (200) and the third package (600). In this case, the outer width and / or planar area of ​​the third package (600) may be smaller than the outer width and / or planar area of ​​the second package (200). In this case, the vertical level of the lower surface of the second package cover layer (800) may be lower than the vertical level of the upper surface of the second package (200). That is, the second package cover layer (800) may be provided to surround a portion of the side of the second package (200) that is not covered by the first package cover layer (400).

[0236] Accordingly, the eighth embodiment may form the package cover layer of the semiconductor package according to FIG. 12 by dividing it into multiple parts. Through this, the embodiment may enable the first package (100), the second package (200), and the third package (600) to be protected more stably.

[0237] That is, the second package cover layer (800) may include a third part disposed to surround at least a portion of the side of the second package (200), a fourth part filling the space between the second package (200) and the third package (600), and a fifth part extending from the fourth part to surround the side of the third package (600).

[0238] Through this, the embodiment can increase the number of packages stacked along the vertical direction, thereby further improving the circuit integration density and further improving the reliability of electrical connections between multiple packages.

[0239]

[0240] FIG. 14 is a cross-sectional view showing a semiconductor package according to the 10th embodiment.

[0241] Referring to FIG. 14, the semiconductor package according to the 10th embodiment may further include a first package (100), a second package (200), and a third package (600).

[0242] For example, the third package (600) may include a fifth redistribution structure, a fourth molding member disposed on the fifth redistribution structure, a fifth semiconductor chip embedded in the fourth molding member, a sixth redistribution structure disposed on the fourth molding member, a third vertical connecting conductor penetrating the fourth molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other, and a sixth semiconductor chip disposed on the sixth redistribution structure.

[0243] At this time, according to the semiconductor packages of FIG. 12a and FIG. 12b, the third package (600) additionally comprises a fourth molding member for molding the sixth semiconductor chip.

[0244] Alternatively, according to the semiconductor package of FIG. 14, the third package (600) may not have a fourth molding member, and the package cover layer (400) may be provided by molding up to the sixth semiconductor chip of the third package (600).

[0245] Specifically, a first connecting bump (300) may be placed between the first package (100) and the second package (200). Additionally, a second connecting bump (700) may be placed between the second package (200) and the third package (600).

[0246] At this time, the package cover layer (400) may be provided to fill the space between the first package (100) and the second package (200), as well as the second package (200) and the third package (600). Furthermore, the package cover layer (400) may be provided to further mold the sixth semiconductor chip of the third package (600).

[0247] For example, the package cover layer (400) may include a first portion disposed between the first package (100) and the second package (200), and a second portion provided between the second package (200) and the third package (600).

[0248] Additionally, the package cover layer (400) may further include a third part that surrounds the side of the second package (200) while being disposed between the first and second parts described above. Additionally, the package cover layer (400) may further include a fourth part that extends upward from the second part described above and surrounds the side of the third package (600). Furthermore, the package cover layer (400) may further include a fifth part that molds the sixth semiconductor chip provided in the third package (600).

[0249] Through this, the embodiment can increase the number of packages stacked along the vertical direction and further improve the circuit integration density accordingly. Furthermore, by having the package cover layer (400) have the first to fifth parts described above, the manufacturing process can be simplified and further improve the product yield.

[0250]

[0251] FIGS. 15a to 15j are cross-sectional views showing the manufacturing method of a semiconductor package illustrated in FIG. 14 in process order. Below, a manufacturing method of the semiconductor package of FIG. 14 according to one embodiment will be described. The manufacturing method described below simplifies the manufacturing process of the semiconductor package illustrated in FIG. 14 as much as possible, while enabling semiconductor chips to be mounted more stably in each package.

[0252] Referring to FIG. 15a, the embodiment may proceed with a process of preparing a carrier member (CM) and manufacturing a part (100-1) of a first package (100) using the carrier member (CM). For example, a process may proceed to form a first redistribution structure, a first semiconductor chip, a first vertical connection conductor, and a second redistribution structure on the carrier member (CM).

[0253] Subsequently, referring to FIG. 15b, the embodiment may proceed with a process of manufacturing a portion (200-1) of the second package (200). For example, a process may proceed to form a third redistribution structure, a third semiconductor chip, a second vertical connection conductor, and a fourth redistribution structure constituting the second package (200) on a carrier member. Subsequently, the carrier member used to manufacture the portion (200-1) of the second package (200) may be removed.

[0254] Subsequently, referring to FIG. 15c, the embodiment may proceed with a process of manufacturing a portion (600-1) of the third package (600). For example, a process may be performed to form a fifth redistribution structure, a fifth semiconductor chip, a third vertical connection conductor, and a sixth redistribution structure constituting the third package (600) on a carrier member. Subsequently, the carrier member used to manufacture the portion (600-1) of the third package (600) may be removed.

[0255] Next, the embodiment may proceed with a process of mounting an additional semiconductor chip while sequentially combining the packages manufactured in FIG. 15a to FIG. 15c.

[0256] Referring to FIG. 15d, the embodiment may proceed with a process of mounting a second semiconductor chip on a portion (100-1) of the first package (100) on the carrier member (CM) manufactured in FIG. 15a. Through this, the first package (200) can be manufactured.

[0257] Next, referring to FIG. 15e, a process of joining a part (200-1) of the second package (200) onto the first package (100) can be carried out using a first connecting bump (300) placed on the lower part (200-1) of the second package (200) manufactured through FIG. 15b.

[0258] Next, referring to FIG. 15f, the embodiment may proceed with a process of mounting a fourth semiconductor chip on a portion (200-1) of a second package (200) coupled to a first package (100). Through this, a second package (200) coupled to a first package (100) can be manufactured.

[0259] Next, referring to FIG. 15g, a process of joining a part (600-1) of the third package (600) onto a second package (200) can be carried out using a second connecting bump (700) placed on the lower part (600-1) of the third package (600) manufactured through FIG. 15c.

[0260] Next, referring to FIG. 15h, the embodiment may proceed with a process of mounting a sixth semiconductor chip on a portion (600-1) of a third package (600) coupled to a second package (200). Through this, a third package (600) coupled to a second package (200) can be manufactured.

[0261] Next, referring to FIG. 15i, the embodiment may proceed with a process of forming a package cover layer (400) that fills the space between the first package (100) and the second package (200), and the space between the second package (200) and the third package (600). Furthermore, the embodiment may allow the package cover layer (400) to mold the sixth semiconductor chip of the third package (600). Accordingly, the package cover layer (400) may include a first part disposed between the first package (100) and the second package (200), a second part provided between the second package (200) and the third package (600), a third part disposed between the first part and the second part and surrounding the side of the second package (200), a fourth part extending upward from the aforementioned second part and surrounding the side of the third package (600), and a fifth part molding a sixth semiconductor chip provided in the third package (600).

[0262] Next, referring to FIG. 15j, after removing the carrier member (CM), a process of forming an external terminal bump (500) on the lower part of the first redistribution structure of the first package (100) can be carried out.

[0263] Through this, the embodiment can easily combine multiple packages stacked sequentially in a vertical direction.

[0264] Although the present invention has been described with reference to an exemplary embodiment illustrated in the accompanying drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true scope of the present invention should be determined only by the appended claims.

Claims

1. A first package comprising a first redistribution structure, a first molding member disposed on the first redistribution structure, a second redistribution structure disposed on the first molding member, and a first vertical connecting conductor that penetrates the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other; A second package comprising a third redistribution structure, a second molding member disposed on the third redistribution structure, a fourth redistribution structure disposed on the second molding member, and a second vertical connecting conductor that penetrates the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other; A connecting bump disposed between the first package and the second package and electrically connecting the second redistribution structure and the third redistribution structure; and, A semiconductor package comprising a package cover layer including a first portion disposed between the first package and the second package and surrounding the connection bump, and a second portion extending from the first portion and surrounding the side of the second package.

2. In Paragraph 1, The first package further comprises a first semiconductor chip embedded within the first molding member and a second semiconductor chip disposed on the second redistribution structure. The second package further comprises a third semiconductor chip embedded within the second molding member and a fourth semiconductor chip disposed on the fourth redistribution structure. The second semiconductor chip is embedded in the first portion of the package cover layer, forming a semiconductor package.

3. In Paragraph 2, The second package further includes a second molding member disposed on the fourth redistribution structure and molding the fourth semiconductor chip, and A semiconductor package, wherein the above package cover layer covers the side of the second molding member of the second package.

4. In Paragraph 2, A semiconductor package, wherein the above package cover layer further comprises a third part extending from the second part and molding the fourth semiconductor chip.

5. In any one of paragraphs 1 through 4, The second portion of the package cover layer has a first horizontal width and a second horizontal width that are different from each other along the perimeter direction of the side of the second package, in a semiconductor package.

6. In any one of paragraphs 1 through 4, Each of the above package cover layer and the above second package includes a plurality of sides, and At least one of the plurality of sides of the second package is aligned along a vertical direction with at least one of the plurality of sides of the package cover layer, and A semiconductor package in which the above package cover layer does not contact at least one side of the aligned second package.

7. In Paragraph 3, The upper surface of the package cover layer is positioned lower than the upper surface of the second package, and A semiconductor package in which at least a portion of the side of the second molding member does not contact the package cover layer.

8. In Paragraph 3, The upper surface of the package cover layer is positioned lower than the upper surface of the second package, and A semiconductor package, wherein the second portion of the package cover layer covers the upper surface of the second molding member.

9. In any one of paragraphs 1 through 4, The first redistribution structure and the second redistribution structure have a symmetrical structure centered on the first molding member, The above third redistribution structure and the above fourth redistribution structure have a symmetrical structure centered on the above second molding member, and A semiconductor package in which the first and second redistribution structures of the first package have a symmetrical structure with respect to the third and fourth redistribution structures of the second package, centered on the first portion of the package cover layer.

10. In any one of paragraphs 1 through 3, It further includes a third package disposed on the second package above, and The above third package is a semiconductor package comprising a fifth redistribution structure, a fourth molding member disposed on the fifth redistribution structure, a sixth redistribution structure disposed on the fourth molding member, and a third vertical connecting conductor that penetrates the fourth molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other.

11. In Paragraph 10, The outer width of the third package is smaller than the outer width of the first package and the outer width of the second package, and A semiconductor package, wherein the above package cover layer further comprises a fourth part extending from the third part toward the third package and arranged to surround the side of the third package.

12. In Paragraph 11, A semiconductor package comprising a package cover layer including a first package cover layer including the first part and the second part, and a second package cover layer disposed on the first package cover layer and including the third part and the fourth part.

13. A step of manufacturing a first package comprising, on a first carrier member, a first redistribution structure, a first molding member disposed on the first redistribution structure, a first semiconductor chip embedded in the first molding member, a second redistribution structure disposed on the first molding member, and a first vertical connecting conductor penetrating the first molding member along a vertical direction to electrically connect the first redistribution structure and the second redistribution structure to each other; A step of manufacturing a second package comprising: a third redistribution structure on a second carrier member; a second molding member disposed on the third redistribution structure; a third semiconductor chip embedded within the second molding member; a fourth redistribution structure disposed on the second molding member; and a second vertical connecting conductor penetrating the second molding member along a vertical direction to electrically connect the third redistribution structure and the fourth redistribution structure to each other. A step of removing the second carrier member and placing a first connection bump on the lower part of the third redistribution structure of the second package; A step of coupling the second package onto the second redistribution structure of the first package using the first connection bump; and A method for manufacturing a semiconductor package, comprising the step of forming a package cover layer including a first portion filling the space between the first package and the second package, and a second portion extending from the first portion and surrounding the side of the second package.

14. In Paragraph 13, Before combining the second package, the method further includes the step of mounting a second semiconductor chip on the second rewiring structure of the first package. The second package is coupled to the first package through the first connection bump after the second semiconductor chip is mounted, and The method further includes the step of mounting a fourth semiconductor chip on the fourth redistribution structure of the second package after the first package and the second package are combined and before forming the package cover layer. The first portion of the package cover layer is provided to mold the second semiconductor chip, and A method for manufacturing a semiconductor package, wherein the above package cover layer further comprises a third part for molding the fourth semiconductor chip.

15. In Paragraph 14, After the step of placing the first connection bump, a third package comprising, on a third carrier member, a fifth redistribution structure, a third molding member disposed on the fifth redistribution structure, a fifth semiconductor chip embedded in the third molding member, a sixth redistribution structure disposed on the third molding member, and a third vertical connection conductor penetrating the third molding member along a vertical direction to electrically connect the fifth redistribution structure and the sixth redistribution structure to each other; and The method further includes the step of removing the third carrier member and placing a second connection bump on the lower part of the fifth redistribution structure of the third package. After the fourth semiconductor chip is mounted and before forming the package cover layer, a step of coupling the third package onto the fourth rewiring structure of the second package using the second connection bump; and The method further includes the step of mounting a sixth semiconductor chip on the sixth redistribution structure of the third package after the second package and the third package are combined and before forming the package cover layer. A method for manufacturing a semiconductor package, wherein the above package cover layer is formed by further including a fourth part extending from the third part and surrounding the side of the third package, and a fifth part disposed on the fourth part and molding the sixth semiconductor chip.

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