Display apparatus

Abstract

Provided in the present application is a display apparatus. The apparatus comprises: a substrate; a first metal layer, which is disposed on the substrate and comprises a plurality of common lines arranged in a second direction; a gate insulating layer; a semiconductor layer; and a second metal layer, which comprises a plurality of shared lines arranged in a first direction. The common lines are electrically connected on two sides in a first direction by means of two first connection lines, and the shared lines are electrically connected in a second direction by means of one second connection line; alternatively, the common lines are electrically connected to connection lines of the second metal layer, and the shared lines are electrically connected to connection lines of the first metal layer. The present application can reduce the risk of electrostatic breakdown and improve the yield.

Description

Display device Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] Currently, to improve the viewing angle characteristics of LCD display panels, three thin-film transistors (TFT1, TFT2, and TFT3) are typically placed in each pixel unit, and shared lines (SCOM1 and SCOM2) are introduced to divide the voltage of the sub-pixels, as shown in Figure 1. However, as the resolution of LCD display panels continues to increase, the size of pixel units is becoming smaller and smaller, resulting in a smaller and smaller spacing between the shared lines (SCOM1 and SCOM2) and the data lines (DL1 and DL2).

[0003] In the manufacturing process of LCD display panels, when using the A-Si 4mask process to fabricate thin-film transistor array substrates, the semiconductor layer typically requires two dry etching processes. The first dry etching etches the non-channel regions of the semiconductor layer. During this first dry etching process, a large amount of static electricity accumulates in the thin-film transistor array substrate due to the high-power ionization of gas into plasma.

[0004] However, during the first dry etching process, the accumulated static electricity will be released between the data lines (DL1, DL2) and the shared lines (SCOM1, SCOM2) in the thin film transistor array substrate, as shown in Figure 2, causing electrostatic breakdown, which leads to the breakage of the shared lines (SCOM1, SCOM2) or the data lines (DL1, DL2), thereby reducing the product yield. Invention Overview

[0005] The purpose of this application is to provide a display device that reduces the risk of electrostatic breakdown during the first dry etching process and improves product yield.

[0006] This application provides a display device, which includes a display panel, comprising a display area and a non-display area. The display panel further includes: a substrate; a first metal layer disposed on the substrate, the first metal layer including a plurality of common lines and two first connecting lines, the length direction of the common lines being parallel to a first direction, the plurality of common lines being arranged along a second direction, the first direction being perpendicular to the second direction, the two first connecting lines being respectively disposed on opposite sides of the non-display area of ​​the display panel in the first direction, the length direction of the first connecting lines being parallel to the second direction, and the two ends of the plurality of common lines being electrically connected to the two first connecting lines respectively; a gate insulating layer disposed on the first metal layer and the substrate; a semiconductor layer disposed on the gate insulating layer; and a second metal layer disposed on the gate insulating layer, the second metal layer including a plurality of shared lines and a second connecting line, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the second connecting line being disposed on the non-display area of ​​the display panel in the second direction, and one end of the plurality of shared lines being electrically connected to the second connecting line.

[0007] Embodiments of this application also provide a display device, the display device including a display panel, the display panel including a display area and a non-display area, the display panel further including: a substrate; a first metal layer disposed on the substrate, the first metal layer including a plurality of common lines and two fourth connecting lines, the length direction of the common lines being parallel to a first direction, the plurality of common lines being arranged along a second direction, the first direction being perpendicular to the second direction, the two fourth connecting lines being respectively disposed on the non-display areas on opposite sides of the display panel in the second direction, the length direction of the fourth connecting lines being parallel to the first direction; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; and a second metal layer disposed on the gate insulating layer, the second metal layer including a plurality of shared lines and two fifth connecting lines, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the plurality of shared lines being electrically connected to the fourth connecting line through a second via penetrating the gate insulating layer, the two fifth connecting lines being respectively disposed on the non-display areas on opposite sides of the display panel in the first direction, the length direction of the fifth connecting lines being parallel to the second direction; wherein, the plurality of shared lines are electrically connected to the fifth connecting lines through a third via penetrating the gate insulating layer. Beneficial effects

[0008] The display device provided in this application effectively reduces the risk of electrostatic breakdown during the first dry etching process through two different wiring design schemes. Specifically, in the first wiring design, the common line of the first metal layer is electrically connected on both sides in the first direction through two first connecting lines, and the shared line of the second metal layer is electrically connected on one side in the second direction through a second connecting line. The common line and the shared line are respectively formed into a mesh structure. During the first dry etching process, even if a large amount of static electricity accumulates in the network of the common line of the first metal layer, since the shared line of the second metal layer also forms a mesh structure, and after the first dry etching and before the second wet etching, all data lines of the display device and the shared line mesh form a unified electrical network, so that no potential difference is generated between the data lines and the shared line in different columns, thereby avoiding electrostatic breakdown. In the second wiring design, the common line of the first metal layer is electrically connected to the fifth connecting line of the second metal layer through a third via, and the shared line of the second metal layer is electrically connected to the fourth connecting line of the first metal layer through a second via. During the first dry etching process, the common line and shared line remain as a single line. Because the electrostatic charge on the single common line coupled to the single shared line via capacitance is small, the potential difference between the shared line and the adjacent data line is small, thus avoiding electrostatic breakdown. Through the above technical solution, the display device of this application effectively solves the problem of shared line or data line breakage due to electrostatic breakdown in the prior art, significantly improving product yield. The technical solution of this application is applicable to high-resolution display devices with small spacing between shared lines and data lines. Attached Figure Description

[0009] Figure 1 is a schematic diagram of the pixel unit of a traditional LCD display panel.

[0010] Figure 2 is a schematic diagram of electrostatic breakdown in the pixel unit of the LCD display panel shown in Figure 1.

[0011] Figure 3 is a block diagram of a display device provided in an embodiment of this application.

[0012] Figure 4 is a schematic diagram of a display device provided in the first embodiment of this application.

[0013] Figure 5 is a schematic diagram of a display device provided in the second embodiment of this application.

[0014] Figure 6 is a cross-sectional view of the thin-film transistor array substrate of the display device provided in the embodiment of this application when the first dry etching is completed. Embodiments of the present invention

[0015] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0016] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0017] The embodiments of this application can be combined with each other.

[0018] In manufacturing the thin-film transistor array (TFT-LCD) substrate for liquid crystal displays, a four-mask amorphous silicon process is typically used. This process requires two dry etching operations on the TFT-LCD substrate. The first dry etching etches the semiconductor layer (A-Si) in the non-channel region of the TFT-LCD substrate. During the first dry etching process, a large amount of static electricity accumulates in the TFT-LCD substrate due to the high-power ionization of gas to form plasma.

[0019] As shown in Figure 1, to improve the viewing angle characteristics of a liquid crystal display panel, three thin-film transistors (TFT1, TFT2, and TFT3) are set in each pixel unit, and a shared line SCOM is introduced to divide the voltage of the sub-pixels. However, as the resolution of liquid crystal display panels continues to increase, the size of the pixel units becomes smaller and smaller, and the spacing between the shared line SCOM and the data lines also becomes smaller and smaller.

[0020] However, during the first dry etching process, if the wiring design of the common line ACOM and the shared line SCOM is improper, the accumulated static electricity can easily be released between the data line and the shared line SCOM, causing electrostatic discharge, as shown in Figure 2. This can lead to breakage of the shared line SCOM or the data line, thereby reducing product yield. Specifically, when the first dry etching is completed, since the channel regions of the thin-film transistors (TFT1, TFT2, and TFT3) are still covered by photoresist PR, each data line and the source, drain, and shared line SCOM of the thin-film transistor of its corresponding pixel (all belonging to the second metal layer M2) are connected together to form a column cell, as shown in Figure 2. At this time, the common line ACOM of the first metal layer M1 will accumulate a large amount of static electricity, which will be coupled to the column cell of the second metal layer M2 through capacitive coupling. Since the via layer has not yet been fabricated, the shared line SCOM has not formed a mesh structure, resulting in the voltage of the data line of the first column of pixels being equal to the voltage of the shared line SCOM of the first column of pixels, but not equal to the voltage of the data line of the second column of pixels (which is equal to the voltage of the shared line SCOM of the second column of pixels). Because there may be a large potential difference between the shared line SCOM of the first column of pixels and the data line of the second column of pixels, electrostatic breakdown is likely to occur when the spacing between them is small.

[0021] To address the aforementioned technical problems, this application proposes two solutions.

[0022] As shown in Figures 4 and 6, the first solution is as follows: the common line ACOM of the first metal layer M1 forms a mesh structure through two first connecting lines CL1, and the shared line SCOM of the second metal layer M2 forms a mesh structure through a second connecting line CL2. Specifically, the first metal layer M1 includes multiple common lines ACOM and two first connecting lines CL1. The common lines ACOM are located in the display area of ​​the display panel, and their length direction is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The first connecting lines CL1 are located in the non-display areas on opposite sides of the display panel in the first direction, and their length direction is parallel to the second direction. The two ends of the multiple common lines ACOM are electrically connected to the two first connecting lines CL1 respectively. The second metal layer M2 includes multiple shared lines SCOM and one second connecting line CL2. The length direction of the shared lines SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The shared lines SCOM are located in the display area of ​​the display panel, and one end of the shared lines SCOM is electrically connected to the second connecting line CL2. The second connecting line CL2 is located in the non-display area of ​​the display panel in the second direction. The first metal layer M1 also includes a third connection line CL3. The third connection line CL3 is located in the non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through the first through hole VH1 that penetrates the gate insulating layer GI.

[0023] The beneficial effect of the first solution is that although the first dry etching process will cause a large amount of static electricity to accumulate on the grid-like common line ACOM of the first metal layer M1, since the shared line SCOM of the second metal layer M2 also forms a grid structure, after the first dry etching and before the second wet etching, since the channel regions of the thin film transistors (TFT1, TFT2 and TFT3) are still covered by photoresist PR, and the source and drain of the thin film transistors (TFT1, TFT2 and TFT3) are directly connected, all data lines form a unified electrical network through the grid-like shared line SCOM, and no potential difference will be generated between the data lines in different columns and the shared line SCOM, thereby avoiding electrostatic breakdown.

[0024] As shown in Figure 5, the second solution is as follows: the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both set as single-line structures, and then a grid structure is formed by connecting lines located in different layers. Specifically, the first metal layer M1 includes multiple common lines ACOM and two fourth connecting lines CL4. The common lines ACOM are located in the display area of ​​the display panel, and the length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The two fourth connecting lines CL4 are respectively located in the non-display areas on opposite sides of the display panel in the second direction, and the length direction of the fourth connecting lines CL4 is parallel to the first direction. The second metal layer M2 includes multiple shared lines SCOM and two fifth connecting lines CL5. The shared lines SCOM are located in the display area of ​​the display panel, and the length direction of the shared lines SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The two fifth connecting lines CL5 are respectively located in the non-display areas on opposite sides of the display panel in the first direction, and the length direction of the fifth connecting lines CL5 is parallel to the second direction. Multiple common lines ACOM are electrically connected to the fifth connection line CL5 through the third via VH3 that penetrates the gate insulating layer GI, and multiple shared lines SCOM are electrically connected to the fourth connection line CL4 through the second via VH2 that penetrates the gate insulating layer GI.

[0025] The beneficial effect of the second solution is that, during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the amount of static electricity of a single common line ACOM coupled to a single shared line SCOM through capacitance is small. Therefore, the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is not easy to occur.

[0026] Through the two solutions described above, this application can effectively reduce the risk of electrostatic breakdown in the manufacturing process of display panels and improve product yield.

[0027] As shown in Figure 3, the display device provided in the embodiments of this application includes a display panel, a timing controller TCON, a source drive circuit DD, and a power management chip (not shown in the figure; the power management chip can be integrated with the timing controller TCON into the same chip). The display panel may be, for example, a liquid crystal display panel.

[0028] The display panel includes a display area and a non-display area. The display area has an array of m×n pixel units P, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (GL1~GLn), multiple data lines (DL1~DLm), and a gate drive circuit GOA. The multiple scan lines (GL1~GLn) extend along a first direction and are arranged along a second direction, and the multiple data lines (DL1~DLm) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate drive circuit GOA is located in the non-display area and is electrically connected to the multiple scan lines (GL1~GLn). The source drive circuit DD is electrically connected to the multiple data lines (DL1~DLm) via a flexible circuit board. The timing controller TCON is electrically connected to both the gate drive circuit GOA and the source drive circuit DD.

[0029] The display panel includes a thin-film transistor array substrate, a counter substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate includes a glass substrate, a first metal layer M1 disposed on the glass substrate, a gate insulating layer GI disposed on the first metal layer M1, a semiconductor layer A-Si disposed on the gate insulating layer GI, a second metal layer M2 disposed on the semiconductor layer A-Si, a passivation layer disposed on the second metal layer M2, and pixel electrodes disposed on the passivation layer. The first metal layer M1 includes scan lines (GL1~GLn), gate electrodes, etc. The second metal layer M2 includes data lines (DL1~DLm), source electrodes, drain electrodes, etc. The counter substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0030] Each pixel unit P includes at least one thin-film transistor (TFT) and a pixel electrode. The gate of the TFT is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the TFT is turned on, and the data signal on the data line is transmitted to the pixel electrode through the TFT; when the scan line outputs a low-level scan signal, the TFT is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0031] The gate drive circuit GOA includes n cascaded gate drive units, each electrically connected to a scan line. Under the control of the timing controller TCON, the gate drive units sequentially output scan signals, scanning each row of pixel units in the display area line by line. The source drive circuit DD, under the control of the timing controller TCON, generates and outputs data signals based on the image data. The timing controller TCON receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source drive circuit DD. The power management chip provides operating voltages to various parts of the liquid crystal display device, including a common voltage for the common electrode, a gate drive voltage for the gate drive circuit GOA, and a gamma voltage for the source drive circuit DD.

[0032] As shown in FIG4, the first embodiment of this application provides a display device, the display device including a display panel, the display panel including a display area and a non-display area, the display panel further including a thin film transistor array substrate, a counter substrate and a liquid crystal layer disposed between the thin film transistor array substrate and the counter substrate.

[0033] The thin-film transistor array substrate includes a substrate SBT, a first metal layer M1 disposed on the substrate SBT, a gate insulating layer GI disposed on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si disposed on the gate insulating layer GI, and a second metal layer M2 disposed on the gate insulating layer GI.

[0034] The first metal layer M1 includes multiple common lines ACOM and two first connecting lines CL1. The length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction, which is perpendicular to the first direction. The two first connecting lines CL1 are respectively disposed on the non-display areas on opposite sides of the display panel in the first direction. The length direction of the first connecting lines CL1 is parallel to the second direction. The two ends of the multiple common lines ACOM are electrically connected to the two first connecting lines CL1 respectively.

[0035] The second metal layer M2 includes multiple shared lines SCOM and a second connecting line CL2. The length direction of the shared lines SCOM is parallel to the second direction, and the multiple shared lines SCOM are arranged along the first direction. The second connecting line CL2 is disposed in the non-display area of ​​the display panel in the second direction. The length direction of the second connecting line CL2 is parallel to the first direction, and one end of the multiple shared lines SCOM is electrically connected to the second connecting line CL2.

[0036] The first metal layer M1 also includes multiple gate lines, the length direction of which is parallel to the first direction.

[0037] The second metal layer M2 also includes multiple data lines, the length direction of which is parallel to the second direction, and a preset spacing between the data lines and the adjacent shared line SCOM. This preset spacing is less than 10 micrometers.

[0038] In this embodiment, the substrate SBT is a glass substrate or a quartz substrate. The first metal layer M1 is a single-layer metal or a multi-layer metal. The gate insulating layer GI can be made of insulating materials such as silicon nitride, silicon oxide, or aluminum oxide. The semiconductor layer A-Si can be made of amorphous silicon. The second metal layer M2 is made of the same material as the first metal layer M1.

[0039] A black matrix and a color filter layer are disposed on the opposing substrate. The black matrix, made of chromium or resin, is used to block light from non-display areas. The color filter layer includes red, green, and blue filter units to achieve color display. A common electrode, made of a transparent conductive material, is disposed on the opposing substrate.

[0040] The display panel also includes multiple pixel units. Each pixel unit includes a main pixel electrode, a secondary pixel electrode, a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), and a third thin-film transistor (TFT3). The gates of TFT1, TFT2, and TFT3 are electrically connected to gate lines. The sources of TFT1 and TFT2 are electrically connected to data lines. The drains of TFT1 and TFT2 are electrically connected to the main pixel electrode and the secondary pixel electrode, respectively. The drain of TFT2 is also electrically connected to the source of TFT3, and the drain of TFT3 is electrically connected to the shared line SCOM. The main pixel electrode and the secondary pixel electrode are made of a transparent conductive material, such as indium tin oxide (ITO). The main pixel electrode and the secondary pixel electrode are electrically connected to the drains of the corresponding thin-film transistors through vias located in the passivation layer. The passivation layer is made of organic or inorganic materials.

[0041] The semiconductor layer A-Si includes a non-channel portion and a channel portion, with the channel portion connecting the source and drain of the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the third thin-film transistor TFT3.

[0042] The gate line is set parallel to the common line ACOM, and the data line is set parallel to the shared line SCOM.

[0043] Within the display area, gate lines and common lines (ACOM) are alternately arranged in the first direction, meaning that one common line (ACOM) is placed between every two adjacent gate lines. Data lines and shared lines (SCOM) are alternately arranged in the first direction, meaning that one shared line (SCOM) is placed between every two adjacent data lines.

[0044] The first connecting line CL1 can have multiple connecting parts in the connection area with the common line ACOM. The width of each connecting part can be 1.5 to 2 times the width of the common line ACOM, for example, 1.5, 1.6, 1.7, 1.8, 1.9, or 2 times. The second connecting line CL2 can also have multiple connecting parts in the connection area with the shared line SCOM. The width of each connecting part can be 1.5 to 2 times the width of the shared line SCOM, for example, 1.5, 1.6, 1.7, 1.8, 1.9, or 2 times.

[0045] In this embodiment, the edges of the first connecting line CL1 and the second connecting line CL2 can be set in a serrated shape. The serrated edges help to release stress and prevent the first connecting line CL1 and the second connecting line CL2 from cracking.

[0046] The first metal layer M1 also includes a third connection line CL3. The third connection line CL3 is disposed in the non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through the first through hole VH1 that penetrates the gate insulating layer GI.

[0047] Multiple first through holes VH1 are spaced apart along the first direction.

[0048] The width of the third connecting line CL3 is greater than the width of the shared line SCOM. For example, the width of the third connecting line CL3 can be 1.2 to 2 times the width of the shared line SCOM, such as 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, 1.8 times, 1.9 times, or 2 times.

[0049] The width of the first connecting wire CL1 is greater than the width of the common wire ACOM; the width of the second connecting wire CL2 is greater than the width of the shared wire SCOM. Specifically, the width of the first connecting wire CL1 can be 1.2 to 2 times the width of the common wire ACOM, for example, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, or 2 times; the width of the second connecting wire CL2 can be 1.2 to 2 times the width of the shared wire SCOM. Increasing the width of the connecting wires improves their conductivity, which is beneficial for the conduction and dispersion of static electricity.

[0050] The first metal layer M1 also includes a lead LW, which is located in the non-display area; the first connecting line CL1 is electrically connected to the lead LW. The lead LW is used to provide the common voltage of the power management chip to the common line ACOM.

[0051] In this embodiment, the lead-out line LW may include multiple parallel sub-lead-out lines LW connected in parallel. The width of each sub-lead-out line LW can be 1.5 to 3 times the width of the common line ACOM, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, or 3 times. By setting multiple parallel sub-lead-out lines LW, the resistance of the lead-out line LW can be reduced, and the stability of the power supply can be improved.

[0052] The lead wire LW gradually widens from the end connected to the first connecting wire CL1 to the end away from the first connecting wire CL1. For example, the width of the lead wire LW at the connection point with the first connecting wire CL1 can be 1 to 1.5 times the width of the first connecting wire CL1, such as 1, 1.1, 1.2, 1.3, 1.4, or 1.5 times. The width of the lead wire LW at the outer end can be 2 to 3 times the width of the first connecting wire CL1. This gradual width design helps to reduce stress concentration.

[0053] In this embodiment, the third connecting line CL3 comprises multiple zigzag segments, with obtuse angles between adjacent segments. This reduces stress concentration at corners. The zigzag structure of the third connecting line CL3 provides a longer trace distance within a limited non-display area. During the use of the display panel, the substrate SBT undergoes thermal expansion or contraction due to changes in ambient temperature, causing the third connecting line CL3 to experience tensile or compressive stress. The zigzag structure of the third connecting line CL3 can buffer these stresses through deformation between the zigzag segments, preventing stress concentration that could lead to breakage of the third connecting line CL3.

[0054] The first through-holes VH1 are arranged in a staggered manner, with multiple first through-holes VH1 staggered in the first direction, meaning the connection between the multiple first through-holes VH1 is a broken line, or they are arranged in a group, meaning multiple small through-holes are set at each intersection of the third connecting line CL3 and the shared line SCOM, and these small through-holes are arranged together to form a through-hole. Since a large current needs to be transmitted at the intersection of the third connecting line CL3 and the shared line SCOM, the large through-hole structure composed of multiple small through-holes can increase the conductive cross-sectional area and reduce the contact resistance.

[0055] Each via has an octagonal profile to reduce stress concentration at the via edges. The sidewalls of the vias are beveled, which helps to improve the coverage of the metal layer within the via.

[0056] The third connecting line CL3 has a structural reinforcement at the position corresponding to the through hole. The width of this structural reinforcement is greater than the width of the rest of the third connecting line CL3. The structural reinforcement is arranged in a ring around the through hole, and the outer edge of the structural reinforcement is rounded. This design can enhance the mechanical strength at the through hole, improve the reliability of the electrical connection, and avoid stress concentration.

[0057] Through the above technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, since the common line ACOM of the first metal layer M1 forms a mesh structure through two first connecting lines CL1, and the shared line SCOM of the second metal layer M2 forms a mesh structure through the second connecting line CL2, after the first dry etching and before the second wet etching, all data lines form a unified electrical network through the mesh-like shared line SCOM, and no potential difference is generated between the data lines in different columns and the shared line SCOM, thereby avoiding electrostatic breakdown.

[0058] As shown in Figure 5, the second embodiment of this application provides a display device. The second embodiment is similar to the first embodiment, except that:

[0059] The display device includes a display panel, which includes a display area and a non-display area. The display panel also includes a substrate SBT, a first metal layer M1 disposed on the substrate SBT, a gate insulating layer GI disposed on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si disposed on the gate insulating layer GI, and a second metal layer M2 disposed on the gate insulating layer GI.

[0060] The first metal layer M1 includes multiple common lines ACOM and two fourth connecting lines CL4. The length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction, and the first direction is perpendicular to the second direction. The two fourth connecting lines CL4 are respectively disposed on the non-display areas on opposite sides of the display panel in the second direction. The length direction of the fourth connecting lines CL4 is parallel to the first direction.

[0061] The second metal layer M2 includes multiple shared lines SCOM and two fifth connecting lines CL5. The length direction of the shared lines SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The multiple shared lines SCOM are electrically connected to the fourth connecting line CL4 through the second through-hole VH2 that penetrates the gate insulating layer GI. The two fifth connecting lines CL5 are respectively disposed on the non-display areas on opposite sides of the display panel in the first direction. The length direction of the fifth connecting lines CL5 is parallel to the second direction.

[0062] Among them, multiple common lines ACOM are electrically connected to the fifth connection line CL5 through the third via VH3 that penetrates the gate insulating layer GI.

[0063] The width of the fourth connector CL4 is greater than the width of the shared connector SCOM; the width of the fifth connector CL5 is greater than the width of the common connector ACOM.

[0064] Multiple second through holes VH2 are spaced apart along the first direction; multiple third through holes VH3 are spaced apart along the second direction.

[0065] The first metal layer M1 also includes a lead line LW, which is located in the non-display area.

[0066] The fifth connection line CL5 is electrically connected to the lead line LW through the fourth via that penetrates the gate insulating layer GI.

[0067] In this embodiment, the fourth connecting line CL4 and the fifth connecting line CL5 include multiple zigzag segments, with obtuse angles between adjacent segments. This reduces stress concentration at corners. The zigzag structure of the fourth connecting line CL4 and the fifth connecting line CL5 provides longer trace distances within limited non-display area space. During the use of the display panel, the substrate SBT undergoes thermal expansion or contraction due to changes in ambient temperature, causing the fourth connecting line CL4 and the fifth connecting line CL5 to experience tensile or compressive stress. The zigzag structure of the fourth connecting line CL4 and the fifth connecting line CL5 can buffer these stresses through deformation between the zigzag segments, preventing stress concentration that could lead to breakage of the fourth connecting line CL4 and the fifth connecting line CL5.

[0068] In this embodiment, the edges of the fourth connecting line CL4 and the fifth connecting line CL5 can be set in a serrated shape. The serrated edges help to release stress and prevent the fourth connecting line CL4 and the fifth connecting line CL5 from cracking.

[0069] The second through-hole VH2 and the third through-hole VH3 are arranged in an alternating manner. Multiple second through-holes VH2 are staggered in the first direction, meaning the line connecting them forms a broken line. Similarly, multiple third through-holes VH3 are staggered in the second direction, also forming a broken line. Alternatively, they can be arranged in groups, where multiple small through-holes are placed at each intersection of the fourth connecting line CL4, the fifth connecting line CL5, and the shared line SCOM. These small through-holes are grouped together to form a through-hole. Since a large current needs to be transmitted at the intersection of the fourth connecting line CL4, the fifth connecting line CL5, and the shared line SCOM, using a large through-hole structure composed of multiple small through-holes can increase the conductive cross-sectional area and reduce contact resistance.

[0070] Each via has an octagonal profile to reduce stress concentration at the via edges. The sidewalls of the vias are beveled, which helps to improve the coverage of the metal layer within the via.

[0071] The fourth connecting line CL4 and the fifth connecting line CL5 have structural reinforcement sections at positions corresponding to the through holes. The width of these reinforcement sections is greater than the width of the other parts of the fourth connecting line CL4 and the fifth connecting line CL5. The structural reinforcement sections are arranged in a ring around the through holes, and the outer edges of the reinforcement sections are rounded. This design can enhance the mechanical strength at the through holes, improve the reliability of the electrical connections, and avoid stress concentration.

[0072] The display panel provided in this application is manufactured through the following steps.

[0073] Forming a thin-film transistor array substrate and an opposing substrate.

[0074] A liquid crystal layer is disposed on a thin-film transistor array substrate.

[0075] An opposing substrate is disposed on a thin-film transistor array substrate.

[0076] The steps for forming the thin-film transistor array substrate include:

[0077] A first metal thin film is deposited on the substrate SBT.

[0078] The first metal thin film is etched to form multiple gate lines and common lines ACOM (first metal layer M1). In the first embodiment of this application, two first connection lines CL1 are also formed in the first metal layer M1. In the second embodiment of this application, two fourth connection lines CL4 are also formed in the first metal layer M1.

[0079] The step of etching the first metal thin film to form multiple gate lines and a common line ACOM includes: coating the first metal thin film with photoresist; exposing and developing the photoresist to form a mask including the common line ACOM, the first interconnect line CL1, and the gate line pattern; etching the first metal thin film using a wet etching method; and removing the photoresist to obtain a first metal layer M1. The material of the first metal layer M1 can be chromium, molybdenum, aluminum, or alloys thereof.

[0080] A gate insulating layer GI is formed on the first metal layer M1 and the substrate SBT.

[0081] A semiconductor layer A-Si is formed on the gate insulating layer GI.

[0082] A second metal thin film is deposited on the semiconductor layer A-Si and the gate insulating layer GI.

[0083] The second metal film is subjected to a first wet etching to form multiple electrically connected data lines and shared lines SCOM. This step includes: coating the second metal film with photoresist PR; exposing and developing the photoresist PR to form a mask including the shared lines SCOM, second connection lines CL2, and a data line pattern; and etching the second metal film using a wet etching method. After the first wet etching, the second metal film exposes the non-channel region of the semiconductor layer A-Si. At this point, the source and drain of the three thin-film transistors (first thin-film transistor TFT1, second thin-film transistor TFT2, and third thin-film transistor TFT3) are not separated; that is, the data lines and shared lines SCOM are a single unit. In the first embodiment of this application, the second metal film also forms the second connection line CL2. In the second embodiment of this application, the second metal film also forms two fifth connection lines CL5.

[0084] The non-channel region of the semiconductor layer A-Si is subjected to the first dry etching.

[0085] A second wet etching process is performed on the second metal thin film to remove the photoresist PR, forming the data line and shared line SCOM (second metal layer M2). At this point, the source and drain of the three thin-film transistors (first thin-film transistor TFT1, second thin-film transistor TFT2, and third thin-film transistor TFT3) are separated, i.e., the data line and shared line SCOM (second metal layer M2) are formed. The material of the second metal layer M2 can be chromium, molybdenum, aluminum, or alloys thereof.

[0086] A second dry etching is performed on the channel region of the semiconductor layer A-Si.

[0087] Through the above technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the electrostatic charge of a single common line ACOM coupled to a single shared line SCOM through capacitance is small. Therefore, the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is not likely to occur. After the first dry etching is completed, the common line ACOM is electrically connected to the fifth connecting line CL5 through the third via VH3 to form a mesh structure, and the shared line SCOM is electrically connected to the fourth connecting line CL4 through the second via VH2 to form a mesh structure. This subsequently formed mesh structure will not affect the electrostatic protection effect during the first dry etching process.

[0088] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, the display device comprising a display panel, the display panel including a display area and a non-display area, the display panel further comprising: substrate; A first metal layer is disposed on a substrate. The first metal layer includes multiple common lines and two first connecting lines. The length direction of the common lines is parallel to the first direction. The multiple common lines are arranged along a second direction. The first direction is perpendicular to the second direction. The two first connecting lines are respectively disposed on the non-display areas on opposite sides of the display panel in the first direction. The length direction of the first connecting lines is parallel to the second direction. The two ends of the multiple common lines are electrically connected to the two first connecting lines respectively. A gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; as well as A second metal layer is disposed on the gate insulating layer. The second metal layer includes multiple shared lines and a second connecting line. The length direction of the shared lines is parallel to the second direction. The multiple shared lines are arranged along the first direction. The second connecting line is disposed in the non-display area of ​​the display panel in the second direction. One end of the multiple shared lines is electrically connected to the second connecting line.

2. The display device according to claim 1, wherein The first metal layer further includes a third connecting line, which is disposed in the non-display area of ​​the display panel opposite to the second connecting line in the second direction. The length direction of the third connecting line is parallel to the first direction, and the third connecting line is electrically connected to the shared line through a first through-hole penetrating the gate insulating layer.

3. The display device according to claim 2, wherein Multiple first through holes are spaced apart along the first direction.

4. The display device according to claim 2, wherein The width of the third connecting line is greater than the width of the shared line.

5. The display device according to claim 2, wherein The third connecting line includes multiple broken line segments, and the included angle between adjacent broken line segments is an obtuse angle.

6. The display device according to claim 2, wherein Multiple first through holes are staggered in the first direction.

7. The display device according to claim 1, wherein The width of the first connecting line is greater than the width of the common line; The width of the second connecting line is greater than the width of the shared line.

8. The display device according to claim 1, wherein The first metal layer also includes lead wires, which are disposed in the non-display area; The first connecting line is electrically connected to the lead-out line.

9. The display device of claim 8, wherein, The lead-out line includes multiple sub-lead-out lines, and the multiple sub-lead-out lines are connected in parallel.

10. The display device of claim 9, wherein, The width of the sub-lead is 1.5 to 3 times the width of the common line.

11. The display device according to claim 1, wherein The edges of the first connecting line and the second connecting line are serrated.

12. A display device, the display device comprising a display panel, the display panel including a display area and a non-display area, the display panel further comprising: substrate; A first metal layer disposed on a substrate includes multiple common lines and two fourth connecting lines. The length direction of the common lines is parallel to a first direction. The multiple common lines are arranged along a second direction. The first direction is perpendicular to the second direction. The two fourth connecting lines are respectively disposed on the non-display areas on opposite sides of the display panel in the second direction. The length direction of the fourth connecting lines is parallel to the first direction. A gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; as well as A second metal layer is disposed on the gate insulating layer. The second metal layer includes multiple shared lines and two fifth connecting lines. The length direction of the shared lines is parallel to the second direction. The multiple shared lines are arranged along the first direction. The multiple shared lines are electrically connected to the fourth connecting line through a second through-hole penetrating the gate insulating layer. The two fifth connecting lines are respectively disposed on the non-display areas on opposite sides of the display panel in the first direction. The length direction of the fifth connecting lines is parallel to the second direction. Among them, multiple common lines are electrically connected to the fifth connection line through a third through-hole that penetrates the gate insulating layer.

13. The display device of claim 12, wherein, The width of the fourth connecting line is greater than the width of the shared line; The width of the fifth connecting line is greater than the width of the common line.

14. The display device of claim 12, wherein, Multiple second through holes are spaced apart along the first direction; The plurality of the third through holes are spaced apart along the second direction.

15. The display device of claim 12, wherein, The first metal layer also includes lead wires, which are disposed in the non-display area; The fifth connection line is electrically connected to the lead line through a fourth through-hole that penetrates the gate insulating layer.

16. The display device of claim 15, wherein, The lead-out line includes multiple sub-lead-out lines, and the multiple sub-lead-out lines are connected in parallel.

17. The display device of claim 16, wherein, The width of the sub-lead is 1.5 to 3 times the width of the common line.

18. The display device of claim 12, wherein, The fourth connecting line and the fifth connecting line include multiple broken line segments, and the included angle between adjacent broken line segments is an obtuse angle.

19. The display device of claim 12, wherein, Multiple second through holes are staggered in the first direction; The plurality of the third through holes are staggered in the second direction.

20. The display device of claim 12, wherein, The edges of the fourth and fifth connecting lines are serrated.

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