Pixel and image sensor

Abstract

A pixel and an image sensor, relating to the technical field of image sensors. The pixel comprises: a photosensitive unit for generating electric charges in response to light; a transmission unit for transmitting the electric charges generated by the photosensitive unit to a floating diffusion node; a reset unit for resetting the pixel; an amplification unit for amplifying a voltage at the floating diffusion node and outputting the amplified voltage to a storage unit; the storage unit for storing a reset voltage and a signal voltage; a switching unit for switching an exposure mode of the pixel and switching a conversion gain of the pixel in the exposure mode, wherein the exposure mode comprises a global shutter mode and a rolling shutter mode; and an output unit for outputting the reset voltage and the signal voltage. The pixel supports global shutter and rolling shutter, and supports a high dynamic range in both a global shutter mode and a rolling shutter mode.

Description

A pixel and image sensor

[0001] This application claims priority to Chinese Patent Application No. 202411608399.1, filed on November 12, 2024, entitled "A Pixel and Image Sensor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of image sensor technology, and in particular to a pixel and image sensor. Background Technology

[0003] CMOS image sensor exposure methods are divided into two categories: global exposure and drum exposure. Global exposure, because the exposure is completed simultaneously, does not produce motion artifacts and is suitable for imaging fast-moving objects. However, global exposure requires simultaneous exposure, so common multi-frame synthesis algorithms for achieving high dynamic range cannot be used with global exposure. Therefore, most high dynamic range CMOS image sensors currently use drum exposure, and most technologies for improving dynamic range are based on pixels developed using drum exposure. Therefore, how to achieve high dynamic range using global exposure has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a pixel and image sensor that supports both global exposure and drum exposure, and supports high dynamic range in both global exposure and drum exposure modes.

[0005] To address the aforementioned technical problems, this application provides a pixel, comprising:

[0006] The unit includes a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit, and an output unit.

[0007] The photosensitive unit is used to generate charge by sensing light;

[0008] The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node.

[0009] The reset unit is used to reset the pixel;

[0010] The amplification unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit;

[0011] The storage unit is used to store the reset voltage and the signal voltage;

[0012] The switching unit is used to switch the exposure mode of a pixel and switch the conversion gain of the pixel in the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode;

[0013] The output unit is used to output reset voltage and signal voltage.

[0014] In some embodiments, the switching unit includes:

[0015] The first switching unit is used to connect the target capacitor in the storage unit to the input terminal of the output unit and to connect the target capacitor in the storage unit to the second switching unit when the first switching unit is turned on.

[0016] The second switching unit is used to connect the floating diffusion node to the input terminal of the output unit and the first switching unit when the second switching unit is turned on.

[0017] In some embodiments, the storage unit includes:

[0018] First storage unit and second storage unit;

[0019] The first storage unit is used to store one of the reset voltage and the signal voltage;

[0020] The second storage unit is used to store one of the reset voltage and the signal voltage;

[0021] The first storage unit and the second storage unit store different voltage types.

[0022] In some embodiments, the storage unit includes a third switching unit, a fourth switching unit, a first capacitor, and a second capacitor; one end of the third switching unit is connected to the output terminal of the amplification unit, the other end of the third switching unit is connected to one end of the first capacitor and one end of the fourth switching unit, the other end of the first capacitor is grounded, the other end of the fourth switching unit is connected to one end of the second capacitor and the first switching unit, and the other end of the second capacitor is grounded.

[0023] In some embodiments, the transmission unit is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit is turned on, connecting the power supply of the floating diffusion node to the reset unit; the amplification unit is controlled by a third control signal, and when the third control signal is a first level signal, the output terminal of the amplification unit is grounded; the third switching unit is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the third switching unit is turned on; the fourth switching unit is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the fourth switching unit is turned on; the first switching unit is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the first switching unit is turned on; the second switching unit is controlled by a seventh control signal, and when the seventh control signal is a first level signal, the second switching unit is turned on; the output unit is controlled by an eighth control signal, and when the eighth control signal is a first level signal, the output unit outputs a voltage.

[0024] In some embodiments, during the memory cell reset phase, the third control signal, the seventh control signal, and the sixth control signal are first-level signals; the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory cell reset phase; and the second control signal, the first control signal, and the eighth control signal are second-level signals. During the photosensitive unit reset phase, the third control signal and the eighth control signal are second-level signals; and the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal and the first control signal are second-level signals; and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal... The third control signal, the second control signal, and the eighth, seventh, and sixth control signals are all second-level signals. The fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase. The fourth control signal changes from a first-level signal to a second-level signal at a third preset time during the frame header time phase. The first control signal changes from a second-level signal to a first-level signal at a fourth preset time during the frame header time phase. The fourth preset time is later than the third preset time, and the third preset time is later than the second preset time. During the readout phase, the third, fourth, second, and first control signals are all second-level signals, while the eighth, seventh, and sixth control signals are all first-level signals. The fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

[0025] In some embodiments, during the memory cell reset phase, the third control signal and the sixth control signal are first-level signals, and the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory cell reset phase; the second control signal, the first control signal, the eighth control signal, and the seventh control signal are second-level signals. During the photosensitive unit reset phase, the third control signal, the eighth control signal, and the seventh control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal, the first control signal, and the seventh control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, and the sixth control signal are first-level signals. The control signal is a first-level signal; during the frame header time phase, the third, second, and seventh control signals are second-level signals, the fourth, eighth, and sixth control signals are first-level signals, the fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase, and the first control signal changes from a second-level signal to a first-level signal at a third preset time during the frame header time phase; the third preset time is later than the second preset time; during the readout phase, the third, second, first, and seventh control signals are second-level signals, the fourth, eighth, and sixth control signals are first-level signals; the fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

[0026] In some embodiments, during the memory cell reset phase, the third control signal and the seventh control signal are first-level signals, and the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory cell reset phase; the second control signal, the first control signal, the eighth control signal, and the sixth control signal are second-level signals. During the photosensitive unit reset phase, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are second-level signals; the second control signal, the first control signal, and the seventh control signal are first-level signals. During the exposure phase, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are second-level signals. The fifth control signal, the first control signal, and the sixth control signal are second-level signals, while the second control signal, the eighth control signal, and the seventh control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second-level signals, while the eighth control signal and the seventh control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, the reset voltage is read. After the frame header time phase and after the first control signal changes to a second-level signal, the signal voltage is read.

[0027] In some embodiments, during the memory cell reset phase, the third control signal, the seventh control signal, and the sixth control signal are first-level signals; the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory cell reset phase; and the second control signal, the first control signal, and the eighth control signal are second-level signals. During the photosensitive unit reset phase, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second-level signals; and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal, the fourth control signal, the fifth control signal, the sixth control signal, the seventh control signal, the eighth control signal, and the ninth control signal are first-level signals. The five control signals are: the first control signal is a second-level signal, and the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, and the second control signal are second-level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, the reset voltage is read. After the frame header time phase and after the first control signal changes to a second-level signal, the signal voltage is read.

[0028] In some embodiments, the first switching unit includes:

[0029] A first transistor; a first terminal of the first transistor is connected to the memory cell, and a second terminal of the first transistor is connected to the input terminal of the second switching unit and the output unit; the first transistor is controlled by the sixth control signal.

[0030] In some embodiments, the second switching unit includes:

[0031] The second transistor; the first terminal of the second transistor is connected to the input terminal of the amplification unit, the second terminal of the second transistor is connected to the input terminals of the first switching unit and the output unit, and the second transistor is controlled by the seventh control signal.

[0032] In some embodiments, the photosensitive unit includes:

[0033] A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

[0034] In some embodiments, the transmission unit includes:

[0035] The third transistor; the first terminal of the third transistor is connected to the photosensitive unit, the second terminal of the third transistor is connected to the input terminal of the amplification unit, and the third transistor is controlled by the first control signal.

[0036] In some embodiments, the reset unit includes:

[0037] The fourth transistor; the first terminal of the fourth transistor is connected to the input terminal of the amplification unit, the second terminal of the fourth transistor is connected to the power supply, and the fourth transistor is controlled by the second control signal.

[0038] In some embodiments, the amplification unit includes:

[0039] The fifth transistor and the sixth transistor; the first terminal of the fifth transistor is connected to the second terminal of the sixth transistor and serves as the output terminal of the amplification unit, the second terminal of the fifth transistor is connected to the power supply, the third terminal of the fifth transistor serves as the input terminal of the amplification unit, the first terminal of the sixth transistor is grounded, and the sixth transistor is controlled by the third control signal.

[0040] In some embodiments, the third switching unit includes:

[0041] A seventh transistor; the first terminal of the seventh transistor is connected to the output terminal of the amplification unit, the second terminal of the seventh transistor is connected to one end of the first capacitor and one end of the fourth switching unit, and the seventh transistor is controlled by the fourth control signal.

[0042] In some embodiments, the fourth switching unit includes:

[0043] The eighth transistor; the first terminal of the eighth transistor is connected to the third switching unit, the second terminal of the eighth transistor is connected to one end of the second capacitor and the first switching unit, and the eighth transistor is controlled by the fifth control signal.

[0044] In some embodiments, the output unit includes:

[0045] The ninth transistor and the tenth transistor; the first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the power supply, the third terminal of the ninth transistor serves as the input terminal of the output unit, the first terminal of the tenth transistor serves as the output terminal of the output unit, and the tenth transistor is controlled by the eighth control signal.

[0046] To address the aforementioned technical problems, this application also provides an image sensor, including the pixels described above.

[0047] The pixel provided in this application includes: a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit, and an output unit; the photosensitive unit is used to generate charge by photosensitive activity; the transmission unit is used to transmit the charge generated by the photosensitive unit to a floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node; the reset unit is used to reset the pixel; the amplification unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit; the storage unit is used to store the reset voltage and the signal voltage; the switching unit is used to switch the exposure mode of the pixel and switch the conversion gain of the pixel in the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode; the output unit is used to output the reset voltage and the signal voltage.

[0048] As can be seen, the pixel provided in this application is equipped with a switching unit, which can switch the pixel's exposure mode to either global exposure mode or drum exposure mode. In global exposure mode, the switching unit can switch between different conversion gains. In drum exposure mode, the switching unit can switch between different conversion gains. This enables the pixel to support both global and drum exposure, and supports high dynamic range in both global and drum exposure modes.

[0049] The image sensor provided in this application also has the aforementioned technical effects. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 is a schematic diagram of a pixel provided in an embodiment of this application;

[0052] Figure 2 is a schematic diagram of a specific pixel provided in an embodiment of this application;

[0053] Figure 3 is a first signal timing diagram provided in an embodiment of this application;

[0054] Figure 4 is a second signal timing diagram provided in an embodiment of this application;

[0055] Figure 5 is a third signal timing diagram provided in the embodiments of this application;

[0056] Figure 6 is a fourth signal timing diagram provided in the embodiments of this application;

[0057] Figure 7 is a schematic diagram of another specific pixel provided in an embodiment of this application;

[0058] Figure 8 is a schematic diagram of yet another specific pixel provided in an embodiment of this application;

[0059] Figure 9 is a schematic diagram of another specific pixel provided in an embodiment of this application. Detailed Implementation

[0060] The core of this application is to provide a pixel and image sensor that supports both global exposure and drum exposure, and supports high dynamic range in both global exposure and drum exposure modes.

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] Please refer to Figure 1, which is a schematic diagram of a pixel provided in an embodiment of this application. As shown in Figure 1, the pixel includes:

[0063] The unit includes a photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplification unit 40, a storage unit 50, a switching unit 60, and an output unit 70.

[0064] The photosensitive unit 10 is used to generate charge by sensing light;

[0065] The transmission unit 20 is used to transmit the charge generated by the photosensitive unit 10 to the floating diffusion node when the transmission unit 20 is turned on; the input terminal of the amplification unit 40 serves as the floating diffusion node.

[0066] The reset unit 30 is used to reset the pixel;

[0067] The amplification unit 40 is used to amplify the voltage of the floating diffusion node and output it to the storage unit 50;

[0068] The storage unit 50 is used to store the reset voltage and the signal voltage;

[0069] The switching unit 60 is used to switch the exposure mode of a pixel and switch the conversion gain of the pixel in the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode.

[0070] The output unit 70 is used to output reset voltage and signal voltage.

[0071] In this embodiment, the pixel includes a photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplification unit 40, a storage unit 50, a switching unit 60, and an output unit 70. The photosensitive unit 10 is connected to the transmission unit 20. Both the transmission unit 20 and the reset unit 30 are connected to the input terminal of the amplification unit 40, which serves as a floating diffusion node. The output terminal of the amplification unit 40 is connected to the storage unit 50. The switching unit 60 connects the floating diffusion node, the storage unit 50, and the output unit 70. The switching unit 60 can switch the pixel's exposure mode to either a global exposure mode or a drum exposure mode. In global exposure mode, the switching unit 60 can switch between different conversion gains. In drum exposure mode, the switching unit 60 can switch between different conversion gains.

[0072] Referring to Figure 2, in some embodiments, the switching unit 60 includes:

[0073] The first switching unit 601 is used to connect the target capacitor in the storage unit to the input terminal of the output unit and to connect the target capacitor in the storage unit to the second switching unit 602 when the first switching unit 601 is turned on.

[0074] The second switching unit 602 is used to connect the floating diffusion node to the input terminal of the output unit and the first switching unit 601 when the second switching unit 602 is turned on.

[0075] One end of the first switching unit 601 is connected to the storage unit 50, and the other end of the first switching unit 601 is connected to one end of the second switching unit 602 and the input terminal of the output unit 70. The other end of the second switching unit 602 is connected to the floating diffusion node. When the first switching unit 601 is turned on, the storage unit 50, the output unit 70, and the second switching unit 602 are connected. When the second switching unit 602 is turned on, the floating diffusion node is connected to the first switching unit 601 and the output unit 70. Thus, by controlling the first switching unit 601 and the second switching unit 602 to be turned on or off, drum exposure and global exposure can be achieved, and different conversion gains can be achieved under different exposure modes. When the first switching unit 601 is turned on and the second switching unit 602 is turned off, the target capacitor in the storage unit 50 is not connected to the floating diffusion node, and the conversion gain is the first conversion gain. When the first switching unit 601 is turned on and the second switching unit 602 is turned on, the target capacitor in the storage unit 50 is connected to the floating diffusion node, the capacitance of the floating diffusion node increases, and the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain. Storage unit 50 stores the reset voltage and signal voltage, and output unit 70 outputs the voltage stored in storage unit 50. In this case, the pixel operates in global exposure mode. Storage unit 50 does not store the reset voltage and signal voltage; the second switching unit 602 is turned on, connecting the floating diffusion node to output unit 70. Output unit 70 directly outputs the reset voltage and signal voltage at the floating diffusion node. In this case, the pixel operates in rolling shutter exposure mode.

[0076] In some embodiments, the storage unit includes:

[0077] First storage unit and second storage unit;

[0078] The first storage unit is used to store one of the reset voltage and the signal voltage;

[0079] The second storage unit is used to store another of the reset voltage and the signal voltage;

[0080] The first storage unit and the second storage unit store different voltage types.

[0081] When the first storage cell is responsible for storing the reset voltage, the second storage cell is responsible for storing the signal voltage.

[0082] Referring to Figure 2, in some embodiments, the storage unit 50 includes a third switching unit 501, a fourth switching unit 502, a first capacitor C1, and a second capacitor C2; one end of the third switching unit 501 is connected to the output terminal of the amplification unit 40, the other end of the third switching unit 501 is connected to one end of the first capacitor C1 and one end of the fourth switching unit 502, the other end of the first capacitor C1 is grounded, the other end of the fourth switching unit 502 is connected to one end of the second capacitor C2 and the first switching unit 501, and the other end of the second capacitor C2 is grounded.

[0083] In this embodiment, the storage unit 50 includes two switching units and two capacitors, with the two capacitors responsible for sampling and storing the voltage. The third switching unit 501 and the first capacitor C1 constitute the first storage unit. The fourth switching unit 502 and the second capacitor C2 constitute the second storage unit.

[0084] In some embodiments, the transmission unit 20 is controlled by a first control signal; when the first control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a second control signal; when the second control signal is a first level signal, the reset unit 30 is turned on, connecting the power supply to the floating diffusion node connected to the reset unit 30. The amplification unit 40 is controlled by a third control signal; when the third control signal is a first level signal, the output terminal of the amplification unit 40 is grounded. The third switching unit 501 is controlled by a fourth control signal; when the fourth control signal is a first level signal, the output terminal of the amplification unit 40 is grounded. The third switching unit 501 is turned on; the fourth switching unit 502 is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the fourth switching unit 502 is turned on; the first switching unit 601 is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the first switching unit 601 is turned on; the second switching unit 602 is controlled by a seventh control signal, and when the seventh control signal is a first level signal, the second switching unit 602 is turned on; the output unit 70 is controlled by an eighth control signal, and when the eighth control signal is a first level signal, the output unit 70 outputs a voltage.

[0085] The first level signal can be a high level.

[0086] This embodiment controls the corresponding units through eight control signals, enabling switching between global exposure and drum exposure, as well as different conversion gains.

[0087] In some embodiments, during the memory unit 50 reset phase, the third control signal, the seventh control signal, and the sixth control signal are first-level signals; the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory unit 50 reset phase; and the second control signal, the first control signal, and the eighth control signal are second-level signals. During the photosensitive unit 10 reset phase, the third control signal and the eighth control signal are second-level signals; and the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal and the first control signal are second-level signals; and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase… The third control signal and the second control signal are second-level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase. The fourth control signal changes from a first-level signal to a second-level signal at a third preset time during the frame header time phase. The first control signal changes from a second-level signal to a first-level signal at a fourth preset time during the frame header time phase. The fourth preset time is later than the third preset time, and the third preset time is later than the second preset time. During the readout phase, the third control signal, the fourth control signal, the second control signal, and the first control signal are second-level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

[0088] The first level signal can be high level, and the second level signal can be low level.

[0089] This embodiment aims to achieve a global exposure mode under a second conversion gain. The second conversion gain is less than the first conversion gain. Referring to the timing diagram of the control signals shown in Figure 3, the working principle of the pixels shown in Figure 2 under this timing is as follows:

[0090] In Figure 3, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal. Additionally, in Figure 3, LCG represents low conversion gain, and Hi represents a high level.

[0091] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 3), the third control signal is high, the output of amplifier unit 40 is grounded, and the fourth and fifth control signals change from low to high at the first preset moment during the reset phase of memory cell 50. This turns on the third switch unit 501 and the fourth switch unit 502. At this time, both ends of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to amplifier unit 40 can be set to ground. This also grounds both ends of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0092] During the reset phase of the photosensitive unit 10 (i.e., the PD reset shown in Figure 3), the third control signal and the eighth control signal are at low level, while the second control signal, the first control signal, the fourth control signal, the fifth control signal, the seventh control signal, and the sixth control signal are at high level. The reset unit 30, the transmission unit 20, the third switch unit 501, the fourth switch unit 502, the second switch unit 602, and the first switch unit 601 are all turned on, thereby realizing the reset of the photosensitive unit 10.

[0093] During the exposure stage, the photosensitive unit 10 generates charge by sensing light. The first control signal is at a low level, so the transmission unit 20 is turned off, and the photosensitive unit 10 accumulates charge.

[0094] At the start of the frame header time phase (i.e., FOT shown in Figure 3), the second control signal goes low, and the fifth and fourth control signals successively change from high to low. After the second control signal goes low, turning off the reset unit 30, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst when both the fourth and fifth control signals are high. After the fifth and fourth control signals go low, the fourth switch unit 502 and the third switch unit 501 turn off. After both the fourth and fifth control signals go low, the first control signal goes high, and the transmission unit 20 turns on. At this time, the seventh and sixth control signals are both high, and both the first switch unit 601 and the second switch unit 602 turn on. Therefore, the second capacitor C2 samples the signal voltage Vsig, and the voltage on the second capacitor C2 becomes Vrst - Vsig.

[0095] During the readout phase, the readout circuit first reads the voltage Vrst - Vsig on the second capacitor C2. The fifth control signal changes from low to high and then back to low. The fourth switch unit 502 is turned on and then off. When the fourth switch unit 502 is on, the reset voltage Vrst on the first capacitor C1 is read. Since the charge on the first capacitor C1 and the second capacitor C2 is redistributed after the fourth switch unit 502 is turned on, and the first capacitor C1 equals the second capacitor C2, according to the principle of charge conservation, the final output signal voltage Vsign = Vrst - 0.5Vsig after the fourth switch unit 502 is turned off is obtained. Therefore, after correlation double sampling, the obtained signal voltage is Vrst - Vsign = 0.5Vsig.

[0096] Throughout the process, the seventh and sixth control signals remain high, and the second switching unit 602 and the first switching unit 601 remain on, connecting the target capacitor (second capacitor C2) in the storage unit 50 to the floating diffusion node. At this time, the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain.

[0097] In some embodiments, during the reset phase of the storage unit 50, the third control signal and the sixth control signal are first-level signals, and the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the reset phase of the storage unit 50. The second control signal, the first control signal, the eighth control signal, and the seventh control signal are second-level signals. During the reset phase of the photosensitive unit 10, the third control signal, the eighth control signal, and the seventh control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal, the first control signal, and the seventh control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, and the sixth control signal are first-level signals. The sixth control signal is a first-level signal; during the frame header time phase, the third, second, and seventh control signals are second-level signals, and the fourth, eighth, and sixth control signals are first-level signals. The fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase, and the first control signal changes from a second-level signal to a first-level signal at a third preset time during the frame header time phase; the third preset time is later than the second preset time. During the readout phase, the third, second, first, and seventh control signals are second-level signals, and the fourth, eighth, and sixth control signals are first-level signals. The fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

[0098] The first level signal can be high level, and the second level signal can be low level.

[0099] This embodiment aims to achieve a global exposure mode under the first conversion gain. Referring to the timing diagram of the control signals shown in Figure 4, the working principle of the pixel shown in Figure 2 under this timing is as follows:

[0100] In Figure 4, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal. In Figure 4, HCG represents high conversion gain, and Lo represents low level.

[0101] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 4), the third control signal is high, the output of amplifier unit 40 is grounded, and the fourth and fifth control signals change from low to high at the first preset moment during the reset phase of memory cell 50. This turns on the third switch unit 501 and the fourth switch unit 502. At this time, both ends of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to amplifier unit 40 can be set to ground. This also grounds both ends of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0102] During the reset phase of the photosensitive unit 10 (i.e., the PD reset shown in Figure 4), the third control signal, the eighth control signal, and the seventh control signal are at low level, while the second control signal, the first control signal, the fourth control signal, the fifth control signal, and the sixth control signal are at high level. The reset unit 30, the transmission unit 20, the third switch unit 501, the fourth switch unit 502, and the first switch unit 601 are all turned on, thereby resetting the photosensitive unit 10.

[0103] During the exposure stage, the photosensitive unit 10 generates charge by sensing light. The first control signal is at a low level, so the transmission unit 20 is turned off, and the photosensitive unit 10 accumulates charge.

[0104] At the start of the frame header time phase (i.e., FOT shown in Figure 4), the second control signal goes low, the fourth control signal remains high, and the fifth control signal changes from high to low at a second preset time after the start of the frame header time phase. When both the fourth and fifth control signals are high, the third switch unit 501 and the fourth switch unit 502 are turned on. After the second control signal goes low and the reset unit 30 is turned off, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. At the third preset time of the frame header time phase, the first control signal changes from low to high, and the transmission unit 20 is turned on. Since the fourth control signal is high at this time, the third switch unit 501 is turned on, so the first capacitor C1 samples the signal voltage Vsig.

[0105] When reading the reset voltage, the reset voltage Vrst sampled on the second capacitor C2 is read. When reading the signal voltage, the fifth control signal first changes from low to high and then back to low to turn on the fourth switch unit 502 and then off. When the fourth switch unit 502 is on, the signal voltage Vsig on the first capacitor C1 is read. Since the charge sampled on the first capacitor C1 and the second capacitor C2 is redistributed after the fourth switch unit 502 is on, and the first capacitor C1 equals the second capacitor C2, according to the principle of charge conservation, the final output signal voltage Vsign after the fourth switch unit 502 is off is Vsign = 0.5Vrst + 0.5Vsig. Therefore, after correlation double sampling, the obtained signal voltage is Vrst - Vsign = 0.5Vrst - 0.5Vsig.

[0106] Throughout the process, the seventh control signal remains at a low level, the second switch unit 602 remains off, and the target capacitor (second capacitor C2) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0107] In some embodiments, during the reset phase of the storage unit 50, the third control signal and the seventh control signal are first-level signals, and the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the reset phase of the storage unit 50; the second control signal, the first control signal, the eighth control signal, and the sixth control signal are second-level signals. During the reset phase of the photosensitive unit 10, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are second-level signals, and the second control signal, the first control signal, and the seventh control signal are first-level signals. During the exposure phase, the third control signal and the fourth control signal... The fifth control signal, the first control signal, and the sixth control signal are second-level signals, while the second control signal, the eighth control signal, and the seventh control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second-level signals, while the eighth control signal and the seventh control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, the reset voltage is read. After the frame header time phase and when the first control signal changes to a second-level signal, the signal voltage is read.

[0108] The first level signal can be high level, and the second level signal can be low level.

[0109] This embodiment aims to achieve a rolling shutter exposure mode under the first conversion gain. Referring to the timing diagram of the control signals shown in Figure 5, the working principle of the pixel shown in Figure 2 under this timing is as follows:

[0110] In Figure 5, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal. In Figure 5, HCG represents high conversion gain, Hi represents high level, and Lo represents low level.

[0111] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 5), the third control signal is high, the output of amplifier unit 40 is grounded, and the fourth and fifth control signals change from low to high at the first preset moment during the reset phase of memory cell 50. This turns on the third switch unit 501 and the fourth switch unit 502. At this time, both ends of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to amplifier unit 40 can be set to ground. This also grounds both ends of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0112] During the reset phase of the photosensitive unit 10 (i.e., the PD reset shown in Figure 5), the third, fourth, fifth, eighth, and sixth control signals are at low level, while the second, first, and seventh control signals are at high level. The reset unit 30, the transmission unit 20, and the second switch unit 602 are all turned on, thereby resetting the photosensitive unit 10.

[0113] During the exposure stage, the photosensitive unit 10 generates charge by sensing light. The first control signal is at a low level, so the transmission unit 20 is turned off, and the photosensitive unit 10 accumulates charge.

[0114] At the start of the frame header time phase (i.e., FOT shown in Figure 5), the second control signal goes low, the seventh control signal remains high, the second switch unit 602 is turned on, and the reset voltage Vrst is read out. At the second preset time of the frame header time phase, the first control signal changes from low to high, the transmission unit 20 is turned on, and the charge generated by the photosensitive unit 10 is transferred to the input terminal of the output unit 70 via the transmission unit 20 and the second switch unit 602. The eighth control signal is high, the output unit 70 is turned on, and the output signal voltage Vsig is obtained after correlation double sampling, which is Vrst - Vsig.

[0115] Throughout the process, the sixth control signal is at a low level, the first switch unit 601 is always off, and the target capacitor (second capacitor C2) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0116] In some embodiments, during the reset phase of the storage unit 50, the third control signal, the seventh control signal, and the sixth control signal are first-level signals; the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the reset phase of the storage unit 50; and the second control signal, the first control signal, and the eighth control signal are second-level signals. During the reset phase of the photosensitive unit 10, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second-level signals; and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure phase, the third control signal, the fourth control signal, and the fifth control signal are first-level signals. The fifth control signal and the first control signal are second-level signals, and the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, and the second control signal are second-level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, the reset voltage is read. After the frame header time phase and after the first control signal changes to a second-level signal, the signal voltage is read.

[0117] The first level signal can be high level, and the second level signal can be low level.

[0118] This embodiment aims to achieve a rolling shutter exposure mode under the second conversion gain. Referring to the timing diagram of the control signals shown in Figure 6, the first conversion gain is less than the second conversion gain. Under this timing, the working principle of the pixel shown in Figure 2 is as follows:

[0119] In Figure 6, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal. In Figure 6, LCG represents low conversion gain, and Hi represents high level.

[0120] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 6), the third control signal is high, the output of amplifier unit 40 is grounded, and the fourth and fifth control signals change from low to high at the first preset moment during the reset phase of memory cell 50. This turns on the third switch unit 501 and the fourth switch unit 502. At this time, both ends of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to amplifier unit 40 can be set to ground. This also grounds both ends of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0121] During the reset phase of the photosensitive unit 10 (i.e., the PD reset shown in Figure 6), the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are at low level, while the second control signal, the first control signal, and the seventh control signal are at high level. The reset unit 30, the transmission unit 20, and the second switch unit 602 are all turned on, thereby resetting the photosensitive unit 10.

[0122] During the exposure stage, the photosensitive unit 10 generates charge by sensing light. The first control signal is at a low level, so the transmission unit 20 is turned off, and the photosensitive unit 10 accumulates charge.

[0123] At the start of the frame header time phase (i.e., FOT shown in Figure 6), the second control signal goes low, the seventh control signal remains high, the second switching unit 602 is turned on, and the reset voltage Vrst is read out. At the second preset time of the frame header time phase, the first control signal changes from low to high, the transmission unit 20 is turned on, and the charge generated by the photosensitive unit 10 is transferred to the input terminal of the output unit 70 via the transmission unit 20 and the second switching unit 602. The eighth control signal is high, the output unit 70 is turned on, and the output signal voltage Vsig is obtained after correlation double sampling, which is Vrst - Vsig.

[0124] Throughout the process, the sixth and seventh control signals are at a high level, and the first switch unit 601 and the second switch unit 602 are always on, connecting the target capacitor (second capacitor C2) in the storage unit 50 to the floating diffusion node. At this time, the conversion gain is the second conversion gain.

[0125] Referring to Figure 7, in some embodiments, the first switching unit 601 includes: a first transistor M1; a first terminal of the first transistor M1 is connected to the storage unit 50, and a second terminal of the first transistor M1 is connected to the input terminal of the second switching unit 602 and the output unit 70; the first transistor M1 is controlled by the sixth control signal.

[0126] The second switching unit 602 includes a second transistor M2; the first end of the second transistor M2 is connected to the input terminal of the amplification unit 40, the second end of the second transistor M2 is connected to the input terminals of the first switching unit 601 and the output unit 70, and the second transistor M2 is controlled by the seventh control signal.

[0127] The photosensitive unit 10 includes a photodiode PD; the anode of the photodiode PD is grounded, and the cathode of the photodiode PD is connected to the transmission unit 20.

[0128] The transmission unit 20 includes a third transistor M3; the first end of the third transistor M3 is connected to the photosensitive unit 10, the second end of the third transistor M3 is connected to the input terminal of the amplification unit 40, and the third transistor M3 is controlled by the first control signal.

[0129] The reset unit 30 includes a fourth transistor M4; the first terminal of the fourth transistor M4 is connected to the input terminal of the amplification unit 40, the second terminal of the fourth transistor M4 is connected to the power supply, and the fourth transistor M4 is controlled by the second control signal.

[0130] The amplification unit 40 includes a fifth transistor M5 and a sixth transistor M6; the first terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6 and serves as the output terminal of the amplification unit 40; the second terminal of the fifth transistor M5 is connected to a power supply; the third terminal of the fifth transistor M5 serves as the input terminal of the amplification unit 40; the first terminal of the sixth transistor M6 is grounded; and the sixth transistor M6 is controlled by the third control signal.

[0131] The third switching unit 501 includes a seventh transistor M7; the first end of the seventh transistor M7 is connected to the output end of the amplification unit 40, the second end of the seventh transistor M7 is connected to one end of the first capacitor C1 and one end of the fourth switching unit 502, and the seventh transistor M7 is controlled by the fourth control signal.

[0132] The fourth switching unit 502 includes an eighth transistor M8; the first end of the eighth transistor M8 is connected to the third switching unit 501, the second end of the eighth transistor M8 is connected to one end of the second capacitor C2 and the first switching unit 601, and the eighth transistor M8 is controlled by the fifth control signal.

[0133] The output unit 70 includes a ninth transistor M9 and a tenth transistor M10; the first terminal of the ninth transistor M9 is connected to the second terminal of the tenth transistor M10, the second terminal of the ninth transistor M9 is connected to a power supply, the third terminal of the ninth transistor M9 serves as the input terminal of the output unit 70, the first terminal of the tenth transistor M10 serves as the output terminal of the output unit 70, and the tenth transistor M10 is controlled by the eighth control signal.

[0134] The first transistor M1 to the tenth transistor M10 can all be MOSFETs. The first terminal of the first transistor M1 to the tenth transistor M10 is the source of the MOSFET, the second terminal of the first transistor M1 to the tenth transistor M10 is the drain of the MOSFET, and the third terminal of the first transistor M1 to the tenth transistor M10 is the gate of the MOSFET.

[0135] Referring to the timing diagram of the control signals shown in Figure 3, the working principle of the pixel shown in Figure 7 under this timing is as follows:

[0136] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 3), the third control signal is high, the first terminal of the fifth transistor M5 is grounded, and the fourth and fifth control signals change from low to high at the first preset time during the reset phase of memory cell 50. This causes the seventh transistor M7 and the eighth transistor M8 to conduct. At this time, both terminals of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to the fifth transistor M5 can be set to ground, which also grounds both terminals of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0137] During the photodiode PD reset stage (i.e., the PD reset shown in Figure 3), the third and eighth control signals are at low level, while the second, first, fourth, fifth, seventh, and sixth control signals are at high level. The fourth transistor M4, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the second transistor M2, and the first transistor M1 are all turned on, thus achieving the reset of the photodiode PD.

[0138] During the exposure stage, the photodiode PD generates charge by absorbing light. The first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charge.

[0139] At the start of the frame header time phase (i.e., FOT shown in Figure 3), the second control signal goes low, and the fifth and fourth control signals successively change from high to low. After the second control signal goes low, turning off the fourth transistor M4, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst when both the fourth and fifth control signals are high. After the fifth and fourth control signals go low, the eighth transistor M8 and the seventh transistor M7 turn off. After both the fourth and fifth control signals go low, the first control signal goes high, and the third transistor M3 turns on. Therefore, the seventh and sixth control signals are both high, and both the first transistor M1 and the second transistor M2 are on. Thus, the second capacitor C2 samples the signal voltage Vsig, and the voltage across the second capacitor C2 at this time is Vrst - Vsig.

[0140] During the readout phase, the readout circuit first reads the voltage Vrst - Vsig on the second capacitor C2. The fifth control signal changes from low to high and then back to low. The eighth transistor M8 turns on and then turns off. When the eighth transistor M8 is on, the reset voltage Vrst on the first capacitor C1 is read. Since the charge on the first capacitor C1 and the second capacitor C2 is redistributed after the eighth transistor M8 turns on, and the first capacitor C1 equals the second capacitor C2, according to the principle of charge conservation, the final output signal voltage Vsign = Vrst - 0.5Vsig after the eighth transistor M8 turns off is obtained. Therefore, after correlation double sampling, the obtained signal voltage is Vrst - Vsign = 0.5Vsig.

[0141] Throughout the process, the seventh and sixth control signals remain high, and the second transistor M2 and the first transistor M1 remain on, connecting the target capacitor (second capacitor C2) in storage cell 50 to the floating diffusion node. At this time, the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain.

[0142] Referring to the timing diagram of the control signals shown in Figure 4, the working principle of the pixel shown in Figure 7 under this timing is as follows:

[0143] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 4), the third control signal is high, the first terminal of the fifth transistor M5 is grounded, and the fourth and fifth control signals change from low to high at the first preset moment during the reset phase of memory cell 50. This turns on the seventh transistor M7 and the eighth transistor M8, and at this time, both terminals of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to the fifth transistor M5 can be set to ground, which also grounds both terminals of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0144] During the photodiode PD reset stage (i.e., the PD reset shown in Figure 4), the third, eighth, and seventh control signals are at low level, while the second, first, fourth, fifth, and sixth control signals are at high level. The fourth transistor M4, the third transistor M3, the seventh transistor M7, the eighth transistor M8, and the first transistor M1 are all turned on, thereby resetting the photodiode PD.

[0145] During the exposure stage, the photodiode PD generates charge by absorbing light. The first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charge.

[0146] At the start of the frame header time phase (i.e., FOT shown in Figure 4), the second control signal goes low, the fourth control signal remains high, and the fifth control signal changes from high to low at the second preset time after the start of the frame header time phase. When both the fourth and fifth control signals are high, the seventh transistor M7 and the eighth transistor M8 are turned on. After the second control signal goes low, turning off the fourth transistor M4, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. At the third preset time of the frame header time phase, the first control signal changes from low to high, and the third transistor M3 is turned on. Since the fourth control signal is high at this time and the seventh transistor M7 is turned on, the first capacitor C1 samples the signal voltage Vsig.

[0147] When reading the reset voltage, the reset voltage Vrst sampled on the second capacitor C2 is read. When reading the signal voltage, the fifth control signal first changes from low to high and then back to low to turn on and then off the eighth transistor M8. When the eighth transistor M8 is on, the voltage Vsig on the first capacitor C1 is read. Since the charge sampled on the first capacitor C1 and the second capacitor C2 is redistributed after the eighth transistor M8 is turned on, and the first capacitor C1 equals the second capacitor C2, according to the principle of charge conservation, the final output signal voltage Vsign after the eighth transistor M8 is turned off is Vsign = 0.5Vrst + 0.5Vsig. Therefore, after correlation double sampling, the obtained signal voltage is Vrst - Vsign = 0.5Vrst - 0.5Vsig.

[0148] Throughout the process, the seventh control signal remains low, the second transistor M2 remains off, and the target capacitor (second capacitor C2) in the storage cell 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0149] Referring to the timing diagram of the control signals shown in Figure 5, the working principle of the pixel shown in Figure 7 under this timing is as follows:

[0150] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 5), the third control signal is high, the first terminal of the fifth transistor M5 is grounded, and the fourth and fifth control signals change from low to high at the first preset time during the reset phase of memory cell 50. This turns on the seventh transistor M7 and the eighth transistor M8, and at this time, both terminals of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to the fifth transistor M5 can be set to ground, which also grounds both terminals of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0151] During the photodiode PD reset stage (i.e., the PD reset shown in Figure 5), the third, fourth, fifth, eighth, and sixth control signals are at low level, while the second, first, and seventh control signals are at high level. The fourth transistor M4, the third transistor M3, and the second transistor M2 are all turned on, thereby resetting the photodiode PD.

[0152] During the exposure stage, the photodiode PD generates charge by absorbing light. The first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charge.

[0153] At the start of the frame header time phase (i.e., FOT shown in Figure 5), the second control signal goes low, the seventh control signal remains high, the second transistor M2 is turned on, and the reset voltage Vrst is read out. At the second preset time of the frame header time phase, the first control signal changes from low to high, the third transistor M3 is turned on, and the charge generated by the photodiode PD is transferred to the input terminal of the output unit 70 via the third transistor M3 and the second transistor M2. The eighth control signal is high, the output unit 70 is turned on, and the output signal voltage Vsig is obtained after correlation double sampling, which is Vrst - Vsig.

[0154] Throughout the process, the sixth control signal is at a low level, the first transistor M1 is always off, and the target capacitor (second capacitor C2) in the storage cell 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0155] Referring to the timing diagram of the control signals shown in Figure 6, the first conversion gain is less than the second conversion gain. Under this timing, the working principle of the pixel shown in Figure 7 is as follows:

[0156] During the reset phase of memory cell 50 (i.e., the MIM capacitor reset shown in Figure 6), the third control signal is high, the first terminal of the fifth transistor M5 is grounded, and the fourth and fifth control signals change from low to high at the first preset time during the reset phase of memory cell 50. This turns on the seventh transistor M7 and the eighth transistor M8, and at this time, both terminals of the first capacitor C1 and the second capacitor C2 are grounded, thus resetting the first capacitor C1 and the second capacitor C2. Alternatively, besides the above method, the voltage of the power supply connected to the fifth transistor M5 can be set to ground, which also grounds both terminals of the first capacitor C1 and the second capacitor C2, thereby resetting them.

[0157] During the photodiode PD reset stage (i.e., the PD reset shown in Figure 6), the third, fourth, fifth, and eighth control signals are at low level, while the second, first, and seventh control signals are at high level. The fourth transistor M4, the third transistor M3, and the second transistor M2 are all turned on, thereby resetting the photodiode PD.

[0158] During the exposure stage, the photodiode PD generates charge by absorbing light. The first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charge.

[0159] At the start of the frame header time phase (i.e., FOT shown in Figure 6), the second control signal goes low, the seventh control signal remains high, the second transistor M2 is turned on, and the reset voltage Vrst is read out. At the second preset time of the frame header time phase, the first control signal changes from low to high, the third transistor M3 is turned on, and the charge generated by the photodiode PD is transferred to the input terminal of the output unit 70 via the third transistor M3 and the second transistor M2. The eighth control signal is high, the output unit 70 is turned on, and the output signal voltage Vsig is obtained after correlation double sampling, which is Vrst - Vsig.

[0160] Throughout the process, the sixth and seventh control signals are at a high level, and the first transistor M1 and the second transistor M2 are always on, connecting the target capacitor (second capacitor C2) in the storage cell 50 to the floating diffusion node. At this time, the conversion gain is the second conversion gain.

[0161] It should be noted that, in addition to the structure of the storage unit 50 shown in the above embodiments, the storage unit 50 can also adopt other structures. For example, as shown in FIG8, the storage unit 50 may include transistors Q1 to Q4, capacitors C1 and C2. In the case where the storage unit 50 adopts the structure shown in FIG8, the storage unit 50 can be directly connected to the output unit 70, and the switching unit 60 may only have a second switching unit 602. Transistors Q2 and Q4 in the storage unit 50 can both function as the first switching unit. As another example, as shown in FIG9, the storage unit 50 may include transistors Q5 to Q7, capacitors C1 and C2.

[0162] In summary, the pixel provided in this application is equipped with a switching unit, which allows the pixel's exposure mode to be switched between global exposure mode and drum exposure mode. In global exposure mode, the switching unit can switch between different conversion gains. In drum exposure mode, the switching unit can also switch between different conversion gains. This enables the pixel to support both global and drum exposure, and supports high dynamic range in both global and drum exposure modes.

[0163] This application also provides an image sensor including the pixels described in the above embodiments. For a description of the image sensor provided in this application, please refer to the above-described pixel embodiments; further details will not be repeated here.

[0164] Due to the complexity of the situation, it is impossible to list and elaborate on them all. Those skilled in the art should realize that there can be multiple examples based on the basic principles of the embodiments provided in this application and in combination with actual situations. Without sufficient creative effort, all of them should be within the scope of this application.

[0165] The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0166] The pixel and image sensor provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0167] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A pixel, characterized by, include: The unit includes a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit, and an output unit. The photosensitive unit is used to generate charge by sensing light; The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input terminal of the amplification unit serves as the floating diffusion node. The reset unit is used to reset the pixel; The amplification unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit; The storage unit is used to store the reset voltage and the signal voltage; The switching unit is used to switch the exposure mode of a pixel and switch the conversion gain of the pixel in the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode; The output unit is used to output reset voltage and signal voltage.

2. The pixel of claim 1, wherein, The switching unit includes: The first switching unit is used to connect the target capacitor in the storage unit to the input terminal of the output unit and to connect the target capacitor in the storage unit to the second switching unit when the first switching unit is turned on. The second switching unit is used to connect the floating diffusion node to the input terminal of the output unit and the first switching unit when the second switching unit is turned on.

3. The pixel of claim 2, wherein, The storage unit includes: First storage unit and second storage unit; The first storage unit is used to store one of the reset voltage and the signal voltage; The second storage unit is used to store one of the reset voltage and the signal voltage; The first storage unit and the second storage unit store different voltage types.

4. The pixel of claim 3, wherein, The storage unit includes a third switching unit, a fourth switching unit, a first capacitor, and a second capacitor; one end of the third switching unit is connected to the output terminal of the amplification unit, the other end of the third switching unit is connected to one end of the first capacitor and one end of the fourth switching unit, the other end of the first capacitor is grounded, the other end of the fourth switching unit is connected to one end of the second capacitor and the first switching unit, and the other end of the second capacitor is grounded.

5. The pixel of claim 4, wherein, The transmission unit is controlled by a first control signal; when the first control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a second control signal; when the second control signal is a first level signal, the reset unit is turned on, connecting the power supply to the floating diffusion node connected to the reset unit. The amplification unit is controlled by a third control signal; when the third control signal is a first level signal, the output terminal of the amplification unit is grounded. The third switching unit is controlled by a fourth control signal; when the fourth control signal is a first level signal, the third switching unit is turned on. The fourth switching unit is controlled by a fifth control signal; when the fifth control signal is a first level signal, the fourth switching unit is turned on. The first switching unit is controlled by a sixth control signal; when the sixth control signal is a first level signal, the first switching unit is turned on. The second switching unit is controlled by a seventh control signal; when the seventh control signal is a first level signal, the second switching unit is turned on. The output unit is controlled by an eighth control signal; when the eighth control signal is a first level signal, the output unit outputs a voltage.

6. The pixel of claim 5, wherein, During the memory cell reset phase, the third control signal, the seventh control signal, and the sixth control signal are first level signals. The fourth control signal and the fifth control signal change from second level signals to first level signals at a first preset time during the memory cell reset phase. The second control signal, the first control signal, and the eighth control signal are second level signals. During the photosensitive unit reset phase, the third control signal and the eighth control signal are second-level signals, while the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure stage, the third control signal and the first control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal and the second control signal are second-level signals, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals, the fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase, the fourth control signal changes from a first-level signal to a second-level signal at a third preset time during the frame header time phase, and the first control signal changes from a second-level signal to a first-level signal at a fourth preset time during the frame header time phase. The fourth preset time is later than the third preset time, and the third preset time is later than the second preset time; During the readout phase, the third control signal, the fourth control signal, the second control signal, and the first control signal are second-level signals, while the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

7. The pixel of claim 5, wherein, During the memory cell reset phase, the third control signal and the sixth control signal are first level signals, and the fourth control signal and the fifth control signal change from second level signals to first level signals at a first preset time during the memory cell reset phase. The second control signal, the first control signal, the eighth control signal, and the seventh control signal are second level signals. During the photosensitive unit reset phase, the third control signal, the eighth control signal, and the seventh control signal are second-level signals, while the fourth control signal, the fifth control signal, the second control signal, the first control signal, and the sixth control signal are first-level signals. During the exposure stage, the third control signal, the first control signal, and the seventh control signal are second-level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal, the second control signal, and the seventh control signal are second-level signals, the fourth control signal, the eighth control signal, and the sixth control signal are first-level signals, the fifth control signal changes from a first-level signal to a second-level signal at a second preset time during the frame header time phase, and the first control signal changes from a second-level signal to a first-level signal at a third preset time during the frame header time phase. The third preset time is later than the second preset time; During the readout phase, the third control signal, the second control signal, the first control signal, and the seventh control signal are second-level signals, while the fourth control signal, the eighth control signal, and the sixth control signal are first-level signals. The fifth control signal changes from a second-level signal to a first-level signal and then back to a second-level signal between the read signal voltage time and the read reset voltage time.

8. The pixel of claim 5, wherein, During the memory cell reset phase, the third control signal and the seventh control signal are first-level signals, and the fourth control signal and the fifth control signal change from second-level signals to first-level signals at a first preset time during the memory cell reset phase. The second control signal, the first control signal, the eighth control signal, and the sixth control signal are all second-level signals. During the photosensitive unit reset phase, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are all second-level signals, and the second control signal, the first control signal, and the seventh control signal are all first-level signals. During the exposure stage, the third control signal, the fourth control signal, the fifth control signal, the first control signal, and the sixth control signal are second-level signals, while the second control signal, the eighth control signal, and the seventh control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second-level signals, and the eighth control signal and the seventh control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, read the reset voltage; After the frame header time phase and after the first control signal changes to the second level signal, read the signal voltage.

9. The pixel of claim 5, wherein, During the memory cell reset phase, the third control signal, the seventh control signal, and the sixth control signal are first level signals. The fourth control signal and the fifth control signal change from second level signals to first level signals at a first preset time during the memory cell reset phase. The second control signal, the first control signal, and the eighth control signal are second level signals. During the photosensitive unit reset phase, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second-level signals, and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first-level signals. During the exposure stage, the third control signal, the fourth control signal, the fifth control signal, and the first control signal are second-level signals, while the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. During the frame header time phase, the third control signal, the fourth control signal, the fifth control signal, and the second control signal are second-level signals, while the eighth control signal, the seventh control signal, and the sixth control signal are first-level signals. The first control signal changes from a second-level signal to a first-level signal at a second preset time during the frame header time phase. During the frame header time phase and when the first control signal is a second-level signal, read the reset voltage; After the frame header time phase and after the first control signal changes to the second level signal, read the signal voltage.

10. The pixel of any one of claims 5 to 9, wherein, The first switching unit includes: A first transistor; a first terminal of the first transistor is connected to the memory cell, and a second terminal of the first transistor is connected to the input terminal of the second switching unit and the output unit; the first transistor is controlled by the sixth control signal.

11. The pixel of any one of claims 5 to 9, wherein, The second switching unit includes: The second transistor; the first terminal of the second transistor is connected to the input terminal of the amplification unit, the second terminal of the second transistor is connected to the input terminals of the first switching unit and the output unit, and the second transistor is controlled by the seventh control signal.

12. The pixel of claim 1, wherein, The photosensitive unit includes: A photodiode; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the transmission unit.

13. The pixel of claim 5, wherein, The transmission unit includes: The third transistor; the first terminal of the third transistor is connected to the photosensitive unit, the second terminal of the third transistor is connected to the input terminal of the amplification unit, and the third transistor is controlled by the first control signal.

14. The pixel of claim 5, wherein, The reset unit includes: The fourth transistor; the first terminal of the fourth transistor is connected to the input terminal of the amplification unit, the second terminal of the fourth transistor is connected to the power supply, and the fourth transistor is controlled by the second control signal.

15. The pixel of claim 5, wherein, The amplification unit includes: The fifth transistor and the sixth transistor; the first terminal of the fifth transistor is connected to the second terminal of the sixth transistor and serves as the output terminal of the amplification unit, the second terminal of the fifth transistor is connected to the power supply, the third terminal of the fifth transistor serves as the input terminal of the amplification unit, the first terminal of the sixth transistor is grounded, and the sixth transistor is controlled by the third control signal.

16. The pixel of claim 5, wherein, The third switching unit includes: A seventh transistor; the first terminal of the seventh transistor is connected to the output terminal of the amplification unit, the second terminal of the seventh transistor is connected to one end of the first capacitor and one end of the fourth switching unit, and the seventh transistor is controlled by the fourth control signal.

17. The pixel of claim 5, wherein, The fourth switching unit includes: The eighth transistor; the first terminal of the eighth transistor is connected to the third switching unit, the second terminal of the eighth transistor is connected to one end of the second capacitor and the first switching unit, and the eighth transistor is controlled by the fifth control signal.

18. The pixel of claim 5, wherein, The output unit includes: The ninth transistor and the tenth transistor; the first terminal of the ninth transistor is connected to the second terminal of the tenth transistor, the second terminal of the ninth transistor is connected to the power supply, the third terminal of the ninth transistor serves as the input terminal of the output unit, the first terminal of the tenth transistor serves as the output terminal of the output unit, and the tenth transistor is controlled by the eighth control signal.

19. An image sensor, comprising: Includes the pixels as described in any one of claims 1 to 18.

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