Information processing method and apparatus

Abstract

An information processing method and apparatus. A first LDPC base matrix can be divided into two types of G×G sub-matrices, and each G×G sub-matrix has a row weight of no greater than 1 and a column weight of no greater than 1, so that hardware implementation complexity is low, and under the same hardware, a longer code length can be supported. In addition, a first region of the first LDPC base matrix comprises a second type of sub-matrices of at least two element arrangement patterns, so that interleaving can be implemented, thereby supporting long codes. In addition, the first region of the first LDPC base matrix comprises a second type of sub-matrices of one element arrangement pattern, so that gains in terms of decoding parallelism can be provided.

Description

An information processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411623894.X, filed on November 13, 2024, entitled "An Information Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more specifically, to an information processing method and apparatus. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used coding schemes. LDPC codes are a channel coding scheme very close to Shannon lines, featuring good performance and low complexity. LDPC codes have been adopted by the 3rd Generation Partnership Project (3GPP) as a data channel coding scheme.

[0004] Current LDPC performs poorly with low iteration counts. Summary of the Invention

[0005] Embodiments of this application provide an information processing method and apparatus to improve the performance of LDPC codes.

[0006] In a first aspect, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (such as modem chips (also known as baseband chips), or system-on-chip (SoC) chips or system-in-package (SIP) chips containing modem cores)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or network device.

[0007] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to a first LDPC base matrix to output a codeword sequence, wherein the first LDPC base matrix includes multiple G×G sub-matrices, the multiple G×G sub-matrices include first-type sub-matrices and second-type sub-matrices, the elements of the first-type sub-matrices are all 0, the row weight of each row of the second-type sub-matrices is 1 and the column weight of each column is 1, the second-type sub-matrices have multiple element arrangements, the first region of the first LDPC base matrix includes second-type sub-matrices with at least two of the multiple element arrangements, the second region of the first LDPC base matrix includes second-type sub-matrices with at most one of the multiple element arrangements, and G is an integer greater than or equal to 2.

[0008] In the above method, the first LDPC base matrix can be divided into two types of G×G submatrices, with each G×G submatrix having a row weight of no more than 1 and a column weight of no more than 1. This reduces hardware implementation complexity and allows for longer code lengths to be supported with the same hardware. Furthermore, the first region of the first LDPC base matrix includes a second type of submatrix with at least two element arrangements, enabling interleaving and thus supporting long codes. Additionally, the first region of the first LDPC base matrix includes a second type of submatrix with only one element arrangement, which provides a gain in decoding parallelism.

[0009] In conjunction with the first aspect, in one possible implementation, G is 2 or 3.

[0010] In conjunction with the first aspect or any of its implementations, in another possible implementation, the translation values ​​corresponding to the non-zero elements at different positions of the second type of submatrix are the same. This implementation is relatively simple.

[0011] In conjunction with the first aspect or any implementation thereof, in another possible implementation, one of the second type of submatrices corresponds to one translation value in the translation value list. Compared to one non-zero element corresponding to one translation value, this implementation can reduce the size of the stored translation value matrix or list. Furthermore, based on this implementation, existing NR translation value matrices or lists can be reused.

[0012] In conjunction with the first aspect or any implementation thereof, in another possible implementation, the first LDPC basis matrix is ​​obtained by extending the second LDPC basis matrix, wherein the first type of submatrix is ​​obtained by extending the zero elements of the second LDPC basis matrix, and the second type of submatrix is ​​obtained by extending the non-zero elements of the second LDPC basis matrix. Compared to encoding using the second LDPC basis matrix, this implementation can obtain a larger first LDPC basis matrix. Encoding based on a larger-scale first LDPC basis matrix helps improve the performance of LDPC codes with low iteration counts.

[0013] In conjunction with the first aspect or any implementation thereof, in another possible implementation, the ratio of the total number of rows in the first region to the total number of rows in the first LDPC base matrix is ​​less than or equal to a first value, the first value including 1 / 4, 1 / 3 or 1 / 2; and / or, the ratio of the total number of columns in the first region to the total number of columns in the first LDPC base matrix is ​​less than or equal to a second value, the second value including 1 / 4, 1 / 3 or 1 / 2.

[0014] In conjunction with the first aspect or any implementation thereof, in another possible implementation, the first region includes X rows and / or Y columns of the first LDPC base matrix, wherein the minimum row weight in the X rows is greater than or equal to the maximum row weight of the rows other than the X rows of the first LDPC base matrix, and the minimum column weight in the Y columns is greater than or equal to the maximum column weight of the columns other than the Y columns of the first LDPC base matrix, and the second region includes part or all of the region of the first LDPC base matrix other than the first region, where X and Y are positive integers.

[0015] In conjunction with the first aspect or any of its implementations, in another possible implementation, the value of X includes 2, 3, 4, 6, 8, 9, 10 or 12; and / or, the value of Y includes 2, 3, 4, 6, 8, 9 or 12, or, the Y column is a punched column.

[0016] In conjunction with the first aspect or any implementation thereof, in another possible implementation, in the second region, adjacent W rows are pairwise orthogonal, or rows with different remainders modulo W are pairwise orthogonal, where W is an integer greater than 1; and / or, in the second region, adjacent R columns are pairwise orthogonal, or columns with different remainders modulo R are pairwise orthogonal, where R is an integer greater than 1. Based on this implementation, the decoding parallelism of LDPC codes can be improved.

[0017] In conjunction with the first aspect or any of its implementations, in another possible implementation, W is 2 or 3; and / or, R is 2 or 3.

[0018] Secondly, embodiments of this application provide an information processing method that can be applied to a decoding side, such as a decoding device, a module within the decoding device (e.g., a circuit, chip, or chip system (such as a modem chip, or a SoC chip or SIP chip containing a modem core)), or a logical node, logical module, or software capable of implementing all or part of the decoding device. The decoding device can be a network device or a terminal. This second aspect corresponds to the decoding side of the first aspect. Terms or features identical to those in the second aspect or implementations of the first aspect can be referenced to the first aspect or its implementations. The technical effects of the second aspect can be referenced to the first aspect or its implementations, and will not be repeated here.

[0019] The method includes: acquiring information to be decoded; decoding the information according to a first LDPC base matrix to obtain a decoded bit sequence, wherein the first LDPC base matrix includes multiple G×G submatrices, the multiple G×G submatrices include first-type submatrices and second-type submatrices, the elements of the first-type submatrices are all 0, the row weight of each row of the second-type submatrices is 1 and the column weight of each column is 1, the second-type submatrices have multiple element arrangements, a first region of the first LDPC base matrix includes second-type submatrices with at least two of the multiple element arrangements, a second region of the first LDPC base matrix includes second-type submatrices with at most one of the multiple element arrangements, and G is an integer greater than or equal to 2.

[0020] In conjunction with the second aspect, in one possible implementation, G is 2 or 3.

[0021] In conjunction with the second aspect or any of its implementations, in another possible implementation, the translation values ​​corresponding to the non-zero elements at different positions of the second type of submatrix are the same.

[0022] In conjunction with the second aspect or any of its implementations, in another possible implementation, a submatrix of the second type corresponds to a translation value in the list of translation values.

[0023] In conjunction with the second aspect or any of its implementations, in another possible implementation, the first LDPC basis matrix is ​​obtained by extending the second LDPC basis matrix, wherein the first submatrix is ​​obtained by extending the zero elements of the second LDPC basis matrix, and the second submatrix is ​​obtained by extending the non-zero elements of the second LDPC basis matrix.

[0024] In conjunction with the second aspect or any of its implementations, in another possible implementation, the ratio of the total number of rows in the first region to the total number of rows in the first LDPC base matrix is ​​less than or equal to a first value, the first value including 1 / 4, 1 / 3 or 1 / 2; and / or, the ratio of the total number of columns in the first region to the total number of columns in the first LDPC base matrix is ​​less than or equal to a second value, the second value including 1 / 4, 1 / 3 or 1 / 2.

[0025] In conjunction with the second aspect or any of its implementations, in another possible implementation, the first region includes X rows and / or Y columns of the first LDPC base matrix, wherein the minimum row weight in the X rows is greater than or equal to the maximum row weight of the rows other than the X rows of the first LDPC base matrix, and the minimum column weight in the Y columns is greater than or equal to the maximum column weight of the columns other than the Y columns of the first LDPC base matrix. The second region includes part or all of the region of the first LDPC base matrix other than the first region, and X and Y are positive integers.

[0026] In conjunction with the second aspect or any of its implementations, in another possible implementation, the value of X includes 2, 3, 4, 6, 8, 9, 10 or 12; and / or, the value of Y includes 2, 3, 4, 6, 8, 9 or 12, or, the Y column is a punched column.

[0027] In conjunction with the second aspect or any of its implementations, in another possible implementation, in the second region, adjacent W rows are pairwise orthogonal, or rows with different remainders modulo W are pairwise orthogonal, where W is an integer greater than 1; and / or, in the second region, adjacent R columns are pairwise orthogonal, or columns with different remainders modulo R are pairwise orthogonal, where R is an integer greater than 1.

[0028] In conjunction with the second aspect or any of its implementations, in another possible implementation, W is 2 or 3; and / or, R is 2 or 3.

[0029] Thirdly, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (such as modem chips, or SoC chips or SIP chips containing modem cores)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or a network device.

[0030] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to a first LDPC basis matrix to output a codeword sequence, wherein the first LDPC basis matrix includes multiple 2×2 sub-matrices, and the 2×2 sub-matrices are... or The first region of the first LDPC basis matrix includes and The second region of the first LDPC basis matrix includes or At most one of them.

[0031] Fourthly, embodiments of this application provide an information processing method that can be applied to a decoding side, such as a decoding device, a module (e.g., a circuit, chip, or chip system (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core) within the decoding device, or a logical node, logical module, or software that can implement all or part of the decoding device. The decoding device can be a network device or a terminal.

[0032] The method includes: acquiring information to be decoded; decoding the information according to a first LDPC basis matrix to obtain a decoded bit sequence, wherein the first LDPC basis matrix includes multiple 2×2 sub-matrices, and the 2×2 sub-matrices are... or The first region of the first LDPC basis matrix includes and The second region of the first LDPC basis matrix includes or At most one of them.

[0033] Fifthly, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (such as modem chips, or SoC chips or SIP chips containing modem cores)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or network device.

[0034] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to a first LDPC basis matrix to output a codeword sequence, wherein the first LDPC basis matrix includes multiple 3×3 sub-matrices, and the 3×3 sub-matrices are... or The first region of the first LDPC basis matrix includes or At least two of them, the second region of the first LDPC basis matrix includes or At most one of them.

[0035] Sixthly, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (e.g., modem chips, also known as baseband chips, or system-on-chip (SoC) chips containing modem cores or system-in-package (SIP) chips)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or network device.

[0036] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to a first LDPC basis matrix to output a codeword sequence, wherein the first LDPC basis matrix includes multiple 3×3 sub-matrices, and the 3×3 sub-matrices are... or The first region of the first LDPC basis matrix includes or At least two of them, the second region of the first LDPC basis matrix includes or At most one of them.

[0037] The steps performed by the encoding device in the third and fifth aspects can refer to the first aspect or its implementation. The steps performed by the decoding device in the fourth and sixth aspects can refer to the second aspect or its implementation. Terms or features in the third, fourth, fifth, and sixth aspects that are the same as those in the first aspect, its implementation, the second aspect, or its implementation can refer to the first aspect, its implementation, the second aspect, or its implementation. The technical effects of the third, fourth, fifth, and sixth aspects can refer to the technical effects in the first aspect, its implementation, the second aspect, or its implementation, and will not be repeated here.

[0038] Seventhly, embodiments of this application provide a communication device that has the function of implementing any of the above aspects or any possible implementation methods. For example, the communication device includes modules, units, or means corresponding to the operations involved in performing any of the above aspects or any possible implementation methods. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0039] Eighthly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in any of the above aspects or any possible implementations thereof. The one or more processors are executable to carry out the computer program or instructions, causing the communication device to implement the methods in any of the above aspects or any possible implementations thereof. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0040] In one possible implementation, the processor is used to communicate with other devices or components through the interface circuit.

[0041] In one possible implementation, the communication device may also include the memory.

[0042] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0043] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0044] Ninthly, embodiments of this application provide a communication system including at least one of the encoding or decoding devices described above.

[0045] In a tenth aspect, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause the computer to perform any of the above aspects or any possible implementation thereof.

[0046] Eleventhly, embodiments of this application provide a computer program product that, when read and executed by a computer, causes the computer to perform any of the above-described aspects or any possible implementation thereof.

[0047] In a twelfth aspect, embodiments of this application provide a computer program that, when run on a computer, causes the methods provided in any of the foregoing aspects or any possible implementation thereof to be executed. Attached Figure Description

[0048] Figure 1 is a schematic diagram of a network architecture applicable to embodiments of this application.

[0049] Figure 2 is a schematic diagram of the information transmission process applicable to an embodiment of this application.

[0050] Figure 3 is the Tanner plot of the parity-check matrix H.

[0051] Figure 4 shows the fifth generation (5) th A schematic diagram of the matrix structure of the base graph of the LDPC code (generation, 5G).

[0052] Figure 5 is a schematic diagram of 5G LDPC code.

[0053] Figure 6 is a schematic flowchart of the information processing method 600 provided in this application.

[0054] Figure 7 is a schematic diagram of an encoding chain provided in an embodiment of this application.

[0055] Figure 8 is an example of the first and second regions.

[0056] Figure 9 is an example of a first LDPC basis matrix according to an embodiment of this application.

[0057] Figure 10 is an example of a submatrix of the translation value matrix in an embodiment of this application.

[0058] Figure 11 is another example of a submatrix of the translation value matrix in an embodiment of this application.

[0059] Figure 12 shows the performance simulation results (I) of the NR base graph (BG)1 and the LDPC base matrix of this application.

[0060] Figure 13 shows the performance simulation results (II) of NR BG1 and the LDPC basis matrix of this application.

[0061] Figure 14 is a schematic diagram of a device provided in an embodiment of this application.

[0062] Figure 15 is another structural schematic diagram of the device provided in an embodiment of this application.

[0063] Figure 16 is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0064] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0065] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the NR protocol, and related protocols applied to future communication systems; this application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as (another) example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as an "example" in this application should not be construed as being better or more advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, R and / or U can mean: R alone, R and U simultaneously, or U alone, where R and U can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "OR" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element S sending messages, information, or data to network element T, and network element T receiving messages, information, or data from network element S, aim to specify which network element the message, information, or data is to be sent to, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective circumstances, not that there is a time limit, nor that the device must perform a judgment action during implementation, nor do they imply any other limitations.

[0066] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0067] The following describes a communication system to which embodiments of this application can be applied.

[0068] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0069] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminals. Optionally, both the transmitting device and the receiving device may be network devices.

[0070] In this application, the transmitting device can be understood as a data or information transmitting device, or an encoding device. The receiving device can be understood as a data or information receiving device, or a decoding device. The following description uses the terms encoding device and decoding device to describe the scheme of this application.

[0071] For example, Figure 1 shows a schematic diagram of a network architecture to which embodiments of this application may be applied.

[0072] Figure 1 illustrates a possible, non-limiting system diagram. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0073] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0074] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0075] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0076] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0077] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0078] In the embodiments of this application, the access network device may also be simply referred to as a network device.

[0079] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as D2D, V2X, MTC, IoT, virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication functions. The terminal can also be configured with program instructions for performing the corresponding communication functions.

[0080] Unless otherwise specified, the means for implementing the functions of a terminal or network device in this application can refer to the terminal or network device itself, or it can refer to a means that enables the terminal or network device to implement the function, such as a system-on-a-chip (SoC) or a chip, specifically a SoC or a modem. This means can be installed in the terminal or network device. In the embodiments of this application, the SoC can be composed of chips, or it can include chips and other discrete devices.

[0081] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0082] Figure 2 is a schematic diagram of the information transmission process according to an embodiment of this application. As shown in Figure 2, information is sent from a source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and other processing, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 2 (including source coding, channel coding, and modulation) is performed on the coding side, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed on the decoding side.

[0083] The embodiments of this application can be implemented in hardware, such as through a dedicated chip or a programmable chip, or by a processor executing software instructions, and mainly involve channel coding and channel decoding as shown in Figure 2. It should be noted that the embodiments of this application can be used for the channel decoding part, and the decoding method of the embodiments of this application is a general decoding means, effective for any coding scheme; therefore, the embodiments of this application do not limit the channel coding scheme.

[0084] Furthermore, the embodiments of this application can be applied to one or more specific application scenarios, or they can be general methods applicable to various application scenarios. Application scenarios may include peak rate scenarios, high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability low latency scenarios, or low power consumption scenarios, etc. High-throughput scenarios include enhanced mobile broadband (eMBB), eMBB+, extended-reality (XR), cloud gaming (CG), and augmented reality (AR). High-reliability and low-latency scenarios include ultra-reliable low-latency communication (URLLC) and hyper-reliable low-latency communication (HRLLC). Low-power scenarios include M2M, MTC, massive MTC (mMTC), IoT, narrowband Internet of Things (NB-IoT), advanced Internet of Things (A-IoT), and low-power wide-area (LPWA).

[0085] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0086] 1. LDPC code

[0087] LDPC codes are linear block codes with sparse parity-check matrices. The proportion of non-zero elements in the parity-check matrix of an LDPC code is extremely small; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with K information bits and a code length of N, its parity-check matrix H has dimensions (NK) × N, and the corresponding codeword c can be defined by the parity-check matrix H as: c = {c|Hc} T =0, c∈{0,1} N}

[0088] .

[0089] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and the NK parity-check equations correspond to the NK parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0090] Where v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0091] LDPC codes can be represented using graphical models, such as Tanner graphs, factor graphs, and tree graphs, with Tanner graphs offering the most concise and intuitive representation. The Tanner graph of the parity-check matrix H is shown in Figure 3. The degree in Figure 3 corresponds to the definition of degree in the parity-check matrix H, where the degree of a node is defined as the number of edges connected to it. In a Tanner graph, a cycle is defined as a structure that starts from a vertex, follows non-repeating edges, passes through non-repeating vertices, and eventually returns to the starting point. Since a Tanner graph is bipartite, the length of its cycles can only be an even number greater than 2, such as 4, 6, or 8. Short cycles are detrimental to LDPC codes, primarily in two ways: short cycles form trap sets, significantly impacting the code distance; and short cycles introduce correlations into the confidence propagation decoding algorithm, leading to inaccurate mutual information estimation. Therefore, short cycles should be avoided as much as possible in the design of LDPC codes.

[0092] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0093] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes.

[0094] QC-LDPC codes are represented using BG (Browser Group). Elements in BG are either 0 or 1, and a 1 in BG can be extended to Z. C ×Z C The cyclic displacement matrix BG, where 0 can be extended to Z C ×Z C The zero matrix is ​​expanded to obtain the parity matrix. Where Z... C Z is the lifting size. C It can also be referred to as boost size, expansion factor, boost value, expansion coefficient, or boost dimension, etc. Z C It can also be denoted as Z. The BG model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F represents the edge relationships. The boosted value is Z. C After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is the edge relationship between the variable node and the check node, corresponding to the number of columns in the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E| = Z. c |F|.

[0095] BG can also be expressed in matrix form, denoted as H. BG Based on the basis matrix H BG And the boost value Zc, which can transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. The lifting process involves... BG The element in the middle is promoted to a Z. C ×Z C A square matrix, where 0 is promoted to Z. C ×Z C A 0 matrix, promote the 1s to an identity matrix by cyclic shifting P (to the right). i,j The matrix, where P i,j This represents the shifting value (SV) corresponding to the i-th row and j-th column. Let Z be the shifting value. C The results of a cyclic shift of 4, -1, 0, 1, 2, 3 are shown below:

[0096] 3. Base map of 5G LDPC code

[0097] The base map of 5G LDPC code includes BG1 and BG2, which share a common matrix structure.

[0098] Figure 4 is a schematic diagram of the matrix structure of the 5G LDPC code base map. The 5G LDPC code base map can be divided into five regions: A, B, C, D, and E. Region A is the high-rate region, corresponding to the high-rate information columns. Region B is the core check region, corresponding to the high-rate. Region C is an all-zero region, a zero matrix. Region D is the incremental redundancy region, corresponding to the low-rate. Region E is a diagonal region (e.g., a raptor-like region), possessing an identity matrix structure.

[0099] The elements of the base graph take values ​​of 0 or 1, where a value of 0 represents an empty element or a zero element, and a value of 1 represents an edge present at that position in the base graph or an association between the corresponding check node and the variable node.

[0100] In 5G LDPC codes, the protocol specifies the storage of the largest base map. In practical applications, different matrix regions are selected based on the code rate. Specifically, rows 1 to M0 and columns 1 to N0 are selected. As the code rate decreases, M0 and N0 gradually increase, and the area of ​​the matrix used also gradually expands. For example, the dashed boxes in Figure 5 that contain high code rate regions correspond to different code rates.

[0101] The base map of 5G LDPC code has a nested characteristic, meaning that low code rate regions contain high code rate regions.

[0102] The 5G LDPC code stores the following information regarding shift values: 1. A list of boost values; 2. A list of shift values ​​that corresponds one-to-one with each row of the boost value list. Table 1 shows an example of a boost value list.

[0103] Table 1

[0104] The main characteristic of a list of promoted values ​​is that the j-th row of the list... Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}.

[0105] Table 2 is a list of edge connections and translation values ​​for a certain part of BG1, where the first two columns correspond to the basis matrix of that part, and the last eight columns correspond to the translation values ​​of that part.

[0106] Table 2

[0107] The row indices of the lift value list correspond one-to-one with the column indices of the shift values. That is, each row of the lift value list corresponds to a set of shift values, and multiple lift values ​​share the same set of shift values. For example, in Table 2, the set index i... LS The boost values ​​{2, 4, 8, 16, 32, 64, 128, 256} that equal 0 correspond to the shift values ​​{250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0}. During code rate matching, 5G LDPC first determines the boost values ​​and then selects the corresponding shift values ​​to construct the parity check matrix.

[0108] It should be noted that, in the embodiments of this application, the base matrix can refer to a matrix with elements of 0 or 1, wherein elements represented as 0 can be replaced by a Z*Z all-zero matrix, and elements represented as 1 can be replaced by a Z*Z cyclic permutation matrix, as shown in the first two columns of Table 2.

[0109] It should also be noted that the embodiments of this application are described based on code length, information length, and code rate, and these terms are explained here. Information length refers to the number of information bits to be transmitted. These information bits may or may not include cyclic redundancy check (CRC) bits, and are not limited thereto. Code length refers to the length of the (to be) transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol. Code rate refers to the ratio of the number of information bits to the number of transmitted bits. Code length, information length, and code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, and can also be directly obtained and calculated by the transceiver. More specifically, code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0110] The relevant terms used in the embodiments of this application have been described above, and will not be explained further below.

[0111] Current LDPC code exhibits poor performance with low iteration counts. To address this issue, this application provides an information processing method and apparatus to improve the performance of LDPC codes.

[0112] The method embodiments of this application are described below with reference to the accompanying drawings.

[0113] Figure 6 is a schematic flowchart of the information processing method 600 provided in this application.

[0114] It is understood that this application uses encoding and decoding devices as examples to illustrate the execution of the interaction, but this application does not limit the execution entities of the interaction. For example, the method executed by the encoding device in this application can also be implemented by modules in the encoding device, or by logic nodes, logic modules, or software that can implement all or part of the functions of the encoding device; similarly, the method executed by the decoding device in this application can also be implemented by modules in the decoding device, or by logic nodes, logic modules, or software that can implement all or part of the functions of the decoding device. Modules in the encoding device and / or decoding device can be, for example, circuits, chips, or chip systems (such as modem chips, or SoC chips or SIP chips containing modem cores, etc.). The encoding device can be a terminal device or a network device, and the decoding device can be a network device or a terminal device.

[0115] Method 600 may include at least a portion of the following.

[0116] Step 601: The encoding device acquires the information bit sequence.

[0117] In other words, if the encoding device needs to communicate with the decoding device, that is, if the encoding device needs to send a signal to the decoding device, the encoding device needs to first obtain the information bit sequence corresponding to the signal to be sent to the decoding device.

[0118] The phrase "the encoding device acquires the information bit sequence" can refer to: the encoding device performing source encoding on source symbols to generate the information bit sequence. Alternatively, it can refer to: the encoding device receiving the information bit sequence from other communication devices.

[0119] Step 602: The encoding device encodes the information bit sequence according to the first LDPC base matrix and outputs the codeword sequence.

[0120] In one implementation, the encoding device selects a first LDPC base matrix and a boost value based on at least one of the target code length, target code rate, or application scenario. Then, it determines the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix based on the first LDPC base matrix and the boost value. Next, based on the boost value and the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix, it expands the first LDPC base matrix into a parity-check matrix. Finally, it uses the expanded parity-check matrix to encode the information bit sequence to obtain a codeword sequence. One implementation where the encoding device selects the first LDPC base matrix based on information such as the target code length, target code rate, and application scenario involves the encoding device selecting a portion or all of the matrix region from the largest stored base matrix based on at least one of the target code length, target code rate, and application scenario.

[0121] For example, Figure 7 is a schematic diagram of an encoding chain provided in an embodiment of this application. The encoding chain in Figure 7 includes: given a target code length, a target code rate, and an application scenario; selecting a first LDPC base matrix and a boost value according to the target code length, target code rate, and application scenario; determining a translation value corresponding to the first LDPC base matrix according to the first LDPC base matrix and the boost value; and completing the encoding according to the first LDPC base matrix, the boost value, and the translation value.

[0122] In step 603, the encoding device sends a symbol sequence to the decoding device based on the codeword sequence. Correspondingly, the decoding device receives the symbol sequence from the encoding device.

[0123] The symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the encoding device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain the symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0124] Understandably, since channel noise signals may be introduced during the transmission of the symbol sequence, the symbol sequence sent by the encoding device and the symbol sequence received by the decoding device may be different.

[0125] Step 604: The decoding device decodes the information to be decoded according to the first LDPC basis matrix to obtain the information bit sequence.

[0126] For example, the information to be decoded can be a sequence of symbols.

[0127] For example, the information to be decoded can also be based on information obtained from a symbol sequence. In other words, the decoding device can process the received symbol sequence to obtain the information to be decoded. For instance, the information to be decoded can be information obtained after demodulation of the symbol sequence. As another example, the information to be decoded can be information obtained after demodulation and distribution matching processing.

[0128] In some implementations, the decoding device can select a first LDPC base matrix and a boost value based on at least one of the target code length, target code rate, or application scenario. Then, based on the first LDPC base matrix and boost value, it determines the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix. Next, based on the boost value and the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix, it expands the first LDPC base matrix into a parity check matrix. Finally, it uses the expanded parity check matrix to decode the information to be decoded, obtaining the information bit sequence. One implementation where the decoding device selects the first LDPC base matrix based on information such as the target code length, target code rate, and application scenario involves the decoding device selecting a portion or all of the matrix region from the largest stored base matrix, based on at least one of the target code length, target code rate, and application scenario.

[0129] In embodiments of this application, the first LDPC basis matrix may include multiple G×G submatrices, where G is an integer greater than or equal to 2. The first LDPC basis matrix may consist of multiple G×G submatrices, meaning the number of rows and columns of the first LDPC basis matrix are both integer multiples of G; the first LDPC basis matrix may also further include regions beyond the multiple G×G submatrices, without limitation. It should be understood that the first LDPC basis matrix may include multiple G×G submatrices, or it can be described as: part or all of the region of the first LDPC basis matrix can be divided into multiple G×G submatrices.

[0130] This involves multiple G×G submatrices, including first-type and second-type submatrices, both of size G×G. The first-type submatrices contain all zeros. The second-type submatrices have a row weight of 1 and a column weight of 1, and can have multiple element arrangements. This multiple element arrangement can also be described as: the elements of the second-type submatrices have multiple permutations.

[0131] Taking G=2 as an example, the first type of submatrix is: The second type of submatrix includes two element arrangement methods. Specifically, the second type of submatrix includes... and

[0132] Taking G as 3 as an example, the first type of submatrix is: The second type of submatrix includes six possible element arrangements. Specifically, the second type of submatrix includes... or

[0133] In embodiments of this application, the first region of the first LDPC base matrix includes second-type submatrices with at least two element arrangements, and the second region of the first LDPC base matrix includes second-type submatrices with at most one element arrangement. Alternatively, the second-type submatrices in the first region of the first LDPC base matrix have at least two element arrangements, and the second-type submatrices in the second region of the first LDPC base matrix have at most one element arrangement. The first region and / or the second region may or may not include the first-type submatrices; this is not limited.

[0134] In method 600, the first LDPC base matrix can be divided into two types of G×G submatrices, with each G×G submatrix having a row weight of no more than 1 and a column weight of no more than 1. This reduces hardware implementation complexity and allows for longer code lengths with the same hardware. Furthermore, the first region of the first LDPC base matrix includes a second type of submatrix with at least two element arrangements, enabling interleaving and thus supporting long codes. Additionally, the first region of the first LDPC base matrix includes a second type of submatrix with only one element arrangement, providing a gain in decoding parallelism.

[0135] The embodiments of this application do not limit the way the first region and the second region are divided.

[0136] In some implementations, the first region includes the X rows and / or Y columns of the first LDPC base matrix, and the second region includes part or all of the region outside the first region of the first LDPC base matrix. Wherein, the minimum row weight in the X rows is greater than or equal to the maximum row weight of the rows outside the X rows of the first LDPC base matrix, the minimum column weight in the Y columns is greater than or equal to the maximum column weight of the columns outside the Y columns of the first LDPC base matrix, and X and Y are positive integers.

[0137] For example, the first region consists of the X rows with the largest row weight in the first LDPC base matrix, and the second region consists of some or all of the rows other than the X rows in the first LDPC base matrix. The value of X includes 2, 3, 4, 6, 8, 9, 10 or 12.

[0138] For example, the first region consists of the X row with the largest row weight in the first LDPC base matrix and several other rows, while the second region consists of some or all of the rows outside the first region of the first LDPC base matrix, and the value of X includes 8 or 12.

[0139] For example, the first region is composed of the Y column with the largest column weight in the first LDPC base matrix, and the second region is composed of some or all of the columns other than the Y column in the first LDPC base matrix. The value of Y includes 2, 3, 4, 6, 8, 9 or 12.

[0140] For example, the first region consists of column Y, which has the largest column weight in the first LDPC base matrix, and several other columns. The second region consists of some or all of the columns outside the first region of the first LDPC base matrix. The value of Y includes 4 or 6.

[0141] For example, the first region is composed of the punched columns of the first LDPC base matrix, and the second region is composed of some or all of the columns other than the punched columns of the first LDPC base matrix.

[0142] Figure 8 shows an example of the first and second regions. As shown in Figure 8, the first region consists of the punched columns of the first LDPC base matrix, and the second region is all the regions other than the first region (the white part in the figure). The second region is not shown in the figure.

[0143] In some implementations, the ratio of the total number of rows in the first region to the total number of rows in the first LDPC base matrix is ​​less than or equal to a first value, and / or the ratio of the total number of columns in the first region to the total number of columns in the first LDPC base matrix is ​​less than or equal to a second value. In other words, the matrix region containing fewer than or equal to the first value in terms of row count and / or fewer than or equal to the second value includes a second type of submatrix with at least two element permutations.

[0144] For example, the first value may include at least one of 1 / 4, 1 / 3, or 1 / 2. And / or, the second value may include at least one of 1 / 4, 1 / 3, or 1 / 2.

[0145] In the embodiments of this application, in the second region, adjacent rows W are pairwise orthogonal, or rows with different remainders modulo W are pairwise orthogonal, where W is an integer greater than 1. And / or, in the second region, adjacent columns R are pairwise orthogonal, or columns with different remainders modulo R are pairwise orthogonal, where R is an integer greater than 1. Here, row A and row B are orthogonal, which can be understood as: the set of positions of non-zero elements in row A and row B have no intersection. For example, row A is (0, 1, 0, 1), row B is {1, 0, 0, 0}, the set of positions of non-zero elements in row A is {column 2, column 4}, and the set of positions of non-zero elements in row B is {column 1}. {column 2, column 4} and {column 1} have no intersection. Similarly, column C and column D are orthogonal, which can be understood as: the set of positions of non-zero elements in column C and column D have no intersection.

[0146] For example, in the second region, adjacent W rows are orthogonal to each other.

[0147] For example, W=2, meaning that adjacent rows in the second region are orthogonal.

[0148] For example, W=3, which means that in the second region, three adjacent rows are orthogonal to each other.

[0149] For example, in the second region, rows with different remainders modulo W are paired orthogonal. Here, the remainder modulo W represents the remainder when divided by W, such as the remainder of 1 modulo 3 being 1, and the remainder of 6 modulo 3 being 0.

[0150] For example, W = 2, meaning that any odd-numbered row in the second region is orthogonal to any even-numbered row.

[0151] For example, W=3, which means that the two rows corresponding to any row numbers with different remainders modulo 3 in the second region are orthogonal.

[0152] For example, in the second region, adjacent R columns are orthogonal to each other.

[0153] For example, R=2, meaning that adjacent columns in the second region are orthogonal.

[0154] For example, R=3, which means that in the second region, three adjacent columns are orthogonal to each other.

[0155] For example, in the second region, the columns corresponding to columns with different remainders modulo R are pairwise orthogonal. Here, the remainder modulo R represents the remainder when divided by R, such as the remainder of 1 modulo 3 being 1, and the remainder of 6 modulo 3 being 0.

[0156] For example, R = 2, meaning that any odd-numbered column in the second region is orthogonal to any even-numbered column.

[0157] For example, R=3, which means that in the second region, the two columns corresponding to column numbers with different remainders modulo 3 are orthogonal.

[0158] For example, in the second region, adjacent rows W are orthogonal to each other, and adjacent columns R are orthogonal to each other.

[0159] For example, W = R = 2, which means that in the second region, adjacent rows are orthogonal and adjacent columns are orthogonal.

[0160] For example, W = R = 3, which means that in the second region, three adjacent rows are pairwise orthogonal and three adjacent columns are pairwise orthogonal.

[0161] For example, in the second region, rows with different remainders modulo W are pairwise orthogonal, and columns with different remainders modulo R are pairwise orthogonal.

[0162] For example, W = R = 2, meaning that in the second region, any odd row is orthogonal to any even row, and any odd column is orthogonal to any even column.

[0163] For example, W = R = 3, which means that in the second region, the two rows corresponding to any row numbers with different remainders modulo 3 are orthogonal, and the two columns corresponding to any column numbers with different remainders modulo 3 are orthogonal.

[0164] In some implementations, the total number of rows with orthogonality in the second region is greater than one-third of the number of rows in the second region.

[0165] Steps 602 and 604 above describe one method for obtaining the first LDPC base matrix: selecting a portion or all of the matrix region from the largest stored base matrix based on at least one of the target code length, target code rate, and application scenario. In another implementation, the first LDPC base matrix can also be obtained by expanding the second LDPC base matrix. It should be noted that the steps or operations after obtaining the first LDPC base matrix are described in steps 602 and 604 and will not be detailed further. It should also be noted that in this implementation, the largest stored LDPC base matrix can be expanded first, and then the expanded LDPC base matrix can be selected or truncated to obtain the first LDPC base matrix, where the second LDPC base matrix is ​​a portion or all of the largest LDPC base matrix, and the first LDPC base matrix corresponds to the second LDPC base matrix; alternatively, the second LDPC base matrix can be selected or truncated from the largest stored LDPC base matrix, and then the second LDPC base matrix can be expanded to obtain the first LDPC base matrix; there is no limitation on this approach.

[0166] In some implementations, the second LDPC basis matrix can be the NR LDPC basis matrix. It should be understood that the NR LDPC basis matrix is ​​an NR-related LDPC basis matrix, which can be the LDPC basis matrix in the NR protocol, or the LDPC basis matrix mentioned in the discussion of the NR protocol. The NR protocol can be any version of the protocol, without restriction.

[0167] The embodiments of this application are not limited to the implementation of extending the second LDPC base matrix into the first LDPC base matrix.

[0168] In some implementations, the first type of submatrix in the first LDPC basis matrix is ​​obtained by expanding the zero elements in the second LDPC basis matrix, and the second type of submatrix in the first LDPC basis matrix is ​​obtained by expanding the non-zero elements in the second LDPC basis matrix. In other words, the zero elements in the second LDPC basis matrix are expanded to obtain the first type of submatrix in the first LDPC basis matrix, and the non-zero elements in the second LDPC basis matrix are expanded to obtain the second type of submatrix in the first LDPC basis matrix.

[0169] Taking G=2 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. Elements in BG are either 0 or 1. The 1s in BG are expanded into a 2×2 matrix. In a 2×2 matrix, the elements on the diagonal are either 0 or the elements on the anti-diagonal are 0. That is, the 1s in BG are expanded to... or Expand the zeros in BG into a 2×2 zero matrix, i.e. After expansion, we get BG0. In the first region of BG0, there are two types of 2×2 matrices corresponding to the 1s in BG: and In the second region of BG0, the 2×2 matrix corresponding to 1 in BG is: and At most one of them.

[0170] Taking G as 3 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. Elements in BG are either 0 or 1. The 1s in BG are then extended to... or Expand the zeros in BG into a 3x3 zero matrix, that is After expansion, we obtain matrix BG0. In the first region of BG0, the 3x3 matrix corresponding to the 1 in BG has at least two of the six types mentioned above, such as 2 or 3 types. In the second region of BG0, the 3x3 matrix corresponding to the 1 in BG has at most one of the six types mentioned above, such as 0 or 1 type. It should be understood that in the second region of BG0, the 3x3 matrix corresponding to the 1 in BG has 0 of the six types mentioned above; that is, the second region of BG0 does not include the second type of submatrix.

[0171] Figure 9 is an example of a first LDPC basis matrix according to an embodiment of this application. Figure 9 uses an example where G is 2, the first region is the first two columns, and the second region is all regions other than the first region. As shown in Figure 9, the first region of the first LDPC basis matrix includes... and Three types of 2×2 matrices, the second region of the first LDPC basis matrix includes and Two types of 2×2 matrices.

[0172] The embodiments of this application do not limit the method of obtaining the translation values ​​corresponding to the non-zero elements of the second type of submatrix.

[0173] One way to obtain translation values ​​is to retrieve the translation values ​​corresponding to the non-zero elements of the second type of submatrix from a translation value list, where each translation value in the list corresponds to a second type of submatrix. In this case, the translation values ​​corresponding to the non-zero elements at different positions in the second type of submatrix are the same. For example, the translation value list can be an NR translation value list. It should be understood that the NR translation value list is an NR-related translation value list, which can be a translation value list in the NR protocol, or a translation value list mentioned during the discussion of the NR protocol. The NR protocol can be any version of the protocol and is not limited thereto. The translation value list can also be a translation value matrix.

[0174] For example, the translation values ​​corresponding to the non-zero elements at different positions of the second type of submatrix are all the first translation values. The first translation value is the translation value corresponding to the first non-zero element of another LDPC basis matrix, which is obtained by looking up a list of translation values. The first LDPC basis matrix is ​​different from the other LDPC basis matrix. For example, the other LDPC basis matrix can be the second LDPC basis matrix described above. That is, the translation values ​​corresponding to the non-zero elements of the second type of submatrix of the first LDPC basis matrix are the translation values ​​corresponding to that position in the second LDPC basis matrix before expansion.

[0175] Taking G as 2 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. For the 2×2 matrix in BG0 corresponding to the 1 in BG, that is... or The same cyclic displacement matrix is ​​selected within the same 2×2 matrix, meaning the same translation value is selected.

[0176] Taking G as 3 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. For the 3×3 matrix in BG0 corresponding to the 1 in BG, that is... or The same cyclic displacement matrix is ​​selected within the same 3×3 matrix, that is, the same translation value is selected.

[0177] Figure 10 is an example of a submatrix of the translation value matrix according to an embodiment of this application. Figure 10 uses G as an example of 2. "-1" in Figure 10 corresponds to a zero element. The translation values ​​in Figure 10 are taken from the NR translation value list, and Zc is 384. As shown in Figure 10, the translation values ​​corresponding to non-zero elements at different positions in each second-type submatrix are the same; for example, the translation value corresponding to the non-zero elements in the first second-type submatrix is ​​307.

[0178] Another way to obtain the translation values ​​is to retrieve the translation values ​​corresponding to the non-zero elements of the second type of submatrix from the translation value list, where each translation value in the translation value matrix corresponds to a non-zero element in the first LDPC basis matrix. In this case, the translation values ​​corresponding to the non-zero elements at different positions in the second type of submatrix can be the same or different.

[0179] In this application, if the third LDPC basis matrix or the translation value matrix corresponding to the third LDPC basis matrix can be obtained by performing a first transformation on the first LDPC basis matrix or the translation value matrix corresponding to the first LDPC basis matrix provided in the embodiments of this application, then the third LDPC basis matrix or the translation value matrix corresponding to the third LDPC basis matrix is ​​considered to be included within the protection scope of this application. The first transformation includes at least one of the following operations: row permutation, column permutation, or translation value transformation. Row permutation may include permuting one or more rows. Column permutation may include permuting one or more columns. Translation value transformation may include simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more rows, and / or simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more columns.

[0180] In other words, the third LDPC basis matrix can be obtained from the first LDPC basis matrix through a first transformation, the shift matrix corresponding to the third LDPC basis matrix can be obtained from the shift matrix corresponding to the first LDPC basis matrix through a first transformation, and the third LDPC parity check matrix can be obtained from the first LDPC parity check matrix through a first transformation. Therefore, "encode the information bit sequence according to the first LDPC basis matrix and output a codeword sequence" can be replaced with "encode the information bit sequence according to the third LDPC basis matrix and output a codeword sequence," and / or, "decode the information to be decoded according to the first LDPC basis matrix to obtain an information bit sequence" can be replaced with "decode the information to be decoded according to the third LDPC basis matrix to obtain an information bit sequence."

[0181] In other words, the first LDPC base matrix or the translation value matrix corresponding to the first LDPC base matrix can be modified to its equivalent or equivalent form. The equivalent or equivalent translation value matrix to the first LDPC base matrix or the translation value matrix corresponding to the first LDPC base matrix differs from the LDPC base matrix or LDPC translation value matrix provided in the embodiments of this application in that the row order is different, and / or the column order is different, and / or the translation values ​​of one or more rows are shifted, and / or the translation values ​​of one or more columns are shifted. Taking the shift value shift as an example, the translation value matrix shown in Figure 10 can be replaced with the translation value matrix shown in Figure 11. Compared to the translation value matrix in Figure 10, the translation value of the non-zero elements in the last row of the translation value matrix shown in Figure 11 is shifted by 1.

[0182] The performance of the LDPC code provided in the embodiments of this application is described below based on simulation results.

[0183] Figure 12 shows the performance simulation results (I) of NR BG1 and the LDPC basis matrix of this application.

[0184] Figure 12 shows the simulation results of LDPC codes obtained using the Min-sum decoding algorithm with 20 iterations. The horizontal axis represents the number of rows in the LDPC basis matrix used. The information length K = 2² * 2 * 384 = 16896, the code length N = (20 + number of rows) * 2 * 384, and the code rate = 2² / (20 + number of rows). In Figure 12, the code rates range from 11 / 12 to 2 / 3 depending on the number of rows, from 4 to 13. The vertical axis represents the signal-to-noise ratio (SNR) corresponding to a block error ratio (BLER) of 1e⁻². A lower value on the vertical axis indicates better performance.

[0185] Curve 1 represents the curve with an information length K = 16896, a basis matrix of NR BG1, and a lift value of 384*2 = 768. Its corresponding translation matrix is ​​obtained through a random search based on NR BG1 and the lift value. This randomly searched translation matrix is ​​generally considered optimal, and therefore it is used as the baseline here.

[0186] Curve 2 is the simulation performance curve of the LDPC code of the embodiment of this application, with a corresponding information length K = 16896. The first expansion is based on NR BG1, and the second expansion uses the translation value corresponding to the boost value of 384 in NR.

[0187] As can be seen from curves 1 and 2, the LDPC code of the embodiments of this application has similar performance at various code rates to the performance of the translation value matrix of random search.

[0188] Figure 13 shows the performance simulation results (II) of NR BG1 and the LDPC basis matrix of this application.

[0189] Figure 13 is the curve obtained by subtracting the corresponding positions of curve 2 and curve 1 in Figure 12. A value less than 0 on the vertical axis indicates that the LDPC code of the embodiment of this application has a performance gain. As shown in Figure 13, the LDPC code of the embodiment of this application has a performance gain when the code rate is less than 22 / 25.

[0190] The method embodiments provided by this application have been described in detail above with reference to Figures 1 to 13. The apparatus embodiments of this application will be described below with reference to Figures 14 to 16.

[0191] It is understood that, in order to achieve the functions in the above embodiments, the apparatuses in Figures 14 to 16 include hardware structures and / or software modules corresponding to perform each function. These apparatuses can be used to implement the functions of the encoding or decoding devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0192] Figure 14 is a schematic diagram of a device provided in an embodiment of this application.

[0193] This application embodiment can divide the encoding or decoding device into functional units according to the above method examples. For example, each function can be divided into different functional units, or two or more functions can be integrated into one unit. Each function can be implemented in hardware or as a software functional module. It should be noted that the division shown in Figure 14 is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0194] As shown in Figure 14, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0195] When device 10 is used to implement the function of the encoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the encoding device, such as step 603, and processing unit 12 is used to execute the processing steps 601 and 602 of the encoding device. When device 10 is used to implement the function of the decoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the decoding device, such as step 603, and processing unit 12 is used to execute the processing steps of the decoding device, such as step 604.

[0196] Optionally, the device 10 also includes a storage unit 13 for storing instructions and / or data.

[0197] For a more detailed description of the transceiver unit 11 and the processing unit 12, please refer to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0198] Figure 15 is another structural schematic diagram of the device provided in an embodiment of this application.

[0199] The device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, which stores instructions. When the device 20 is used to implement the method described above, the processing circuit 21 executes the instructions in the memory 23 to implement the function of the processing unit 12 described above.

[0200] Optionally, the device 20 further includes a memory 23 for implementing the functions of the aforementioned storage unit 13.

[0201] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 can be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 executes instructions to implement the function of the processing unit 12, and the transceiver circuit 22 implements the function of the transceiver unit 11.

[0202] Optionally, device 20 can be an encoding device or a decoding device, and correspondingly, the transceiver circuit can be a transceiver.

[0203] Optionally, the device 20 can be a chip used in encoding or decoding equipment, and correspondingly, the transceiver circuit can be an input / output interface.

[0204] For example, when device 20 is a chip applied to an encoding or decoding device, the chip implements the functions of the encoding or decoding device in the above method embodiments. The chip receives information from other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to the encoding or decoding device by other devices; or, the chip sends information to other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to other devices by the encoding or decoding device.

[0205] Figure 16 is a schematic diagram of a chip system provided in an embodiment of this application. The chip system 30 (or may also be called a processing system) includes logic circuitry 31 and an input / output interface 32.

[0206] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 30 to implement the methods and functions of the embodiments of this application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting processed information from the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0207] As an alternative, the chip system 30 may also include a memory unit.

[0208] As one approach, the chip system 30 is used to implement the operations performed by the encoding or decoding device in the various method embodiments described above.

[0209] For example, logic circuit 31 is used to implement processing-related operations performed by the encoding or decoding device in the above method embodiments; input / output interface 32 is used to implement sending and / or receiving-related operations performed by the encoding or decoding device in the above method embodiments.

[0210] This application also provides a communication device including a processing circuit coupled to a memory for storing computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or to read the data stored in the memory, to perform the methods in the above-described method embodiments. Optionally, the processing circuit may be one or more. Optionally, the communication device includes a memory. Optionally, the memory may be one or more. Optionally, the memory may be integrated with the processing circuit, or may be separately disposed.

[0211] This application also provides a chip including a processing circuit coupled to a memory. The memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the encoding or decoding device in the above-described method embodiments. The memory may be located within the chip or independently of the chip, located outside the chip; this is not limited thereto.

[0212] This application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by an encoding or decoding device in the above-described method embodiments.

[0213] This application also provides a computer program product comprising instructions which, when executed by a computer, implement the methods performed by an encoding or decoding device in the above-described method embodiments.

[0214] This application also provides a computer program that, when executed by a computer, implements the methods performed by the encoding or decoding device in the above-described method embodiments.

[0215] This application also provides a communication system that includes at least one of the encoding or decoding devices described in the above embodiments.

[0216] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0217] It is understood that the processing circuit in the embodiments of this application may be a processor or a circuit in a processor for performing processing operations. The processor may include one or more of the following: a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0218] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored in non-volatile memory, such as the aforementioned memory 23 or at least a portion of the storage cells (e.g., one or more of ROM, flash memory, EPROM, or hard disk).

[0219] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Furthermore, the ASIC can reside in an encoding or decoding device. Alternatively, the processor and storage medium can exist as discrete components in the encoding or decoding device.

[0220] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive.

[0221] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0222] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

Claims

1. An information processing method characterized by comprising: The method includes: Obtain the information bit sequence; The information bit sequence is encoded according to the first LDPC base matrix to output a codeword sequence. The first LDPC base matrix includes multiple G×G submatrices, which include first-type submatrices and second-type submatrices. The elements of the first-type submatrices are all 0. The row weight of each row and the column weight of each column of the second-type submatrices are 1. The second-type submatrices have multiple element arrangements. The first region of the first LDPC base matrix includes second-type submatrices with at least two of the multiple element arrangements. The second region of the first LDPC base matrix includes second-type submatrices with at most one of the multiple element arrangements. G is an integer greater than or equal to 2.

2. The method of claim 1, wherein, G is 2 or 3.

3. The method according to claim 1 or 2, characterized in that, The translation values ​​corresponding to the non-zero elements at different positions in the second type of submatrix are the same.

4. The method according to claim 3, characterized in that, A submatrix of the second type corresponds to a translation value in the list of translation values.

5. The method according to any one of claims 1 to 4, characterized in that, The first LDPC basis matrix is ​​obtained by extending the second LDPC basis matrix, wherein the first submatrix is ​​obtained by extending the zero elements of the second LDPC basis matrix, and the second submatrix is ​​obtained by extending the non-zero elements of the second LDPC basis matrix.

6. The method according to any one of claims 1 to 5, characterized in that, The ratio of the total number of rows in the first region to the total number of rows in the first LDPC base matrix is ​​less than or equal to a first value, which includes 1 / 4, 1 / 3, or 1 / 2; and / or, the ratio of the total number of columns in the first region to the total number of columns in the first LDPC base matrix is ​​less than or equal to a second value, which includes 1 / 4, 1 / 3, or 1 / 2.

7. The method according to any one of claims 1 to 6, characterized in that, The first region includes the X rows and / or Y columns of the first LDPC base matrix, wherein the minimum row weight in the X rows is greater than or equal to the maximum row weight of the rows other than the X rows of the first LDPC base matrix, and the minimum column weight in the Y columns is greater than or equal to the maximum column weight of the columns other than the Y columns of the first LDPC base matrix. The second region includes part or all of the region of the first LDPC base matrix other than the first region, where X and Y are positive integers.

8. The method according to claim 7, characterized in that, The value of X includes 2, 3, 4, 6, 8, 9, 10, or 12; and / or, The value of Y includes 2, 3, 4, 6, 8, 9 or 12, or the Y column is a punched column.

9. The method according to any one of claims 1 to 8, characterized in that, In the second region, adjacent rows W are pairwise orthogonal, or rows with different remainders modulo W are pairwise orthogonal, where W is an integer greater than 1; and / or, In the second region, adjacent R columns are orthogonal to each other, or columns with different remainders modulo R are orthogonal to each other, where R is an integer greater than 1.

10. The method according to claim 9, characterized in that, W is 2 or 3; and / or, R is 2 or 3.

11. An information processing method characterized by comprising: The method includes: Obtain the information to be decoded; The information is decoded based on the first LDPC base matrix to obtain a decoded bit sequence. The first LDPC base matrix includes multiple G×G submatrices, which include first-type submatrices and second-type submatrices. The elements of the first-type submatrices are all 0. The row weight of each row and the column weight of each column of the second-type submatrices are 1. The second-type submatrices have multiple element arrangements. The first region of the first LDPC base matrix includes second-type submatrices with at least two of the multiple element arrangements. The second region of the first LDPC base matrix includes second-type submatrices with at most one of the multiple element arrangements. G is an integer greater than or equal to 2.

12. The method of claim 11, wherein, G is 2 or 3.

13. The method according to claim 11 or 12, characterized in that, The translation values ​​corresponding to the non-zero elements at different positions in the second type of submatrix are the same.

14. The method according to claim 13, characterized in that, A submatrix of the second type corresponds to a translation value in the list of translation values.

15. The method according to any one of claims 11 to 14, characterized in that, The first LDPC basis matrix is ​​obtained by extending the second LDPC basis matrix, wherein the first submatrix is ​​obtained by extending the zero elements of the second LDPC basis matrix, and the second submatrix is ​​obtained by extending the non-zero elements of the second LDPC basis matrix.

16. The method according to any one of claims 11 to 15, characterized in that, The ratio of the total number of rows in the first region to the total number of rows in the first LDPC basis matrix is ​​less than or equal to a first value, where the first value includes 1 / 4, 1 / 3, or 1 / 2; and / or, The ratio of the total number of columns in the first region to the total number of columns in the first LDPC base matrix is ​​less than or equal to a second value, which includes 1 / 4, 1 / 3, or 1 / 2.

17. The method according to any one of claims 11 to 16, characterized in that, The first region includes the X rows and / or Y columns of the first LDPC base matrix, wherein the minimum row weight in the X rows is greater than or equal to the maximum row weight of the rows other than the X rows of the first LDPC base matrix, and the minimum column weight in the Y columns is greater than or equal to the maximum column weight of the columns other than the Y columns of the first LDPC base matrix. The second region includes part or all of the region of the first LDPC base matrix other than the first region, where X and Y are positive integers.

18. The method according to claim 17, characterized in that, The value of X includes 2, 3, 4, 6, 8, 9, 10, or 12; and / or, The value of Y includes 2, 3, 4, 6, 8, 9 or 12, or the Y column is a punched column.

19. The method according to any one of claims 11 to 18, characterized in that, In the second region, adjacent rows W are pairwise orthogonal, or rows with different remainders modulo W are pairwise orthogonal, where W is an integer greater than 1; and / or, In the second region, adjacent R columns are orthogonal to each other, or columns with different remainders modulo R are orthogonal to each other, where R is an integer greater than 1.

20. The method according to claim 19, characterized in that, W is 2 or 3; and / or, R is 2 or 3.

21. A communications device, characterized by Includes modules or units for performing the method as described in any one of claims 1 to 20.

22. A communications device, characterized by The device includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, and the processor is used to implement the method as described in any one of claims 1 to 20 through logic circuits or execution code instructions.

23. The communication apparatus according to claim 22, wherein, The communication device is a terminal device, network device, chip, or chip system.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1 to 20.

25. A computer program product, characterised in that, Includes a computer program that, when run, implements the method as described in any one of claims 1 to 20.

26. A communication system, characterized by include: An encoding device for performing the method as described in any one of claims 1 to 10, and a decoding device for performing the method as described in any one of claims 11 to 20.

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