Photodetection element and electronic device

Abstract

[Problem] To provide a photodetection element capable of reliably detecting an event and appropriately resetting a threshold. [Solution] This photodetection element comprises: a plurality of pixels each including a light receiving unit that photoelectrically converts incident light and generates an electric signal, and a detection circuit that compares a first signal corresponding to the electric signal with a threshold voltage and outputs an event signal, the plurality of pixels being two-dimensionally arranged in a first direction and a second direction; a first decoder that outputs, to a pixel unit, a first selection signal for selecting a row composed of the plurality of pixels arranged in the first direction; and a second decoder that outputs, to the pixel unit, a second selection signal for selecting a column composed of the plurality of pixels arranged in the second direction. The detection circuits that have output the event signals are reset according to the outputting of the event signals, and the detection circuits of the plurality of pixels are periodically reset, and, in a periodic reset operation, at least one of the first and second decoders randomly selects a row or a column by the first or second selection signal.

Description

Photodetector and Electronic Device

[0001] The present disclosure relates to a photodetector and an electronic device.

[0002] A photodetector that detects an event signal in real time when the light amount of a pixel exceeds a threshold has been developed. A photodetector that detects such an event signal is called an EVS (Event-based Vision Sensor).

[0003] U.S. Patent Application Publication No. 2023 / 0047774

[0004] After detecting an event, the EVS resets pixel circuits such as an AFE (Analog Front End). If the light amount changes during the reset period, the threshold for detecting an event is set at an inappropriate position. In this case, the EVS cannot detect an event appropriately.

[0005] Therefore, the present disclosure provides a photodetector and an electronic device that can surely detect an event of an object and can appropriately set a threshold for detecting the event.

[0006] The photodetector according to one aspect of the present disclosure includes a light receiving unit that photoelectrically converts incident light to generate an electrical signal, and a detection circuit that compares a first signal corresponding to the electrical signal with a threshold voltage and outputs an event signal when the first signal exceeds or falls below the threshold voltage. The plurality of pixels are two-dimensionally arranged in a first direction and a second direction intersecting the first direction, and a first decoder that outputs a first selection signal for selecting a row composed of a plurality of pixels arranged in the first direction to the pixel unit, and a second decoder that outputs a second selection signal for selecting a column composed of a plurality of pixels arranged in the second direction to the pixel unit. The detection circuit that outputs an event signal is reset in response to the output of the event signal, and the detection circuits of the plurality of pixels are periodically reset. In the periodic reset operation, at least one of the first or second decoders randomly selects a row or a column by the first or second selection signal.

[0007] During the periodic reset operation, the first and second decoders randomly select both rows and columns using the first and second selection signals.

[0008] During a periodic reset operation, the first decoder randomly selects rows by row using a first selection signal, or during a periodic reset operation, the second decoder randomly selects columns by column using a second selection signal.

[0009] Each of the multiple detection circuits includes a comparator having a first input section that receives a first signal, a second input section that receives a threshold voltage, and an output section that outputs an event signal when the first signal exceeds or falls below the threshold voltage; a first switching element connected between the first input section and the output section; and a logic circuit that outputs an enable signal that causes the first switching element to conduct when an event signal is output or when both the first and second selection signals are activated.

[0010] The logic circuit includes an AND operation circuit that receives first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and an event signal and outputs an enable signal.

[0011] The photodetector further comprises a signal generator that outputs a second signal whose voltage changes over time, and each of the plurality of detection circuits further comprises a second switching element connected between the signal generator and the control unit of the first switching element.

[0012] The second switching element becomes conductive in response to the second signal, and then gradually becomes non-conductive in an analog manner.

[0013] During a periodic reset operation, the first and second decoders randomly select multiple pixels using the first and second selection signals, and the detection circuit for the selected pixels is reset by making the first switching element conduct.

[0014] During a periodic reset operation, the first decoder randomly selects a row by a first selection signal, and the detection circuit for the selected row is reset by making the first switching element conduct.

[0015] When an event signal is output, the detection circuit that output the event signal is reset individually, and in the case of a periodic reset operation, all of the multiple pixels are reset periodically.

[0016] An electronic device according to one aspect of the present disclosure includes a plurality of pixels, each comprising: a light receiving unit that converts incident light into electrical signals by photoelectric conversion; and a detection circuit that compares a first signal corresponding to the electrical signal with a threshold voltage and outputs an event signal when the first signal exceeds or falls below the threshold voltage, wherein the plurality of pixels are arranged two-dimensionally in a first direction and a second direction intersecting the first direction; a first decoder that outputs a first selection signal to a pixel unit for selecting a row consisting of the plurality of pixels arranged in the first direction; and a second decoder that outputs a second selection signal to a pixel unit for selecting a column consisting of the plurality of pixels arranged in the second direction, wherein the detection circuit that outputs the event signal is reset according to the output of the event signal, the detection circuit of the plurality of pixels is reset periodically, and in the periodic reset operation, at least one of the first or second decoder has a photodetector element that randomly selects a row or column according to the first or second selection signal.

[0017] During the periodic reset operation, the first and second decoders randomly select both rows and columns using the first and second selection signals.

[0018] During a periodic reset operation, the first decoder randomly selects rows by row using a first selection signal, or during a periodic reset operation, the second decoder randomly selects columns by column using a second selection signal.

[0019] Each of the multiple detection circuits includes a comparator having a first input section that receives a first signal, a second input section that receives a threshold voltage, and an output section that outputs an event signal when the first signal exceeds or falls below the threshold voltage; a first switching element connected between the first input section and the output section; and a logic circuit that outputs an enable signal that causes the first switching element to conduct when an event signal is output or when both the first and second selection signals are activated.

[0020] The logic circuit includes an AND operation circuit that receives first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and an event signal and outputs an enable signal.

[0021] The photodetector further comprises a signal generator that outputs a second signal whose voltage changes over time, and each of the plurality of detection circuits further comprises a second switching element connected between the signal generator and the control unit of the first switching element.

[0022] The second switching element becomes conductive in response to the second signal, and then gradually becomes non-conductive in an analog manner.

[0023] During a periodic reset operation, the first and second decoders randomly select multiple pixels using the first and second selection signals, and the detection circuit for the selected pixels is reset by making the first switching element conduct.

[0024] During a periodic reset operation, the first decoder randomly selects a row by a first selection signal, and the detection circuit for the selected row is reset by making the first switching element conduct.

[0025] When an event signal is output, the detection circuit that output the event signal is reset individually, and in the case of a periodic reset operation, all of the multiple pixels are reset periodically.

[0026] A block diagram showing an example configuration of a photodetector element according to the first embodiment. A diagram showing an example of the stacked structure of a solid-state image sensor according to the first embodiment. An example of a plan view of a light-receiving chip. An example of a plan view of a pixel array. An example of a plan view of a detection chip. An example of a plan view of a detection unit. A block diagram showing an example of the configuration of an event detection circuit. A block diagram showing an example configuration of a detection unit, a row decoder, a column decoder, and a DAC. A circuit diagram showing an example configuration of an event detection circuit. A timing diagram showing the reset operation when an event is detected. A timing diagram showing a periodic reset operation. A conceptual diagram showing a periodic forced reset operation according to the first embodiment. A diagram showing event detection when an object falls in synchronization with the reset. A conceptual diagram showing a periodic forced reset operation according to a comparative example. A diagram showing event detection when an object falls in synchronization with the reset in the comparative example. A conceptual diagram showing a periodic forced reset operation according to the second embodiment. A diagram showing event detection when an object falls in synchronization with the reset in the second embodiment. A block diagram showing an example configuration of a detection chip, a row decoder, and a DAC according to the second embodiment. An explanatory diagram of the reset operation when an event is detected. An explanatory diagram of the reset operation when an event is detected. Diagram illustrating the reset operation upon event detection. Diagram illustrating the forced event operation. Block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology relating to this disclosure may be applied. Diagram showing an example of the installation position of the imaging unit.

[0027] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0028] (First Embodiment) Figure 1 is a block diagram showing an example configuration of a photodetector 1 according to the first embodiment. The photodetector 1 is, for example, an EVS or DVS (Dynamic Vision Sensor). The photodetector 1 comprises an imaging lens 10, a solid-state image sensor 20, a recording area 30, and a control unit 40. Examples of photodetector 1 include electronic devices such as cameras mounted on industrial robots, in-vehicle cameras, and surveillance cameras.

[0029] The imaging lens 10 focuses the incident light and guides it to the solid-state image sensor 20. The solid-state image sensor 20 converts the incident light into photoelectric power to generate a voltage signal corresponding to the amount of light received, and detects changes in the amount of light received as an event signal based on the voltage signal. The detected event signal is output to the recording area 30.

[0030] The recording area 30 records event signals from the solid-state image sensor 20. The recording area 30 may be, for example, a latch circuit, a DRAM (Dynamic Random Access Memory), or a semiconductor memory such as flash memory. The internal configuration of the recording area 30 will be described in more detail later.

[0031] The control unit 40 is composed of a microcomputer equipped with, for example, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM, etc., and controls the operation of the photodetector element 1 by having the CPU execute processing according to the program. In particular, the control unit 40 controls the solid-state image sensor 20 to perform the event signal detection operation described above, controls the recording area 30 to record the event signal, and executes processing to read the event signal from the recording area 30.

[0032] Figure 2 shows an example of a stacked structure of a solid-state image sensor 20 according to the first embodiment. The solid-state image sensor 20 comprises a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. In such a stacked structure, the light-receiving chip 201 and the detection chip 202 are electrically connected via a connection part such as a TSV (Through Silicon Via). In addition to vias, the light-receiving chip 201 and the detection chip 202 can also be connected by wiring connections (e.g., Cu-Cu connections) or bumps.

[0033] Figure 3 is an example of a plan view of the light-receiving chip 201. The light-receiving chip 201 is provided with a pixel array section 220 and via arrangement sections 211, 212, and 213. Vias connected to the detection chip 202 are arranged in the via arrangement sections 211, 212, and 213.

[0034] Figure 4 is an example of a plan view of the pixel array section 220. The pixel array section 220 has a plurality of light-receiving sections 221 arranged in a two-dimensional grid. The light-receiving sections 221 are, for example, photodiodes. The light-receiving sections 221 convert incident light into photoelectric current. Each light-receiving section 221 is assigned a pixel address consisting of a row address and a column address.

[0035] Figure 5 is an example of a plan view of the detection chip 202. The detection chip 202 is provided with via arrangement sections 231, 232, and 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, and a detection unit 260. Vias connected to the light receiving chip 201 are arranged in the via arrangement sections 231, 232, and 233.

[0036] The row drive circuit 251 includes a row decoder RD that selects a pixel row according to the row address of the pixel array unit 220, and outputs the photocurrent from the selected pixel row to the detection unit 260. The column drive circuit 252 includes a column decoder CD that selects a pixel column according to the column address of the pixel array unit 220, and outputs the photocurrent from the selected pixel column to the detection unit 260.

[0037] The detection unit 260 detects an event signal by quantizing the voltage signal (first signal) obtained by logarithmically transforming the input photocurrent (electrical signal), and outputs the detected event signal to the signal processing circuit 240. An event indicates that the voltage signal obtained by logarithmically transforming the photocurrent has exceeded or fallen below a predetermined threshold. The event signal is activated (for example, raised) when an event occurs. The event signal is a signal that has been quantized (binarized) by the quantizer 330. The signal processing circuit 240 performs predetermined signal processing on the event signal output from the detection unit 260 and outputs it to the recording area 30.

[0038] Figure 6 is an example of a plan view of the detection unit 260. Multiple event detection circuits 300 are arranged in a two-dimensional grid within the detection unit 260. Each event detection circuit 300 is assigned a pixel address and connected to a light receiving unit 221 with the same address. In other words, one light receiving unit 221 and one event detection circuit 300 constitute one pixel (PX in Figure 8) and can be selected by pixel address. The event detection circuit 300 quantizes a voltage signal corresponding to the photocurrent from the corresponding light receiving unit 221 and outputs it as an event signal.

[0039] Figure 7 is a block diagram showing an example of the configuration of the event detection circuit 300. The event detection circuit 300 includes a logarithmic transformation circuit 310, a buffer 320, and a quantizer 330. The event detection circuit 300 compares the voltage signal generated by the light receiving unit 221 with a threshold, and outputs an event signal when the voltage signal exceeds or falls below the threshold.

[0040] The logarithmic conversion circuit 310 converts the photocurrent from the corresponding light receiving unit 221 into a logarithmically converted voltage signal. The logarithmic conversion circuit 310 supplies the converted voltage signal to the buffer 320.

[0041] The buffer 320 corrects the voltage signal from the logarithmic transformation circuit 310. The buffer 320 outputs the corrected voltage signal to the quantizer 330.

[0042] The quantizer 330 compares the input voltage signal with a predetermined threshold value and detects an event signal indicating that the voltage signal has exceeded or fallen below the threshold value. The quantizer 330 quantizes the voltage signal after the decrease into a digital signal and outputs it as an event signal to the recording area 30.

[0043] The control unit 40 performs operation control on the quantizer 330 and controls the reading of the detection signal recorded in the recording area 30. The control unit 40 can be configured by, for example, a computer.

[0044] FIG. 8 is a block diagram showing a configuration example of the detection chip 202, row decoder RD, column decoder CD, and DAC 50. The detection chip 202 is a so-called AFE (Analog Front End) and includes a plurality of event detection circuits 300 provided corresponding to each of the plurality of light receiving parts 221 of the pixel array part 220. The plurality of event detection circuits 300 are two-dimensionally arranged in a matrix within the X-Y plane. A plurality of pixels (light receiving part 221, event detection circuit 300) arranged in the X direction as the first direction are called "rows", and a plurality of pixels (light receiving part 221, event detection circuit 300) arranged in the Y direction as the second direction are called "columns". The X direction and the Y direction intersect (for example, are orthogonal) to each other.

[0045] The row decoder RD outputs a selection signal SEL_Y according to a row address that selects at least one row from the plurality of rows arranged in the Y direction. The selection signal SEL_Y selectively activates at least one row among the plurality of rows of the event detection circuit 300.

[0046] The column decoder CD outputs a selection signal SEL_X according to a column address that selects at least one column from the plurality of columns arranged in the X direction. The selection signal SEL_X selectively activates at least one column among the plurality of columns of the event detection circuit 300. Thereby, the event detection circuit 300 corresponding to the selected row and the selected column is activated.

[0047] Note that the row address and the column address are issued without depending on the normal event detection operation.

[0048] The DAC (Digital-to-Analog Converter) 50 is provided corresponding to a plurality of rows. Each DAC 50 supplies a reference signal Ramp to the event detection circuit 300 of the corresponding row. The DAC 50 is provided commonly for the plurality of event detection circuits 300 included in each row. Incidentally, the DAC 50 may be provided commonly for the entire detection unit 260. The reference signal Ramp is a signal whose voltage changes over time and is used for the reset operation of the event detection circuit 300.

[0049] FIG. 9 is a circuit diagram showing an example of the configuration of the event detection circuit 300. The logarithmic conversion circuit 310 includes N-type transistors 311 and 313 and a P-type transistor 312. As these transistors, for example, MOS (Metal-Oxide-Semiconductor) transistors are used.

[0050] The source of the N-type transistor 311 is connected to the cathode of the light receiving unit 221, and the drain is connected to the power supply line. The P-type transistor 312 and the N-type transistor 313 are connected in series between the power supply line and the ground. Also, the connection point of the P-type transistor 312 and the N-type transistor 313 is connected to the gate of the N-type transistor 311 and the input part of the buffer 320. Also, a predetermined bias voltage Vbias1 is applied to the gate of the P-type transistor 312.

[0051] The drains of the N-type transistors 311 and 313 are connected to the power supply side, and such a circuit is called a source follower. By these two source followers connected in a loop shape, the photocurrent from the light receiving unit 221 is converted into a voltage signal that has been logarithmically converted. Also, the P-type transistor 312 supplies a constant current to the N-type transistor 313.

[0052] By the above-described logarithmic conversion circuit 310, the light intensity received by the light receiving unit 221 is converted into a voltage signal that has been logarithmically converted.

[0053] Furthermore, the ground of the light-receiving chip 201 and the ground of the detection chip 202 are separated from each other to prevent interference. The light-receiving chip 201 is equipped with the light-receiving unit 221 and the N-type transistors 311 and 313 of the event detection circuit 300, while the detection chip 202 is equipped with the event detection circuit 300 other than the N-type transistors 311 and 313.

[0054] The quantizer 330 comprises a capacitor 331, a comparator 332, an OR operation circuit 333, an AND operation circuit 334, a logic circuit 335, and switching elements SW1 and SW2.

[0055] One end of capacitor 331 is connected to the output of buffer 320, and the other end is connected to the first input of comparator 332. Therefore, the output of buffer 320 is capacitively coupled to the first input of comparator 332. As a result, the voltage signal from buffer 320 is input to the first input of comparator 332. In other words, the pixel signal Vpx, which corresponds to the amount of light (luminance) detected by photoelectric conversion, is input to the first input of comparator 332. The threshold voltage Vth is input to the second input of comparator 332.

[0056] The comparator 332 compares the pixel signal Vpx input to the first input and the threshold voltage Vth input to the second input, and outputs an output signal S332 according to the detection result. The comparator 332 outputs an event signal Ve as output signal S332 from its output unit when the pixel signal Vpx exceeds or falls below the threshold voltage Vth. When an event occurs, the output signal S332 is activated as a high-level event signal Ve. The event signal Ve is a high-level signal of the output signal S332 that is output when the pixel signal Vpx exceeds or falls below the threshold voltage Vth, based on the voltage difference between the pixel signal Vpx and the threshold voltage Vth. The output signal S332 is output to the outside of the event detection circuit 300, so that the occurrence of an event due to the event signal Ve can be notified to the outside.

[0057] The comparator 332 is reset when the switching element SW1 becomes conductive (on). The reset operation connects the first input of the comparator 332 to its output. As a result, the voltage at the first input of the comparator 332 becomes equal to the output signal S332 (for example, the event signal Ve). Furthermore, the reset operation updates the threshold voltage Vth based on the output signal S332 of the comparator 332. For example, if the comparator 332 is reset when an event occurs, the threshold voltage Vth is updated based on the event signal Ve. The threshold voltage Vth is set to an upper limit of +Vt and a lower limit of -Vt relative to the voltage of the output signal S332 of the comparator 332 at the time of reset. ±Vt indicates the voltage range of the threshold voltage Vth and can be set arbitrarily. For example, when a reset operation is performed when an event occurs, the output signal S332 becomes the event signal Ve, and the threshold voltage Vth is set to an upper limit Ve + Vt and a lower limit Ve - Vt. Therefore, after the reset operation, when the pixel signal Vpx exceeds the upper limit Ve + Vt of the threshold voltage Vth, or when the pixel signal Vpx falls below the lower limit Ve - Vt of the threshold voltage Vth, the next event occurs. When an event occurs, the reset operation is performed again based on the new event signal Ve. In this embodiment, the reset operation is performed not only when an event occurs, but also periodically. A more detailed explanation of the reset operation will be given later.

[0058] One input of the OR arithmetic circuit 333 is connected to the output of the comparator 332, and the other input is connected to the output of the AND arithmetic circuit 334. The OR arithmetic circuit 333 performs an OR operation between the output signal S332 from the output of the comparator 332 and the output signal S334 from the output of the AND arithmetic circuit 334, and outputs the result of the operation as the output signal S333 from its output section. Therefore, the OR arithmetic circuit 333 is activated by raising the voltage of the output signal S333 of its output section to a high level at least when the output of the comparator 332 outputs an event signal Ve, or when the output of the AND arithmetic circuit 334 outputs a reset signal FAZ. The activation of the output signal S333 of the OR arithmetic circuit 333 is triggered by the logic circuit 335 outputting an enable signal LampEn.

[0059] One input of the AND operation circuit 334 is connected to the row decoder RD, and the other input is connected to the column decoder CD. The AND operation circuit 334 performs an AND operation amplifier with the selection signal SEL_Y from the row decoder RD and the selection signal SEL_X from the column decoder CD, and outputs the result of the operation as the output signal S334 from the output unit. The selection signal SEL_Y is a signal that selects a row of the pixel circuit of the detection chip 202 shown in Figure 8 according to the row address. The selection signal SEL_X is a signal that selects a column of the pixel circuit of the detection chip 202 shown in Figure 8 according to the column address.

[0060] During a periodic reset operation, when a certain pixel PX is selected, the row decoder RD and column decoder CD activate the selection signals SEL_Y and SEL_X corresponding to the selected pixel PX to a high level. In this case, the AND operation circuit 334 in the event detection circuit 300 of the selected pixel PX activates the output signal S334 to a high level and outputs the reset signal S334.

[0061] Thus, the output signal S333 of the OR operation circuit 333 is activated to a high level not only when the event signal Ve is output, but also when the reset signal FAZ is output.

[0062] The logic circuit 335 activates output signal S335 to a high level in response to the activation of output signal S333 and outputs an enable signal, LampEn. The enable signal, LampEn, turns on the switching element SW2. In other words, the AND operation circuit 334, the OR operation circuit 333, and the logic circuit 335 output the enable signal, LampEn, and perform a reset operation in both cases: when the event signal Ve is output, and when both selection signals SEL_Y and SEL_X are activated.

[0063] Switching element SW2 is connected between the gate (control unit) of switching element SW1 and DAC 50. Switching element SW2 turns on when it receives the enable signal LampEn. When switching element SW2 is turned on, DAC 50 is connected to the gate of switching element SW1. As a signal generator, DAC 50 is provided in common for multiple event detection circuits 300 included in a selected row, and supplies a reference signal Lamp as a second signal to the gates of switching element SW1 of the multiple event detection circuits 300. The reference signal Lamp is a signal whose voltage changes over time, for example, a signal that rises to a high level and then decreases linearly over time. By using the reference signal Lamp, switching element SW1 can be analogously and gradually switched from a conducting state (on) to a non-conducting state (off) over time.

[0064] The switching element SW1 is connected between the first input and output of the comparator 332. When the switching element SW1 is turned on, it short-circuits the first input and output of the comparator 332, resetting the comparator 332. While the comparator 332 is performing event detection operations, the switching element SW1 is in the off state.

[0065] During the reset operation, the switching element SW1 gradually changes analogously from on to off in response to the reference signal Ramp. This causes the switching element SW1 to slowly disconnect the first input and output of the comparator 332 over time, suppressing charge imbalance between the first input and output of the comparator 332. In other words, by controlling the switching element SW1 on / off using the reference signal Ramp, the switching element SW1 can disconnect the first input and output of the comparator 332 while maintaining approximately equal voltage.

[0066] Thus, the event detection circuit 300 according to this embodiment can perform a reset operation not only when an event occurs, but also periodically by activating the selection signals SEL_Y and SEL_X.

[0067] Figure 10 is a timing diagram showing the reset operation when an event is detected. When an event is detected, the comparator 332 activates by raising the output signal S332 and outputs the event signal Ve. As a result, the OR arithmetic circuit 333 raises the output signal S333, and the logic circuit 335 outputs the enable signal LampEn.

[0068] The DAC 50 continuously outputs a reference signal Ramp based on a clock signal (not shown). When the event signal Ve and the reset signal FAZ are not output, the logic circuit 335 keeps the output signal S335 inactive. In this case, the switching element SW2 remains in the off state, so the reference signal Ramp is not supplied to the switching element SW1.

[0069] On the other hand, when the event signal Ve is output, the logic circuit 335 activates the output signal S335 and outputs the enable signal RampEn. In this case, the switching element SW2 turns on, and the reference signal Ramp is supplied to the switching element SW1. If the reference signal Ramp supplied to the switching element SW1 is called the reference signal RampI, then the reference signal RampI is the reference signal Ramp that passes through when the enable signal RampEn is activated. For example, in t1 to t2, when the enable signal RampEn is activated, the reference signal Ramp passes through the switching element SW2 and is supplied to the switching element SW1 as the reference signal RampI.

[0070] The switching element SW1 is turned on in response to the reference signal RampI. For example, between t1 and t2, the switching element SW1 is turned on. As a result, after being turned on, the switching element SW1 is gradually turned off in an analog manner over time. That is, in the reset operation, the first input and output of the comparator 332 are connected and then gradually disconnected. In this way, the reset operation upon event detection is performed in response to the activation of the output signal S332 of the comparator 332 (output of the event signal Ve).

[0071] The reset operation upon event detection is selectively and individually performed on the event detection circuit 300 of the pixel PX where the event occurred. In this case, since the occurrence of events is irregular, it is impossible to predict when the reset operation will be performed.

[0072] Figure 11 is a timing diagram showing the periodic reset operation. The periodic reset operation is performed by activating the selection signals SEL_Y and SEL_X, regardless of the event. For example, at t10, when both selection signals SEL_Y and SEL_X are activated, the AND operation circuit 334 raises output signal S334 and outputs the reset signal FAZ. As a result, the OR operation circuit 333 raises output signal S333, and the logic circuit 335 outputs the enable signal LampEn.

[0073] When the event signal Ve and the reset signal FAZ are not output, the logic circuit 335 keeps the output signal S335 inactive. In this case, the switching element SW2 remains in the off state, so the reference signal Ramp is not supplied to the switching element SW1.

[0074] On the other hand, when the reset signal FAZ is output, the logic circuit 335 activates the output signal S335 and outputs the enable signal RampEn. In this case, the switching element SW2 is turned on, and the reference signal Ramp is supplied to the switching element SW1. Therefore, for example, when the enable signal RampEn is activated between t10 and t11, the reference signal Ramp passes through the switching element SW2 and is supplied to the switching element SW1 as the reference signal RampI.

[0075] The switching element SW1 is turned on in response to the reference signal RampI. For example, between t10 and t11, the switching element SW1 is turned on. As a result, after being turned on, the switching element SW1 is gradually turned off in an analog manner over time. That is, in the reset operation, the first input and output of the comparator 332 are connected and then gradually disconnected.

[0076] The periodic reset operation using the reset signal FAZ is forcibly performed by periodically issuing the reset signal FAZ, regardless of whether an event occurs. Therefore, the reset operation using the reset signal FAZ is also called a forced reset operation.

[0077] The forced reset operation is performed periodically on the event detection circuit 300 of all pixels PX in the pixel array section 220, regardless of whether an event occurs. In this case, the timing of the reset operation is known in advance.

[0078] In this embodiment, both an event-triggered reset operation and a periodic forced reset operation are performed.

[0079] Figure 12 is a conceptual diagram showing the periodic forced reset operation according to the first embodiment. R1 to R4 represent row addresses. C1 to C4 represent column addresses. The row decoder RD and column decoder CD can selectively access a specific pixel PX by outputting selection signals SEL_Y and SEL_X according to the row addresses R1 to R4 and column addresses C1 to C4, respectively. The numerical value mn displayed for each pixel PX in Figure 12 is a combination of the numerical value m of the row address Rm and the numerical value n of the column address Cn. For example, pixel "11" is a pixel that is selectively accessed by the row address R1 and column address C1. faz1 to faz4 written for each pixel PX indicate the reset order in one periodic forced reset operation. In this embodiment, reset faz1 to faz4 each reset the event detection circuit 300 of four pixels PX at once. However, there is no particular limit to the number of pixels that are reset at one time in each reset faz1 to faz4.

[0080] In this embodiment, during reset faz1, the row decoder RD and column decoder CD select pixels "31", "42", "23", and "34". As a result, during reset faz1, the event detection circuits 300 for the four pixels "31", "42", "23", and "34" are reset simultaneously.

[0081] In reset faz2, the row decoder RD and column decoder CD select pixels "41", "12", "43", and "24". As a result, in reset faz2, the event detection circuits 300 for the four pixels "41", "12", "43", and "24" are reset simultaneously.

[0082] In reset faz3, the row decoder RD and column decoder CD select pixels "21", "32", "33", and "14". As a result, in reset faz3, the event detection circuits 300 for the four pixels "21", "32", "33", and "14" are reset simultaneously.

[0083] In reset faz4, the row decoder RD and column decoder CD select pixels "11", "22", "13", and "44". As a result, in reset faz4, the event detection circuits 300 for the four pixels "11", "22", "13", and "44" are reset simultaneously.

[0084] This resets all of the pixels PX within the pixel array 220. The number of pixels PX, rows, and columns in the pixel array 220 are not particularly limited. This forced reset operation is repeated at arbitrary intervals.

[0085] In this embodiment, the periodic forced reset operation outputs selection signals SEL_Y and SEL_X according to randomly generated row addresses R1 to R4 and column addresses C1 to C4, thereby randomly selecting multiple pixels PX. The event detection circuit 300 of the selected pixel PX is reset by making the switching elements SW1 and SW2 conduct. The row decoder RD and column decoder CD may also reset pixels PX randomly, arbitrarily, or at random.

[0086] According to this embodiment, since the reset operation is performed randomly on multiple pixels PX, even if the movement of object B is synchronized with the reset operation, detection errors (so-called event missings) in which the photodetector 1 does not detect object B can be suppressed.

[0087] For example, Figure 13 shows the event detection when object B falls in the column C3 from R1 to R4 in synchronization with reset faz1 to faz4. In reset faz1, object B is at the position of pixel "13" corresponding to row address R1 and column address C3. When reset faz1 is executed, pixel "13" is not reset, so pixel "13" is capable of event detection of object B.

[0088] Similarly, in reset faz2, object B is located at pixel "23" corresponding to row address R2 and column address C3. Since pixels "23" are not reset when reset faz2 is executed, pixel "23" can detect object B as an event.

[0089] In reset faz3, object B is located at pixel "33" corresponding to row address R3 and column address C3. Since pixel "33" is reset when reset faz3 is executed, pixel "33" does not detect object B. In other words, in this case, event missing occurs.

[0090] In reset faz4, object B is located at pixel "43", which corresponds to row address R4 and column address C3. Since pixel "43" is not reset when reset faz4 is executed, pixel "43" is capable of detecting object B as an event.

[0091] Thus, even if object B falls in sync with the reset operation, an event missing occurs in one pixel "33," but object B can be detected as an event in the other pixels "13," "23," and "43." Therefore, the optical detection element 1 can suppress event missing as much as possible and detect object B as a whole. As a result, the optical detection element 1 according to this embodiment can reliably detect events of object B.

[0092] Figure 14 is a conceptual diagram showing the periodic forced reset operation in the comparative example. In the comparative example, resets faz1 to faz4 are executed for all column pixels PX in the order of row addresses R1 to R4. That is, resets faz1 to faz4 are executed by scanning row by row in row address order.

[0093] For example, Figure 15 shows the event detection in a comparative example when object B falls in the column C3 from R1 to R4 in synchronization with reset faz1 to faz4. In reset faz1, object B is at the position of pixel "13" corresponding to row address R1 and column address C3. When reset faz1 is executed, pixel "13" is reset, so pixel "13" does not detect object B.

[0094] Similarly, in reset faz2, object B is located at pixel "23" corresponding to row address R2 and column address C3. Since pixel "23" is reset when reset faz2 is executed, pixel "23" does not detect object B.

[0095] In reset faz3, object B is located at pixel "33" corresponding to row address R3 and column address C3. Since pixel "33" is reset when reset faz3 is executed, pixel "33" does not detect object B.

[0096] In reset faz4, object B is located at pixel "43", which corresponds to row address R4 and column address C3. Since pixel "43" is reset when reset faz4 is executed, pixel "43" does not detect object B.

[0097] Thus, when reset faz1 to faz4 are executed row by row in row address order, when the movement of object B falls in synchronization with the reset operation, all pixels "13", "23", "33", and "43" at column address C3 become insensitive, resulting in event missing. In this case, the photodetector as a whole cannot detect object B.

[0098] In contrast, in this embodiment, during a periodic forced reset operation, the row decoder RD and column decoder CD output selection signals SEL_Y and SEL_X according to randomly generated row addresses R1 to R4 and column addresses C1 to C4, thereby randomly selecting both the rows and columns of multiple pixels PX. As a result, the photodetector 1 can suppress event missing as much as possible and detect the target object B as a whole. Consequently, the photodetector 1 according to this embodiment can reliably detect events of the target object B.

[0099] Furthermore, since the light detection element 1 can select a reset position on a pixel PX basis, it becomes possible to display images with a pseudo-ROI (Region of Interest), which leads to a reduction in the amount of data.

[0100] (Second Embodiment) Figure 16 is a conceptual diagram showing the periodic forced reset operation according to the second embodiment. In the second embodiment, the row decoder RD performs a reset for each row at once during reset faz1 to faz4. However, the row decoder RD does not select row addresses R1 to R4 in address order, but selects them randomly.

[0101] For example, in the example shown in Figure 16, the row decoder RD selects row address R2 in reset faz1, row address R4 in reset faz2, row address R3 in reset faz3, and row address R1 in reset faz4. As a result, in reset faz1, the row decoder RD outputs a selection signal SEL_Y according to row address R2, and simultaneously resets the event detection circuits 300 of the four pixels "21" to "24" corresponding to row address R2.

[0102] Similarly, in reset faz2, the row decoder RD outputs a selection signal SEL_Y according to the row address R4, and simultaneously resets the event detection circuits 300 for the four pixels "41" to "44" corresponding to the row address R4.

[0103] During reset faz3, the row decoder RD outputs a selection signal SEL_Y according to the row address R3, and simultaneously resets the event detection circuits 300 for the four pixels "31" to "34" corresponding to the row address R3.

[0104] During reset faz4, the row decoder RD outputs a selection signal SEL_Y according to the row address R1, and simultaneously resets the event detection circuits 300 for the four pixels "11" to "14" corresponding to the row address R1.

[0105] In this way, the row decoder RD randomly selects a pixel PX for each row and resets the event detection circuit 300 for the pixel PX of the selected row. As a result, even if the operation of object B is synchronized with the reset operation, the photodetector 1 can suppress event missing.

[0106] For example, Figure 17 shows the event detection in the second embodiment when object B falls in the column C3 from R1 to R4 in synchronization with reset faz1 to faz4. In reset faz1, object B is at the position of pixel "13" corresponding to row address R1 and column address C3. When reset faz1 is executed, pixel "13" is not reset, so pixel "13" is capable of event detection of object B.

[0107] Similarly, in reset faz2, object B is located at pixel "23" corresponding to row address R2 and column address C3. Since pixel "23" is not reset when reset faz2 is executed, pixel "23" is capable of detecting object B as an event.

[0108] In reset faz3, object B is located at pixel "33" corresponding to row address R3 and column address C3. Since pixel "33" is reset when reset faz3 is executed, pixel "33" does not detect object B. In other words, in this case, event missing occurs.

[0109] In reset faz4, object B is located at pixel "43", which corresponds to row address R4 and column address C3. Since pixel "43" is not reset when reset faz4 is executed, pixel "43" is capable of detecting object B as an event.

[0110] Thus, even if the object B falls in sync with the reset operation, an event missing occurs in one pixel "33," but the other pixels "13," "23," and "43" can still detect the object B as an event. Therefore, the optical detection element 1 according to the second embodiment can suppress event missing as much as possible and detect the object B as a whole.

[0111] Figure 18 is a block diagram showing an example configuration of the detection chip 202, row decoder RD, and DAC 50 according to the second embodiment. In the second embodiment, the row decoder RD performs a reset for each row in reset faz1 to faz4. Therefore, the column decoder CD is optional. In this case, the row decoder RD is connected to the DAC 50. The DAC 50 is provided corresponding to the rows of pixels PX and selectively outputs a reference signal Ramp according to the selection signal SEL_Y output according to the row address. The reference signal Ramp is supplied to the pixel PX of the corresponding row. This allows the event detection circuit 300 to be reset row by row. Other configurations of the second embodiment may be the same as those of the first embodiment.

[0112] (Modification) In the second embodiment, resets are performed row by row in reset faz1 to faz4. However, although not shown in the figures, resets may also be performed column by column in reset faz1 to faz4. In this case, the column decoder CD does not select column addresses C1 to C4 in address order, but selects them randomly. The column decoder CD outputs a selection signal SEL_X according to the randomly selected column address and simultaneously resets the event detection circuits 300 of the four pixels corresponding to the column address. The same effects as in the second embodiment can be obtained even in this way.

[0113] (Regarding periodic forced reset operation) Figures 19 to 21 are explanatory diagrams of the reset operation when an event is detected. The vertical axis of the graph is voltage, and the horizontal axis is time.

[0114] The threshold voltage Vth is set to ±Vt relative to the initial pixel signal Vpx (voltage at the first input of comparator 332).

[0115] Next, as shown in Figure 19, an event occurs when the amount of light received changes and the pixel signal Vpx crosses the threshold voltage Vth (±Vt). For example, as shown in Figure 19, when the pixel signal Vpx exceeds the upper limit of the threshold voltage Vth + Vt (t0), a positive event (or on-event) is detected, an event signal Ve is output, and the system enters a reset state.

[0116] During the reset operation from t1 to t2, the threshold voltage Vth is updated according to the pixel signal Vpx at the end of the reset operation (t2). For example, in Figure 19, at t2, the threshold voltage Vth is set to ±Vt1. ±Vt1 is typically a voltage obtained by using the pixel signal Vpx at the end of the reset operation as an intermediate voltage and differentiating it by a predetermined voltage in the positive and negative directions.

[0117] After that, wait for the next event to occur.

[0118] Next, for example, as shown in Figure 20, when the pixel signal Vpx falls below the lower limit value -Vt of the threshold voltage Vth (t3), a negative event (or off-event) is detected, an event signal Ve is output, and the system enters a reset operation.

[0119] During the reset operation at t4 to t5, the threshold voltage Vth is updated according to the pixel signal Vpx at the end of the reset operation. For example, in Figure 20, at t5, the threshold voltage Vth is set to ±Vt2. ±Vt2 is typically a voltage obtained by using the pixel signal Vpx at the end of the reset operation (t5) as an intermediate voltage and varying it by a predetermined voltage in the positive and negative directions.

[0120] After that, wait for the next event to occur.

[0121] Here, in the reset operation shown in Figure 19, we assume that the pixel signal Vpx changes during or immediately after the reset operation, as shown in Figure 21. In this case, the threshold voltage Vth (±Vt1) set based on the pixel signal Vpx at the end of the reset operation t2 does not take into account the change in the pixel signal Vpx after the reset operation. Therefore, the reference pixel signal Vpx during standby after t2 will be a voltage that is skewed from the midpoint between the upper limit +Vt1 and the lower limit -Vt1 of the threshold voltage Vth. In this case, the margin mrg between the pixel signal Vpx and one of the threshold voltages Vth becomes relatively small. For example, in Figure 21, the margin between the pixel signal Vpx and the lower limit -Vt is smaller than that between the upper limit +Vt. In this case, an event will occur when the pixel signal Vpx changes only slightly to the negative side. Conversely, an event will not occur even if the pixel signal Vpx changes significantly to the positive side. This makes it impossible for the photodetector to accurately detect events.

[0122] In contrast, the photodetector element 1 according to this embodiment employs not only a reset operation when an event is detected, but also a periodic forced reset operation. Figure 22 is an explanatory diagram of the forced event operation. At t13, the reset signal FAZ is activated, and the forced reset operation is performed. As a result, the upper limit +Vt2 and lower limit -Vt2 of the threshold voltage Vth are set so that the pixel signal Vpx in standby mode is approximately an intermediate voltage. Thus, in this embodiment, even in standby mode when there are no events, the threshold voltage Vth is appropriately set based on the pixel signal Vpx in standby mode by periodically executing the above forced reset operation. Therefore, even if the pixel signal Vpx changes during or immediately after the reset operation when an event is detected, and the setting of the threshold voltage Vth is not appropriate, the threshold voltage Vth can be set to an appropriate position by the periodic forced reset operation. As a result, the photodetector element 1 can accurately detect events.

[0123] (Examples of application to mobile devices) The technology disclosed herein (the technology) can be applied to various electronic devices. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0124] Figure 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0125] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0126] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0127] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0128] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0129] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0130] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0131] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0132] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0133] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12030 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0134] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 23, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0135] Figure 24 shows an example of the installation position of the imaging unit 12031.

[0136] In Figure 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0137] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0138] Figure 24 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0139] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0140] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0141] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0142] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0143] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031, among the configurations described above.

[0144] Furthermore, this technology can be configured as follows:

[0145] (1) A photodetector comprising: a light receiving unit that converts incident light into electrical signals; and a detection circuit that compares a first signal corresponding to the electrical signal with a threshold voltage and outputs an event signal when the first signal exceeds or falls below the threshold voltage, wherein the plurality of pixels are arranged two-dimensionally in a first direction and a second direction intersecting the first direction; a first decoder that outputs a first selection signal to the pixel unit for selecting a row consisting of the plurality of pixels arranged in the first direction; and a second decoder that outputs a second selection signal to the pixel unit for selecting a column consisting of the plurality of pixels arranged in the second direction, wherein the detection circuit that has output the event signal is reset in accordance with the output of the event signal; the detection circuits of the plurality of pixels are periodically reset; and in the periodic reset operation, at least one of the first or second decoder randomly selects the row or the column according to the first or second selection signal.

[0146] (2) The photodetector according to (1), wherein in the periodic reset operation, the first and second decoders randomly select both the row and the column by the first and second selection signals.

[0147] (3) The photodetector according to (1), wherein in the periodic reset operation, the first decoder randomly selects each row by the first selection signal, or in the periodic reset operation, the second decoder randomly selects each column by the second selection signal.

[0148] (4) The optical detection element according to any one of (1) to (3), wherein each of the plurality of detection circuits comprises a comparator having a first input section for receiving the first signal, a second input section for receiving the threshold voltage, and an output section for outputting an event signal when the first signal exceeds or falls below the threshold voltage, a first switching element connected between the first input section and the output section, and a logic circuit for outputting an enable signal that causes the first switching element to conduct when the event signal is output and when both the first and second selection signals are activated.

[0149] (5) The photodetector according to (4), wherein the logic circuit comprises an AND operation circuit that receives the first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and the event signal and outputs the enable signal.

[0150] (6) The photodetector according to (4) or (5), further comprising a signal generator that outputs a second signal whose voltage changes over time, wherein each of the plurality of detection circuits further comprises a second switching element connected between the signal generator and the control unit of the first switching element.

[0151] (7) The photodetector described in (6), wherein the second switching element becomes conductive in response to the second signal and then gradually becomes non-conductive in an analog manner.

[0152] (8) The photodetector according to (4), wherein in the periodic reset operation, the first and second decoders randomly select the plurality of pixels by the first and second selection signals, and the detection circuit of the selected pixel is reset by making the first switching element conduct.

[0153] (9) The photodetector according to (4), wherein in the periodic reset operation, the first decoder randomly selects the row by the first selection signal, and the detection circuit of the selected row is reset by making the first switching element conduct.

[0154] (10) The photodetector according to any one of (1) to (9), wherein when the event signal is output, the detection circuit that output the event signal is individually reset, and in the periodic reset operation, all of the plurality of pixels are periodically reset.

[0155] (11) An electronic device having a photodetector, comprising: a light receiving unit that converts incident light into electrical signals; and a detection circuit that compares a first signal corresponding to the electrical signal with a threshold voltage and outputs an event signal when the first signal exceeds or falls below the threshold voltage, wherein the plurality of pixels are arranged two-dimensionally in a first direction and a second direction intersecting the first direction; a first decoder that outputs a first selection signal to the pixel unit for selecting a row consisting of the plurality of pixels arranged in the first direction; and a second decoder that outputs a second selection signal to the pixel unit for selecting a column consisting of the plurality of pixels arranged in the second direction, wherein the detection circuit that has output the event signal is reset in accordance with the output of the event signal; the detection circuits of the plurality of pixels are periodically reset; and in the periodic reset operation, at least one of the first or second decoder randomly selects the row or the column according to the first or second selection signal.

[0156] (12) The electronic device according to (11), wherein in the periodic reset operation, the first and second decoders randomly select both the row and the column by the first and second selection signals.

[0157] (13) The electronic device according to (11), wherein in the periodic reset operation, the first decoder randomly selects each row by the first selection signal, or in the periodic reset operation, the second decoder randomly selects each column by the second selection signal.

[0158] (14) The electronic device according to any one of (11) to (13), wherein each of the plurality of detection circuits comprises a comparator having a first input section for receiving the first signal, a second input section for receiving the threshold voltage, and an output section for outputting an event signal when the first signal exceeds or falls below the threshold voltage; a first switching element connected between the first input section and the output section; and a logic circuit for outputting an enable signal that causes the first switching element to conduct when the event signal is output and when both the first and second selection signals are activated.

[0159] (15) The electronic device according to (14), wherein the logic circuit comprises an AND operation circuit that receives the first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and the event signal and outputs the enable signal.

[0160] (16) The electronic device according to (14) or (15), further comprising a signal generator that outputs a second signal whose voltage changes over time, and each of the plurality of detection circuits further comprising a second switching element connected between the signal generator and the control unit of the first switching element.

[0161] (17) The electronic device according to (16), wherein the second switching element becomes conductive in response to the second signal and then gradually becomes non-conductive in an analog manner.

[0162] (18) The electronic device according to (14), wherein in the periodic reset operation, the first and second decoders randomly select the plurality of pixels by the first and second selection signals, and the detection circuit of the selected pixel is reset by making the first switching element conduct.

[0163] (19) The electronic device according to (14), wherein in the periodic reset operation, the first decoder randomly selects the row by the first selection signal, and the detection circuit of the selected row is reset by making the first switching element conduct.

[0164] (20) The electronic device according to any one of (11) to (19), wherein when the event signal is output, the detection circuit that output the event signal is individually reset, and in the periodic reset operation, all of the plurality of pixels are periodically reset.

[0165] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist.

[0166] 1. Photodetector 10. Imaging lens 20. Solid-state image sensor 30. Recording area 40. Control unit 50. DAC RD Row decoder CD Column decoder 202. Detection chip 201. Light receiving chip 220. Pixel array section 221. Light receiving section 260. Detection section 300. Event detection circuit 310. Logarithmic transformation circuit 320. Buffer 330. Quantizer 331. Capacitor 332. Comparator 333. OR operation circuit 334. AND operation circuit 335. Logic circuit SW1, SW2 Switching elements

Claims

1. A photodetector comprising: a plurality of light receiving units that convert incident light into electrical signals; and a plurality of detection circuits that compare a first signal corresponding to the electrical signal with a threshold voltage and output an event signal when the first signal exceeds or falls below the threshold voltage, wherein the plurality of pixels are arranged two-dimensionally in a first direction and a second direction intersecting the first direction; a first decoder that outputs a first selection signal to the pixels for selecting a row consisting of the plurality of pixels arranged in the first direction; and a second decoder that outputs a second selection signal to the pixels for selecting a column consisting of the plurality of pixels arranged in the second direction, wherein the detection circuit that has output the event signal is reset in accordance with the output of the event signal; the detection circuits of the plurality of pixels are periodically reset; and in the periodic reset operation, at least one of the first or second decoder randomly selects the row or the column according to the first or second selection signal.

2. The photodetector according to claim 1, wherein in the periodic reset operation, the first and second decoders randomly select both the row and the column by the first and second selection signals.

3. The photodetector according to claim 1, wherein in the periodic reset operation, the first decoder randomly selects each row by the first selection signal, or in the periodic reset operation, the second decoder randomly selects each column by the second selection signal.

4. The optical detection element according to claim 1, wherein each of the plurality of detection circuits comprises: a comparator having a first input section for receiving the first signal, a second input section for receiving the threshold voltage, and an output section for outputting an event signal when the first signal exceeds or falls below the threshold voltage; a first switching element connected between the first input section and the output section; and a logic circuit for outputting an enable signal that causes the first switching element to conduct when the event signal is output and when both the first and second selection signals are activated.

5. The photodetector according to claim 4, wherein the logic circuit comprises an AND operation circuit that receives the first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and the event signal and outputs the enable signal.

6. The photodetector according to claim 4, further comprising a signal generator that outputs a second signal whose voltage changes over time, wherein each of the plurality of detection circuits further comprises a second switching element connected between the signal generator and the control unit of the first switching element.

7. The photodetector element according to claim 6, wherein the second switching element becomes conductive in response to the second signal and then gradually becomes non-conductive in an analog manner.

8. The photodetector according to claim 4, wherein in the periodic reset operation, the first and second decoders randomly select the plurality of pixels by the first and second selection signals, and the detection circuit of the selected pixel is reset by making the first switching element conductious.

9. The photodetector according to claim 4, wherein in the periodic reset operation, the first decoder randomly selects the row by the first selection signal, and the detection circuit of the selected row is reset by making the first switching element conduct.

10. The photodetector according to claim 1, wherein when the event signal is output, the detection circuit that output the event signal is individually reset, and in the periodic reset operation, all of the plurality of pixels are periodically reset.

11. An electronic device having a photodetector, comprising: a plurality of light receiving units that convert incident light into electrical signals by photoelectric conversion; and a plurality of detection circuits (300) that compare a first signal corresponding to the electrical signal with a threshold voltage and output an event signal when the first signal exceeds or falls below the threshold voltage, wherein the plurality of pixels are arranged two-dimensionally in a first direction and a second direction intersecting the first direction; a first decoder that outputs a first selection signal to the pixels for selecting a row consisting of the plurality of pixels arranged in the first direction; and a second decoder that outputs a second selection signal to the pixels for selecting a column consisting of the plurality of pixels arranged in the second direction, wherein the detection circuit that has output the event signal is reset in accordance with the output of the event signal; the detection circuits of the plurality of pixels are periodically reset; and in the periodic reset operation, at least one of the first or second decoder randomly selects the row or the column according to the first or second selection signal.

12. The electronic device according to claim 11, wherein in the periodic reset operation, the first and second decoders randomly select both the row and the column by the first and second selection signals.

13. The electronic device according to claim 11, wherein in the periodic reset operation, the first decoder randomly selects each row by the first selection signal, or in the periodic reset operation, the second decoder randomly selects each column by the second selection signal.

14. The electronic device according to claim 11, wherein each of the plurality of detection circuits comprises: a comparator having a first input section for receiving the first signal, a second input section for receiving the threshold voltage, and an output section for outputting an event signal when the first signal exceeds or falls below the threshold voltage; a first switching element connected between the first input section and the output section; and a logic circuit for outputting an enable signal that causes the first switching element to conduct when the event signal is output and when both the first and second selection signals are activated.

15. The electronic device according to claim 14, wherein the logic circuit comprises an AND operation circuit that receives the first and second selection signals and performs an AND operation on both, and an OR operation circuit that performs an OR operation on the result of the AND operation circuit and the event signal and outputs the enable signal.

16. The electronic device according to claim 14, further comprising a signal generator that outputs a second signal whose voltage changes over time, and each of the plurality of detection circuits further comprising a second switching element connected between the signal generator and the control unit of the first switching element.

17. The electronic device according to claim 16, wherein the second switching element becomes conductive in response to the second signal and then gradually becomes non-conductive in an analog manner.

18. The electronic device according to claim 14, wherein in the periodic reset operation, the first and second decoders randomly select the plurality of pixels by the first and second selection signals, and the detection circuit of the selected pixel is reset by making the first switching element conductious.

19. The electronic device according to claim 14, wherein in the periodic reset operation, the first decoder randomly selects the row by the first selection signal, and the detection circuit of the selected row is reset by making the first switching element conduct.

20. The electronic device according to claim 11, wherein when the event signal is output, the detection circuit that output the event signal is individually reset, and in the periodic reset operation, all of the plurality of pixels are periodically reset.

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