Co-packaged buffer

Abstract

A data buffer die is stacked with multiple memory die and interconnected with wire bonds. This packaging configuration helps reduce transmit power by reducing the electrical distance between memory die only packages and a separately packaged data buffer. This packaging configuration may also reduce the cost of memory modules using this type of packaging configuration by eliminating the need for separate packaging for the data buffer die. This configuration may be used to aggregate data communicated with the multiple memory die allowing a common timing signal to be used for communication with a host. This configuration may allow for reduced size memory modules by eliminating the need for separate space on memory modules to be used for the separately packaged data buffer devices. This configuration may help improve data routing on memory module by providing for the re-orientation (e.g., rotate by 90°) of signals to / from the multiple die packages.

Description

Docket: 765-0249P - 11426US01CO-PACKAGED BUFFERBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1 A-1B are isometric view diagrams illustrating an example assembly with a data buffer die stacked with multiple memory dies.

[0002] Figure 2 is a block diagram illustrating a memory system with a co-packaged data buffer die stacked with multiple memory dies.

[0003] Figure 3 is a diagram illustrating a module with co-packaged memory and data buffer die packages.

[0004] Figures 4A-4B are isometric view diagrams illustrating an example assembly with a load reduced buffer die stacked with multiple memory dies.

[0005] Figure 5 is a diagram illustrating a module with co-packaged memory and load reduced buffer die packages.

[0006] Figure 6 is a diagram illustrating a module with co-packaged memory and registering clock driver die packages.

[0007] Figure 7A-7B are isometric view diagrams illustrating an example assembly with multiple memory die stacks.

[0008] Figure 8 is a block diagram illustrating a module with multiple memory die stack packages.

[0009] Figure 9 is a block diagram illustrating a module that shares a registering clock driver with multiple memory die stack packages.

[0010] Figure 10 is an isometric view diagram illustrating an example assembly with copackaged memory and registering clock driver die.

[0011] Figure 11 is a block diagram illustrating a module sharing a registering clock driver with multiple packages and multiple ranks.

[0012] Figure 12 is a flowchart illustrating a method of operating an assembly with a data buffer die stacked with multiple memory dies.

[0013] Figure 13 is a flowchart illustrating a method of operating a memory component.

[0014] Figure 14 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] In an embodiment, a data buffer (DB) die is stacked with multiple memory die and interconnected with wire bonds. This packaging configuration helps reduce transmit power by reducing the electrical distance between memory die only packages and a separately packaged data buffer. This packaging configuration may also reduce the cost ofDocket: 765-0249P - 11426US01memory modules using this type of packaging configuration by eliminating the need for separate packaging for the data buffer die. This configuration may be used to aggregate data communicated with the multiple memory die allowing a common timing signal to be used for communication with a host. This configuration may allow for reduced size memory modules by eliminating the need for separate space on memory modules to be used for the separately packaged data buffer devices. This configuration may help improve data routing on memory module by providing for the re-orientation (e.g., rotate by 90°) of signals to / from the multiple die packages.

[0016] Figures 1 A-1B are isometric view diagrams illustrating an example assembly with a data buffer die stacked with multiple memory dies. Figure 1 A illustrates memory component 100 without, for the purposes of visual clarity, wire bond interconnections that should be understood to be present (as illustrated in Figure IB).

[0017] In Figures 1A-1B, memory component 100 comprises substrate 101 memory dies 110a-l lOd, and data buffer die 130. Memory dies 110a-l lOd and data buffer die 130 are stacked with each other to form an integrated circuit stack. Substrate 101 includes command / address (CA) interface bonding pads 102 and host data (DQ) interface bonding pads 103. Memory die 110a includes data (DQ) interface bonding pads Illa and command / address (CA) interface bonding pads 112a. Memory die 110b includes data (DQ) interface bonding pads 111b and command / address (CA) interface bonding pads 112b.Memory die 110c includes data (DQ) interface bonding pads Illa and command / address (CA) interface bonding pads 112c. Memory die 1 lOd includes data (DQ) interface bonding pads 11 Id and command / address (CA) interface bonding pads 112d. Data buffer die 130 includes memory die data (DQ) interface bonding pads 131 and host data (DQ) interface bonding pads 133.

[0018] In Figures 1 A-1B, memory die 110a is illustrated disposed on top of substrate 101 in a manner that exposes at least one row of bonding pads along two adjacent edges of substrate 101. The bonding pads are exposed in a manner that allows for the connection of wire bonds (e.g., using bonding pads 102 and bonding pads 103) along both of these edges. Memory die 110b is illustrated disposed on top of memory die 110a and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads Illa and bonding pads 112a) along an edge of memory die 110a is exposed in a manner that allows for the connection of wire bonds. Memory die 110c is illustrated disposed on top of memory die 110b and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 11 lb and bonding pads 112b) along an edge of memory die 110b is exposed in a mannerDocket: 765-0249P - 11426US01that allows for the connection of wire bonds. Memory die 1 lOd is illustrated disposed on top of memory die 110c and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 111c and bonding pads 112c) along an edge of memory die 110c is exposed in a manner that allows for the connection of wire bonds. Data buffer die 130 is illustrated disposed on top of memory die 1 lOd and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 11 Id and bonding pads 112d) along an edge of memory die 1 lOd is exposed in a manner that allows for the connection of wire bonds.

[0019] Figure IB illustrates memory component 100 with wire bond interconnections. In Figure IB, wire bonds connect individual and unique ones of DQ interface bonding pads 11 la to individual and unique ones of DQ interface bonding pads 131, individual and unique ones of DQ interface bonding pads 11 lb to individual and unique ones of DQ interface bonding pads 131, individual and unique ones of DQ interface bonding pads 111c to individual and unique ones of DQ interface bonding pads 131, and individual and unique ones of DQ interface bonding pads 11 Id to individual and unique ones of DQ interface bonding pads 131. Wire bonds connect individual and unique ones of CA interface bonding pads 102 to corresponding individual ones of CA interface bonding pads 112a-l 12d. Finally, wire bonds connect individual and unique ones of host DQ interface bonding pads 133 to host DQ interface bonding pads 103.

[0020] Figure 2 is a block diagram illustrating a memory system with a co-packaged data buffer die stacked with multiple memory dies. In Figure 2, memory system 200 comprises packaged memory component 240 and controller 220. Packaged memory component 240 may be or comprise an example of memory component 100. Packaged memory component 240 includes die stack 245, command / address (CA) interface 241, and data (DQ) interface 243. Die stack 245 includes memory dies 210a-210e stacked with each other and buffer device 230. Controller 220 includes command / address (CA) interface 221 and data (DQ) interface 222.

[0021] Controller 220, memory dies 210a-210e may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 220, manages the flow of data going to and from memory devices and / or memory modules.Packaged memory component 240 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory dies 210a-210e may be devices that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory dies 210a-210e may be, orDocket: 765-0249P - 11426US01comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 220 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled with one or more microprocessors via a fabric interconnect or other type of interconnect.

[0022] CA interface 221 of controller 220 is operatively coupled with CA interface 241 of packaged memory component 240. DQ interface 222 of controller 220 is operatively coupled with DQ interface 243 of packaged memory component 240. CA interface 241 of packaged memory component 240 is operatively coupled in parallel with CA interfaces of memory dies 210a-210e. In some embodiment, CA interface 241 may be operatively coupled with the individual CA interface of memory dies 210a-210e via buffer device 230 (e.g., buffer device 230 may include registering clock driver circuitry / functionality). Buffer device 230 includes memory die DQ interfaces 23 la-23 le and host DQ interface 233. Memory die interfaces 23 la-23 le are operatively coupled with host DQ interface 233. Memory die interfaces 23 la-23 le are operatively coupled with host DQ interface 233 such that DQ signals communicated via respective ones of memory die interfaces 23 la-23 le in association with an access are communicated with DQ interface 243 (and thus with controller 220 via DQ interface 222) as groups that are aggregated to or from separate sets of DQ signals communicated with memory die 210a-210e. For example, if each memory die 210a-210e communicates using four bits per transfer (e.g., two two-bit wide data pseudo-channels), host DQ interface 233 may communicate using 20 bits per transfer (e.g., two ten-bit wide data pseudo-channels aggregated from the ten (two per memory die) two-bit pseudo-channels. In addition, for example, if each four bit transfer communicated with each of five memory die 210a-210e is timed by separate data strobe (DQS) signals (which may use differential signaling), buffer device 230 may aggregate and / or distribute data strobe signals for the data communications with these memory die 210a-210e based on a single (or at least less than five) DQS signal (which may use differential signaling) communicated with DQ interface 243 (and thus with controller 220 via DQ interface 222).

[0023] In an embodiment, buffer device 230 may also invert DQ signals communicated via memory die DQ interfaces 23 la-23 le and host DQ interface 233 based on a data bus inversion signal received from host DQ interface 233. Similarly, buffer device 230 mayDocket: 765-0249P - 11426US01generate and transmit a data bus inversion signal based on DQ signals received from memory die DQ interfaces 23 la-23 le.

[0024] Figure 3 is a diagram illustrating a module with co-packaged memory and data buffer die packages. In Figure 3, module 350 comprises packaged integrated circuit stack 340a0, packaged integrated circuit stack 340b0, packaged integrated circuit stack 340c0, packaged integrated circuit stack 340d0, packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340cl, packaged integrated circuit stack 340dl, channel 0 command / address (CA) interface 35 lab, channel 1 CA interface 35 led, pseudo-channel A data (DQ) interface 352a, pseudo-channel B DQ interface 352b, pseudo-channel C DQ interface 352c, pseudo-channel D DQ interface 352d, registering clock driver (RCD) 355ab, RCD 355cd, and power management integrated circuit (PMIC) 359. Packaged integrated circuit stack 340a0, packaged integrated circuit stack 340b0, packaged integrated circuit stack 340c0, and packaged integrated circuit stack 340d0, respectively include integrated circuit die stacks that include memory die (e.g., memory die 110a-l lOd) stacked with a respective data buffer (DB) 343a0, DB 343b0, DB 343c0, DB 343d0. (e.g., buffer device 230). Packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340cl, and packaged integrated circuit stack 340dl also include respective integrated circuit stacks that include memory die (e.g., memory die 110a-l lOd) stacked with respective data buffers (not shown in Figure 3 for the sake of visual clarity). Packaged integrated circuit stack 340a0, packaged integrated circuit stack 340b0, packaged integrated circuit stack 340c0, packaged integrated circuit stack 340d0, packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340c 1, and packaged integrated circuit stack 340dl may be, or comprise, examples of, and / or arrangements of, memory component 100 and / or packaged memory component 240.

[0025] In Figure 3, packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340c 1, and packaged integrated circuit stack 340dl are on the back side of module 350. This is illustrated in Figure 3 by depicting packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340cl, and packaged integrated circuit stack 340dl using dotted lines. Also in Figure 3, packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340c 1, packaged integrated circuit stack 340dlare respectively located opposite (i.e., directly on the other side of the substrate of module 350) of packaged integrated circuit stack 340a0, packaged integrated circuit stack 340b0, packagedDocket: 765-0249P - 11426US01integrated circuit stack 340c0, and packaged integrated circuit stack 340d0. In an embodiment, packaged integrated circuit stack 340a0, packaged integrated circuit stack 340b0, packaged integrated circuit stack 340c0, and packaged integrated circuit stack 340d0 are each as accessed as being part of a first rank (e.g., rank 0) on their respective channel and packaged integrated circuit stack 340al, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340cl, and packaged integrated circuit stack 340dlare each accessed as being part of a second rank (e.g., rank 1) on those respective channels.

[0026] RCD 355ab is operatively coupled with channel 0 CA interface 35 lab. RCD 355ab is operatively coupled with CA interface 35 lab to distribute command and address signals to packaged integrated circuit stack 340a0, packaged integrated circuit stack 340al, packaged integrated circuit stack 340b0, and packaged integrated circuit stack 340b 1.Packaged integrated circuit stack 340a0 and packaged integrated circuit stack 340al are operatively coupled with RCD 355ab and pseudo-channel A DQ interface 352a. Packaged integrated circuit stack 340a0 is operatively coupled with pseudo-channel A DQ interface 352a via DB 343a0. Packaged integrated circuit stack 340al is operatively coupled with pseudo-channel A DQ interface 352a via a DB that is included in packaged integrated circuit stack 340al (not shown in Figure 3). Packaged integrated circuit stack 340b0 and packaged integrated circuit stack 340bl are operatively coupled with RCD 355ab and pseudo-channel B DQ interface 352b. Packaged integrated circuit stack 340b0 is operatively coupled with pseudo-channel B DQ interface 352b via DB 343b0. Packaged integrated circuit stack 340b 1 is operatively coupled with pseudo-channel B DQ interface 352a via a DB that is included in packaged integrated circuit stack 340b 1 (not shown in Figure 3). Thus, it should be understood that the data interface of channel 0 is formed by pseudo-channel A DQ interface 352a and pseudo-channel B DQ interface 352b.

[0027] RCD 355cd is operatively coupled with channel 1 CA interface 35 led. RCD 355cd is operatively coupled with CA interface 35 led to distribute command and address signals to packaged integrated circuit stack 340b0, packaged integrated circuit stack 340b 1, packaged integrated circuit stack 340d0, and packaged integrated circuit stack 340dl.Packaged integrated circuit stack 340c0 and packaged integrated circuit stack 340cl are operatively coupled with RCD 355cd and pseudo-channel C DQ interface 352c. Packaged integrated circuit stack 340c0 is operatively coupled with pseudo-channel C DQ interface 352c via DB 343c0. Packaged integrated circuit stack 340cl is operatively coupled with pseudo-channel C DQ interface 352c via a DB that is included in packaged integrated circuit stack 340c 1 (not shown in Figure 3). Packaged integrated circuit stack 340d0 and packagedDocket: 765-0249P - 11426US01integrated circuit stack 340dl are operatively coupled with RCD 355cd and pseudo-channel D DQ interface 352d. Packaged integrated circuit stack 340d0 is operatively coupled with pseudo-channel D DQ interface 352d via DB 343d0. Packaged integrated circuit stack 340dl is operatively coupled with pseudo-channel D DQ interface 352d via a DB that is included in packaged integrated circuit stack 340dl (not shown in Figure 3). Thus, it should be understood that the data interface of channel 1 is formed by pseudo-channel C DQ interface 352c and pseudo-channel D DQ interface 352d.

[0028] In an embodiment, module 350 may include additional RCDs on the back side of module 350. In this case, for example, RCD 355ab may only be operatively coupled with packaged integrated circuit stack 340a0 and packaged integrated circuit stack 340al, while an additional RCD on the back side of module and opposite of RCD 355ab is operatively coupled with packaged integrated circuit stack 340b0 and packaged integrated circuit stack 340b 1. A similar arrangement / coupling may be used in this example for another additional RCD on the back side of module and opposite of RCD 355cd.

[0029] Figures 4A-4B are isometric view diagrams illustrating an example assembly with a load reduced buffer die stacked with multiple memory dies. Figure 4A illustrates memory component 400 without, for the purposes of visual clarity, wire bond interconnections that should be understood to be present (as illustrated in Figure 4B).

[0030] In Figures 4A-4B, memory component 400 comprises substrate 401 memory dies 410a-410d, and data buffer and registering clock driver and (DB / RCD) die 430. Memory dies 410a-410d and DB / RCD die 430 are stacked with each other to form an integrated circuit stack. Substrate 401 includes command / address (CA) interface bonding pads 402 and host data (DQ) interface bonding pads 404. Memory die 410a includes data (DQ) interface bonding pads 411a and command / address (CA) interface bonding pads 412a. Memory die 410b includes data (DQ) interface bonding pads 411b and command / address (CA) interface bonding pads 412b. Memory die 410c includes data (DQ) interface bonding pads 411a and command / address (CA) interface bonding pads 412c. Memory die 410d includes data (DQ) interface bonding pads 41 Id and command / address (CA) interface bonding pads 412d.DB / RCD die 430 includes memory die data (DQ) interface bonding pads 431a, DQ interface bonding pads 43 lb, CA interface input bonding pads 432i (i.e., CA bus signals from host), CA interface output bonding pads 432o (i.e., buffered CA bus signals to memory dies 410a-410d), and host data (DQ) interface bonding pads 434.

[0031] In Figures 4A-4B, memory die 410a is illustrated disposed on top of substrate 401 in a manner that exposes at least one row of bonding pads along two adjacent edges ofDocket: 765-0249P - 11426US01substrate 401. These bonding pads are exposed in a manner that allows for the connection of wire bonds (e.g., using bonding pads 402 and bonding pads 404) along both of these edges. Memory die 410b is illustrated disposed on top of memory die 410a and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 411a and bonding pads 412a) along an edge of memory die 410a is exposed in a manner that allows for the connection of wire bonds. Memory die 410c is illustrated disposed on top of memory die 410b and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 411b and bonding pads 412b) along an edge of memory die 410b is exposed in a manner that allows for the connection of wire bonds. Memory die 410d is illustrated disposed on top of memory die 410c and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 411c and bonding pads 412c) along an edge of memory die 410c is exposed in a manner that allows for the connection of wire bonds. DB / RCD die 430 is illustrated disposed on top of memory die 410d and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 41 Id and bonding pads 412d) along an edge of memory die 410d is exposed in a manner that allows for the connection of wire bonds.

[0032] Figure 4B illustrates memory component 400 with wire bond interconnections. In Figure 4B, wire bonds connect individual and unique ones of DQ interface bonding pads 41 la to individual and unique ones of DQ interface bonding pads 431a, individual and unique ones of DQ interface bonding pads 41 lb to individual and unique ones of DQ interface bonding pads 43 lb. Similarly, but not shown in Figures 4A-4B for the sake of visual clarity, individual and unique ones of DQ interface bonding pads 411c wire bonded to individual and unique ones of DQ interface bonding pads 431a, and individual and unique ones of DQ interface bonding pads 41 Id to individual and unique ones of DQ interface bonding pads 43 lb. Wire bonds connect individual and unique ones of CA interface output bonding pads 432o to corresponding individual ones of CA interface bonding pads 412a-412d. Wire bonds connect individual and unique ones of CA interface input bonding pads 432i to corresponding individual ones of CA interface bonding pads 402. Finally, wire bonds connect individual and unique ones of host DQ interface bonding pads 434 to host DQ interface bonding pads 404.

[0033] Figure 5 is a diagram illustrating a module with co-packaged memory and load reduced buffer die packages. In Figure 5, module 550 comprises packaged integrated circuit stack 540a, packaged integrated circuit stack 540b, packaged integrated circuit stack 540c, packaged integrated circuit stack 540d, channel 0 command / address (CA) interface 55 lab, channel 1 CA interface 55 led, pseudo-channel A data (DQ) interface 552a, pseudo-channel BDocket: 765-0249P - 11426US01DQ interface 552b, pseudo-channel C DQ interface 552c, pseudo-channel D DQ interface 552d, and power management integrated circuit (PMIC) 559. Packaged integrated circuit stack 540a, packaged integrated circuit stack 540b, packaged integrated circuit stack 540c, and packaged integrated circuit stack 540d, respectively include integrated circuit die stacks that include memory die (e.g., memory die 410a-410d) stacked with a respective data buffer and registering clock driver (DB / RCD) 544a, DB / RCD 544b, DB / RCD 544c, DB / RCD 544d. (e.g., DB / RCD die 430). Packaged integrated circuit stack 540a, packaged integrated circuit stack 540b, packaged integrated circuit stack 540c, packaged integrated circuit stack 540d, may be, or comprise, examples of, and / or arrangements of, memory component 400 and / or packaged memory component 240.

[0034] DB / RCD 544a is operatively coupled with channel 0 CA interface 55 lab.DB / RCD 544a is operatively coupled with CA interface 55 lab to distribute command and address signals to the memory die of packaged integrated circuit stack 540a. DB / RCD 544b is operatively coupled with channel 0 CA interface 55 lab. DB / RCD 544b is operatively coupled with CA interface 55 lab to distribute command and address signals to the memory die of packaged integrated circuit stack 540b. DB / RCD 544a of packaged integrated circuit stack 540a is operatively coupled with pseudo-channel A DQ interface 552a. DB / RCD 544b of packaged integrated circuit stack 540b is operatively coupled with pseudo-channel B DQ interface 552b. Thus, it should be understood that the data interface of channel 0 is formed by pseudo-channel A DQ interface 552a and pseudo-channel B DQ interface 552b.

[0035] DB / RCD 544c is operatively coupled with channel 1 CA interface 55 led.DB / RCD 544c is operatively coupled with CA interface 55 led to distribute command and address signals to the memory die of packaged integrated circuit stack 540c. DB / RCD 544d is operatively coupled with channel 1 CA interface 55 led. DB / RCD 544d is operatively coupled with CA interface 55 led to distribute command and address signals to the memory die of packaged integrated circuit stack 540d. DB / RCD 544c of packaged integrated circuit stack 540c is operatively coupled with pseudo-channel C DQ interface 552c. DB / RCD 544d of packaged integrated circuit stack 540d is operatively coupled with pseudo-channel D DQ interface 552d. Thus, it should be understood that the data interface of channel 1 is formed by pseudo-channel C DQ interface 552c and pseudo-channel D DQ interface 552d. In an embodiment, module 550 may include additional packaged integrated circuit stacks (e.g., on the back side of module 550).

[0036] Figure 6 is a diagram illustrating a module with co-packaged memory and registering clock driver die packages. In Figure 6, module 650 comprises packagedDocket: 765-0249P - 11426US01integrated circuit stack 640a, packaged integrated circuit stack 640b, packaged integrated circuit stack 640c, packaged integrated circuit stack 640d, channel 0 command / address (CA) interface 65 lab, channel 1 CA interface 65 led, pseudo-channel A data (DQ) interface 652a, pseudo-channel B DQ interface 652b, pseudo-channel C DQ interface 652c, pseudo-channel D DQ interface 652d, and power management integrated circuit (PMIC) 659. Packaged integrated circuit stack 640a, packaged integrated circuit stack 640b, packaged integrated circuit stack 640c, and packaged integrated circuit stack 640d, respectively include integrated circuit die stacks that include memory die (e.g., memory die 410a-410d) stacked with a respective registering clock driver (RCD) 647a, RCD 647b, RCD 647c, RCD 647d. Packaged integrated circuit stack 640a, packaged integrated circuit stack 640b, packaged integrated circuit stack 640c, packaged integrated circuit stack 640d, may be, or comprise, examples of, and / or arrangements of, packaged memory component 240.

[0037] RCD 647a is operatively coupled with channel 0 CA interface 65 lab. RCD 647a is operatively coupled with CA interface 65 lab to distribute command and address signals to the memory die of packaged integrated circuit stack 640a. RCD 647b is operatively coupled with channel 0 CA interface 65 lab. RCD 647b is operatively coupled with CA interface 65 lab to distribute command and address signals to the memory die of packaged integrated circuit stack 640b. The memory die of packaged integrated circuit stack 640a are operatively coupled with pseudo-channel A DQ interface 652a. The memory die of packaged integrated circuit stack 640b are operatively coupled with pseudo-channel B DQ interface 652b. Thus, it should be understood that the data interface of channel 0 is formed by pseudo-channel A DQ interface 652a and pseudo-channel B DQ interface 652b.

[0038] RCD 647c is operatively coupled with channel 1 CA interface 65 led. RCD 647c is operatively coupled with CA interface 65 led to distribute command and address signals to the memory die of packaged integrated circuit stack 640c. RCD 647d is operatively coupled with channel 1 CA interface 65 led. RCD 647d is operatively coupled with CA interface 65 led to distribute command and address signals to the memory die of packaged integrated circuit stack 640d. The memory die of packaged integrated circuit stack 640c are operatively coupled with pseudo-channel C DQ interface 652c. The memory die of packaged integrated circuit stack 640d are operatively coupled with pseudo-channel D DQ interface 652d. Thus, it should be understood that the data interface of channel 1 is formed by pseudo-channel C DQ interface 652c and pseudo-channel D DQ interface 652d. In an embodiment, module 650 may include additional packaged integrated circuit stacks (e.g., on the back side of module 650).Docket: 765-0249P - 11426US01

[0039] Figure 7A-7B are isometric view diagrams illustrating an example assembly with multiple memory die stacks. Figures 7A-7B illustrate memory component 700 without, for the purposes of visual clarity, wire bond interconnections that should be understood to be present.

[0040] In Figures 7A-7B, memory component 700 comprises substrate 701, integrated circuit device stack 771, and integrated circuit device stack 772. Integrated circuit device stack 771 comprises memory dies 710a-710d, and registering clock driver (RCD) die 730. Integrated circuit device stack 772 comprises memory dies 710e-710h. Memory dies 710a-710d and RCD die 730 are stacked with each other to form integrated circuit device stack 771. Memory dies 710e-710h are stacked with each other to form integrated circuit device stack 772. Substrate 701 includes command / address (CA) input (a.k.a., host) interface bonding pads 702, buffered CA interface bonding pads 703, and buffered CA interface bonding pads 705. Memory die 710a includes data (DQ) interface bonding pads 711a and command / address (CA) interface bonding pads 712a. Memory die 710e includes data (DQ) interface bonding pads 71 le and command / address (CA) interface bonding pads 712e.Memory die 710b includes data (DQ) interface bonding pads and command / address (CA) interface bonding pads. Memory die 710c includes data (DQ) interface bonding pads and command / address (CA) interface bonding pads. Memory die 710d includes data (DQ) interface bonding pads and command / address (CA) interface bonding pads. RCD die 730 includes memory die data (DQ) interface bonding pads 731a, DQ interface bonding pads 73 lb, CA interface input bonding pads 732i (i.e., CA bus signals from host), CA interface output bonding pads 732a (i.e., buffered CA bus signals to memory dies 710a-710d), CA interface output bonding pads 732b (i.e., buffered CA bus signals to memory dies 710e-710h via buffered CA interface bonding pads 703, and buffered CA interface bonding pads 705).

[0041] In Figures 7A-7B, memory die 710a is illustrated disposed on top of substrate 701 in a manner that exposes at least one row of bonding pads along two adjacent edges of memory die 710a. These bonding pads are exposed in a manner that allows for the connection of wire bonds (e.g., using bonding pads 706a, bonding pads 703, and bonding pads 704) along both of these edges. Memory die 710b is illustrated disposed on top of memory die 710a and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 711a and bonding pads 712a) along an edge of memory die 710a is exposed in a manner that allows for the connection of wire bonds. Memory die 710c is illustrated disposed on top of memory die 710b and with a horizonal offset that ensures at least one row of bonding pads along an edge of memory die 710b is exposed in a manner thatDocket: 765-0249P - 11426US01allows for the connection of wire bonds. Memory die 710d is illustrated disposed on top of memory die 710c and with a horizonal offset that ensures at least one row of bonding pads along an edge of memory die 710c is exposed in a manner that allows for the connection of wire bonds. RCD die 730 is illustrated disposed on top of memory die 710d and with a horizonal offset that ensures at least one row of bonding pads along an edge of memory die 710d is exposed in a manner that allows for the connection of wire bonds.

[0042] In Figures 7A-7B, memory die 710e is illustrated disposed on top of substrate 701 in a manner that exposes at least one row of bonding pads along two adjacent edges of memory die 710e. These bonding pads are exposed in a manner that allows for the connection of wire bonds (e.g., using bonding pads 706b and bonding pads 703) along both of these edges. Memory die 71 Of is illustrated disposed on top of memory die 710e and with a horizonal offset that ensures at least one row of bonding pads (e.g., bonding pads 71 le and bonding pads 712e) along an edge of memory die 710e is exposed in a manner that allows for the connection of wire bonds. Memory die 710g is illustrated disposed on top of memory die 71 Of and with a horizonal offset that ensures at least one row of bonding pads along an edge of memory die 710e is exposed in a manner that allows for the connection of wire bonds. Memory die 71 Oh is illustrated disposed on top of memory die 710g and with a horizonal offset that ensures at least one row of bonding pads along an edge of memory die 710g is exposed in a manner that allows for the connection of wire bonds.

[0043] Figure 7B illustrates memory component 700 with notional interconnections. For the sake of visual clarity, some reference numbers illustrated in Figure 7A have been omitted in Figure 7B. It should be understood, however, those elements are the same in Figure 7B as were illustrated in Figure 7B. In Figure 7B, host CA signals received via bonding pads 702 and 732i are buffered by RCD die 730 and output via output bonding pads 732a and 732b. This is illustrated in Figure 7B by arrow 791 running from bonding pads 732i to bonding pads 732a. The CA signals output by bonding pads 732a are distributed to each of memory dies 710a-710c (e.g., via bonding pads 712a). The CA signals output by bonding pads 732b are coupled to bonding pads 703. This is illustrated in Figure 7B by arrow 793 running from bonding pads 732b to bonding pads 703. The CA signals received via bonding pads 703 are coupled to bonding pads 705. This is illustrated in Figure 7B by arrow 794 running from bonding pads 703 are coupled to bonding pads 705. The CA signals output by bonding pads 705 are distributed to each of memory dies 710e-710h. This is illustrated in Figure 7B by arrows 795 running from bonding pads 705 to each of memory dies 710e-710h (e.g., via bonding pads 712e).Docket: 765-0249P - 11426US01

[0044] Figure 8 is a block diagram illustrating a module with multiple memory die stack packages. In Figure 8, module 850 comprises dual integrated circuit stack package 861, dual integrated circuit stack package 862, channel 0 command / address (CA) interface 85 lab, channel 1 CA interface 85 led, pseudo-channel A data (DQ) interface 852a, pseudo-channel B DQ interface 852b, pseudo-channel C DQ interface 852c, and pseudo-channel D DQ interface 852d. Dual integrated circuit stack package 861 includes integrated circuit die stack 841a and integrated circuit die stack 841b. Integrated circuit die stack 841a includes stacked memory die (e.g., memory die 710a-710d) stacked with a registering clock driver (RCD) 847ab. Integrated circuit die stack 841b includes stacked memory die (e.g., memory die 710e-710h). Dual integrated circuit stack package 862 includes integrated circuit die stack 841c and integrated circuit die stack 84 Id. Integrated circuit die stack 841c includes stacked memory die (e.g., memory die 710a-710d) stacked with a registering clock driver (RCD) 847cd. Integrated circuit die stack 841d includes stacked memory die (e.g., memory die 710e-710h). In an embodiment, dual integrated circuit stack package 861 and dual integrated circuit stack package 862, may be, or comprise, examples of, and / or arrangements of, memory component 700 and / or packaged memory component 240.

[0045] RCD 847ab is operatively coupled with channel 0 CA interface 85 lab. RCD 847ab is operatively coupled with CA interface 85 lab to distribute command and address signals to the memory die of integrated circuit die stack 841a. RCD 847ab is operatively coupled integrated circuit die stack 841b. RCD 847b is operatively coupled with integrated circuit die stack 841b to distribute command and address signals to the memory die of integrated circuit die stack 841b. The memory die of integrated circuit die stack 841a are operatively coupled with pseudo-channel A DQ interface 852a. The memory die of integrated circuit die stack 841b are operatively coupled with pseudo-channel B DQ interface 852b. Thus, it should be understood that the data interface of channel 0 is formed by pseudochannel A DQ interface 852a and pseudo-channel B DQ interface 852b.

[0046] RCD 847cd is operatively coupled with channel 1 CA interface 85 led. RCD 847cd is operatively coupled with CA interface 85 led to distribute command and address signals to the memory die of integrated circuit die stack 841c. RCD 847cd is operatively coupled integrated circuit die stack 84 Id. RCD 847cd is operatively coupled with integrated circuit die stack 84 Id to distribute command and address signals to the memory die of integrated circuit die stack 84 Id. The memory die of integrated circuit die stack 841c are operatively coupled with pseudo-channel C DQ interface 852c. The memory die of integrated circuit die stack 84 Id are operatively coupled with pseudo-channel D DQ interfaceDocket: 765-0249P - 11426US01852d. Thus, it should be understood that the data interface of channel 1 is formed by pseudochannel C DQ interface 852c and pseudo-channel D DQ interface 852d. In an embodiment, module 850 may include additional packaged integrated circuit stacks (e.g., on the back side of module 850).

[0047] Figure 9 is a block diagram illustrating a module that shares a registering clock driver with multiple memory die stack packages. In Figure 9, module 950 comprises dual integrated circuit stack package 961, dual integrated circuit stack package 962, channel 0 command / address (CA) interface 951a, pseudo-channel A data (DQ) interface 952a, pseudochannel B DQ interface 952b, pseudo-channel C DQ interface 952c, and pseudo-channel D DQ interface 952d. Dual integrated circuit stack package 961 includes integrated circuit die stack 941a and integrated circuit die stack 941b. Integrated circuit die stack 941a includes stacked memory die (e.g., memory die 710a-710d) stacked with a registering clock driver (RCD) 947. Integrated circuit die stack 941b includes stacked memory die (e.g., memory die 710e-710h). Dual integrated circuit stack package 962 includes integrated circuit die stack 941c and integrated circuit die stack 94 Id. Integrated circuit die stack 941c includes stacked memory die (e.g., memory die 710a-710d). Integrated circuit die stack 941d includes stacked memory die (e.g., memory die 710e-710h).

[0048] Integrated circuit die stacks 94 la-94 Id are each configured to be accessed / addressed as two ranks. For example, if integrated circuit die stacks 941a-941d each have five memory die (e.g., four for data and one for error detect and correct information), two memory die of a given stack may be accessed / addressed by a host as part of a first rank, and three other die of that stack may be accessed as part of a second rank. In an embodiment, dual integrated circuit stack package 961 and dual integrated circuit stack package 962, may be, or comprise, examples of, and / or arrangements of, memory component 700 and / or packaged memory component 240.

[0049] RCD 947 is operatively coupled with channel 0 CA interface 951a. RCD 947 is operatively coupled with CA interface 951a to distribute command and address signals to the memory die of each of integrated circuit stacks 941a-941b. The memory die of integrated circuit die stack 941a are operatively coupled with pseudo-channel A DQ interface 952a. The memory die of integrated circuit die stack 941b are operatively coupled with pseudochannel B DQ interface 952b. The memory die of integrated circuit die stack 941c are operatively coupled with pseudo-channel C DQ interface 952c. The memory die of integrated circuit die stack 94 Id are operatively coupled with pseudo-channel D DQ interface 952d. Thus, it should be understood that the data interface of channel 0 is formed by pseudoDocket: 765-0249P - 11426US01channel A DQ interface 952a, pseudo-channel B DQ interface 952b, pseudo-channel C DQ interface 952c, and pseudo-channel D DQ interface 952d. It should also be understood that channel 0 may be accessed as two distinct ranks of memory die. In an embodiment, module 950 may include additional packaged integrated circuit stacks (e.g., on the back side of module 950).

[0050] Figure 10 is an isometric view diagram illustrating an example assembly with copackaged memory and registering clock driver die. In Figure 10, memory component 1000 comprises substrate 1001 memory dies lOlOa-lOlOe, and die 1030. Die 1030 may be one or more of an RCD die, DB die, or DB / RCD die. Memory dies lOlOa-lOlOe and die 1030 are stacked with each other to form an integrated circuit stack. Substrate 101 includes command / address (CA) interface bonding pads and host data (DQ) interface bonding pads (not shown in Figure 10). Memory die lOlOa-lOlOe each include data (DQ) interface bonding pads and command / address (CA) interface bonding pads. Die 1030 includes at least two groups of bonding pads each configured to be a one of memory die data (DQ) interface bonding pads, host data (DQ) interface bonding pads, memory die command / address (CA) interface bonding pads, and host command / address (CA) interface bonding pads.

[0051] In Figure 10, memory die 1010a is illustrated disposed on top of substrate 1001 in a manner that exposes at least one row of bonding pads along two opposite edges of substrate 1001. The bonding pads are exposed in a manner that allows for the connection of wire bonds along both of these edges. Memory die 1010b is illustrated disposed on top of memory die 1010a and with a horizonal offset that ensures at least one row of bonding pads along a first edge of memory die 1010a is exposed in a manner that allows for the connection of wire bonds. Memory die 1010c is illustrated disposed on top of memory die 1010b and with a horizonal offset that ensures at least one row of bonding along a second edge, opposite of the first edge, of memory die 1010b is exposed in a manner that allows for the connection of wire bonds. Memory die lOlOd is illustrated disposed on top of memory die 1010c and with a horizonal offset that ensures at least one row of bonding pads along the first edge of memory die 1010c is exposed in a manner that allows for the connection of wire bonds. Memory die lOlOe is illustrated disposed on top of memory die lOlOd and with a horizonal offset that ensures at least one row of bonding pads along the second edge of memory die lOlOd is exposed in a manner that allows for the connection of wire bonds. Die 1030 is illustrated disposed on top of memory die lOlOe and with a horizonal offset that ensures at least one row of bonding pads along the first edge of memory die lOlOd is exposed in a manner that allows for the connection of wire bonds.Docket: 765-0249P - 11426US01

[0052] In an embodiment, memory die 1010a, memory die 1010c, and memory die lOlOe may be accessed as a first rank (or part of a first rank) and memory die 1010b and memory die lOlOd may be accessed as a second rank (or part of a second rank). Thus, for example, the offset configuration of memory component 1000 may be seen as an example of two rank integrated circuit die stack 941a, and the offset configuration of memory component 1000 without die 1030 may be seen as an example of two rank stacks 941b-941d.

[0053] Figure 11 is a block diagram illustrating a module sharing a registering clock driver with multiple packages and multiple ranks. In Figure 11, module 1150 comprises integrated circuit stack package 1140a, integrated circuit stack package 1140b, channel 0 command / address (CA) interface 115 lab, pseudo-channel A data (DQ) interface 1152a, and pseudo-channel B DQ interface 1152b. Integrated circuit stack package 1140a includes stacked memory die (e.g., memory die lOlOa-lOlOe) stacked with a registering clock driver (RCD) 1147. Integrated circuit stack package 1140b includes stacked memory die (e.g., memory die lOlOa-lOlOe) optionally stacked with a redistribution layer die (RDL) 1148.

[0054] Integrated circuit stack packages 1141 a- 1141b are each configured to be accessed / addressed as two ranks. For example, if integrated circuit stack packages 1141a-1141b each have five memory die (e.g., four for data and one for error detect and correct information), two memory die of a each stack may be accessed / addressed by a host as part of a first rank, and three other die of that stack may be accessed as part of a second rank. In an embodiment, integrated circuit stack package may be, or comprise, examples of, and / or arrangements of, memory component 1000 and / or packaged memory component 240.

[0055] RCD 1147 is operatively coupled with channel 0 CA interface 1151ab. RCD 1147 is operatively coupled with CA interface 1151ab to distribute command and address signals to the memory die of each of integrated circuit stack packages 1141 a- 1141b. The memory die of integrated circuit stack package 1141a are operatively coupled with pseudochannel A DQ interface 1152a. The memory die of integrated circuit stack package 1141b are operatively coupled with pseudo-channel B DQ interface 1152b. Thus, it should be understood that the data interface of channel 0 is formed by pseudo-channel A DQ interface 1152a and pseudo-channel B It should also be understood that channel 0 may be accessed as two distinct ranks of memory die. In an embodiment, module 1150 may include additional packaged integrated circuit stacks.

[0056] Figure 12 is a flowchart illustrating a method of operating an assembly with a data buffer die stacked with multiple memory dies. One or more steps illustrated in Figure 12 may be performed by, for example, memory component 100, system 200, module 350,Docket: 765-0249P - 11426US01memory component 400, module 550, module 650, memory component 700, module 850, module 950, memory component 1000, and / or module 1150, and / or their components. By a memory component comprising a first integrated circuit device stack that includes a plurality of stacked memory devices and a data buffer device, a first command is received that is to be performed by each of the plurality of stacked memory devices (1202). For example, packaged memory component 240 may receive, from controller 220 via CA interface 221 and CA interface 241, a first command that is to be performed by each of memory dies 210a-210e of memory die stack 245.

[0057] Data signals and timing signals associated with the first command are communicated, by the data buffer device, with each of the plurality of stacked memory devices (1204). For example, buffer device 230 may communicate data and timing signals (e.g., data strobes) with each of memory dies 210a-210e. The data signals associated with the first command are communicated, by the data buffer device, via an external data interface of the memory component (1206). For example, buffer device 230 may communicate, with controller 220 and via DQ interface 243 and DQ interface 222, data associated with the first command.

[0058] Figure 13 is a flowchart illustrating a method of operating a memory component. One or more steps illustrated in Figure 13 may be performed by, for example, memory component 100, system 200, module 350, memory component 400, module 550, module 650, memory component 700, module 850, module 950, memory component 1000, and / or module 1150, and / or their components. By a memory component comprising a first integrated circuit device stack that includes a plurality of stacked memory devices and a buffer device, a first command is received that is to be performed by each of the plurality of stacked memory devices (1302). For example, packaged memory component 240 may receive, from controller 220 via CA interface 221 and CA interface 241, a first command that is to be performed by each of memory dies 210a-210e of memory die stack 245.

[0059] Individual copies of the first command are transmitted, by the buffer device, to respective ones of the plurality of stacked memory devices (1304). For example, buffer device 230 may transmit the first command each of memory dies 210a-210e of memory die stack 245. A common timing signal associated with the first command is received by the buffer device (1306). For example, buffer device 230 may receive, from controller 220 via DQ interface 222 and DQ interface 243 a timing signal (e.g., write clock, DQS) to time transfers via DQ interface 222 and DQ interface 243. In another example, buffer device 230Docket: 765-0249P - 11426US01may receive, from a one of memory dies 210a-210e, a timing signal (e.g., DQS) that is to be the basis for a timing signal to time transfers via DQ interface 222 and DQ interface 243.

[0060] Respective individual timing signals associated with the first command are transmitted by the buffer device to the plurality of stacked memory devices (1308). For example, buffer device 230 may transmit, individual timing signals (e.g., write clock, DQS) to time transfers with memory dies 210a-210e via respective DQ interfaces 23 la-23 le. Data signal associated with the first command are communicated by the buffer device with each of the plurality of stacked memory devices (1310). For example, buffer device 230 may communicate, data signals (e.g., four data signal) with memory dies 210a-210e via respective DQ interfaces 23 la-23 le. The data signals associated with the first command are communicated via an external data interface of the memory component by the buffer device (1312). For example, buffer device 230 may communicate, via host DQ interface 233, data signals communicated with memory dies 210a-210e via respective DQ interfaces 23 la-23 le.

[0061] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory component 100, system 200, module 350, memory component 400, module 550, module 650, memory component 700, module 850, module 950, memory component 1000, and / or module 1150, and their components. These software descriptions may be: Behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0062] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0063] Figure 14 is a block diagram illustrating one embodiment of a processing system 1400 for including, processing, or generating, a representation of a circuit component 1420.Docket: 765-0249P - 11426US01Processing system 1400 includes one or more processors 1402, a memory 1404, and one or more communications devices 1406. Processors 1402, memory 1404, and communications devices 1406 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1408.

[0064] Processors 1402 execute instructions of one or more processes 1412 stored in a memory 1404 to process and / or generate circuit component 1420 responsive to user inputs 1414 and parameters 1416. Processes 1412 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1420 includes data that describes all or portions of memory component 100, system 200, module 350, memory component 400, module 550, module 650, memory component 700, module 850, module 950, memory component 1000, and / or module 1150, and their components, as shown in the Figures.

[0065] Representation 1420 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1420 may be stored on storage media or communicated by carrier waves.

[0066] Data formats in which representation 1420 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0067] User inputs 1414 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1416 may include specifications and / or characteristics that are input to help define representation 1420. For example, parameters 1416 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0068] Memory 1404 includes any suitable type, number, and / or configuration of non-transitory computer-readable storage media that stores processes 1412, user inputs 1414, parameters 1416, and circuit component 1420.Docket: 765-0249P - 11426US01

[0069] Communications devices 1406 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1400 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1406 may transmit circuit component 1420 to another system. Communications devices 1406 may receive processes 1412, user inputs 1414, parameters 1416, and / or circuit component 1420 and cause processes 1412, user inputs 1414, parameters 1416, and / or circuit component 1420 to be stored in memory 1404.

[0070] Implementations discussed herein include, but are not limited to, the following examples:

[0071] Example 1: A memory component, comprising: an external command / address (CA) interface to receive commands and addresses from a device external to the memory component; an external data interface to communicate data signals and timing reference signals with the device external to the memory component; a first set of stacked memory devices comprising memory cell circuitry, each of the first set of stacked memory devices to receive commands and addresses received by the memory component via the external CA interface; and a data buffer device stacked with the first set of stacked memory devices, the data buffer device to relay the data signals and timing signals between the external data interface and each of the first set of stacked memory devices.

[0072] Example 2: The memory component of claim 1, wherein the data buffer device is to communicate separate timing signals with each of the set of stacked memory devices.

[0073] Example 3: The memory component of claim 2, wherein the data buffer device is to communicate common, among the set of stacked memory devices, timing signals with the device external to the memory component.

[0074] Example 4: The memory component of claim 1, wherein the data buffer device is to generate a data bus inversion signal and is to communicate the data bus inversion signal with the device external to the memory component.

[0075] Example 5: The memory component of claim 1, wherein the data buffer device and each of the set of stacked memory devices are to communicate the data signals and timing signals via wire bonds.

[0076] Example 6: The memory component of claim 1, wherein the data buffer device is to relay the commands and addresses between the external CA interface and each of the first set of stacked memory devices.Docket: 765-0249P - 11426US01

[0077] Example 7: The memory component of claim 1, further comprising: a second set of stacked memory devices, the data buffer device to relay the data signals and timing signals between the external data interface and each of the second set of stacked memory devices.

[0078] Example 8: An assembly, comprising: a first set of stacked memory devices each comprising at least one memory array, the at least one memory array to be accessed via signals of an external interface; and a data buffer device electrically coupled with, and stacked with, the first set of stacked memory devices, the data buffer device to communicate data signals and timing signals between the external interface and each of the first set of stacked memory devices.

[0079] Example 9: The assembly of claim 8, wherein the data buffer device further comprises: timing signal distribution circuitry to receive a common data timing signal and to, based on the common data timing signal, distribute individual data timing signals to each of the first set of stacked memory devices.

[0080] Example 10: The assembly of claim 8, wherein the data buffer device further comprises: data bus inversion signal circuitry to, based on the data signals communicated with the first set of stacked memory devices, communicate a data bus inversion signal via the external interface.

[0081] Example 11: The assembly of claim 10, wherein the data buffer device further comprises: data bus inversion circuitry to, based on the data bus inversion signal, selectively invert the data signals communicated between the external interface and each of the first set of stacked memory devices.

[0082] Example 12: The assembly of claim 8, wherein the data buffer device is to communicate command and address signals between the external interface and each of the first set of stacked memory devices.

[0083] Example 13: The assembly of claim 12, further comprising: a second set of stacked memory devices each comprising at least one memory array, the at least one memory array to be accessed via signals of the external interface.

[0084] Example 14: The assembly of claim 13, wherein the data buffer device is to communicate data signals and timing signals between the external interface and each of the second set of stacked memory devices.

[0085] Example 15: A method, comprising: receiving, by a memory component comprising a first integrated circuit device stack that includes a plurality of stacked memory devices and a data buffer device, a first command to be performed by each of the plurality of stacked memory devices; communicating, by the data buffer device, data signals and timingDocket: 765-0249P - 11426US01signals associated with the first command with each of the plurality of stacked memory devices; and communicating, by the data buffer device, the data signals associated with the first command via an external data interface of the memory component.

[0086] Example 16: The method of claim 15, wherein the data buffer device is electrically connected to each of the plurality of stacked memory devices using wire bonds.

[0087] Example 17: The method of claim 15, further comprising: receiving, from the external data interface, a common timing signal associated with the first command.

[0088] Example 18: The method of claim 17, further comprising: transmitting, to each of the plurality of stacked memory devices, a respective individual timing signal associated with the first command.

[0089] Example 19: The method of claim 15, further comprising: based on a data bus inversion signal received via the external data interface, inverting data signals transmitted to each of the plurality of stacked memory devices.

[0090] Example 20: The method of claim 15, further comprising: transmitting individual copies of the first command to respective ones of the plurality of stacked memory devices.

[0091] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

Docket: 765-0249P - 11426US01CLAIMSWhat is claimed is:

1. A memory component, comprising:an external command / address (CA) interface to receive commands and addresses from a device external to the memory component;an external data interface to communicate data signals and timing reference signals with the device external to the memory component;a first set of stacked memory devices comprising memory cell circuitry, each of the first set of stacked memory devices to receive commands and addresses received by the memory component via the external CA interface; and a data buffer device stacked with the first set of stacked memory devices, the data buffer device to relay the data signals and timing signals between the external data interface and each of the first set of stacked memory devices.

2. The memory component of claim 1, wherein the data buffer device is to communicate separate timing signals with each of the set of stacked memory devices.

3. The memory component of claim 2, wherein the data buffer device is to communicate common, among the set of stacked memory devices, timing signals with the device external to the memory component.

4. The memory component of claim 1, wherein the data buffer device is to generate a data bus inversion signal and is to communicate the data bus inversion signal with the device external to the memory component.

5. The memory component of claim 1, wherein the data buffer device and each of the set of stacked memory devices are to communicate the data signals and timing signals via wire bonds.

6. The memory component of claim 1, wherein the data buffer device is to relay the commands and addresses between the external CA interface and each of the first set of stacked memory devices.Docket: 765-0249P - 11426US017. The memory component of claim 1, further comprising:a second set of stacked memory devices, the data buffer device to relay the data signals and timing signals between the external data interface and each of the second set of stacked memory devices.

8. An assembly, comprising:a first set of stacked memory devices each comprising at least one memory array, the at least one memory array to be accessed via signals of an external interface; anda data buffer device electrically coupled with, and stacked with, the first set of stacked memory devices, the data buffer device to communicate data signals and timing signals between the external interface and each of the first set of stacked memory devices.

9. The assembly of claim 8, wherein the data buffer device further comprises:timing signal distribution circuitry to receive a common data timing signal and to, based on the common data timing signal, distribute individual data timing signals to each of the first set of stacked memory devices.

10. The assembly of claim 8, wherein the data buffer device further comprises:data bus inversion signal circuitry to, based on the data signals communicated with the first set of stacked memory devices, communicate a data bus inversion signal via the external interface.

11. The assembly of claim 10, wherein the data buffer device further comprises:data bus inversion circuitry to, based on the data bus inversion signal, selectively invert the data signals communicated between the external interface and each of the first set of stacked memory devices.

12. The assembly of claim 8, wherein the data buffer device is to communicate command and address signals between the external interface and each of the first set of stacked memory devices.

13. The assembly of claim 12, further comprising:Docket: 765-0249P - 11426US01a second set of stacked memory devices each comprising at least one memory array, the at least one memory array to be accessed via signals of the external interface.

14. The assembly of claim 13, wherein the data buffer device is to communicate data signals and timing signals between the external interface and each of the second set of stacked memory devices.

15. A method, comprising:receiving, by a memory component comprising a first integrated circuit device stack that includes a plurality of stacked memory devices and a data buffer device, a first command to be performed by each of the plurality of stacked memory devices;communicating, by the data buffer device, data signals and timing signals associated with the first command with each of the plurality of stacked memory devices; andcommunicating, by the data buffer device, the data signals associated with the first command via an external data interface of the memory component.

16. The method of claim 15, wherein the data buffer device is electrically connected to each of the plurality of stacked memory devices using wire bonds.

17. The method of claim 15, further comprising:receiving, from the external data interface, a common timing signal associated with the first command.

18. The method of claim 17, further comprising:transmitting, to each of the plurality of stacked memory devices, a respective individual timing signal associated with the first command.

19. The method of claim 15, further comprising:based on a data bus inversion signal received via the external data interface, inverting data signals transmitted to each of the plurality of stacked memory devices.Docket: 765-0249P - 11426US0120. The method of claim 15, further comprising:transmitting individual copies of the first command to respective ones of the plurality of stacked memory devices.

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