Self alignment technique for phased array system

Abstract

Apparatus and methods are provided for self-phase alignment in a phased-array transceiver. Detectors receive a first signal from a TX-path input of a first channel and a second signal from an RX-path output of a second channel, producing a DC value representing the phase difference between the signals, iteratively adjust RX phase shifters based on the DC values until the phase difference equals a predetermined amount, then apply a corrective phase opposite in sign and equal in magnitude to that amount to generate a final alignment value for normal operation. The predetermined amount may be ±90°. Each detector may include twin double-balanced mixers, a low-pass filter, and comparator. In one embodiment, a TX phase alignment is performed before the RX phase alignment, no additional RX-phase correction is required when the TX phase-offset values determined by the TX alignment are applied to each TX phase shifter for the RX alignment.

Description

KI I -00 9-PCT PATENTSELF ALIGNMENT TECHNIQUE FOR PHASED ARRAY SYSTEMCROS S REFERENCE TO RELATED APPLICAT IONS

[0001] Thi s appl icat ion claims priority under 35 U. S. C.§11 9 from U. S. Provi sional Appl icat ion Number 63 / 71 9, 248 ent it led " RF Sel f Phase and Amplitude Al ignment Technique for Transmit Path in Phased Array Mult i-channel s Beamforming Transceiver, " fi led on Nov. 12, 2024, the sub ject matter of which i s incorporated herein by re ference. Thi s applicat ion claims priority under 35 U. S. C. §119 from U. S. Provis ional Applicat ion Number 63 / 883, 38 6 ent it led " SELF PHASE ALIGNMENT TECHNIQUE FOR RECEIVE PATHS IN A PHASED ARRAY SYSTEM, " f i led on Sept. 17, 2025, the sub j ect matter o f which i s incorporated herein by re ference.TECHNICAL F IELD

[0002] The disclosed embodiment s relate generally to transceivers, and, more part icularly, to radio frequency (RF ) sel f-phase and sel f-ampl itude al ignment.BACKGROUND

[0003] Phase and ampl itude alignment o f the t ransmit and receive channel s are crit i ca l to en sure performance o f an elect ronical ly steerable phased a rray antenna. The tradit ional al ignment methods rely upon expens ive and t ime-consuming over-the-air measurement s. There fore, there is a need to devel op more cost-e f fect ive methods o f reducing the channel phase vari at ion along with over -the-air cal ibrat ionKI I-009-PCT PATENT

[0004] FIG. 1A (prior art ) illustrates a conventional phase alignment. The conventional method for phase alignment utilizes additional source signal to down-convert from radio frequency (RF ) 116 to IF (intermediate frequency) 115. RF signal at RF FREQ. 116 is translated to IF FREQ. 115 by frequency down-conversion 113. The IF signals 115 are compared in an IF phase comparison block 111, and the resulting DC voltage control 117 feeds into RF phase adjustment 112. The same loop is replicated for N identical loops for N channels ( 118 ). It may also use a high resolution analog to digital converter (ADC) in order to distinguish the difference in phases and then adjust the phase. Furthermore, because the channels ' output is mixed with the LO, there is finite phase error contributed by the network mismatch and LO j itter.

[0005] FIG. 1B (Prior Art ) illustrates a conventional alignment. RF signal at RF FREQ. 126 is translated to IF FREQ. 125 by power detector 123. The IF signals 125 are compared in an IF amplitude comparison block 121, and the resulting DC voltage control 127 feeds into RF amplitude adjustment 122. The same loop is replicated for N identical loops for N channels ( 128 ). Similar to conventional phase alignment, conventional amplitude alignment has finite amplitude error because of the network mismatch and DC reference noise. Furthermore, the conventional approach for both phase and amplitude alignment requires that phase and amplitude be measured for every single channel.

[0006] Improvements are needed to reduce the channel phase and amplitude variation and the over-the-air calibration cost.KI I-009-PCT PATENTSUMMARY

[0007] Method and apparatus are provided for self-phase phase alignment for receiving (RX) paths of multi-channel transceiver circuits in a phased-array transceiver (TRX). In one novel aspect, the transceiver receives at a phase detector, a first signal corresponding to a transmission (TX) input of a first channel and a second signal corresponding to a receiving (RX) output of a second channel, iteratively adjusts an RX phase shift element of the second channel until a phase difference between the first and second signals equals a predetermined amount, applies a corrective phase opposite in sign and equal in magnitude to the predetermined amount to obtain a final alignment value, and configures the RX phase shift element with the final alignment value during normal operation. In one embodiment, the predetermined amount is ±90 °. In one embodiment, the TRX comprises a plurality of channels, each includes a TX path with a TX phase shift element, and a RX path with an RX phase shift element, and wherein the iteratively adjusting are performed for non-overlapping adjacent pairs of channels of the plurality of channels. In one embodiment, each iteratively adjusting is performed for non-overlapping adjacent pairs of channels of the plurality of channels. In one embodiment, in response to successful completing a RX path alignment, performing a TX path calibration that aligns TX paths across the plurality of channels.

[0008] In another novel aspect, the transceiver performs a transmission (TX) path phase alignment that aligns all TX paths the plurality of TRX channels, in response to completing the TX path phase alignment, performing, for each non-overlapping pair of adjacent TRX channels, aKI I-009-PCT PATENTreceiving (RX) path phase alignment. In one embodiment, TX phase-offset values determined by the TX path phased alignment are applied to each TX phase shift element, and wherein no phase offset correction factors are needed for each RX phase shift element after the RX alignment.

[0009] Method and apparatus are provided for self-phase and self-amplitude alignment for RF transmission. In one novel aspect, the apparatus directly compares the phase and amplitude at RF frequency and then adjusts the phase and amplitude as needed at RF frequency. In one embodiment, an apparatus with a plurality of antenna elements comprises a plurality of channels, and a plurality of detectors, each being coupled between radio frequency (RF ) signals of two channels. The detector is switchable between a phasedetection mode that detects and outputs a phase direct current (DC) value indicating a phase difference between its coupled two channels, and an amplitude-detection mode that detects and outputs an amplitude DC value indicating an amplitude difference between its coupled two channels. The apparatus further includes a plurality of controllers, each controller is coupled to a corresponding detector comprising a comparator being configured to output at least one offset value comprising a phase offset value based on the phase DC value of the corresponding detector and an amplitude offset value based on the amplitude DC value from the corresponding detector. In one embodiment, each detector is a twin double balanced mixer (TDBM) comprises a pair of double-balanced mixers (DBMs ) with identical topology. In one embodiment, each controller further comprises a calibration circuit being configured to adjust at least one corresponding phase shifter based onKI I-009-PCT PATENTcorresponding phase offset value and to adjust at least one VGA based on corresponding amplitude offset value.

[0010] Other embodiments and advantages are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1A (prior art ) illustrates a conventional phase alignment.

[0012] FIG. 1B (Prior Art ) illustrates a conventional amplitude alignment.

[0013] FIG. 1C illustrates a method for directly comparing the phase and amplitude at RF frequency.

[0014] FIG. 2 illustrates exemplary diagrams showing the self-phase and self-amplitude architecture for a transceiver.

[0015] FIG. 3A illustrates an exemplary diagram for a phase and amplitude detector that uses two identical mixers to perform phase and amplitude detection.

[0016] FIG. 3B illustrates a circuit diagram for a phase and amplitude detector that uses two identical mixers to perform phase and amplitude detection.

[0017] FIG. 4A illustrates the PDout DC value over the phase difference sweeping from 0-degrees to 360-degrees.

[0018] FIG. 4B illustrates the ADoutl and ADout2 DC value over amplitude sweeping from -20dBm to l OdBm.

[0019] FIG. 5A illustrates a block diagram depicting phase and amplitude calibration.

[0020] FIG. 5B is an exemplary process for performing transmit path phase alignment operations between the transceiver channels, according to one embodimentKI I-009-PCT PATENT

[0021] FIG. 5C is an exemplary process for performing transmit path amplitude alignment operations between the transceiver channels, according to one embodiment.

[0022] FIG. 6 is an exemplary process for performing transmit path phase alignment operations between two transceiver channels, according to an embodiment.

[0023] FIG. 7 is an exemplary process for performing transmit path amplitude alignment operations between two transceiver channels, according to an embodiment.

[0024] FIG. 8 is an exemplary process for performing transmit path amplitude and / or path alignment operations between two transceiver channels, according to an embodiment.

[0025] FIG. 9A is a diagram illustrating an exemplary transceiver channel with selectively switchable transmit and receive paths with respective variable phase shift elements and variable gain amplifiers, according to an embodiment.

[0026] FIG. 9B illustrates a diagram for multiple transceiver channels circuitry for performing phase alignment between the transceiver channels, according to an embodiment.

[0027] FIG. 9C is a diagram illustrating first and second configurations of the circuitry for performing phase alignment between a given pair of the transceiver channels, according to an embodiment.

[0028] FIG. 9D is an exemplary process for performing receive path phase alignment operations between the transceiver channels after performing transmit path phase alignment operations between the transceiver channels, according to one embodiment.KI I-009-PCT PATENT

[0029] FIG. 9E is an exemplary process for compiling a transceiver calibration table based on transceiver phase alignment operations, according to an embodiment.

[0030] FIG. 9F illustrates an exemplary embodiment of a receiver-path self-alignment configuration for a phased-array transceiver (TRX) system.

[0031] FIG. 9G illustrates an exemplary embodiment of a receiver-path self-phase and amplitude-alignment configuration in a phased-array transceiver (TRX) system.

[0032] FIG. 10A is a diagram illustrating inputs to exemplary circuitry used to perform receive path phase alignment operations between two transceiver channels, according to an embodiment.

[0033] FIG. 10B is an exemplary process for performing receive path phase alignment operations between two transceiver channels, according to an embodiment.

[0034] FIG. 11 illustrates exemplary flow chart for the self phase alignment for RX path according to an embodiment.

[0035] FIG. 12 illustrates an exemplary flow chart for performing a RX path phase alignment after a successful TX path phase alignment according to an embodiment.DETAILED DESCRIPTION

[0036] Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings.RF SELF PHASE AND AMPLITUDE ALIGNMENT FOR TRANSMIT PATH

[0037] FIG. 1C illustrates a method for directly comparing the phase and amplitude at RF frequency. In one novelKI I-009-PCT PATENTaspect, phase differences and / or amplitude differences are directly compared at RF frequency. Both the phase and amplitude of corresponding transceivers are then adjusted as needed at RF frequency. There is no need for the LO signal to go to the channel' s output, and therefore no LO distribution issues for the calibration circuit.Furthermore, LO j itter can be removed by channel-to-channel frequency mixing to DC.

[0038] A reference channel is chosen to start the calibration, and then its phase and amplitude is compared to the phase and amplitude of another channel. As an exemplary illustration, a pair of channels Channel#! of RF frequency 181 and channel#2 of RF frequency 182 are compared at RF phase & amplitude comparison module 161 and 162. DC voltage control 167a are generated based on the comparison and the phase and amplitude of channel#1 181 and / or channel#2 are adjusted. The second exemplary pair of channel#2 182 and channel#3 183 are compared at RF phase & amplitude comparison module 163 and 164. DC voltage control 167b are generated based on the comparison and the phase and amplitude of channel#3 183 are adjusted. The same loop continues until comparing and adjusting channels n-1 and n for n channels. The reference channel in the example above is channel#!, but any channel can be chosen as the reference channel.

[0039] FIG. 2 illustrates exemplary diagrams showing the self-phase and self-amplitude architecture for a transceiver. The transceiver has n channels and n-1 phase and amplitude detectors. A detector is placed between each pair of adjacent channels so that calibration proceeds pairwise along the transmit chain. Self-calibration begins at reference Channel#1 201, proceeds to Channel#2 202, thenKI I -00 9-PCT PATENTChannel # 3 203, and cont inues through Channel#N 205. Each pairwi se detector compares either phase or ampl itude o f the two channel s at RF, low-pass f i lters the product to DC, and supplies a digital deci s ion to a local cal ibrat ionf inite-state machine (FSM) that steers the downstream phase shi fter (PS ) and variable gain ampl i f ier (VGA) o f the channel being trimmed.

[0040] Within each channel block (Channel#1 201; Channel #2 202; Channel # 3 203; Channel#N 205 ), the transmit path includes a phase shi fter labeled P S and a variable-gain ampli f ier labeled VGA, fol lowed by a power ampl i f ier (PA). Sampling after the PA, such as 212, 222, 232, 252, ensures the cal ibrat ion includes the full transmit path and thus captures al l variat ions acros s PS, VGA, and PA. Each path al so may include low-noi se ampl i fier (LNA), such as 211, 221, 231, and 251. The sampled PA output s of adj acent channel s feed the corresponding interposed mixer. MIXER1 210 is between Channels # 1 and #2; MIXER2 220 i s between Channel s #2 and # 3; and MIXER (N- l ) 250 i s between Channel s # (N-1 ) and #N. For each channel, the baseband path includes a low pas s filter ( LPF ) ( LPF 215, 225, 235, 255 ) that removes high- frequency mixing product s and pas ses the DC component, a DC MUX ( 21 6, 22 6, 236, 256 ) that select s the des ired detector output (phase or ampl itude ), and a comparator ( 217, 227, 237, 257 ). The digital output o f the comparator i s consumed by a per-channel cal ibrat ion f inite-state machine (FSM) ( 218, 228, 238, 258 ), which orchestrates the cal ibrat ion sequence and feeds to the PS and VGA via P S OFFSET 282 a / 282b / 282 c / 282d and VGA OFFSET 28 l a / 28 lb / 28 l c / 28 Id.

[0041] For example, Sel f-cal ibrat ion for the transceiver start s at the reference channel #! 201. Channel #! 201 andKI I-009-PCT PATENTchannel#2 202 transmit RF signals, which go through a power amplifier (PA) 212 and 222, respectively, and then to the phase and amplitude detector. By sampling after the PA, it is possible to include the entire transmit path and address all variations. The mixer will compare the phase or amplitude of the two channels and then output the DC value to the comparator, such comparator 217 and 227, respectively. The low pass filter (LPF ), such as 215 and 225, filters out unwanted high frequency harmonics. The comparator, such as 217, and 227, will output the results as a digital signal to a finite state machine (FSM), such as FSM 218 and FSM 228. I f phase and amplitude are different between the two channels (channel#1 201 and channel#2 202 ), then the FSM 218 and 228 will adjust the phase shifter (PS ) 223, and variable gain amplifier (VGA) 224 to sweep the phase and amplitude in channel#2. The FSM 214 and 224 will output a phase offset value to a phase shifter 213 and 223 and output an amplitude offset value to the VGA 214 and 224.

[0042] Calibration starts by enabling the detector between the first channel pair and selecting that path (EN SELECT 261 for MIXER1 210 ). Channel#1 201 acts as the reference; Channel#1 and Channel#2 transmit RF signals, which are sampled at PAout from PA ( 212 and 222 ) and mixed in MIXER1 210. The LPF 215 / 225 filters the product to DC and the DC MUX 216 / 226 forwards the appropriate DC term to the comparator 217 / 227. If the comparator indicates that phase and / or amplitude between the two channels differ, the FSM 218 / 228 adjusts PS 223 and VGA 224 in Channel#2 202, sweeping phase and amplitude until the threshold criterion is met. The FSM then stores the resulting PS OFFSET 282bKI I-009-PCT PATENTand VGA OFFSET 281b for Channel#2 and disables the detector path for this pair.

[0043] Calibration between the two channels will stop, and both the phase and amplitude detector and comparator will be disabled once a threshold is reached. For example, the threshold may be that there is zero difference in phase and amplitude in an analog phase shifter and VGA, or the threshold may be that the phase and amplitude difference is below one least significant bit (LSB) in a digital phase shifter and VGA between the channels.

[0044] After calibration has been completed between channel#! 201 and channel#2 202, calibration then starts between channel#2 202 and channel#3 203. Calibration proceeds in a similar manner as described between channel#! 201 and channel#2 202. The process repeats for Channel#2 and Channel#3 using MIXER2 220 (enabled by EN SELECT 262 ). I f a difference is detected, FSM 228 / 238 adjusts PS 233 and VGA 234 of Channel#3 203, sweeps to convergence, and stores PS OFFSET 282c and VGA OFFSET 281c. The same procedure continues pairwise down the array until calibration between Channel# (N-l ) and Channel#N 205 (via MIXER (N-l ) 250 enabled by EN SELECT 265 ) is completed and PS OFFSET 282d and VGA OFFSET 281d are stored for Channel #N. Once all pairs are calibrated, the required per-channel phase offsets are known. The offset phase shift for each channel is retained in a register as offset bits; during operation, the channel ' s effective phase shift equals the originally assigned beamforming phase plus the stored PS OFFSET value. Likewise, the VGA OFFSET value is applied to realize the intended amplitude while preserving the calibrated balance. The offset phase shift register may be stored in the register as the offset bits, and therefore the new phaseKI I-009-PCT PATENTshift will be the original assigned phase shift plus the offset.

[0045] FIG. 3A illustrates an exemplary diagram for a phase and amplitude detector that uses two identical mixers to perform phase and amplitude detection. In one novel aspect, a detector compares two RF channels using a TDBM that is comprised of two identical mixers DBM 301 and DBM 302 arranged in parallel branches. The inputs to be compared are RF signal from channel#! 305 and RF signal from channel#! 306. Each branch produces a baseband DC output that can be used for amplitude readout, such as ADoutl 307 and ADout2 308, and the two branches together provide a differential phase readout Pout 309. In one embodiment, the same twin-mixer structure can be used to read either phase or amplitude directly at RF, producing a DC value that is then low-pass filtered and evaluated by a simple comparator and a calibration finite-state machine. In phase mode, the phase path is enabled while amplitude sensing is disabled. In amplitude mode, the opposite holds. Because adjacent channels are upconverted, their LO j itter is coherent and cancels after mixing down to DC. In one embodiment, the TDBM detector is placed between two adjacent channels. ADoutl 307 and ADout2 308 provide per-branch amplitude indications, and PDout 309 supplies a signed measure of phase difference.

[0046] FIG. 3B illustrates a circuit diagram for a phase and amplitude detector that uses two identical mixers to perform phase and amplitude detection. The design of double-balanced mixer (DBM) 1 320 is identical to DBM2 330. The Chi RF signal 311a will go to the MN1 381a, MN2 382a transconductance stage of the DBM1 320 and the MB1 351b, MB2 352b, MB3 353b, MB4 354b switching stage of the DBM2KI I-009-PCT PATENT330. Similarly, the Ch2 RF signal 312a will go to the MN1 381b, MN2 382b transconduct nce stage of the DBM2 330 and the MB1 351a, MB2 352a, MB3 353a, MB4 354a switching stage of the DBM1 320. By using complementary routing channels to DBMs 320 and 330, the output signal of channels 1 experiences the combined loading of Zmn_DBMl in parallel with Zmb_ DBM2, while the output signal of channel 2 experiences the combined loading of Zmn_DBM2 in parallel with Zmb_DBMl. Here, Zmn_DBMl and Zmn_DBM2 refer to the input impedances of the transconductance stages of DBM1 and DBM2, respectively, while Zmb_DBMl and Zmb_DBM2 refer to the input impedances of the switching stages of DBM1 and DBM2, respectively. Since DBM1 320 and DBM2 330 are identical, we have Zmn_DBMl = Zmn_DBM2 and Zmb_DBMl = Zmb_DBM2. As a result, the mixer input loading seen from both channels will be identical, which helps reduce the phase error of the mixer.

[0047] By utilizing twin double-balanced mixers (TDMBs ), it is possible to have the same impedance presented to both channels over process, voltage, and temperature (PVT ) variation. In other words, consistent impedance is maintained across all the channels, which is crucial for phase detectors operating at radio frequency and beyond.

[0048] Another advantage of complimentary routing channels to the DBMs is that it is easier to implement the amplitude detector in the mixers for each channel. I f the Chi represents the transmit RF signal of the channel#! where the < D is the frequency, the Al is the amplitude, the 9 is the phase, and the L0]ltter is the LO jitter. The Ch2 represents the transmit RF signal of channel#! where the a> is the frequency, the A2 is the amplitude, the 9 is the phase, and L0:itter is the LO j itter.KI I -00 9-PCT PATENT

[0049] S ince RF s ignal s o f channel #! and channel #! are upconverted us ing the same LO s ignal, the LO j itter on channel #! and on channel #! i s coherent, there fore, the LO j itter can be removed after the RF s ignal s are down-converted to DC.Chi = Al * COS (cot + 01 + LOjitter )Ch! = A2 * COS (cot + 02 + L0:1tter )

[0050] When phase cal ibrat ion i s to be performed, the phase detector is enabled by sett ing the Phase_EN ( 301 ) =1, and the ampl itude detector wi l l be disabled by making Amp_EN ( 313a and 313b ) =0. The bias o f the MN1 and MN! is opt imi zed for the best transconductance. The output loading o f the mixer is designed to have maximum output ful l swing range to increase the output DC resolution of the mixer. The mixer output DC resolut ion is de f ined as: mi smatch error of the mixer / output ful l swing range

[0051] MP 4 304 and MP T 307 are the negat ive 1 / gml loading, and the gml i s the transconductance o f the MP 4 304 and MP T 307. The MP5 305 and MP 8 308 are pos itive 1 / gm! loading, the gm! i s the transconductance of the MP5 305 and MP 8 308. The pos it ive 1 / gm! i s des igned to be equal to negat ive 1 / gml, so that the output loading wi l l have inf inite impedance for DC and there fore wil l have the maximum DC gain. The MP 6 30 6 and MP 9 30 9 are the switch to di sable the phase detector. The output DC, PDout 317, after mixing Chi and Ch2 RF signal wi l l be:PDout | DC = | 2 * A1 *A2 * cos ( 0i - 02) l

[0052] The low pass f i lter C_LPF 303 and 304 wil l f ilter out the unwanted high frequency harmonics.

[0053] When doing the ampl itude calibrat ion, the ampl itude detector is enabled by setting the Amp_EN ( 313a and 313b ) =1, and the phase detector wi l l be di sabled by makingKI I-009-PCT PATENTPhase_ EN (301 and 302 ) =0. The bias of the MN1 ( 381a, 381b) and the MN2 ( 382a and 382b) are optimized for the maximum output common mode current, usually a Class-B biasing. The MN1 381a, MN2 382a, MP1 371a, MP2 372a, MP3 373a of DBM1 320 is the amplitude detector of the Chi RF signal. It will rectify the Chi RF signal and output the ADoutl DC signal 315. MN1 381a, MN2 382a acts as the rectifier circuit, and the MP1 371a, MP2 372a, MP3 373a sense the common mode current of the MN1 381a, MN2 382a. The MP3 373a converts the current signal to voltage signal and outputs the ADoutl DC signal 315.

[0054] Similarly, for DBM2 330, MN1 381b, MN2 382b, MP1 371b, MP2 372b, MP3 373b of DBM2 330 is the amplitude detector of the Ch2 RF signal. It will rectify the Ch2 RF signal and output the ADoutl DC signal 316. The MN1 381b, MN2 382b acts as the rectifier circuit, and the MP1 371b, MP2 372b, MP3 373b sense the common mode current of the MN1 381b, MN2 382b. The MP3 373b converts the current signal to voltage signal and outputs the ADoutl DC signal 316.

[0055] There will be two DC signal outputs:2 * AlADoutl | DC = - Tl2 * A2ADout2|DC = -nThe low pass filter C_LPF will filter out the unwanted high frequency harmonics.

[0056] FIG. 4A shows the PDout DC value over the phase difference sweeping from 0-degrees to 360-degrees. The slope in the curve is the phase gain of the mixer, and it should be larger than mismatch error of the mixer / phase resolution of the phase shifter as following:KI I-009-PCT PATENTV mismatch error of the mixerPhase gain (Slope, - ) > - degree phase resolution of the phase shifter output DC resolution of the mixer= - x output full swing range phase resolution of the phase shifter

[0057] In order to have the highest phase gain to tolerate a higher mismatch error of the mixer and be capable of having a higher phase resolution of the phase shifter, the preferred phase acquisition will be at around +90 or -90 degrees. In other words, the two channels phase difference will be +90 or -90 degrees after the sweeping of the phase shifter is stopped; therefore, another code shift vector of -90 degrees or +90 degrees will be applied to the phase shifter so that the two channels' phases will be equal to each other, and then the phase calibration is done. Range 411 denotes digital=l; range 412 denotes digital=l and range 413 denotes digital=0.

[0058] FIG. 4B shows the ADoutl and ADout2 DC value over amplitude sweeping from Plowto Phigh - In one exemplary setting as shown in FIG. 4B, the sweeping is from -20dBm to l OdB, the Plow being -20dBm and Phigh being 20dBm. The slope in the curve is the amplitude gain of the mixer, and it should be larger than mismatch error of the mixer / amplitude resolution of the VGA as following:VAmplitude gain (Slope, - ) >degreemismatch error of the mixeramplitude resolution of the VGA

[0059] In order to have the highest amplitude gain so that we can tolerate a higher mismatch error of the mixer and be capable of having a higher amplitude resolution of the VGA,KI I-009-PCT PATENTthe preferred amplitude acquisition will be at larger than -l OdBm region 431. In other words, the two channels amplitude will be larger than -lOdBm in this case. Once amplitude acquisition occurs, it stops sweeping the VGA amplitude and the amplitude calibration is done.

[0060] FIG. 5A illustrates a block diagram depicting phase and amplitude calibration. A first channel input 501 and a second channel input 502 are applied to a phase & amplitude detector 511. The detector produces phase or amplitude indicative outputs shown as PDout or (ADoutl - ADout2 ) 512. PDout 512 signal is filtered by an LPF to suppress high-frequency components and then provided to a comparator 513, which outputs a digital indication of the sign to Calibration FSM 517.

[0061] In one embodiment, after phase / amplitude calibration is done, the FSM will stop sweeping the phase shifter and VGA and generate a phase and amplitude offset vector for the phase shifter and VGA. The final phase and amplitude setting for a particular beamforming setting for the phase shifter and VGA will be the sum of phase vector 505 and phase offset vector 508 and the sum of amplitude vector 506 and amplitude offset 507, respectively. Phase offset vector 508 and amplitude offset 507, in turn are derived from the calibration FSM 517. The calibration loop with FSM can be a foreground or background loop. RFin 503 is applied into PS 516 and VGA 515.

[0062] FIG. 5B is an exemplary process for performing transmit path phase alignment operations between the transceiver channels, according to one embodiment. Steps described in connection with the process of FIG. 5B may be implemented by or performed in conjunction with alignment orchestration circuitry that controls the variousKI I -00 9-PCT PATENTcomponent s as described by the proces s. In a pre ferred embodiment, F IG. 5B commences with step 531, where a control ler for al ignment operat ions init iates transmit ( TX ) phase al ignment o f channel s # 1 through #M (where M i s the total number o f transceiver channel s to be cal ibrated). At step 531, an index N for ident i fying TX channel s undergoing phase al ignment operat ions may be set to two.

[0063] Fol lowing step 531, the method may proceed to step 532, where a control ler for al ignment operations may align a phase o f TX (N ) o f TRX (N ) to TX (N- l ) of TRX (N- l ). For example, when N=2, the phase o f TX2 in TRX2 i s aligned t o the phase of TX1 in TRX1. In such an example, the phase o f TX1 may be cons idered a re ference channel to which al l the remaining TX channel s are ef fect ively al igned ( i. e., by the transit ive property of the transmit phase alignment operat ions ). In other examples, any TX channel may be used as a re ference channel to which al l the remaining TX channel s are e f fect ively aligned.

[0064] Step 532 may compri se a component step 533.General ly, step 533 involves determining a cal ibrat ion phase o f f set for TX (N ), which i s TX2 when N=2, based on the phase o f a re ference channel TX (N- l ), which i s TX1 when N=2. Speci f ic operat ions of step 533 are described by component steps 534 - 1, 534 -2, 534-3, and 534- 4. At step 534 -1, a detector coupled between an output o f TX (N- l ) and an output TX (N ) may be configured to detect phase, speci f ically to detect a phase di f ference ( i. e., PDout of F IG. 5A). When N=2, the detector configured at step 534 - 1 may correspond to MIXER1 210. In some embodiment s, step 534 -1 may correspond to sett ing Phase_EN to 1, and setting Amp_ EN to zero. At step 534 -2, transmit paths TX (N- l ) and TX (N ) o f the respect ive transceiver channel s TRX (N- l ) andKI I-009-PCT PATENTTRX (N) are enabled. At step 534-3, a controller coupled to the detector configured at step 534-1 may determine a phase offset for a variable phase shift element within TX (N) that is required to align the phase of TX (N) to TX (N-l ) based on an output of the detector configured at step 534-1.Specific operations of step 534-3 may be described by steps of FIG. 6, and are not repeated in the description of FIG.5B. At step 534-4, a controller may configure a phase shift element within TX (N) using the phase offset determined at step 534-3.

[0065] Proceeding to step 536, alignment orchestration circuitry may determine if any transceiver channel transmit paths remain that have not yet been included in phase alignment operations such as those described by step 532. I f there are indeed any remaining transceiver channels that have not yet been included in phase alignment operations, then the value of N may be incremented by one, and the method may proceed to step 532 and repeat the phase alignment operations for TX (N) relative to TX (N-l ) for the new value of N. The method of FIG. 5B may conclude with the performance of phase alignment operations for TX (N) and TX (N-l ) where N is equal to M, and M is the total number of transceiver channels.

[0066] In some embodiments, the transmit phase alignment operations of FIG. 5B align every TX path within the transceiver (TRX) channels with reference to a single TX path, such as the TX path of a first TRX, sometimes referred to as TX1 of TRX1. TX1 and TRX1 may be used as the reference transmit path to which the phases of other TX paths in other TRXs are effectively calibrated, although any TX of any TRX may be used as the reference transmit path to which phases of other TX paths in other TRXs areKI I-009-PCT PATENTcalibrated. Following the completion of transmit phase alignment operations of FIG. 5B, the phase offset configuration values for configurable phase shift elements within TX paths of the transceiver channels, determined by performance of the transmit phase alignment operations, may be applied to the configurable phase shift elements within TX paths of the transceiver paths. Following the application of the determined phase offset configuration values for phase shift elements within TX paths of the transceiver channels, all of the TX path phase angles are set to be the same angle, and additional alignment operations such as RX phase alignment operations may be performed. Due to variation in components of the individual TX paths, setting all of the TX path phase values to be the same angle, e. g. 0 ° or 100 °, may be achieved by applying different respective phase offset configuration values as determined during transmit phase alignment operations to each configurable phase shift element within the TX paths.

[0067] FIG. 5C is an exemplary process for performing transmit path amplitude alignment operations between the transceiver channels, according to one embodiment. Steps described in connection with the process of FIG. 5C may be implemented by or performed in conjunction with alignment orchestration circuitry that controls the various components as described by the process. In a preferred embodiment, FIG. 5C commences with step 581, where a controller for alignment operations initiates transmit (TX) amplitude alignment of channels #1 through #M (where M is the total number of transceiver channels to be calibrated). At step 581, an index N for identifying TX channelsKI I -00 9-PCT PATENTundergoing ampl itude al ignment operat ions may be set to two.

[0068] Fol lowing step 581, the method may proceed to step 582, where a control ler for al ignment operat ions may align an ampl itude o f TX (N ) o f TRX (N ) to an ampl itude o f TX (N-l ) o f TRX (N- l ). For example, when N=2, the ampl itude o f TX2 in TRX2 i s al igned to the ampl itude o f TX1 in TRX1. In such an example, the ampl itude o f TX1 may be considered a re ference channel amplitude to which all the remaining TX channel s are e f fect ively aligned ( i. e., by the trans it ive property of the transmit ampl itude al ignment operat ions ). In other examples, any TX channel may be used as a re ference channel to which al l the remaining TX channels are ef fect ively al igned.

[0069] Step 582 may compri se a component step 583.General ly, step 583 involves determining a cal ibrat ion amplitude of f set for TX (N ), which i s TX2 when N=2, based on the ampl itude o f a reference channel TX (N- l ), which i s TX1 when N=2. Speci f ic operat ions o f step 583 are described by component steps 584 - 1, 584 -2, 584-3, and 584- 4. At step 584 -1, a detector coupled between an output o f TX (N- l ) and an output TX (N ) may be configured to detect ampl itude, speci f ically to detect an ampl itude di f ference ( i. e., ADout l - Adout 2 o f F IG. 5A). When N=2, the detector conf igured at step 584- 1 may correspond to MIXER1 210. In some embodiment s, step 584 -1 may correspond to sett ing Amp_EN to " 1", and sett ing Phase_EN to " 0". At step 584 -2, transmit paths TX (N- l ) and TX (N ) o f the respect ive transceiver channel s TRX (N-l ) and TRX (N) are enabled. At step 584 -3, a controller coupled to the detector conf igured at step 584 - 1 may determine an ampl itude o f fset for a variable gain ampl i f ier (VGA) within TX (N ) that is requiredKI I-009-PCT PATENTto align the amplitude of TX (N) to TX (N-l ) based on an output of the detector configured at step 584-1. Specific operations of step 584-3 may be described by steps of FIG.7, and are not repeated in the description of FIG. 5C. At step 584-4, a controller may configure a VGA within TX (N) using the amplitude offset determined at step 584-3.

[0070] Proceeding to step 536, a controller may determine if any transceiver channel transmit paths remain that have not yet been included in amplitude alignment operations such as those described by step 532. If there are indeed some remaining transceiver channels that have not yet been included in amplitude alignment operations, then the value of N may be incremented by one, and the method may proceed to step 532 and repeat the amplitude alignment operations for TX (N) relative to TX (N-l ) for the new value of N.

[0071] In some embodiments, the transmit amplitude alignment operations of FIG. 5C align every TX path amplitude within the TRX channels with reference to a single TX path amplitude, such as the TX path amplitude of a first TRX, sometimes referred to as TX1 of TRX1. TX1 and TRX1 may be used as the reference transmit path to which the amplitudes of other TX paths in other TRXs are effectively calibrated, although any TX of any TRX may be used as the reference transmit path to which phases of other TX paths in other TRXs are calibrated. Following the completion of transmit amplitude alignment operations of FIG. 5C, the phase offset configuration values for configurable phase shift elements within TX paths of the transceiver channels, determined by performance of the transmit amplitude alignment operations, may be applied to the VGAs within TX paths of the transceiver paths.Following the application of the determined amplitudeKI I-009-PCT PATENToffset configuration values for VGAs within TX paths of the transceiver channels, all of the TX path amplitudes are set to be the same value. Due to variation in components of the individual TX paths, setting all of the TX path amplitude values to be the same value may be achieved by applying different respective amplitude offset configuration values as determined during transmit amplitude alignment operations to each VGA within the TX paths.

[0072] Notably, although the phase alignment and amplitude alignment processes of FIGS. 5B and 5C are presented as separate, distinct, and non-overlapping processes, such a presentation is merely illustrative and should not limit the scope of these processes. Ordinarily skilled artisans will appreciate that some embodiments may involve interleaving the processes of FIGS. 5B and 5C so that TX phase alignment and TX amplitude alignment are performed for a given pair of TRX channels before proceeding to perform TX phase alignment and TX amplitude alignment for a subsequent pair of TRX channels. As an example, in some embodiments the process of FIG. 5B performed by alignment orchestration circuitry may proceed to step 582 of FIG. 5C after performing step 532, rather than proceeding directly to step 536 of FIG. 5B. In such an example, after performing step 582 of FIG. 5C, a value of N may be incremented ( for the indices used by both FIGS. 5B and 5C ) before proceeding to step 532 of FIG. 5B. As another example, alignment orchestration circuitry in some embodiments may first perform step 582 of FIG. 5C for a given pair of TRX channels before proceeding to perform step 532 of FIG. 5B for the given pair, and thenKI I-009-PCT PATENTincrementing N ( for the indices used by both FIGS. 5C and 5B).

[0073] FIG. 6 is an exemplary process for performing transmit path phase alignment operations between two transceiver channels, according to an embodiment. The process of FIG. 6 may refer to operations performed using the TDBMs coupled between output terminals of the TX channels, specifically the operations associated with determining a phase offset of a variable phase shift element within a TX path whose calibration phase offset is being determined. The process of FIG. 6 may refer to operations performed at step 534-3 of FIG. 5B. At step 601, first and second signals are received at a phase detector. The first and second signals correspond to respective TX output signals of first and second TRXs, where a first TRX is adjacent to the second TRX. As an example, the first signals may correspond to the TX (N-l ) output and the second signals may correspond to the TX (N) output for any given value of N from 2 to M, where M is the total number of TRXs to perform phase alignment operations on. As an example, step 601 may correspond to signals 501 and 502 being received at detector 511 of FIG. 5A. At step 602, a low pass filter such as LPF 512 receives an output of the phase detector.

[0074] At step 603, an output of the low pass filter corresponding to a DC value that is proportional to a phase difference between the adjacent channels is received at a comparator such as comparator 513 of FIG. 5A. Notably, the DC value received at the comparator is proportional to the phase difference between the respective entireties of components of the adjacent channels, not just the phase difference between the configurable phase shift elementsKI I-009-PCT PATENTwithin said adjacent channels. At step 604, a digital output of the comparator, indicative of whether the phase difference between the signals for two adjacent channels is egual to a predetermined amount, is received at a calibration FSM. In some examples, a first input terminal of the comparator may receive the LPF output signal, and a second input terminal of the comparator may receive a fixed reference voltage value corresponding to phase detector output when a phase difference between the signals for two adjacent channels is egual to the predetermined amount.The predetermined amount may correspond to ±90 °. In some embodiments, a single fixed reference voltage provided to the second input terminal of the comparator may correspond to the predetermined amount of ±90 °, due to the shape of the DC output of the phase detector over the phase differences of signals at its inputs. As an example, the DC output of the phase detector (shown by FIG. 4A) may have an equivalent level when a phase difference of its input signals is +90 ° and when a phase difference of input signals is -90 °, or equivalently, 270 °.

[0075] The process then proceeds to step 605, where the calibration FSM iteratively adjusts a phase shift configuration value for a phase shift element that provides the second signals to the phase detector. Step 605 may also be referred to as sweeping the phase shift configuration value of the phase shift element in a transmit path being phase aligned to a reference transmit path. In some embodiments, the iterative adjustment of the phase shift configuration value may be performed using a binary search or by iteratively decrementing or incrementing a phase shift configuration value by a fixed step size. As an example, the sweep or iterativeKI I-009-PCT PATENTadjustment of the phase offset configuration value may begin by setting the transmit path phase shift configuration value of the phase shift element in the transmit path being aligned to a respective transmit path to a value of 0 ° and then modifying the phase offset configuration value according to a binary search method, a positive ramp method, or a negative ramp method, until the DC output of the phase detector indicates a phase difference between its input signals corresponds to the predetermined amounts of ±90 °, corresponding to phase differences of 90 ° or 270 °.

[0076] At step 606, the calibration FSM halts further adjustment or sweeping of the phase offset configuration value provided to the phase shift element that provides signals to the second input of the phase detector, in response to determining that the digital output of the comparator indicates the phase difference between the signals for two adjacent channels is equal to the predetermined amounts of ±90 °. Calibration FSM may determine that further adjustment or sweeping of the phase offset configuration value can be halted in response to a change in the output of the comparator, in embodiments where the adjustment or sweeping of the phase offset configuration value occurs by a positive ramp method ( incrementing the phase offset configuration value) or a negative ramp method (decrementing the phase offset configuration value ). Such a change in the comparator output may indicate that the phase offset configuration value has caused the DC output of the phase detector to cross the reference voltage, indicating that the phase difference between the signals for two adjacent channels is equal to the predetermined amounts of ±90 °. In embodimentsKI I-009-PCT PATENTwhere the adjustment or sweeping of the phase offset configuration occurs by a binary search method, determination of the highest resolution phase offset configuration values associated with changes to the comparator output may indicate that further adjustment or sweeping the phase offset configuration value can be halted. The two channels phase difference will be +90 ° or -90 ° after the adjustment of the of the phase offset configuration value is halted

[0077] The process then proceeds to step 607, where the system applies a code shift vector corresponding to a negative phase shift with a magnitude equal to the predetermined amount to the phase shift element that provides the second signals to the phase detector. An intermediate calibration value, corresponding to the value of the phase offset vector or configuration value at the time the adjustment was halted, may be modified by adding a predetermined offset value corresponding to the predetermined amount of phase offset from the intermediate calibration value to generate a final calibration value. As an example, if the two channels ' phase difference is +90 ° when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offset corresponding to a -90 ° (negative 90 ° ) offset to the intermediate calibration value. As another example, if the two channels ' phase difference is -90 ° (negative 90 ° ) when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offset corresponding to a +90 ° (positive 90 ° ) offset to the intermediate calibration value. Code shift vectors or phase offsets correspondingKI I-009-PCT PATENTto negative 90 ° and positive 90 ° may be determined by a processor (not illustrated), stored in a memory (not illustrated), and applied to the configurable phase shift element by the calibration FSM. The phase shift element of each transmit path may be configured using the final calibration value during normal operations. By the process of step 607, the phases of the two transmit paths input to the phase detector may be phase aligned.

[0078] At step 607, the calibration vector that aligns the phases of the first and second signals may be saved in a calibration table. In some embodiments, a configuration value during normal operations, for a configurable phase shift element within the TX channel that provides the second signals to the detector, may be based on a combination of a phase value derived from or otherwise reguired by a particular beamforming setting and the calibration vector that aligns the phases of the first and second signals.

[0079] FIG. 7 is an exemplary process for performing transmit path amplitude alignment operations between two transceiver channels, according to an embodiment. The process of FIG. 7 may refer to operations performed using the TDBMs coupled between output terminals of the TX channels, specifically the operations associated with determining an amplitude offset of a VGA within a TX path whose calibration amplitude offset is being determined.The process of FIG. 7 may refer to operations performed at step 584-3 of FIG. 5C. At step 701, first and second signals are received at an amplitude detector. The first and second signals correspond to respective TX output signals of first and second TRXs, where a first TRX is adjacent to the second TRX. As an example, the firstKI I-009-PCT PATENTsignals may correspond to the TX (N-l ) output and the second signals may correspond to the TX (N) output for any given value of N from 2 to M, where M is the total number of TRXs to perform amplitude alignment operations on. As an example, step 701 may correspond to signals 501 and 502 being received at detector 511 of FIG. 5A. At step 702, a low pass filter such as LPF 512 receives an output of the amplitude detector.

[0080] At step 703, an output of the low pass filter corresponding to a DC value that is proportional to an amplitude difference between the adjacent channels is received at a comparator such as comparator 513 of FIG. 5A. Notably, the DC value received at the comparator is proportional to the amplitude difference between the respective entireties of components of the adjacent channels, not just the amplitude difference between the configurable VGAs within said adjacent channels. At step 704, a digital output of the comparator, indicative of whether the amplitude difference between the signals for two adjacent channels is equal to a predetermined amount, is received at a calibration FSM. In some examples, a first input terminal of the comparator may receive the LPF output signal, and a second input terminal of the comparator may receive a fixed reference voltage value corresponding to amplitude detector output when a amplitude difference between the signals for two adjacent channels is equal to zero.

[0081] The process then proceeds to step 705, where the calibration FSM iteratively adjusts an amplitude shift configuration value for a VGA that provides the second signals to the amplitude detector. Step 705 may also be referred to as sweeping the amplitude shift configurationKI I-009-PCT PATENTvalue of the VGA in a transmit path being amplitude aligned to a reference transmit path. In some embodiments, the iterative adjustment of the amplitude shift configuration value may be performed using a binary search or by iteratively decrementing or incrementing an amplitude shift configuration value by a fixed step size. As an example, the sweep or iterative adjustment of the amplitude offset configuration value may begin by setting the transmit path amplitude shift configuration value of the VGA in the transmit path being aligned to a respective transmit path to a particular value and then modifying the amplitude offset configuration value according to a binary search method, a positive ramp method, or a negative ramp method, until the DC output of the amplitude detector indicates a amplitude difference between its input signals corresponds to zero amplitude difference (or a difference within 1 least significant bit (LSB) of a digital VGA configuration value).

[0082] At step 706, the calibration FSM halts further adjustment or sweeping of the amplitude offset configuration value provided to the VGA that provides signals to the second input of the amplitude detector, in response to determining that the digital output of the comparator indicates the amplitude difference between the signals for two adjacent channels is equal to zero (or is within 1 LSB of a digital VGA configuration value ).Calibration FSM may determine that further adjustment or sweeping of the amplitude offset configuration value can be halted in response to a change in the output of the comparator, in embodiments where the adjustment or sweeping of the amplitude offset configuration value occurs by a positive ramp method (incrementing the amplitude offsetKI I-009-PCT PATENTconfiguration value ) or a negative ramp method (decrementing the amplitude offset configuration value ). Such a change in the comparator output may indicate that the amplitude offset configuration value has caused the DC output of the amplitude detector to cross the reference voltage, indicating that the amplitude difference between the signals for two adjacent channels is equal to zero. In embodiments where the adjustment or sweeping of the amplitude offset configuration occurs by a binary search method, determination of the highest resolution amplitude offset configuration values associated with changes to the comparator output may indicate that further adjustment or sweeping the amplitude offset configuration value can be halted. The two channels ' amplitude difference will be zero or within one LSB of a digital VGA configuration value after the adjustment of the of the amplitude offset configuration value is halted.

[0083] The process then proceeds to step 707, where the system saves the calibration vector that aligns the amplitudes of the first and second signals in a calibration table. In some embodiments, a configuration value during normal operations, for a VGA within the TX channel that provides the second signals to the detector, may be based on a combination of an amplitude value derived from or otherwise required by a particular beamforming setting and the calibration vector that aligns the amplitudes of the first and second signals.

[0084] FIG. 8 is an exemplary process for performing transmit path amplitude and / or path alignment operations between two transceiver channels, according to an embodiment. The process of FIG. 8 may refer to operations performed using the TDBMs coupled between output terminalsKI I-009-PCT PATENTof the TX channels, specifically the operations associated with determining a phase offset of a variable phase shift element within a TX path whose calibration phase offset is being determined and / or determining an amplitude offset of a VGA within a TX path whose calibration amplitude offset is being determined. At step 801, the process configures a first detector coupled between first and second channels of the transceiver channels to operate in a phase detection mode. At step 802, in response to configuring the first detector in the phase detection mode, the process performs phase alignment operations for the first and the second channels based on outputs of the first detector. At step 803, the process configures the first detector coupled between the first and the second channels to operate in an amplitude detection mode. At step 803, the process configures the first detector coupled between the first and the second channels to operate in an amplitude detection mode. At step 804, in response to configuring the first detector in the amplitude detection mode, the process performs amplitude alignment operations for the first and the second channels based on the outputs of the first detector. At step 805, in response to performing the phase alignment operations and the amplitude alignment operations for the first and the second channels, the process configures a second detector coupled between the second channel and a third channel of the transceiver channels in the phase detection mode or the amplitude detection mode. At step 806, in response to configuring the second detector in the phase detection mode or the amplitude detection mode, the process performs the phase alignment operations or the amplitude alignment operations for the second and the third channels based on outputs of the second detector.KI I-009-PCT PATENTSELF PHASE ALIGNMENT FOR RECEIVE PATHS

[0085] Self-phase alignment for receiving (RX) paths is critical to ensure performance. In one novel aspect, RX phase alignment is performed first by iteratively adjusting RX phase shifters using mixer-based detectors that measure phase differences between paired channels. A TX calibration may subsequently be performed, generating TX phase-offset values that are used to correct stored RX alignment values. In one embodiment, a TX path phase alignment is performed first. In one embodiment, the TX path phase alignment is a self-phase alignment as described above in the application. All TX paths are aligned first to establish reference phase offsets. RX alignment is then performed using those TX offsets as a reference, such that no further RX correction is required. This arrangement provides a fully reciprocal calibration process suitable for beamforming, radar, or multi-antenna communication systems

[0086] FIG. 9A is a diagram illustrating an exemplary transceiver channel with selectively switchable transmit and receive paths with respective variable phase shift elements and variable gain amplifiers, according to an embodiment. Two switches, SW1 910a and SW2 910b, are shown in a first configuration that is selected to switch a receive path into use between a first terminal, RFout 902, and a second terminal, IF 903. The first terminal may be referred to as an RX input or a TX output of the transceiver (TRX), and the second terminal may be referred to as a TX input or RX output of the TRX. In some embodiments, the receive path may comprise a low-noise amplifier (LNA) 911a, a variable phase shift (PS ) elementKI I-009-PCT PATENT913a, a variable gain amplifier (VGA) 914a, and a mixer 912a. A receive path of a given transceiver may be referred to as a receiver and may be denoted as being "an RX of the given TRX" or generalized as being a receiver of an N-th transceiver, or "an RX (N) of a TRX (N)

[0087] A second configuration of SW1 910a and SW2 910b may be selected to switch a transmit path into use between a first terminal and a second terminal. In some embodiments, the transmit path may comprise a mixer 912b, a VGA 914b, a variable PS element 913b, and a power amplifier (PA) 911b. A transmit path of a given transceiver may be referred to as a transmitter and may be denoted as being "a TX of the given TRX" or generalized as being a transmitter of an N-th receiver, or "a TX (N) of a TRX (N). " An exemplary transceiver channel shown by Fig. 9A may also include a low-pass filter (LPF ) 915 that receives a signal from a phase detector 908 for receiver phase alignment operations in addition to other circuitries. An output of the LPF may be coupled to an input of a DC multiplexer (MUX) 916 that receives a select input from a selector 909 that is configurable to select the LPF output based on an output of the phase detector for receiver phase alignment operations to be output by the DC MUX 916. An output of the DC MUX may be coupled to an input of a comparator 917. A calibration finite-state-machine (FSM) 918 receives comparator output. It may generate offset values ("offset vectors" ), including VGA offset 919a, and PS Offset 919b, based on the value of the comparator output, or it may generate offset values that are respectively provided to the variable PS element and the VGA of both the receive path and the transmit path.KI I-009-PCT PATENT

[0088] During RX phase alignment operations, the calibration FSM 918 determines a phase offset 919b for the variable PS element of the receive path. Details of the operation of the calibration FSM during receive phase alignment operations are discussed in greater depth in the context of FIGS. 10A and 10B.

[0089] FIG. 9B illustrates a diagram for multiple transceiver channels circuitry for performing phase alignment between the transceiver channels, according to an embodiment. The transceiver circuitry comprises a plurality of channels, denoted TRX1 925a, TRX2 925b, TRX3 925c, and TRX4 925d, which may be respectively coupled to antenna elements ANTI 921a, ANT2 921b, ANT3 921c, and ANT4 921d. Each transceiver channel may be substantially identical in construction to channel 901 described in FIG.9A, including selectively switchable TX and RX paths, variable phase shifters, and calibration circuitry. Each channel includes a pair of interface terminals: a radiofrequency output terminal (RFout ) and an intermediatefrequency terminal ( IF, 927a-927d), which are used in the phase calibration operations. The arrangement shown in FIG. 9B allows the phase and amplitude relationships among adjacent or paired channels to be measured and aligned in both transmit and receive modes.

[0090] The transceiver may have N channels and N / 2 phase detectors for performing RX path phase alignment operations. Exemplary phase detectors for performing receive phase alignment operations are labeled Rmxl2 926a and Rmx34 926b. Phase detectors Rmxl2 926a and Rmx34 925b, and additional phase detectors (not illustrated) provided between pairs of transceiver channels may be twin double balanced mixers (TDBMs ) as shown in FIG 3B. AdditionalKI I-009-PCT PATENTcircuitry for performing RX path phase alignment operations may include switches coupled between first terminal (RFout ) outputs of every two transceivers or every non-overlapping pair of transceivers. Said switches are labeled Swl2 922a and Sw34 922b.

[0091] FIG. 9B also shows several phase and amplitude detectors, where there are N-l phase and amplitude detectors for N transceiver channels for performing transmit phase and transmit amplitude alignment operations, labeled Tmxl2 923a, Tmx23 923b, Tmx34 923c, and so on. TX path phase and transmit amplitude alignment operations may be performed between each pair of adjacent transceivers.

[0092] FIG. 9C is a diagram illustrating first and second configurations of the circuitry for performing phase alignment between a given pair of the transceiver channels, according to an embodiment. The first configuration 920a and second configuration 920b illustrated by FIG. 9C relate to receive phase alignment operations performed with respect to a receive path of a first transceiver channel (RX1 of TRX1 ) and a receive path of a second transceiver channel (RX2 of TRX2 ).

[0093] In the first configuration 920a, the transceiver circuitry is the same as shown in FIG. 9B, comprises a plurality of channels, denoted TRX1 925a, TRX2 925b, TRX3 925c, and TRX4 925d, which may be respectively coupled to antenna elements ANTI 921a, ANT2 921b, ANT3 921c, and ANT4 921d. Each channel includes a pair of interface terminals: a radio-frequency output terminal (RFout ) and an intermediate-frequency terminal ( IF, 927a-927d), phase detectors for performing receive phase alignment operations are labeled Rmxl2 926a and Rmx34 926b, N-l phase andKI I-009-PCT PATENTamplitude detectors for TX path, Tmxl2 923a, Tmx23 923b, Tmx34 923c; and switches including Swl2 922a and Sw34 922b.

[0094] In configuration 920a, switch Swl2 922a coupled between first terminal (RFout ) outputs of the first transceiver channel (TRX1 ) and the second transceiver channel (TRX2 ) is closed (ON 931a) to connect the RFout terminal of TRX1 925a to the RFout terminal of TRX2 925b. Also in the first configuration, a transmit path (TX1 ) of TRX1 is enabled ( 934a), and a receive path (RX2 ) of TRX2 is enabled ( 934b), so that transmissions of TX1 are received at RX2 via the path formed by the closed switch Swl2 922a. With each of the transceiver channels shown by FIG. 9C being substantially similar to the transceiver channel shown in FIG. 9A, enabling TX1 in the first configuration may involve or require disabling RX1 of TRX1 ( 934a), and enabling RX2 in the first configuration may involve or require disabling TX2 of TRX2 ( 934b). Receive phase alignment operations associated with TRX1 and TRX2 channels in the first configuration are described in FIG. 9D specifically in connection with step 954-1. In the first configuration 920a associated with receive phase alignment operations, transceiver channels other than those undergoing the receive phase alignment operations may be fully disabled ( 934c and 934d). In configuration 920a, Tmx 923a, 923b, and 923c are OFF ( 932a, 932b, and 932c). Rmx12 926a is ON ( 933a) and Rmx34 926b is OFF ( 933b).

[0095] In the second configuration 920b, the transceiver circuitry is the same as shown in FIG. 9B, comprises a plurality of channels, denoted TRX1 925a, TRX2 925b, TRX3 925c, and TRX4 925d, which may be respectively coupled to antenna elements ANTI 921a, ANT2 921b, ANT3 921c, and ANT4 921d. Each channel includes a pair of interface terminals:KI I-009-PCT PATENTa radio-frequency output terminal (RFout ) and an intermediate-frequency terminal ( IF, 927a, 927b, 927c, and 927d), phase detectors for performing receive phase alignment operations are labeled Rmxl2 926a and Rmx34 926b, N-l phase and amplitude detectors for TX path, Tmxl2 923a, Tmx23 923b, Tmx34 923c; and switches including Swl2 922a and Sw34 922b.

[0096] In second configuration 920b the switch Swl2 922a remains closed (ON 935a), transceiver channels other than TRX1 925a and TRX2 925b remain disabled ( such as 937c for TRX3 925c and 937d for TRX 925d), a receive path (RX1 ) of TRX1 925a is enabled (requiring TX1 to be disabled) ( 937a), and a transmit path (TX2 ) of TRX2 is enabled (requiring RX2 to be disabled) ( 937b). Receive phase alignment operations associated with TRX1 and TRX2 channels in this configuration are described in FIG. 9D specifically in connection with step 954-2.

[0097] FIG. 9D is an exemplary process for performing receive path phase alignment operations between the transceiver channels after performing transmit path phase alignment operations between the transceiver channels, according to one embodiment. Steps described in connection with the process of FIG. 9D may be implemented by or performed in conjunction with alignment orchestration circuitry that controls the various components as described by the process. In a preferred embodiment, FIG. 9D commences with step 952, relating to the completion of transmit phase alignment operations of TX channels of each pair of adjacent TRX channels. In some embodiments, transmit phase alignment operations of step 952 calibrates every TX path within the TRX channels with reference to a single TX path, such as the TX path of a first TRX. TX1KI I-009-PCT PATENTand TRX1 may be used as the reference transmit path to which the phases of other TX paths in other TRXs are calibrated, although any TX of any TRX1 may be used as the reference transmit path to which phases of other TX paths in other TRXs are calibrated. Following the completion of transmit phase alignment operations of step 952, the phase offset configuration values for configurable phase shift elements within TX paths of the transceiver channels determined by performance of the transmit phase alignment operations may be applied to the configurable phase shift elements within TX paths of the transceiver paths for the duration of the RX phase alignment operations, that is, all of the TX path phase angles are set to be the same angle, and the process of FIG. 9D proceeds to step 954. Due to variation in components of the individual TX paths, setting all of the TX path phase values to be the same angle, e. g.0 ° or 100 °, may be achieved by applying different respective phase offset configuration values as determined during transmit phase alignment operations to each configurable phase shift element within the TX paths.

[0098] At step 954, circuitry for performing receive phase alignment performs phase alignment operations to align a phase of RX (N-l ) in TRX (N-l ) with a phase of RX (N) in TRX (N), where N=2, 4, 6, and so on incrementing by two, up to the total number of TRXs. For example, when N=2, the phase of RX1 in TRX1 is aligned to the phase of RX2 in TRX2.

[0099] Step 954 may comprise two component steps, 954-1 and 954-2. Generally, the phase of RX (N-l ) may be aligned to the phase of RX (N) by aligning a phase of RX (N) to a phase of TX (N-l ) as described at step 954-1 and by aligning a phase of RX (N-l ) to a phase of TX (N) as described at stepKI I -00 9-PCT PATENT954 -2. The order in which the proces s o f F IG. 9D performs component steps 954 - 1 and 954 -2 can be reversed in some embodiments. Step 954 - 1 may correspond to placing the transceiver channel s whose receive phases are being al igned into the first conf igurat ion 920a i l lustrated in FIG. 9C, when N=2. Step 954 - 1 may have three component steps 955- 1, 955-2, and 955-3.

[0100] Step 955- 1 corresponds to coupl ing TX output terminal s of TRX (N- l ) and TRX (N ) by clos ing an appropriate switch interposed between said terminals, such as Sw (N-1 ) (N ) or Swl 2 when N=2. In embodiment s where step 154 -2 i s performed be fore step 954 - 1, step 955-1 may be performed as a f irst component step o f step 954 -2. Fol lowing step 955-1, the proces s proceeds to step 955-2, where TRX (N- l ) is conf igured to transmit by enabl ing TX (N- l ), and TRX (N ) is conf igured to receive by enabl ing RX (N ). When N=2, step 955-2 may correspond to the conf igurat ion o f TRX ( l ) and TRX ( 2 ) on the left o f F IG. 90. At step 955-2, TRX (N- l ) and TRX (N) may be conf igured such that RF signals output by TX (N-l ), based on intermediate frequency s ignal s IF (N- l ) that are input to TX (N- l ), are conveyed over the path formed by the closure o f the Sw (N- l ) (N ) switch, for example, when N=2, Swl 2, and received at RX (N). RX (N ) may in turn output intermediate frequency signals IF (N) that are based on the RF signal s output by TX (N- l ). IF (N ) s ignal s output by RX (N) may have an associated phase, denoted as " ZIF (N ) ". ZIF (N ) may be equal to the sum of: the phase o f the IF (N- l ) signals input to TX (N- l ) denoted as " ZIF (N- l ) ", the phase o f f set contributed by TX (N- l ), denoted as " ZTX (N- l ) ", and the phase o f f set contributed by RX (N ), denoted as " ZRX (N ) ". Although TX (N- l ) and RX (N ) may have respect ive variable P S element s within their s ignalKI I -00 9-PCT PATENTpaths, the respect ive phase o f f set s contributed by TX (N-l ) and RX (N ) may include phase o f f set s contributed by al l component s o f said s ignal paths including the variable PS element s. The phase of the IF (N ) s ignal s may be related to the phase of the IF (N-l ) s ignal s by the fol lowing equality or relat ionship: ZIF (N) = ZIF (N- l ) + ZTX (N- l ) + ZRX (N ).Rearranging terms o f said equal ity can yield the fol lowing equality: ZTX (N-l ) + ZRX (N ) = ZIF (N) - ZIF (N- l ).

[0101] Fol lowing step 955-2, the proces s proceeds to step 955-3, where an appropriate phase o f f set value for the conf igurable or variable P S element within RX (N ) is determined based on an output s ignal from the phase detector coupled to the TX (N- l ) input and the RX (N) output. The phase detector may be labeled Rmx (N- l ) (N), or Rmxl 2 when N=2. Based on the output signal from the phase detector, a cal ibrat ion FSM may provide a control s ignal, speci f ically a phase of f set conf iguration value, to the conf igurable P S element within RX (N ). Phase detector Rmx (N- l ) (N) has f irst and second input s respect ively conf igured to receive the IF (N- l ) s ignal s provided to the TX (N-l ) input and to receive the IF (N ) s ignal s provided by the RX (N ) output. For example, phase detector Rmx (N- l ) (N ) may be a twin double balanced mixer ( TDBM) when N = 2, Rmxl 2. The phase detector Rmx (N-l ) (N ) used for receiving phase al ignment at step 155-3 may output a DC value to a comparator, where the DC value output by Rmx (N- l ) (N ) i s proport ional to the phase di f ference between f irst and second input s to Rmx (N- l ) (N). Based on the DC value output by Rmx (N- l ) (N ), a comparator and a calibrat ion FSM may iterat ively adjust a phase of f set provided to the variable P S element within RX (N) based on control s ignal s provided to the variable P S element by the cal ibrat ion FSM.KI I-009-PCT PATENTIterative adjustment of the phase offset provided to the variable PS element within RX (N) may involve performing a sweep of phase offset values. In response to the DC value output by Rmx (N-l ) (N) indicating that a given adjustment to the phase offset provided to the variable PS element within RX (N) resulted in a desired predetermined phase difference between first and second inputs to Rmx (N-l ) (N), where the predetermined phase difference is 90 ° or -90 °, the iterative adjustment of the phase offset may be halted. A predetermined phase offset adjustment may then be applied to the phase offset value to subtract or add a value corresponding to a 90 ° phase offset from the phase offset value at the time the iterative adjustment of the phase offset value is halted, based on whether the adjustment of the phase offset value was halted at 90 ° or -90 °. The resulting phase offset value after application of the predetermined phase offset adjustment may be referred to as a calibrated phase offset value and may correspond to a phase offset value at which ZTX (N-l ) + ZRX (N) = ZIF (N) -ZIF (N-l ) = 0 °. Such a calibrated phase offset value may correspond to a phase offset value at which ZIF (N) = ZIF (N-1 ), and ZTX (N-l ) = -ZRX (N). In this way, the overall phase contributed by the RX (N) signal path using the calibrated phase offset value for the variable PS element within RX (N) may be aligned to the phase of the TX (N-l ) signal path, The calibrated phase offset value for the variable PS element within RX2 may be applied to the variable PS element within RX2 during normal operations of the TRXs coupled to the phased-array antenna and may be saved to a calibration table containing calibrated phase values for both TX channels and RX channels in each of the TRXs coupled to the phased array antenna.KI I -00 9-PCT PATENT

[0102] Fol lowing step 955-3, the proces s proceeds to step 954 -2, which corresponds to placing the transceiver channel s whose receive phases are being al igned, namely TRX (N- l ) and TRX (N ), into the second conf igurat ion 920b i l lustrated in FIG. 9C. Step 954-2 may have two component steps 955-4 and 955-5. In embodiment s where step 954 -2 i s performed be fore 954 -1, step 955-1 may be included as the f irst component step of step 954-2. At step 955- 4, TRX (N-1 ) may be conf igured to receive by enabl ing RX (N- l ), and TRX (N) may be conf igured to transmit by enabl ing TX (N ). At step 955- 4, TRX (N- l ) and TRX (N ) may be conf igured such that RF signal s output by TX (N ), based on intermediate frequency s ignal s IF2 that are input to TX (N ), are conveyed over the path formed by the closure of the Sw (N-l ) (N ) switch and received at RX (N- l ). RX (N-l ) may in turn output intermediate frequency s ignal s IF (N- l ) that are based on the RF s ignal s output by TX (N ). IF (N- l ) s ignal s output by RX (N-l ) may have an associated phase, ZIF (N-I ). ZIF (N- I ) may be equal to the sum o f: the phase of the IF (N ) s ignal s input to TX (N ), ZIF (N ), the phase contributed by TX (N ), ZTX (N), and the phase contributed by RX (N- l ), ZRX (N- l ).Although TX (N ) and RX (N- l ) may have respect ive variable P S element s within their s ignal paths, the respect ive phase contributed by TX (N ) and RX (N- l ) may include phase contributed by al l component s o f said signal paths including the variable P S element s, i. e., ZTX (N ) may correspond to phase shi ft through the ent ire transmit chain o f component s o f TRX (N) and ZRX (N-l ).

[0103] Fol lowing step 955- 4, the proces s proceeds to step 955-5, where an appropriate phase o f f set value for the conf igurable or variable P S element within RX (N- l ) may be determined based on an output s ignal from the phaseKI I -00 9-PCT PATENTdetector coupled to the TX (N-2 ) input and the RX (N- l ) output. Based on the output s ignal from the phase detector, a cal ibrat ion FSM may provide a control s ignal, speci f ically a phase of f set conf igurat ion value, to the conf igurable P S element within RX (N- l ). Phase detector Rmx (N- l ) (N) has f irst and second inputs respect ively conf igured to receive the IF (N ) signals provided to the TX (N ) input and to receive the IF (N- l ) s ignal s provided by the RX (N- l ) output. The phase detector Rmx (N- l ) (N) used for RX phase al ignment at step 155-5 may output a DC value to a comparator, where the DC value output by Rmx (N- l ) (N) may be proport ional to the phase di f ference between f irst and second input s to Rmxl 2. Based on the DC value output by Rmx (N- l ) (N ), a comparator and a calibrat ion FSM may iterat ively adjust a phase o f f set provided to the variable P S element within RX (N- l ). Iterat ive adjustment of the phase o f f set provided to the variable PS element within RX (N-l ) may involve per forming a sweep o f phase o f f set values. In response to the DC value output by Rmx (N- l ) (N ), indicat ing that a given adjustment to the phase o f f set provided to the variable P S element within RX1 resulted in a desired predetermined phase di f ference between first and second input s to Rmx (N- l ) (N), where the predetermined phase di f ference i s ± 90 °, the iterat ive adjustment o f the phase o f f set may be halted. A predetermined phase o f f set adjustment may then be applied to the phase o f f set value to subtract or add a value corresponding to a 90 ° phase (based on whether the of f set value corresponds to a pos it ive or negat ive 90 ° phase o f fset ) from the phase o f f set value at the time the iterat ive adjustment o f the phase o f fset value i s halted. The resulting phase of f set value after applicat ion o f the predetermined phase o f f set adjustmentKI I -00 9-PCT PATENTmay be re ferred to as a calibrated phase o f fset value and may correspond to a phase of f set value at which ZTX (N ) + ZRX (N- l ) ZIF (N- I ) - ZIF (N ) = 0 °. Such a cal ibrated phase o f f set value may correspond to a phase o f f set value at which ZIF (N- l ) = ZIF (N ) and ZTX (N ) = -ZRX (N- l ). In thi s way, the overal l phase o f f set cont ributed by the RX1 s ignal path us ing the cal ibrated phase of f set value for the variable PS element within RX (N- l ) within may be cons idered to be al igned to the phase of f set o f the TX (N) s ignal path, where the phase o f f set contributed by the TX (N ) signal path i s already al igned phase based on operat ions corresponding to phase al ignment o f the TX channel s performed at step 952. The cal ibrated phase of f set value for the variable P S element within RX (N- l ) may be appl ied to the variable PS element within RX (N- l ) during normal operat ions o f the TRXs coupled to the phased-array antenna and may be saved to a cal ibrat ion table containing calibrated phase values for both TX channel s and RX channel s in each o f the TRXs coupled to the phased array antenna.

[0104] Notably, due to the alignment o f RX channel s being performed by aligning RX channels to already-al igned TX channels (by step 952 ), RX channel phase al ignment requires that only unique pairs of RX channel s to be al igned or cal ibrated t o one another, that is RX (M) to RX (N ) where Hand N are channel numbers, M does not equal N, and channel numbers can only be selected once. In other words, the embodiment o f F IG. 9D can perform RX channel phase al ignment by aligning unique pairs o f RX channel s in TRXs, e. g. RX1 / RX2, RX3 / RX4, RX5 / RX6, and so on. By performing al ignment of unique pairs of RX channels in adj acent TRXs the total number o f reconf igurat ions or operat ions as sociated with receive phase al ignment may beKI I-009-PCT PATENTreduced relative to performing alignment of all RX channels to a single reference RX channel.

[0105] FIG. 9E is an exemplary process for compiling a transceiver calibration table based on transceiver phase alignment operations, according to an embodiment. The exemplary process of FIG. 9E may overlap significantly with the exemplary process of FIG. 9D. Steps described in connection with the process of FIG. 9E may be implemented by or performed in conjunction with alignment orchestration circuitry that controls the various components as described by the process. The process of FIG. 9E begins with step 972 of complete phase alignment of TX channels, which may be equivalent to step 952 of FIG. 9D. The process then proceeds to step 974 that performs phase alignment of RX channels of first pair of TRXs, which may be equivalent to steps 954 and 956 of FIG. 9D. The process then proceeds to step 976 that performs phase alignment of RX channels of next non-overlapping pairs of TRXs, which may be equivalent to steps 958 and (the first performance of ) step 960 of FIG. 9D. The process then proceeds to step 978 that performs phase alignment of RX channels of subsequent remaining non-overlapping paris of TRXs, which may be equivalent to the remaining performances (or iterations ) of steps 952, 954, 964, and 960 of FIG. 9D. The process proceeds to step 980. At step 980, a TRX calibration table is compiled based on calculations using determined TX calibration factors, such as the TX calibration factors determined at step 972, and determined RX calibration factors, such as the RX calibration factors determined at steps 974, 976, and 978.

[0106] An exemplary calibration table may include rows corresponding to TRX channels, columns corresponding to TXKI I-009-PCT PATENTcalibration factors for each respective TRX channel, and RX calibration factors for each respective TRX channel that are calculated / determined based on the TX calibration factors. In preferred embodiments where TX phase alignment is performed prior to RX phase alignment, and where the phase offset configuration values for TX channel PS elements determined by TX phase alignment operations are applied to the TX channel PS elements during RX phase alignment operations, no additional correction factors to the phase offset configuration values for RX channel PS elements determined may be required after RX phase alignment operations have been performed. Other embodiments may determine initial RX channel PS element configuration values by first performing RX channel phase alignment using TX channel PS elements that are set to some predetermined reference value, followed by determining TX channel PS element configuration values by subsequently performing TX channel phase alignment, and finally followed by determining final RX channel PS element configuration values by applying respective correction values, that are based on the determined TX channel PS element configuration values, to the initial RX channel PS element configuration values. In such other embodiments where the order of RX channel phase alignment and TX channel phase alignment is reversed relative to preferred embodiments, i. e., embodiments where TX channel phase alignment is performed after RX channel phase alignment, the TX channel phase alignment may be performed as the RX channel phase alignment has been described above in connection with FIG.9D.

[0107] The following sections describe self-phase and self-amplitude alignment for RX path. Methods andKI I -00 9-PCT PATENTapparatus are provided to perform RX path phase and / or amplitude al ign after succes s ful TX path al ignment.Detailed exemplary procedures and apparatus are provided. S imilar procedures appl ies to TX path sel f-phase and sel famplitude al ignment after success ful RX path al ignment.

[0108] FIG. 9F i l lustrates an exemplary embodiment of a receiver-path sel f-alignment configuration for a phased-array transceiver ( TRX) system. The system includes four transceiver channel s, labeled TRX1 ( 925aa ), TRX2 ( 925bb ), TRX3 ( 925cc ), and TRX4 ( 925dd), opt ional ly respect ively coupled to antenna element s ANT I ( 921 aa ), ANT2 ( 921bb ), ANT3 ( 921 cc ), and ANT4 ( 921dd). Each transceiver includes a transmit sect ion ( TX1 91 a, TX2 91b, TX3 91c, TX4 91d) and a receive sect ion (RX1 92 a, RX2 92b, RX3 92 c, RX4 92d).Each channel has a detector input, Detector 928 aa, 928bb, 928 cc, and 928dd for TRX1, TRX2, TRX3, and TRX4, respect ively. Each sect ion contains a variable phase shi fter (PS ), variable-gain ampl i f ier (VGA), and mixer.Channel operat ion i s governed by individual select l ines SEL 922 aa, SEL 922bb, SEL 922 cc, and SEL 922dd, which independent ly enable or di sable the transmit and receive paths o f each TRX during cal ibrat ion or normal operat ion.

[0109] The conf igurat ion further includes N- l receivepath detectors for ampl itude and phase implemented as twin double-balanced mixers ( TDBMs ): Rmxl 2 ( 92 6aa ), Rmx23 ( 92 6bb ), and Rmx34 ( 926cc ).Each detector i s configured to compare the RX-path output s ignal s o f two adj acent TRX channel s and to produce a DC output indicat ive o f the ampl itude or phase di f ference between the compared RX output s. For example, Rmxl 2 ( 92 6aa ) compares RX1 ( 92 a ) and RX2 ( 92b ); Rmx23 ( 92 6bb ) compares RX2 ( 92b ) and RX3 ( 92 c ); and Rmx34 ( 92 6cc )KI I -00 9-PCT PATENTcompares RX3 ( 92c ) and RX4 ( 92d). Transmit-path detectors Tmxl 2 ( 923aa ), Tmx23 ( 923bb ), and Tmx34 ( 923cc ) may be included for TX cal ibrat ion but remain inactive during RX al ignment.

[0110] FIG. 9F al so shows an exemplary channel 901 a.Each transceiver channel, exempli f ied by Channel # 1 ( 901 a ), includes a pair o f s ignal terminal s and internal cal ibrat ion circuitry. A first terminal ( IF_RXOUT 903a ) corresponds to the RX-path output interface. A second terminal, the input to the TX path i s denoted IF_ TXIN 904 a. Within Channel # 1 ( 901a ), the receive path includes a low-noi se ampli f ier ( LNA 911 a ), a variable phase shi fter (PS 913a ), a variable-gain ampli f ier (VGA 914 a ), and a mixer 912 a coupled to the IF_RXOUT 903a terminal. The transmit path includes a mixer 912b, a VGA 914b, a phase shi fter 913b, and a power ampli f ier (PA 911b ) is electrically coupled to LNA 911 aa by swit ch 910 a. The internal cal ibrat ion loop compri ses a low-pas s fi lter ( LPF 915 ) that receives detector output s, a DC mult iplexer (DC MUX 91 6 ), a comparator 917, and a cal ibrat ion f inite-state machine (FSM 918 ). The FSM may store or generate both a VGA o f f set 91 9a and a phase-shi fter of f set 91 9b for use in al ignment operat ions. The comparator output indicates the sign of the detector ' s DC voltage, and the FSM computes a corresponding correct ion code to adjust the RX phase shi fter or VGA of the channel.

[0111] FIG. 9G i l lustrates an exemplary embodiment of a receiver-path sel f-phase and amplitude-al ignment conf igurat ion in a phased-array transceiver ( TRX ) system. The embodiment comprises four transceiver channels TRX1 ( 925aa ), TRX2 ( 925bb ), TRX3 ( 925cc ), and TRX4 ( 925dd), respect ively may be coupled to antenna element s ANT IKI I -00 9-PCT PATENT( 921aa ), ANT2 ( 921bb ), ANT3 ( 921cc ), and ANT 4 ( 921dd).Each TRX includes a transmit path, a receive path, and as sociated switches ( SEL 922 aa- 922dd) that selectively connect RF terminal s of adj acent channel s to the corresponding mixers for cal ibrat ion. Each TRX also contains internal enable controls— TX ON / RX ON 934aa- 934dd, 937 aa- 937dd— to act ivate or deact ivate it s transmit and receive chains during cal ibrat ion. Only the transceivers participating in the current compari son are switched on; al l other transceivers and their as sociated mixers may be di sabled to i solate the measurement paths.

[0112] During RX-path alignment, the system sequent ial ly compares ad acent-channel pairs us ing N- l detectors implemented as twin double-balanced mixers ( TDBMs ): Rmxl 2 ( 92 6aa ) couples between TRX1 ( 925aa ) and TRX2 ( 925bb ), Rmx23 ( 92 6bb ) couples between TRX2 ( 925bb ) and TRX3 ( 925cc ), and Rmx34 ( 92 6cc ) couples between TRX3 ( 925cc ) and TRX4 ( 925dd). Addit ional transmit-mode detectors Tmxl 2 ( 923aa ), Tmx23 ( 923bb ), and Tmx34 ( 923cc ) may be provided for TX-path cal ibrat ion but remain di sabled during the RX al ignment sequence. Each channel al so has a detector input, Detector 928 aa, 928bb, 928cc, and 928dd for TRX1, TRX2, TRX3, and TRX4, respect ively. Intermediate-frequency ( IF ) terminal s IF 1 - IF4 ( 927aa- 927dd) represent IF. IF la, IF2 a, IF3a and IF 4 a ( 92 9aa- 92 9dd) are IF_ RXout, each connected t o corresponding mixers.

[0113] In one embodiment, sel f-phase and ampl itude al ignment for RX paths i s performed after the succes s ful complet ion o f the TX path al ignment that al igns all TX paths the plurality of channel s. At 920 c for a given pair ( for example, TRX1 and TRX2 ), both TX and RX paths o f the part icipat ing channels are enabled ( TX1 0N / RX1 ON, TX2KI I-009-PCT PATENT0N / RX2 ON), while remaining channels (TRX3 and TRX4 ) are disabled (TX3 OFF / RX3 OFF, TX4 OFF / RX4 OFF ). The corresponding receive-path mixer Rmxl2 ( 926aa) is enabled. Other mixers (Rmx23, Rmx34 ) may be disabled.

[0114] The signal flow is IFlin to TX1 to RX1 IFlout to Rmxl2 and IF2in to TX2 to RX2 to IF2out to Rmxl2. The mixer output will be| IF1 | + | TX1 | + | RX1 | - | IF2 | - | TX2 | - | RX2 | Since TX amplitude is calibrated first, that is:I IF1 | + | TX1 | = | IF2 | + | TX2 |We have mixer output = I RX1 | - | RX2. Using mixer output to adjust the VGA in RX2 to make. | RX2 | = | RX1 |

[0115] At 920d, we compare channel 2 and 3. Select to amplitude mode. TX2 on, RX2 on, TX3 on, and RX3 on. Rmx23 on. Others are off. Signal path is: IF2INto TX2 to RX2 to Rmx23, and IF3INto TX3 to RX3 to Rmx23. The mixer output will be:| IF2 | + | TX2 | + | RX2 | - | IF3 | - | TX3 | - | RX3 | Since TX phase is calibrated first, that is:| IF2 | + | TX2 | = | IF3 | + | TX3 |We have mixer output = | RX2 | - | RX3. Using mixer output to adjust the VGA in RX3 to make I RX3 I = | RX2 |.

[0116] By the same way, we can have | RX3 | = | RX4 |, | RX4 | = | RX5 |... | RXn-1 | = | RXn | (n >1 ). Which means | RXn | = | RXn-1 |...= | RX4 | = | RX3 | = | RX2 | = | RX1 |. RX channels amplitude alignment is completed

[0117] 920c and 920d setting similarly applies for RX path phase alignment after the successful completion of the TX path alignment that aligns all TX paths the plurality of channels. First, at 920c We turn on both TX and RX for the two adjacent channels and the mixer we want to compare, and turn off both TX and RX for the channels and mixers notKI I-009-PCT PATENTused in the comparison. At 920c, we compare channel #1 and #2. Select to phase mode. TX1 on, RX1 on, TX2 on, and RX2 on. Rmxl2 on. Others are off. The signal paths are IF1INTX1 — RX1 IF IQUT “* Rmxl2 and IF2IN— TX2 — RX2 — IF20UT Rmxl2. The mixer output will beZIF1 + ZTX1 + ZRX1 - ZIF2 - ZTX2 - ZRX2Since TX phase is calibrated first, that is:ZIF1 + ZTX1 = ZIF2 + ZTX2.We have mixer output = ZRX1 - ZRX2. Using mixer output to adjust the phase shifter in RX2 to make ZRX2 = ZRX1

[0118] Subsequently, at 920d, we compare channel #2 and #3. Select to phase mode. TX2 on, RX2 on, TX3 on, and RX3 on. Rmx23 on. Others are off. The signal path is IF2iNto TX2 to RX2 to IF20UT to Rmx23, and IF3ZNto TX3 to RX3 to IF3QUT to Rmx23.The mixer output will be:ZIF2 + ZTX2 + ZRX2 - ZIF3 - ZTX3 - ZRX3Since TX phase is calibrated first, that is:ZIF2 + ZTX2 = ZIF3 + ZTX3We have mixer output = ZRX2 - ZRX3. Using mixer output to adjust the phase shifter in RX3 to make ZRX3 = ZRX2.

[0119] By the same way, we can have ZRX3 = ZRX4, ZRX4 = ZRX5... ZRXn-1 = ZRXn (n >1 ). Which means ZRXn =ZRXn-l...= ZRX4 = ZRX3 = ZRX2 = ZRX1. RX channels phase alignment is complete.

[0120] FIG. 10A is a diagram illustrating inputs to exemplary circuitry used to perform receive path phase and amplitude alignment operations between two transceiver channels, according to an embodiment. The phase detector of FIG. 10A may correspond to the TDBMs coupled between IFOUT terminals of the TRX channels, CHI 1001 and CH2 1002.KI I-009-PCT PATENTA signal output by the phase detector of FIG. L OA may be provided to circuitry coupled to a LPF 1012, comparator 1013, and calibration FSM 1017 of each TX and RX signal path of a TRX channel. A calibration FSM 1017 may output a control signal that adjusts the phase offset 1008 configuration of a variable phase shift element based on the signal output by the phase detector of FIG. 10A. Phase vector for PS 1016 is based on the sum of Phase vector 1005 and phase offset vector 1008. VGA 1105 uses amplitude vector which is based on the sum of amplitude vector 1006 and amplitude offset vector 1007. The calibration loop with FSM can be a foreground or background loop. RFin 1003 is applied into PS 1016 and VGA 1015.

[0121] FIG. 10B is an exemplary process for performing receive path phase alignment operations between two transceiver channels, according to an embodiment. The process of FIG. 10B may refer to operations performed by the TDBMs coupled between IF terminals of the TRX channels, specifically the operations associated with determining a phase offset of a variable phase shift element within an RX path whose calibration phase offset is being determined. At step 1081, first and second signals are received at a phase detector. The first and second signals correspond to TX input signals to a first TRX and RX output signals from a second TRX that is adjacent to the first TRX. As an example, the first signals may correspond to the IF1 inputs provided to TX1 in the first configuration of transceiver channels shown on the left of FIG. 9C, in connection with step 954-1 of FIG. 9D. In such an example, the second signals may correspond to the IF2 outputs output by RX2 in the first configuration of transceiver channels shown on the right of FIG. 9C, in connection with step 954-2 of FIG.KI I-009-PCT PATENT9D. At step 1082, a low pass filter receives an output of the phase detector.

[0122] At step 1083, an output of the low pass filter corresponding to a DC value that is proportional to a phase difference between the adjacent channels is received at a comparator. Notably, the DC value is proportional to the phase difference between the respective entireties of components of the adjacent channels, not just the phase difference between the configurable phase shift elements within said adjacent channels. At step 1084, a digital output of the comparator, indicative of whether the phase difference between the signals for two adjacent channels is equal to a predetermined amount, is received at a calibration FSM. In some examples, a first input terminal of the comparator may receive the signal mentioned at step 1083, and a second input terminal of the comparator may receive a fixed reference voltage value corresponding to phase detector output when a phase difference between the signals for two adjacent channels is equal to the predetermined amount. The predetermined amount may correspond to ±90 °. In some embodiments, a single fixed reference voltage provided to the second input terminal of the comparator may correspond to the predetermined amount of ±90 °, based on the shape of the DC output of the phase detector over the phase differences of signals at its inputs. As an example, the DC output of the phase detector may have an equivalent level when a phase difference of its input signals is +90 ° and when a phase difference of input signals is -90 °, or equivalently, 270 °.

[0123] The process then proceeds to step 1085, where the calibration FSM iteratively adjusts a phase shift configuration value for a phase shift element that providesKI I-009-PCT PATENTthe second signals to the phase detector. Step 1085 may also be referred to as sweeping the phase shift configuration value of the phase shift element in a receive path being aligned to a respective transmit path. In some embodiments, the iterative adjustment of the phase shift configuration value may be performed using a binary search or by iteratively decrementing or incrementing a phase shift configuration value by a fixed step size. As an example, the sweep or iterative adjustment of the phase offset configuration value may begin by setting the receive path phase shift configuration value of the phase shift element in the receive path being aligned to a respective transmit path to a value of 0 ° and then modifying the phase offset configuration value according to a binary search method, a positive ramp method, or a negative ramp method, until the DC output of the phase detector indicates a phase difference between its input signals corresponds to the predetermined amounts of ±90 °, corresponding to phase differences of 90 ° or 270 °.

[0124] At step 1086, the calibration FSM halts further adjustment or sweeping of the phase offset configuration value provided to the phase shift element that provides signals to the second input of the phase detector, in response to determining that the digital output of the comparator indicates the phase difference between the signals for two adjacent channels is equal to the predetermined amounts of ±90 °. Calibration FSM may determine that further adjustment or sweeping of the phase offset configuration value can be halted in response to a change in the output of the comparator, in embodiments where the adjustment or sweeping of the phase offset configuration value occurs by a positive ramp methodKI I-009-PCT PATENT( incrementing the phase offset configuration value) or a negative ramp method (decrementing the phase offset configuration value ). Such a change in the comparator output may indicate that the phase offset configuration value has caused the DC output of the phase detector to cross the reference voltage, indicating that the phase difference between the signals for two adjacent channels is equal to the predetermined amounts of ±90 °. In embodiments where the adjustment or sweeping of the phase offset configuration occurs by a binary search method, determination of the highest resolution phase offset configuration values associated with changes to the comparator output may indicate that further adjustment or sweeping the phase offset configuration value can be halted. The two channels phase difference will be +90 ° or - 90 ° after the adjustment of the of the phase offset configuration value is halted.

[0125] The process then proceeds to step 1087, where the system applies a code shift vector corresponding to a negative phase shift with a magnitude equal to the predetermined amount to the phase shift element that provides the second signals to the phase detector. An intermediate calibration value, corresponding to the value of the phase offset vector or configuration value at the time the adjustment was halted, may be modified by adding a predetermined offset value corresponding to the predetermined amount of phase offset from the intermediate calibration value to generate a final calibration value. As an example, if the two channels ' phase difference is +90 ° when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offset correspondingKI I-009-PCT PATENTto a -90 ° (negative 90 ° ) offset to the intermediate calibration value. As another example, if the two channels ' phase difference is -90 ° (negative 90 ° ) when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offset corresponding to a +90 ° (positive 90 ° ) offset to the intermediate calibration value. Code shift vectors or phase offsets corresponding to negative 90 ° and positive 90 ° may be determined by a processor (not illustrated), stored in a memory (not illustrated), and applied to the configurable phase shift element by the calibration FSM. The phase shift element of each receive path may be configured using the final calibration value during normal operations. By the process of step 1087, the phases of the two channels input to the phase detector may be phase aligned

[0126] At step 1087, the calibration vector that aligns the phases of the first and second signals may be saved in a calibration table. In some embodiments, such as when TX phase alignment is performed after RX phase alignment, the TX phase shift element calibration vector or value that aligns the phase of a given TX channel to a reference TX channel may be used to determine a correction factor to be applied to the RX phase shift element calibration vector or value determined to align the phase of an RX channel that was aligned to said given TX channel prior to TX phase alignment operations. The calibration table may include the RX phase shift element calibration vector or values that have been adjusted by said correction factor.

[0127] FIG. 11 illustrates exemplary flow chart for the self-phase alignment for RX path according to an embodiment. At step 1101, the process receives, at a phaseKI I-009-PCT PATENTdetector, a first signal corresponding to a transmission (TX) input of a first channel and a second signal corresponding to a receiving (RX) output of a second channel. At step 1102, the process iteratively adjusts an RX phase shift element of the second channel until a phase difference between the first and second signals equals a predetermined amount. At step 1103, the process applies corrective phase opposite in sign and equal in magnitude to the predetermined amount to obtain a final alignment value. At step 1104, the process configures the RX phase shift element with the final alignment value during normal operation.

[0128] FIG. 12 illustrates an exemplary flow chart for performing a RX path alignment according to an embodiment. At step 1201, the process a detector in a phase detection mode. At step 1202, the process receives at the detector, first and second signals associated with respective first and second channels of the TRX. At step 1203, the process at a calibration controller, receives an output of the detector, and based on the output of the detector, determines an RX phase offset value for a reception (RX) path of the second channel of the TRX.

[0129] FIG. 13 is an exemplary process for performing receive path amplitude alignment operations between two RX paths in different respective channels, according to an embodiment. The process of FIG. 13 may refer to operations performed by controllers based on outputs from the TDBM detectors coupled between RX output terminals of the TRX channels, specifically the operations associated with determining an amplitude offset of a variable gain amplifier within an RX path whose calibration amplitude offset being determined, i. e., a given RX path undergoingKI I-009-PCT PATENTan amplitude alignment process or operation relative to a reference RX path. The process of FIG. 13 may correspond or otherwise relate to the amplitude-alignment operation configurations of the TRXs and detectors described above in connection with FIG. 9G. At step 1301, a switch within a first transceiver channel, i. e., a reference channel, may be configured to couple a TX path output of the first TRX channel to a RX path input of the first TRX channel, corresponding to a configuration of SWla 910aa and SWlb 910bb of FIG. 9F. At step 1301, another switch, within a second transceiver channel, i. e., a channel undergoing amplitude alignment operations, may be similarly configured to couple its TX path output to its RX path input. At step 1302, first and second signals are received at an amplitude detector, i. e., a detector or TDBM configured to detect amplitude. The first and second signals may respectively correspond to RX output signals from a first TRX and RX output signals from a second TRX. RX output signals from the first TRX may be based on output signals from a TX path of the first TRX that receives IF1 input signals such as IF_TXIN 904a or IF1 927aa of FIG. 9F. RX output signals from the second TRX may be similarly based on output signals from a TX path of the second TRX that receives IF2 input signals such as IF2 927bb of FIG. 9F. As an example, the first signals may correspond to the RX output of TRX1 in the configuration of transceiver channels shown by 920c of FIG. 9G, and the second signals may correspond to the RX output of TRX2 in the configuration of transceiver channels shown by 920c of FIG. 9G. In such an example, the detector may correspond to Rmxl2 926aa, which may be configured in an amplitude detection mode for the process of FIG. 13. At step 1303, a low-pass filter receives an output of theKI I-009-PCT PATENTdetector. An output signal of the detector may be proportional to the amplitude difference between the RX outputs of the first and second channels.

[0130] At step 1304, an output of the low pass filter, corresponding to a DC value that is proportional to an amplitude difference between the RX output of TRX1, i. e., RX1, and the RX output of TRX2, i. e., RX2, is received at a comparator. Notably, the DC value is proportional to the amplitude difference between the outputs produced by respective entireties of components of RX1 and RX2, not just the amplitude difference between the VGAs within RX1 and RX2. At step 1305, a digital output of the comparator, indicative of whether the amplitude difference between the signals output by RX1 and RX2 is within 1 least significant bit (LSB) of a VGA setting for the second channel, is received at a calibration FSM in TRX2. In some examples, a first input terminal of the comparator may receive the signal mentioned at step 1303, and a second input terminal of the comparator may receive a fixed reference voltage value corresponding to amplitude detector output when an amplitude difference between the signals output by RX1 and RX2 is within 1 LSB of a VGA setting for the second channel (or, when an amplitude difference between the signals for first and second channels is equal to zero ).

[0131] The process then proceeds to step 1306, where the calibration FSM iteratively adjusts an amplitude shift configuration value for a VGA in the second channel RX path that provides the second signals to the phase detector.Step 1306 may also be referred to as sweeping the amplitude shift / offset configuration value of the VGA in a (second) receive path being aligned to a reference ( first ) receive path. In some embodiments, the iterative adjustment of theKI I-009-PCT PATENTamplitude offset configuration value may be performed using a binary search or by iteratively decrementing or incrementing an amplitude offset configuration value by a fixed step size. As an example, the sweep or iterative adjustment of the amplitude offset configuration value may begin by setting the receive path amplitude offset configuration value of the VGA in the receive path being aligned (RX2 ) to a reference receive path (RX1 ) to a baseline value (e. g., unity gain) and then modifying the amplitude offset configuration value according to a binary search method, a positive ramp method, or a negative ramp method, until the DC output of the amplitude detector indicates an amplitude difference between its input signals is within 1 LSB of a setting for a VGA in the second channel (or, the amplitude difference is equal to zero ).

[0132] At step 1307, the calibration FSM halts further adjustment or sweeping of the amplitude offset configuration value provided to the VGA of the RX2 path that provides signals to the second input of the phase detector, in response to determining that the digital output of the comparator indicates the amplitude difference between the signals for the first and second receive paths, RX1 and RX2, is within 1 LSB of a setting for a VGA in the RX path undergoing the alignment process (or, indicates the amplitude difference is equal to zero ). Calibration FSM may determine that further adjustment or sweeping of the amplitude offset configuration value can be halted in response to a change in the output of the comparator, in embodiments where the adjustment or sweeping of the phase offset configuration value occurs by a positive ramp method ( incrementing the phase offset configuration value) or a negative ramp method (decrementing the phase offsetKI I-009-PCT PATENTconfiguration value ). Such a change in the comparator output may indicate that the amplitude offset configuration value has caused the DC output of the amplitude detector to cross a reference voltage, indicating that the amplitude difference between the signals for two adjacent channels is within 1 LSB of a setting for the VGA in the second channel, or egual to zero. In embodiments where the adjustment or sweeping of the amplitude offset configuration occurs by a binary search method, determination of the highest resolution amplitude offset configuration values (e. g., amplitude offset configuration values differing by 1 LSB) associated with changes to the comparator output may indicate that further adjustment or sweeping the amplitude offset configuration value can be halted. The two channels amplitude difference will be egual to zero or within 1 LSB of the setting for a VGA in the RX path undergoing the alignment process after the adjustment of the amplitude offset configuration value is halted.

[0133] The process then proceeds to step 1308, where the system saves an amplitude vector (that is based on the amplitude offset configuration value reached at step 1307 ) that aligns the amplitude of signals output by the RX path in the second channel to the amplitude of signals output by the RX path in the first channel. The amplitude vector may be saved in a calibration table. In some embodiments, such as when TX amplitude alignment is performed after RX amplitude alignment, the TX amplitude vector or value that aligns the phase of a given TX path in a particular channel to a reference TX path in a reference channel may be used to determine a correction factor to be applied to the RX amplitude vector determined to align the phase of an RXKI I-009-PCT PATENTpath in the particular channel to a reference RX path in the reference channel. The calibration table may include the RX path amplitude vectors that have been adjusted by said correction factor where applicable. The process of FIG. 13 may proceed to be repeated for each subsequent pair of RX paths in TRXs as described in connection with 920c and 920d of FIG. 9G. Although the description of the process of FIG. 13 refers to RX1 and RX2 as examples, using RX1 as the reference path, the process of FIG. 13 may be performed for any pair of RX paths, using any given RX path as a reference path to which the other RX path is aligned. As an example, the process of FIG. 13 may be performed for the pairs RX1 / RX2, RX2 / RX3, RX3 / RX4, and so on.

[0134] FIG. 14 is an exemplary process for performing RX path phase alignment operations between two RX paths in different respective channels, according to an embodiment. The process of FIG. 14 may refer to operations performed by the controllers based on outputs from the TDBM detectors coupled between RX output terminals of the TRX channels, specifically the operations associated with determining a phase offset of a variable phase shift element within an RX path whose calibration phase offset is being determined, i. e., a given RX path undergoing a phase alignment process or operation relative to a reference RX path. The process of FIG. 14 may correspond or otherwise relate to the phasealignment operation configurations of the TRXs and detectors described above in connection with FIG. 9G. At step 1401, a switch within a first transceiver channel, i. e., a reference channel, may be configured to couple a TX path output of the first TRX channel to a RX path input of the first TRX channel, corresponding to a configuration of SWla 910aa and SWlb 910bb of FIG. 9F. At step 1401,KI I -00 9-PCT PATENTanother switch, within a second transceiver channel, i. e., a channel undergoing ampl itude alignment operat ions, may be s imilarly conf igured to couple its TX path output to its RX path input. At step 1402, f irst and second s ignals are received at a phase detector, i. e., a detector or TDBM conf igured to detect phase. The f irst and second s ignals may respect ively correspond to RX output s ignal s from a f irst TRX and RX output s ignal s from a second TRX. RX output s ignal s from the f irst TRX may be based on output s ignal s from a TX path o f the f irst TRX that receives IF1 input s ignal s such as IF_TXIN 904a or IF 1 927 aa o f F IG. 9F. RX output s ignals from the second TRX may be s imilarly based on output s ignals from a TX path o f the second TRX that receives IF2 input s ignal s such as IF2 927bb o f F IG. 9F. As an example, the f irst s ignal s may correspond to the RX output of TRX1 in the conf igurat ion o f transceiver channel s shown by 920c o f FIG. 9G, and the second s ignals may correspond to the RX output of TRX2 in the conf igurat ion o f transceiver channel s shown by 920c o f FIG.9G. In such an example, the detector may correspond to Rmxl 2 92 6aa, which may be conf igured in a phase detect ion mode for the proces s of F IG. 13. At step 1403, a low-pas s f i lter receives an output of the detector. An output s ignal o f the detector may be proport ional to the phase di f ference between the RX output s o f the f irst and second channel s.

[0135] At step 1404, an output o f the low pas s f i lter corresponding to a DC value that i s proport ional to a phase di f ference between the RX output o f TRX1, i. e., RX1, and the RX output o f TRX2, i. e., RX2, i s received at a comparator. Notably, the DC value i s proport ional to the phase di f ference between the respect ive ent iret ies o fKI I-009-PCT PATENTcomponents of RX1 and RX2, not just the phase difference between the configurable phase shift elements within RX1 and RX2. At step 1405, a digital output of the comparator, indicative of whether the phase difference between the signals output by RX1 and RX2 is equal to a predetermined amount, is received at a calibration FSM in TRX2. In some examples, a first input terminal of the comparator may receive the signal mentioned at step 1403, and a second input terminal of the comparator may receive a fixed reference voltage value corresponding to phase detector output when a phase difference between the RX1 and RX2 signals is equal to the predetermined amount. The predetermined amount may correspond to ±90 °. In some embodiments, a single fixed reference voltage provided to the second input terminal of the comparator may correspond to the predetermined amount of ±90 °, based on the shape of the DC output of the phase detector over the phase differences of signals at its inputs. As an example, the DC output of the phase detector may have an equivalent level when a phase difference of its input signals is +90 ° and when a phase difference of input signals is -90 °, or equivalently, 270 °.

[0136] The process then proceeds to step 1406, where the calibration FSM iteratively adjusts a phase shift configuration value for a phase shift element within RX2 that provides the second signals to the phase detector.Step 1406 may also be referred to as sweeping the phase shift configuration value of the phase shift element in a ( second) RX path being aligned to a reference ( first ) RX path. In some embodiments, the iterative adjustment of the phase shift configuration value may be performed using a binary search or by iteratively decrementing orKI I-009-PCT PATENTincrementing a phase shift configuration value by a fixed step size. As an example, the sweep or iterative adjustment of the phase offset configuration value may begin by setting the receive path phase shift configuration value of the phase shift element in the receive path being aligned (RX2 ) to a reference receive path (RX1 ) to a value of 0 ° and then modifying the phase offset configuration value according to a binary search method, a positive ramp method, or a negative ramp method, until the DC output of the phase detector indicates a phase difference between its input signals corresponds to the predetermined amounts of ±90 °, corresponding to phase differences of 90 ° or 270 °.

[0137] At step 1407, the calibration FSM halts further adjustment or sweeping of the phase offset configuration value provided to the phase shift element of the RX2 path that provides signals to the second input of the phase detector, in response to determining that the digital output of the comparator indicates the phase difference between the signals for RX1 and RX2 two adjacent channels is equal to the predetermined amounts of ±90 °. Calibration FSM may determine that further adjustment or sweeping of the phase offset configuration value can be halted in response to a change in the output of the comparator, in embodiments where the adjustment or sweeping of the phase offset configuration value occurs by a positive ramp method ( incrementing the phase offset configuration value) or a negative ramp method (decrementing the phase offset configuration value ). Such a change in the comparator output may indicate that the phase offset configuration value has caused the DC output of the phase detector to cross the reference voltage, indicating that the phase difference between the signals for RX1 and RX2 is equal toKI I-009-PCT PATENTthe predetermined amounts of ±90 °. In embodiments where the adjustment or sweeping of the phase offset configuration occurs by a binary search method, determination of the highest resolution phase offset configuration values (e. g., phase offset configuration values differing by 1 LSB) associated with changes to the comparator output may indicate that further adjustment or sweeping the phase offset configuration value can be halted. The phase difference of the two RX paths' outputs will be +90 ° or - 90 ° after the adjustment of the of the phase offset configuration value is halted.

[0138] The process then proceeds to step 1408, where the system applies a code shift vector corresponding to an inverse phase shift with a magnitude equal to the predetermined amount, to the phase shift element within RX2 that provides the second signals to the phase detector. An intermediate calibration value, corresponding to the value of the phase offset vector or configuration value at the time the adjustment was halted at step 1407, may be modified by adding a predetermined offset value corresponding to the predetermined amount of phase offset from the intermediate calibration value to generate a final calibration value. As an example, if the phase difference of the two RX paths ' outputs is +90 ° when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offset corresponding to a -90 ° (negative 90 ° ) offset to the intermediate calibration value. As another example, if the phase difference of the two RX paths ' outputs is -90 ° (negative 90 ° ) when the sweeping of the phase shifter is stopped, then a final calibration value may be determined by applying a code shift vector or phase offsetKI I-009-PCT PATENTcorresponding to a +90 ° (positive 90 ° ) offset to the intermediate calibration value. Code shift vectors or phase offsets corresponding to negative 90 ° and positive 90 ° may be determined by a processor (not illustrated), stored in a memory (not illustrated), and applied to the configurable phase shift element by the calibration FSM. The phase shift element of each receive path may be configured using the final calibration value during normal operations. By the process of step 1408, the phases of the two RX paths whose outputs were received at the phase detector may be phase aligned.

[0139] At step 1408, the calibration vector that aligns the phases of the first and second signals may also be saved in a calibration table. The amplitude vector may be saved in a calibration table. In some embodiments, such as when TX amplitude alignment is performed after RX amplitude alignment, the TX amplitude vector or value that aligns the phase of a given TX path in a particular channel to a reference TX path in a reference channel may be used to determine a correction factor to be applied to the RX amplitude vector determined to align the phase of an output of the RX path in the particular channel to an output of a reference RX path in the reference channel. The calibration table may include the RX phase shift element calibration vector or values that have been adjusted by said correction factor where applicable. The process of FIG. 14 may proceed to be repeated for each subsequent pair of RX paths in TRXs as described in connection with 920c and 920d of FIG. 9G. Although the description of the process of FIG. 14 refers to RX1 and RX2 as examples, using RX1 as the reference path, the process of FIG. 14 may be performed for any pair of RX paths, using any given RX pathKI I-009-PCT PATENTas a reference path to which the other RX path is aligned. As an example, the process of FIG. 14 may be performed for the pairs RX1 / RX2, RX2 / RX3, RX3 / RX4, and so on. The processes of FIGS. 13 and 14 may be interleaved, such that both processes are performed for a given pair of RX paths, in any order, before moving onto a subsequent pair of RX paths and reperforming said processes

[0140] Although the present invention has been described in connection with certain specific embodiments for instructional purposes, the present invention is not limited thereto. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

KI I-009-PCT PATENTCLAIMSWhat is claimed is:

1. An apparatus with a phased array transceiver (TRX), the apparatus comprising:a plurality of channels, wherein each channel includes a transmission (TX) path and a receiving (RX) path;a plurality of detectors, each detector being coupled between respective first and second channels of the plurality of channels, and being configured to receive first and second signals from the respective first and second channels; anda plurality of calibration controllers, each associated with a respective detector of the plurality of detectors, and each configured to:determine an RX phase offset value for the respective second channel of the respective detector associated with the calibration controller.

2. The apparatus of claim 1, wherein to determine the RX phase offset value for the respective second channel of the respective detector associated with each calibration controller, each calibration controller is further configured to:iteratively adjust a phase vector for the RX path of the respective second channel;halt iterative adjustment of the phase vector in response to determining, based on an output of the respective detector, that a phase difference between the RX path of the respective second channel and the RX path of the respective first channel is equal to a predetermined amount; andKI I-009-PCT PATENTmodify the phase vector by applying a phase offset vector that removes the predetermined amount from the phase vector.

3. The apparatus of claim 2, wherein the predetermined amount is ±900.

4. The apparatus of claim 1, wherein each detector of the plurality of detectors comprises a first double-balanced mixer (DBM) and a second DBM, and wherein the first DBM and the second DBM are identical.

5. The apparatus of claim 1, wherein each calibration controller of the plurality of calibration controllers comprises a finite-state machine (FSM) that performs a sweep or a binary search to determine the RX phase offset value.

6. The apparatus of claim 1, wherein the plurality of detectors are arranged for non-overlapping adjacent pairs of the channels and comprise N / 2 detectors for N channels.

7. The apparatus of claim 6, further comprising:a plurality of switches, each coupled between RF output terminals of a corresponding non-overlapping adjacent pairs of the channels.

8. The apparatus of claim 1, wherein the plurality of calibration controllers are further configured to determine the RX phase offset values for their respective second channels based on corresponding TX phase offset values obtained from a TX path phase alignment process that aligns TX paths of the plurality of channels.KI I-009-PCT PATENT9. The apparatus of claim 8, wherein the TX path phase alignment process for TX paths of the plurality of channels is performed prior to a RX alignment process for RX paths of the plurality of channels and the TX phase offset values determined by the TX path phase alignment process are applied to each TX phase shift element during the RX alignment process and during normal operations, and wherein no phase offset correction factors are needed for each RX phase shift element after the RX alignment.

10. The apparatus of claim 8, wherein, in response to an update to one or more TX phase offset values, the calibration controllers apply corresponding corrections to corresponding stored RX phase offset values.

11. The apparatus of claim 8, wherein TX phase offset values for the TX paths of the plurality of channels are based on corresponding RX phase offset values for the RX paths of the plurality of channels.

12. The apparatus of claim 1, wherein each RX path further comprises: a low-pass filter (LPF), a DC multiplexer (MUX), and a comparator.

13. The apparatus of claim 1, wherein each calibration controller is further configured to:determine an RX amplitude offset value for the respective second channel of the respective detector associated with the calibration controller.

14. The apparatus of claim 13, wherein to determine the RX amplitude offset for the respective second channel of theKI I-009-PCT PATENTrespective detector associated with each calibration controller, each calibration controller is further configured to:iteratively adjust an amplitude vector for the RX path of the respective second channel;halt iterative adjustment of the phase vector in response to determining, based on an output of the respective detector, that an amplitude difference between the RX path of the respective second channel and the RX path of the respective first channel is within 1 LSB of a setting applied to a variable gain amplifier in the RX path of the respective second channel.

15. A method for phase alignment in a phased-array transceiver (TRX), comprising:configuring a detector in a phase detection mode; receiving, at the detector, first and second signals associated with respective first and second channels of the TRX; andat a calibration controller:receiving an output of the detector; and based on the output of the detector, determining an RX phase offset value for a reception (RX) path of the second channel of the TRX.

16. The method of claim 15, wherein receiving the first and second signals at the detector comprises:receiving an input to a transmission (TX) path to the first channel at a first input of the detector; and receiving an output of the RX path of the second channel at a second input of the detector.

17. The method of claim 16, further comprising:KI I-009-PCT PATENTclosing a switch coupled between a TX path output of the first channel and a TX path output of the second channel.

18. The method of claim 15, wherein receiving the first and second signals at the detector comprises:receiving an output of an RX path of the first channel at a first input of the detector; andreceiving an output of an RX path of the second channel at a second input of the detector.

19. The method of claim 18, further comprising:closing a switch coupled between a TX path output of the first channel and an RX path input of the first channel; andclosing a switch coupled between a TX path output of the second channel and an RX path input of the second channel.

20. The method of claim 15, further comprising:configuring the detector in an amplitude detection mode; andat a calibration controller, determine an RX amplitude offset value for an RX path of the second channel of the TRX.

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