Array substrate, display module, and display apparatus

Abstract

An array substrate, comprising: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a first control signal line, and a second control signal line. One of the data lines is electrically connected to one column of the sub-pixels. The plurality of multiplexing circuits are disposed in a first peripheral region, and each multiplexing circuit is electrically connected to at least two of the data lines. The first control signal line and the second control signal line are disposed in the first peripheral region, and are both electrically connected to the multiplexing circuit. The first control signal line and the second control signal line are configured to transmit voltage signals having opposite polarities, and control the multiplexing circuit to respectively transmit data signals to the at least two data lines connected to the multiplexing circuit. The plurality of data lines comprise a plurality of first data lines. Orthographic projections of the first data lines on the base substrate partially overlap with the first control signal line and the second control signal line. Capacitance formed between at least one of the first data lines and the first control signal line and capacitance formed between the at least one first data line and the second control signal line are equal.

Description

Array substrate, display module and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display module, and a display device. Background Technology

[0002] Touch and Display Driver Integration (TDDI) display products are one of the mainstream screen display technologies today. TDDI products are widely used in various display products due to their more sensitive touch technology, lighter and thinner appearance, and lower cost advantages. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of multiplexing circuits, a first control signal line, and a second control signal line. The substrate includes a display area and a first peripheral area adjacent to one side of the display area. The plurality of sub-pixels are disposed in the display area and arranged in multiple rows and columns, with each row including a plurality of sub-pixels arranged along a first direction and each column including a plurality of sub-pixels arranged along a second direction; the first direction and the second direction intersect. The plurality of data lines pass through the display area and extend to the first peripheral area, with each data line electrically connected to a column of sub-pixels. The plurality of multiplexing circuits are disposed in the first peripheral area, and each multiplexing circuit is electrically connected to at least two of the data lines. The first control signal line and the second control signal line are disposed in the first peripheral area and are both electrically connected to the multiplexing circuits, and the first control signal line and the second control signal line are configured to transmit voltage signals of opposite polarity. The first control signal line and the second control signal line are configured to control the multiplexing circuit to transmit data signals to at least two data lines connected to the multiplexing circuit, respectively. The plurality of data lines include a plurality of first data lines, the orthographic projection of each first data line on the substrate partially coinciding with the first control signal line and the second control signal line, and at least one first data line has an equal capacitance to both the first control signal line and the second control signal line.

[0004] In some embodiments, the multiplexing circuit includes a first transistor and a second transistor, the first transistor being located on the side of the second transistor away from the display area. A first control signal line is located on the side of the second control signal line away from the display area, the first control signal line being configured as the gate of the first transistor, and the second control signal line being configured as the gate of the second transistor. The first data line includes a first extension and a first electrode portion located in a first peripheral region, the orthographic projections of the first extension and the second control signal line on the substrate intersect each other, the orthographic projection of the first electrode portion on the substrate coincides with the orthographic projection portion of the first control signal line on the substrate, and is configured as the first electrode of the first transistor.

[0005] In some embodiments, the first electrode portion includes a plurality of sub-portions arranged side-by-side along the first direction, the sum of the dimensions of the plurality of sub-portions along the first direction being greater than the dimension of the first extension portion along the first direction. The second control signal line includes a first extension segment and a second extension segment, the orthographic projection of the first extension segment on the substrate at least partially coinciding with the orthographic projection of the first data line on the substrate, and the orthographic projection of the second extension segment on the substrate not coinciding with the orthographic projection of the first data line on the substrate. The dimension of the first extension segment along the second direction is greater than the dimension of the second extension segment along the second direction.

[0006] In some embodiments, the plurality of first transistors included in the plurality of multiplexing circuits are arranged in multiple rows along the second direction, with each row including a plurality of first transistors arranged along the first direction. The first control signal line includes a plurality of first sub-lines, and one first sub-line is configured as the gate of a row of first transistors. And / or, the plurality of second transistors included in the plurality of multiplexing circuits are arranged in multiple rows along the second direction, with each row including a plurality of second transistors arranged along the first direction. The second control signal line includes a plurality of second sub-lines, and one second sub-line is configured as the gate of a row of second transistors.

[0007] In some embodiments, the first control signal line includes two first sub-lines, and the second control signal line includes two second sub-lines. The multiplexing circuit is electrically connected to the two data lines, and the plurality of multiplexing circuits include a plurality of first multiplexing circuits and a plurality of second multiplexing circuits, each of which is electrically connected to one first sub-line and one second sub-line, respectively. The data lines electrically connected to the first and second multiplexing circuits transmit data signals of opposite polarity in the same frame, and each data line transmits data signals of opposite polarity in adjacent frames. The two first sub-lines are configured to transmit control signals of the same polarity but different magnitudes; and / or, the two second sub-lines are configured to transmit control signals of the same polarity but different magnitudes.

[0008] In some embodiments, one of the two first sub-lines that controls the transmission of negative polarity data signals by the first multiplexing circuit and the second multiplexing circuit is designated as a first target sub-line, and the other is designated as a second target sub-line. One of the two second sub-lines that controls the transmission of negative polarity data signals by the first multiplexing circuit and the second multiplexing circuit is designated as a third target sub-line, and the other is designated as a fourth target sub-line. The voltage of the control signal transmitted by the first target sub-line is less than the voltage of the control signal transmitted by the second target sub-line; and / or, the voltage of the control signal transmitted by the third target sub-line is less than the voltage of the control signal transmitted by the fourth target sub-line.

[0009] In some embodiments, the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the first target sub-line is equal to the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the second target sub-line. And / or, the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the third target sub-line is equal to the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the fourth target sub-line.

[0010] In some embodiments, the first target sub-line and the third target sub-line transmit control signals of equal magnitude but opposite polarity. And / or, the second target sub-line and the fourth target sub-line transmit control signals of equal magnitude but opposite polarity.

[0011] In some embodiments, the plurality of first transistors included in the plurality of multiplexing circuits are arranged in a row along the first direction, and the first control signal line is configured as the gate of the plurality of first transistors. And / or, the plurality of second transistors included in the plurality of multiplexing circuits are arranged in a row along the first direction, and the second control signal line is configured as the gate of the plurality of second transistors.

[0012] In some embodiments, the plurality of data lines further includes a plurality of second data lines, wherein the orthographic projection of each second data line on the substrate does not coincide with the first control signal line, but partially coincides with the second control signal line. The substrate further includes a second peripheral region located in the display area away from the first peripheral region. The array substrate further includes auxiliary signal lines disposed in the second peripheral region and configured to transmit voltage signals with polarity opposite to the second control signal lines. The orthographic projection of the auxiliary signal lines on the substrate does not coincide with the orthographic projection of the first data lines on the substrate, but partially coincides with the orthographic projection of the second data lines on the substrate. At least one of the second data lines has an equal capacitance to both the second control signal line and the auxiliary signal line.

[0013] In some embodiments, the array substrate further includes a plurality of third transistors and a plurality of fourth transistors. The plurality of third transistors are disposed in the second peripheral region, arranged in a row along the first direction, and a first data line is electrically connected to one of the third transistors. The plurality of fourth transistors are disposed in the second peripheral region, located on the side of the plurality of first transistors away from the display area, and a second data line is electrically connected to one of the fourth transistors. The auxiliary signal line is disposed between the third transistors and the fourth transistors.

[0014] In some embodiments, the plurality of data lines further includes a plurality of second data lines, wherein the orthographic projection of each second data line on the substrate does not coincide with the first control signal line, but partially coincides with the second control signal line. A scan cycle is configured to transmit a data signal to a row of sub-pixels, and the scan cycle includes a first stage and a second stage configured sequentially. The multiplexing circuit is configured to: transmit a data signal to the first data line during the first stage of each scan cycle; and transmit a data signal to the second data line during the second stage of each scan cycle.

[0015] In some embodiments, a scan cycle is configured to transmit data signals to a row of subpixels, and the scan cycle includes a first stage and a second stage arranged sequentially. The multiplexing circuit is configured to: transmit data signals to the first data line and the second data line respectively in the first stage and the second stage of the same scan cycle; and transmit data signals to the first data line and the second data line respectively in the first stage or the second stage of two adjacent scan cycles.

[0016] In some embodiments, the array substrate further includes a plurality of first scan signal lines, one of which is electrically connected to a row of sub-pixels. The first scan signal lines are configured to control the plurality of data lines to transmit data signals to the row of sub-pixels. The plurality of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels. The first sub-pixels include a first pixel electrode, and the second sub-pixels include a second pixel electrode. A scan cycle is configured to transmit data signals to a row of sub-pixels, and the scan cycle includes a first stage and a second stage sequentially configured. In the first stage, the multiplexing circuit transmits data signals to the first pixel electrode, and in the second stage, the multiplexing circuit transmits data signals to the second pixel electrode. The capacitances formed between the first scan signal lines and the first and second pixel electrodes are not equal.

[0017] In some embodiments, the capacitance formed between the first scan signal line and the first pixel electrode is smaller than the capacitance formed between the first scan signal line and the second pixel electrode.

[0018] In some embodiments, the first sub-pixel includes a fifth transistor, the control electrode of which is electrically connected to a first scan signal line, a first source pattern electrically connected to the data line, and a first drain pattern electrically connected to the first pixel electrode. The second sub-pixel includes a sixth transistor, the control electrode of which is electrically connected to the first scan signal line, a second source pattern electrically connected to the data line, and a second drain pattern electrically connected to the second pixel electrode. In the orthographic projection of the first scan signal line, the first drain pattern, and the second drain pattern onto the substrate, the area of ​​the second drain pattern is larger than the area of ​​the first drain pattern, and the area of ​​the second drain pattern overlapping with the first scan signal line is larger than the area of ​​the first drain pattern overlapping with the first scan signal line.

[0019] On the other hand, a display module is provided. The display module includes a driving circuit board and an array substrate as described in any of the above embodiments. The array substrate includes a plurality of first sub-pixels and a plurality of second sub-pixels. A scan cycle is configured to transmit data signals to a row of sub-pixels, and the scan cycle includes a first stage and a second stage arranged sequentially. In the first stage, a multiplexing circuit transmits a first data signal to the first sub-pixels, and in the second stage, the multiplexing circuit transmits a second data signal to the second sub-pixels. The driving circuit board includes a data processing unit electrically connected to the multiplexing circuit. The data processing unit is configured to transmit data signals to the multiplexing circuit and to compensate for different voltage values ​​for the first data signal and / or the second data signal used to make the first sub-pixels and second sub-pixels display the same grayscale.

[0020] In some embodiments, the data processing unit is configured to compensate the first data signal with a positive voltage.

[0021] In some embodiments, the data processing unit is configured to compensate for negative voltage in the second data signal.

[0022] In some embodiments, the data processing unit is configured to compensate the first data signal with a positive voltage and the second data signal with a negative voltage.

[0023] In some embodiments, the first control signal line of the array substrate includes two first sub-lines, and the second control signal line includes two second sub-lines. The plurality of multiplexing circuits include a plurality of first multiplexing circuits and a plurality of second multiplexing circuits, each of which is electrically connected to one of the first sub-lines and one of the second sub-lines. The data lines electrically connected to the first and second multiplexing circuits transmit data signals of opposite polarity in the same frame, and each data line transmits data signals of opposite polarity in adjacent frames.

[0024] The drive circuit board further includes a power supply unit, a timing controller, and a power output circuit. The power supply unit is configured to provide a first set of voltage signals and a second set of voltage signals. The first set of voltage signals includes a first operating voltage and a first non-operating voltage, and the second set of voltage signals includes a second operating voltage and a second non-operating voltage. The first operating voltage is less than the second operating voltage, and the first non-operating voltage is less than the second non-operating voltage. The timing controller is configured to output a first set of selection signals based on the polarity of the data signals transmitted to the first multiplexing circuit, and to output a second set of selection signals based on the polarity of the data signals transmitted to the second multiplexing circuit. The power output circuit is electrically connected to the timing controller, the power supply unit, the two first sub-lines, and the two second sub-lines. The power output circuit is configured to: transmit one of the first set of voltage signals and the second set of voltage signals to a first sub-line and a second sub-line electrically connected to the first multiplexing circuit based on the first set of selection signals; and transmit the other of the first set of voltage signals and the second set of voltage signals to a first sub-line and a second sub-line electrically connected to the second multiplexing circuit based on the second set of selection signals.

[0025] On the other hand, a display device is provided. The display device includes an array substrate as described in any of the above embodiments.

[0026] Alternatively, the display device may include a display module as described in any of the above embodiments. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 is a structural diagram of a display module according to some embodiments;

[0030] Figure 3 is a structural diagram of an array substrate according to some embodiments;

[0031] Figure 4 is a connection diagram of a multiplexing circuit according to some embodiments;

[0032] Figure 5 is a driving timing diagram of an array substrate according to some embodiments;

[0033] Figure 6 is a structural diagram of an array substrate according to some embodiments;

[0034] Figure 7 is another structural diagram of the array substrate according to some embodiments;

[0035] Figure 8 is another structural diagram of an array substrate according to some embodiments;

[0036] Figure 9 is another structural diagram of an array substrate according to some embodiments;

[0037] Figure 10 is another driving timing diagram of the array substrate according to some embodiments;

[0038] Figure 11 is a structural diagram of the first sub-pixel and the second sub-pixel according to some embodiments;

[0039] Figure 12 is a structural block diagram of a data processing unit according to some embodiments;

[0040] Figure 13 is a schematic diagram of compensation for a first data signal according to some embodiments;

[0041] Figure 14 is a schematic diagram of compensation for a second data signal according to some embodiments;

[0042] Figure 15 is a schematic diagram of compensation for a first data signal and a second data signal according to some embodiments;

[0043] Figure 16 is a timing diagram of the drive of the first sub-line and the second sub-line according to some embodiments;

[0044] Figure 17 is a structural block diagram of a driver circuit board according to some embodiments;

[0045] Figure 18 is another structural block diagram of a driver circuit board according to some embodiments. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0049] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0051] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0052] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0053] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0054] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0055] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0057] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0058] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0059] The transistors provided in the embodiments of this disclosure can be thin-film transistors (TFTs), metal oxide semiconductors (MOSs), or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example. Thin-film transistors can be P-type transistors or N-type transistors. P-type transistors conduct at low potentials and are cut off at high potentials; N-type transistors conduct at high potentials and are cut off at low potentials. The embodiments of this disclosure are all described using N-type transistors as an example. The first electrode of each transistor is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor.

[0060] Referring to FIG1, an embodiment of the present disclosure provides a display device 1000, which is a product having an image display function. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0061] In some embodiments, the display device described above may be an augmented reality (AR) device, a virtual reality (VR) device, or a mixed reality (MR) device. Alternatively, in other embodiments, the display device may also be a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, camera view display (e.g., a rearview camera display in a vehicle), wearable device, in-vehicle display, flight display, or any other product or component with display functionality.

[0062] In some embodiments, regarding the type of light emission of the display device 1000, the display device 1000 may be a liquid crystal display (LCD), or it may be an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display, etc. Regarding the shape of the display device 1000, it may be a flat panel display or a curved display, etc. Regarding the shape of the display device 1000, it may be rectangular or circular, etc. The following uses a rectangular, flat liquid crystal display as an example to illustrate some embodiments of this disclosure; however, the embodiments of this disclosure are not limited to this, and any other display device can be considered, as long as the same technical concept is applied.

[0063] In some embodiments, referring to FIG2, the display device 1000 includes a display module 1100, which may include a display panel 100 and a driving circuit board (not shown in the figure). The driving circuit board may be a printed circuit board (PCB), and may include a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. The driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 100 and is used to transmit control signals to the display panel 100, thereby driving the display panel 100 to display images. In addition, the display module 1100 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display module 1100 to realize various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0064] Referring again to Figure 2, when the display device is a liquid crystal display device, the display module 1100 may further include a backlight module 200 disposed on the backlight side of the display panel 100. For example, the backlight module 200 may be a direct-lit backlight module or an edge-lit backlight module, etc. The backlight module 200 is used to provide a light source for the display panel 100. The display panel 100 includes multiple sub-pixels, each of which can adjust the amount of light passing through the display panel 100, thereby enabling each sub-pixel to display the same or different gray levels to achieve the purpose of image display.

[0065] As shown in Figure 2, when the display panel 100 is a liquid crystal display panel, the display panel 100 may include an array substrate 110, a counter substrate 120 disposed opposite to each other, and a liquid crystal layer 130 disposed between the array substrate 110 and the counter substrate 120. The counter substrate 120 may also be referred to as a color filter substrate or an encapsulation substrate. Of course, the structure of the display panel 100 is not limited to this; the display panel 100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 110 near the liquid crystal layer 130, and a second alignment film (not shown in the figure) disposed on the side of the counter substrate 120 near the liquid crystal layer 130, etc.

[0066] The aforementioned multiple sub-pixels may include at least two types of sub-pixels that emit light of different colors, which is beneficial for the display substrate to achieve color display. In one example, the multiple sub-pixels may include a red light sub-pixel that emits red light, a green light sub-pixel that emits green light, and a blue light sub-pixel that emits blue light. The opposing substrate 120 may include a light filter and a black matrix. The light filter is used to filter the light incident on the opposing substrate 120 so that each sub-pixel emits light of a single color (e.g., red, green, or blue). Different sub-pixels can emit the same or different colors of light, thereby enabling the display panel 100 to achieve color display. The black matrix can be used to cover the signal lines on the array substrate, improving the contrast of the display module.

[0067] In some embodiments, referring to FIG3, the array substrate 110 may include a substrate 101, which includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA refers to the area in the array substrate 110 used for displaying images, and the aforementioned plurality of sub-pixels P may be disposed within the display area AA. The peripheral area BB may be used for setting signal traces (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits and source driving circuits, etc.), and bonding portions (for bonding with a driving circuit board or chip), etc. Of course, the structure and function of the peripheral area BB are not limited to these, and will not be listed here.

[0068] For example, as shown in FIG3, the peripheral area BB may include a first peripheral area BB1 adjacent to one side of the display area AA, a second peripheral area BB2 located on the side of the display area AA away from the first peripheral area BB1, and a third peripheral area BB3 located on the left and right sides of the display area AA. The first peripheral area BB1 may be a region for setting the source drive circuit, and the first peripheral area BB1 may also be called the fan-out region. The second peripheral area BB2 and the first peripheral area BB1 are located on opposite sides of the display area AA, respectively. The third peripheral area BB3 may be used for setting the gate drive circuit GOA, for example.

[0069] The aforementioned sub-pixels P are arranged in multiple rows and columns within the display area AA. A row includes multiple sub-pixels P arranged along a first direction X, and a column includes multiple sub-pixels arranged along a second direction Y. That is, the first direction X refers to the arrangement direction of a row of sub-pixels P, and the second direction Y refers to the arrangement direction of a column of sub-pixels; wherein, the first direction Y intersects with the second direction X, for example, the first direction Y and the second direction X are perpendicular to each other.

[0070] As shown in Figure 3, the array substrate 110 also includes multiple data lines 10. These data lines 10 are spaced apart along a first direction X and extend along a second direction Y. For example, the data lines 10 pass through the display area AA along the second direction Y and extend to a first peripheral area BB1 and a second peripheral area BB2. One data line 10 is electrically connected to a column of sub-pixels P. For example, one data line 10 is used to transmit data signals to the column of sub-pixels P electrically connected to it.

[0071] The array substrate 110 also includes a plurality of first scan signal lines 14, which are spaced apart along the second direction Y and all extend along the first direction X. For example, the first scan signal lines 14 pass through the display area AA along the first direction X and extend to the peripheral area BB, and are electrically connected to the gate driving circuit GOA in the peripheral area BB. One first scan signal line 14 is electrically connected to a row of sub-pixels P, and the gate driving circuit GOA transmits scan signals to the row of sub-pixels P through the first scan signal lines 14.

[0072] When the display substrate is a liquid crystal display substrate, a sub-pixel P may include a data writing transistor T20, a pixel electrode PX, and a common electrode COM. The control electrode of the data writing transistor T20 is electrically connected to the first scan signal line 14, the first electrode is electrically connected to the data line 10, and the second electrode is electrically connected to the pixel electrode PX. The data writing transistor T20 can be configured to be turned on or off under the control of the scan signal of the first scan signal line 14. When the data writing transistor T20 is turned on, the data signal transmitted by the data line 10 is transmitted to the pixel electrode PX. A capacitor Cst can be formed between the pixel electrode PX and the common electrode COM, and an electric field can be generated between the pixel electrode PX and the common electrode COM. This electric field can drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby displaying the grayscale of the sub-pixel and realizing image display. The common electrodes COM of multiple sub-pixels P can be interconnected to form a whole. This facilitates the transmission of a common voltage signal to the common electrodes COM of multiple sub-pixels P, meaning that the voltage on the common electrodes of different sub-pixels P is the same. For example, a common voltage signal line (not shown in the figure) is also provided in the peripheral area BB, and the common electrode COM is electrically connected to the common voltage signal line in the peripheral area BB.

[0073] In some embodiments, the data writing transistor T20 can be an oxide thin-film transistor (OTFT). OTFTs are characterized by low leakage current, which helps reduce leakage current in the pixel circuit, thereby simplifying the pixel circuit structure, increasing the aperture ratio of the array substrate, and improving the light transmittance of the display substrate. Furthermore, array substrates using OTFTs have advantages in low-frequency driving and have broad application prospects.

[0074] In some embodiments, the display module 1100 may further include a source driver IC, which is a chip used to transmit data signals to multiple data lines 10. The aforementioned source driver IC may also be a Touch and Display Driver Integrated Chip (TDDI chip). In this case, the display module 1100 may be a touch-enabled display module 1100, and the display device may also be referred to as a TDDI display device. The array substrate may further include input signal lines 15. The source driver chip can be electrically connected to the multiplexing circuit 20 through the input signal lines 15, and the source driver chip can transmit data signals to multiple data lines 10 and touch signals to the touch structure through the input signal lines. For example, when the array substrate 110 is a liquid crystal display substrate, the touch structure may be disposed on the array substrate 110.

[0075] To reduce the cost of the source driver chip, multiple multiplexers (MUX) 20 and multiple control signal lines 30 can be disposed within the first peripheral region BB1. Each multiplexer 20 is electrically connected to at least two control signal lines 30 and at least two data lines 10. The multiplexer 20 is configured to, at different time periods, respond to the at least two control signal lines 30 electrically connected to it and sequentially transmit data signals to the at least two data lines 10. The multiplexer 20 can reduce the number of signals (such as data signals) output by the source driver chip at the same time, thereby reducing the cost of the source driver chip and the fabrication cost of the array substrate 110. In the following embodiments of this disclosure, the multiplexer 20 is electrically connected to two control signal lines 30 and two data lines 10 as an example for illustrative description. Of course, the embodiments of this disclosure are not limited to this, and any other feasible implementation can be considered.

[0076] Some embodiments of this disclosure also provide a driving method for an array substrate. For each row of sub-pixels P, the driving method includes: during a scan cycle, a first scan signal line 14 electrically connected to the row of sub-pixels P always outputs a working voltage, that is, the data write transistors T20 of the multiple (all) sub-pixels P included in the row are all in the on state; multiple control signal lines 30 electrically connected to the multiplexing circuit 20 sequentially output working voltages to control the multiplexing circuit 20 to transmit data signals to the sub-pixels P in the same row but different columns through different multiple data lines 10 in time periods. Here, the "scan cycle" described in the embodiments of this disclosure refers to the time period used to transmit data signals to a row of sub-pixels P; the "working voltage" refers to the voltage that can drive the multiplexing circuit 20 to electrically connect the data lines 10 and the input signal lines 15.

[0077] For example, when the multiplexing circuit 20 is electrically connected to two control signal lines 30 and two data lines 10, a scan cycle may include a first stage and a second stage. In the first stage, one control signal line 30 controls the multiplexing circuit 20 to transmit a data signal to one data line 10, and in the second stage, another control signal line 30 controls the multiplexing circuit 20 to transmit a data signal to the other data line 10.

[0078] Furthermore, the driving method of the array substrate may also include: at least two adjacent data lines 10 transmitting positive and negative data signals respectively in the same frame, and the same data line 10 transmitting positive and negative data signals respectively in adjacent frames; that is, the array substrate adopts a column-inverted driving method. In this case, for each sub-pixel P, the common electrode of sub-pixel P has an optimal setting voltage, which can be the median value of the voltage on the pixel electrode when the sub-pixel P displays the same grayscale in two adjacent frames. For example, when sub-pixel P displays the maximum grayscale in two adjacent frames, it is the median value of the voltage of the positive data signal and the voltage of the negative data signal on the pixel electrode.

[0079] The inventors discovered that for each data line 10, its projection onto the substrate 101 coincides with the orthographic projection of the control signal line 30 (hereinafter referred to as the corresponding control signal line 30') used to control the transmission of data signals to that data line 10, thus generating a first parasitic capacitance. Within the same scan cycle, for the data line 10 that transmits data signals earlier (e.g., the data line 10 that transmits data in the first stage), after the data signal transmission is completed (hereinafter referred to as the first time node), the voltage on the corresponding control signal line 30' undergoes a jump. Since the data writing transistor T20 of the sub-pixel P (hereinafter referred to as the first sub-pixel) electrically connected to the data line 10 is still in the on state, the pixel electrode of the first sub-pixel is in the floating state. Under the action of the first parasitic capacitance, the data line 10 and the pixel electrode of the first sub-pixel electrically connected to the data line 10 are pulled by the voltage jump on the corresponding control signal line 30', which causes the voltage on the pixel electrode of the first sub-pixel P1 to change, and the voltage change on the first sub-pixel P1 is ΔVP1. That is to say, the pull of the corresponding control signal line 30' on the pixel electrode of the first sub-pixel P1 is ΔVP1.

[0080] Wherein: C1 refers to the capacitance between the data line 10 electrically connected to the first sub-pixel P1 and the corresponding control signal line 30'; C2 is the parasitic capacitance between the data line 10 and other structures in the array substrate (such as the first scan signal line, pixel electrode and common electrode, etc.); and ΔVG1 is the voltage change on the corresponding control signal line 30'.

[0081] However, for the data line 10 that transmits the last data signal (e.g., the data line 10 that transmits the data signal in the second stage), after the data signal transmission is completed (hereinafter referred to as the second time node), the first scan signal line 14 changes from the output working voltage (the voltage that can drive the data writing transistor T20 to turn on) to the output non-working voltage (the voltage that can drive the data writing transistor T20 to turn off). Multiple data writing transistors T20 of a row of sub-pixels P are all turned off, and the voltage on the corresponding control signal line 30' jumps.

[0082] Although the voltage on data line 10 is pulled by the first parasitic capacitance, since the second transistor T2 is already in the off state, it will not affect the voltage on the pixel electrode of the sub-pixel electrically connected to data line 10, and the voltage on the pixel electrode of the second sub-pixel is more stable. The sub-pixel P electrically connected to the data line 10 that transmits the last data signal is called the second sub-pixel P2. In other words, voltage changes on control signal line 30 will not pull the voltage of the second sub-pixel P2.

[0083] In addition, each row of sub-pixels P also forms a second parasitic capacitance with the first scan signal line 14. After the last data transmission signal 10 completes the transmission of the data signal (second time node), the voltage on the first scan signal line 14 also changes abruptly (from the output working voltage to the output non-working voltage). Under the influence of the second parasitic capacitance, the first scan signal line 14 will also pull the voltage of the pixel electrode of the row of sub-pixels P, and the voltage change on the pixel electrode is ΔVP2. That is to say, the pull of the first scan signal line 14 on the pixel electrode of the row of sub-pixels P is ΔVP2.

[0084] Wherein: Cgs refers to the capacitance between the pixel electrode of each sub-pixel P and the first scan signal line 14; Clc refers to the liquid crystal capacitance of each sub-pixel P; Cst refers to the pixel capacitance of each sub-pixel P (the capacitance between the pixel electrode and the common electrode); ΔVG1 is the voltage change on the first scan signal line 14.

[0085] For the reasons mentioned above, when displaying the same grayscale and the source driver chip outputs the same data signal Vdata, the sub-pixel P (first sub-pixel) that writes the data signal first in the same row is pulled by the control signal line 30 and the first scan signal line 14, and the pixel electrode voltage of the first sub-pixel is pulled by ΔVP1 + ΔVP2. The sub-pixel P (second sub-pixel) that writes the data signal later is only pulled by the first scan signal line 14, and the pixel electrode voltage of the second sub-pixel is pulled by ΔVP2. That is to say, when the first sub-pixel and the second sub-pixel display the same grayscale and input the same data signal, there is a certain difference in the voltage on the pixel electrode of the first sub-pixel and the second sub-pixel. This will cause the common electrode of the first sub-pixel P1 and the second sub-pixel P2 to have different optimal setting voltages. However, the common electrode of the first sub-pixel P1 and the second sub-pixel P2 is connected to each other as a whole, and the voltage value on the common electrode of the first sub-pixel P1 and the second sub-pixel P2 is equal (ignoring the voltage drop factor on the common electrode). This results in flickering issues in display modules that use TDDI driver chips, oxide thin-film transistors, and multiplexing circuits when displaying at low frequencies (such as refresh rates less than 30 Hz).

[0086] To address the aforementioned technical problems, referring to Figures 3, 4, and 5, the embodiment of this disclosure provides an array substrate 110. The array substrate 110 (multiple control signal lines 30) includes a first control signal line 31 and a second control signal line 32. The first control signal line 31 and the second control signal line 32 are disposed in the first peripheral area BB1. Both the first control signal line 31 and the second control signal line 32 are electrically connected to a multiplexing circuit 20. The first control signal line 31 and the second control signal line 32 are configured to control the multiplexing circuit 20 to transmit data signals to at least two data lines 10 connected to the multiplexing circuit 20 in time-sharing periods (at different time periods). The first control signal line 31 and the second control signal line 32 are configured to transmit voltage signals of opposite polarity. Exemplarily, the first control signal line 31 and the second control signal line 32 transmit voltage signals of equal magnitude but opposite polarity.

[0087] It should be understood that in the embodiments of this disclosure, the first control signal line 31 and the second control signal line 32 do not refer to a specific signal line, but rather to a class of signal lines used simultaneously to transmit control signals of the same polarity to the multiplexing circuit 20. For example, as shown in FIG6, the first control signal line 31 and the second control signal line 32 may each include two signal lines (two first sub-lines 33 and two second sub-lines 34), or, as shown in FIG7 and FIG8, the first control signal line 31 and the second control signal line 32 may each include one signal line. Of course, the specific number of signal lines included in the first control signal line 31 and the second control signal line 32 can be designed according to actual needs, as long as the same technical concept is adopted.

[0088] The multiple data lines 10 include multiple first data lines 11. The orthographic projection of each first data line 11 on the substrate 101 partially overlaps with the first control signal line 31 and the second control signal line 32, respectively. In other words, the first data line 11 refers to the data line 10 among the multiple data lines 10 whose orthographic projection on the substrate 101 coincides with the orthographic projection of the first control signal line 31 and the second control signal line 32 on the substrate 101. At least one first data line 11 has an equal capacitance with the first control signal line 31 and the second control signal line 32. Based on this, after the first data line 11 completes the transmission of data signals, the voltages of the first control signal line 31 and the second control signal line 32 simultaneously change abruptly. One of the voltages decreases while the other increases. This reduces or completely cancels out the combined voltage pull of the first control signal line 31 and the second control signal line 32 on the first data line 11, thus reducing voltage fluctuations on the first data line 11 and consequently reducing or eliminating voltage fluctuations on the sub-pixel P electrically connected to the first data line 11. For example, the driving method of the array substrate can be configured to control the first data line 11 to transmit data signals first; that is, data signals are transmitted to the first sub-pixel via the first data line 11. This reduces voltage fluctuations on the pixel electrode of the sub-pixel P (first sub-pixel) electrically connected to the first data line 11, and reduces or eliminates the voltage change generated on the pixel electrode of the first sub-pixel at the first time node, i.e., reduces the pull ΔVP1 on the pixel electrode of the first sub-pixel caused by the control signal line 30. This helps to reduce the voltage difference on the pixel electrodes of different sub-pixels P (first sub-pixel and second sub-pixel) when displaying the same grayscale, and reduces the risk of flickering in the display module during low-frequency display.

[0089] In some embodiments, referring to Figures 4 and 6, the multiplexing circuit 20 includes a first transistor T1 and a second transistor T2, with the first transistor T1 located on the side of the second transistor T2 away from the display area AA. In this case, the multiplexing circuit 20 is electrically connected to two data lines 10. A first control signal line 31 is located on the side of the second control signal line 32 away from the display area AA. The first control signal line 31 is configured as the gate of the first transistor T1, and the second control signal line 32 is configured as the gate of the second transistor T2. The first control signal line 31 can control the on and off states of the first transistor T1, and the second control signal line 32 can control the on and off states of the second transistor T2.

[0090] Referring again to Figures 4 and 6, the array substrate 110 may further include an input signal line 15. One end of the input signal line 15 is electrically connected to the source driver chip, and the other end is electrically connected to the multiplexing circuit 20. For example, the input signal line 15 is electrically connected to the first transistor T1 and the second transistor T2, respectively. One of the input signal line 15 and the data line 10 is also used to form the first electrode of the first transistor T1 and the second transistor T2, and the other is used to form the second electrode of the first transistor T1.

[0091] For example, when the first control signal line 31 transmits a working voltage and the second control signal line 32 transmits a non-working voltage, the first transistor T1 is turned on and the second transistor T2 is turned off. The first transistor T1 electrically connects the input signal line 15 to a data line 10 (first data line 11), and the input signal line 15 transmits a data signal to the first data line 11. When the second control signal line 32 transmits a working voltage and the first control signal line 31 transmits a non-working voltage, the second transistor T2 is turned on and the first transistor T1 is turned off. The second transistor T2 electrically connects the input signal line 15 to a data line 10 (second data line 12), and the input signal line 15 transmits a data signal to the second data line 12. Here, the "working voltage" transmitted by the first control signal line 31 / second control signal line 32 refers to the voltage capable of driving the first transistor T1 / second transistor T2 to turn on, and the "non-working voltage" refers to the voltage capable of driving the first transistor T1 / second transistor T2 to turn off.

[0092] As shown in Figure 6, the first data line 11 includes a first extension 111 and a first electrode 112 located in the first peripheral region BB1. The orthographic projections of the first extension 111 and the second control signal line 32 on the substrate 101 intersect each other. The orthographic projection of the first electrode 112 on the substrate 101 partially coincides with the orthographic projection of the first control signal line 31 on the substrate 101, and the first electrode 112 is configured as the first electrode of the first transistor T1. The area of ​​the overlapping portion of the orthographic projections of the first extension 111 and the second control signal line 32 on the substrate 101 can be equal to the area of ​​the overlapping portion of the orthographic projections of the first electrode 112 and the first control signal line 31 on the substrate 101, so that the capacitance formed between the first data line 11 and the first control signal line 31 and the second control signal line 32 is equal.

[0093] In some embodiments, as shown in FIG6, the first electrode portion 112 includes a plurality of sub-portions 113 arranged side by side along the first direction X, and the sum of the dimensions of the plurality of sub-portions 113 along the first direction X is greater than the dimension of the first extension portion 111 along the first direction X. This is beneficial for increasing the number of channels of the first transistor T1 and the width-to-length ratio of the channel structure, thereby improving the on-state current of the first transistor T1.

[0094] The second control signal line 32 includes a first extension 321 and a second extension 322. The orthographic projection of the first extension 321 on the substrate 101 at least partially coincides with the orthographic projection of the first data line 11 on the substrate 101. The orthographic projection of the second extension 322 on the substrate 101 does not coincide with the orthographic projection of the first data line 11 on the substrate 101. The dimension of the first extension 321 along the second direction Y is larger than the dimension of the second extension 322 along the second direction Y. This is beneficial to increase the relative area between the first data line 11 and the second control signal line 32, and increase the parasitic capacitance between the first data line 11 and the second control signal line 32, so that the capacitance formed between the first data line 11 and the first control signal line 31 and the second control signal line 32 is equal.

[0095] In some embodiments, continuing to refer to FIG6, the plurality of multiplexed circuits 20 include a plurality of first transistors T1 arranged in multiple rows along the second direction Y, with each row including a plurality of first transistors T1 arranged along the first direction X. And / or, the plurality of multiplexed circuits 20 include a plurality of second transistors T2 arranged in multiple rows along the second direction Y, with each row including a plurality of second transistors T2 arranged along the first direction X. The number of rows of the plurality of first transistors T1 can be equal to the number of rows of the plurality of second transistors T2 to improve the structural uniformity of the array substrate 110. The first control signal line 31 includes a plurality of first sub-lines 33, one of which is configured as the gate of a row of first transistors T1. The second control signal line 32 includes a plurality of second sub-lines 34, one of which is configured as the gate of a row of second transistors T2. In this way, the load on each control signal line 30 can be reduced, and the voltage drop on the control signal line 30 can be reduced.

[0096] In a specific example, as shown in Figure 6, multiple first transistors T1 are arranged in a first row and a second row along the second direction Y, with the first row of first transistors T1 located on the side of the second row of first transistors T1 away from the display area AA. Multiple second transistors T2 are arranged in two rows along the second direction Y.

[0097] As shown in Figure 6, the orthographic projection of the first data line 11, which is electrically connected to the first transistor T1 in the first row, on the substrate 101 coincides with the orthographic projection of the two first sub-lines 33 on the substrate 101. At this time, the capacitance formed between the first data line 11 and the two first sub-lines 33 is relatively large. Therefore, the first extension segment 321 can be provided on both second sub-lines 34 (as shown in Figure 6), or the first extension segment 321 can be provided on one of the second sub-lines 34 (as shown in Figure 6).

[0098] As shown in Figure 6, the orthographic projection of the first data line 11, which is electrically connected to the first transistor T1 in the second row, onto the substrate 101 only coincides with the orthographic projection of the first sub-line 33 near the display area AA onto the substrate 101, and does not coincide with the orthographic projection of the first sub-line 33 away from the display area AA onto the substrate 101. At this time, the capacitance formed between the first data line 11 and the first sub-line 33 is relatively small. The first extension segment 321 can be provided on both second sub-lines 34, or the first extension segment 321 can be provided on one of the second sub-lines 34, or neither of the two second sub-lines 34 can be provided with the first extension segment 321 (as shown in Figure 6). Of course, embodiments of this disclosure include, but are not limited to, the specific method shown in Figure 6, as long as the capacitance formed between the first data line 11 and the first sub-line 33 away from the display area AA is equal to the capacitance formed between the first data line 11 and the two second sub-lines 34.

[0099] In the embodiments of this disclosure, as shown in FIG6, the same multiplexing circuit 20 can be electrically connected to two adjacent data lines 10 in the display area AA. Alternatively, as shown in FIG4, the same multiplexing circuit 20 can be electrically connected to two data lines 10 spaced apart in the display area AA, that is, between the two data lines 10 electrically connected to the same multiplexing circuit 20, there are also data lines electrically connected to other multiplexing circuits 20. The choice can be made as needed during the actual fabrication of the array substrate.

[0100] In some embodiments, referring to Figures 7 and 8, the plurality of multiplexed circuits 20, including a plurality of (all) first transistors T1, are arranged in a row along a first direction X, and a first control signal line 31 is configured as the gate of the plurality of (all) first transistors T1. And / or, the plurality of multiplexed circuits, including a plurality of (all) second transistors T2, are arranged in a row along the first direction X, and a second control signal line 32 is configured as the gate of the plurality of (all) second transistors T2. Compared to the embodiment shown in Figure 6, this embodiment arranges the plurality of first transistors T1 and the plurality of second transistors T2 in a row, so that the first control signal line 31 and the second control signal line 32 each only need to include one signal line. This helps to reduce the area occupied by the multiplexed circuits 20 and the first and second control signal lines 31 and 32 within the first peripheral area BB1, which is beneficial for achieving a narrow bezel. Furthermore, as shown in Figure 7, the areas of the orthographic projections of each first data line 11 and the first control signal line 31 on the substrate 101 are equal, and the capacitance formed between each first data line 11 and the first control signal line 31 is uniform and equal, which is beneficial to improving the structural uniformity of the array substrate.

[0101] In some embodiments, referring to FIG8, the second control signal line 32 may include an alternately connected first extension 321 and second extension 322. The orthographic projection of the first extension 321 on the substrate 101 at least partially coincides with the orthographic projection of the first data line 11 on the substrate 101, and the orthographic projection of the second extension 322 on the substrate 101 does not coincide with the orthographic projection of the first data line 11 on the substrate 101. The dimension of the first extension 321 along the second direction Y is larger than the dimension of the second extension 322 along the second direction Y. This is beneficial to increase the relative area between the first data line 11 and the second control signal line 32, thereby increasing the capacitance between the first data line 11 and the second control signal line 32, so that the capacitance formed between the first data line 11 and the first control signal line 31 and the second control signal line 32 is equal.

[0102] In some embodiments, referring to Figures 6, 7, and 8, the plurality of data lines 10 further include a plurality of second data lines 12. The orthographic projection of each second data line 12 on the substrate 101 does not coincide with the first control signal line 31, but partially coincides with the second control signal line 32. Parasitic capacitance can be generated between the second data line 12 and the second control signal line 32. For the second data line 12, after the second data line 12 completes the transmission of data signals, the voltage on the second control signal line 32 undergoes a jump. Under the influence of the aforementioned parasitic capacitance, the voltage jump on the second control signal line 32 will pull up the voltage on the second data line 12.

[0103] For example, to prevent voltage fluctuations on the second data line 12 from being transmitted to the pixel electrode of the sub-pixel P, the second data line 12 can be configured to transmit data signals in the last stage of a scan cycle. In this way, voltage fluctuations on the second data line 12 caused by voltage changes on the second control signal line 32 will not affect the sub-pixel (second sub-pixel) connected to the second data line 12. This helps reduce voltage differences on the pixel electrodes of different sub-pixels P when displaying the same grayscale, reducing the risk of flickering in low-frequency displays. For instance, data signals can be transmitted to the second data line 12 in the second stage of a scan cycle.

[0104] In some embodiments, referring to Figures 4 and 5, a scan cycle H is configured to transmit data signals to a row of sub-pixels P, and the scan cycle H includes a first stage H1 and a second stage H2 arranged sequentially. The multiplexing circuit 20 is configured to: transmit data signals to the first data line 11 in the first stage H1 of each scan cycle H; and transmit data signals to the second data line 12 in the second stage H2 of each scan cycle.

[0105] Exemplary embodiments of this disclosure also provide a driving method for an array substrate, which can be used to drive the array substrate 110 shown in Figures 6, 7, and 8. In this method, the capacitance formed between the first data line 11 of the array substrate 110 and the first control signal line 31 and the second control signal line 32 is equal, and no compensation design is required for the capacitance formed between the second data line 12 and the second control signal line 32. Referring to Figure 5, a scan cycle H may include a first stage H1 and a second stage H2 set sequentially. The driving method may include:

[0106] In the first stage H1 of the Nth scan cycle, the first scan signal line 14(N) connected to the Nth row sub-pixel P transmits the working voltage, and the data writing transistor T20 of the Nth row sub-pixel P is turned on; the first control signal line 31 outputs the working voltage, and the second control signal line 32 outputs the non-working voltage. The first transistor T1 of the multiplexing circuit 20 is turned on, and the second transistor T2 is turned off. The multiplexing circuit 20 electrically connects the input signal line 15 to the first data line 11 and transmits the data signal to the first data line 11. The first data line 11 transmits the data signal to the pixel electrode of the first sub-pixel through the data writing transistor T20.

[0107] In the second stage H2 of the Nth scan cycle, the first scan signal line 14(N) connected to the Nth row sub-pixel P continues to transmit the operating voltage, and the data writing transistor T20 of the Nth row sub-pixel P is turned on. The first control signal line 31 outputs a non-operating voltage, and the second control signal line 32 outputs an operating voltage. The first transistor T1 of the multiplexing circuit 20 is turned off, and the second transistor T2 is turned on. The multiplexing circuit 20 electrically connects the input signal line 15 to the second data line 12 and transmits the data signal to the second data line 12. The second data line 12 transmits the data signal to the pixel electrode of the second sub-pixel through the data writing transistor T20.

[0108] In the first stage H1 of the (N+1)th scan cycle, the first scan signal line 14(N+1), connected to the (N+1)th row sub-pixel P, transmits the working voltage, and the data writing transistor T20 of the (N+1)th row sub-pixel P is turned on; the first control signal line 31 outputs the working voltage, and the second control signal line 32 outputs the non-working voltage. The first transistor T1 of the multiplexing circuit 20 is turned on, and the second transistor T2 is turned off. The multiplexing circuit 20 electrically connects the input signal line 15 to the first data line 11 and transmits the data signal to the first data line 11. The first data line 11 transmits the data signal to the pixel electrode of the first sub-pixel through the data writing transistor T20.

[0109] Then, data signals are written to the multiple rows of sub-pixels P in the order described above. In the first stage H1 of each scan cycle H, the multiplexing sub-circuit 20 transmits data signals to the first data line 11. In the second stage H1 of each scan cycle H, the multiplexing sub-circuit 20 transmits data signals to the second data line 12. The order in which the data signals are written in this embodiment can also be called: Z-shaped driving.

[0110] Specifically, at the time node where the first stage H1 and the second stage H2 are connected (the first time node), that is, at the time node when the voltage transmitted on the first control signal line 31 and the second control signal line 32 changes abruptly, the pull of the first control signal line 31 and the second control signal line 32 on the first data line 11 can cancel each other out, thereby reducing the voltage fluctuation on the first data line 11, and thus reducing or eliminating the voltage fluctuation on the pixel electrode of the sub-pixel P that is electrically connected to the first data line 11. At the second time node (the point in time at which the second stage H2 of a scan cycle is connected to the first stage H1 of the next scan cycle), the voltages transmitted on the first control signal line 31 and the second control signal line 32 both undergo a jump. However, the orthographic projections of the first control signal line 31 and the second data line 12 on the substrate 101 do not coincide. Therefore, the first control signal line 31 does not pull on the second data line 12. The second data line 12 is only affected by the voltage jump on the second control signal line 32. However, at the second time node, the first scan signal line 14 begins to output a non-working voltage signal. The voltage change on the second data line 12 will not affect the voltage on the pixel electrode of the sub-pixel electrically connected to the second data line 12.

[0111] In some embodiments, referring to Figures 3 and 9, the substrate 101 further includes a second peripheral region BB2 located in the display area AA, away from the first peripheral region BB1. The array substrate 110 also includes an auxiliary signal line 36 disposed in the second peripheral region BB2. The auxiliary signal line 36 is configured to transmit a voltage signal with the opposite polarity to the second control signal line 32; that is, the auxiliary signal line 36 and the second control signal line 32 transmit voltage signals with opposite polarities. Exemplarily, the auxiliary signal line 36 and the second control signal line 32 transmit voltage signals of equal magnitude but opposite polarities. For example, the auxiliary signal line 36 transmits the exact same voltage signal as the first control signal line 31, which simplifies the control of the array substrate.

[0112] The orthographic projection of the auxiliary signal line 36 on the substrate 101 does not coincide with the orthographic projection of the first data line 11 on the substrate 101. This avoids the formation of a capacitor between the auxiliary signal line 36 and the first data line 11, thereby preventing voltage jumps on the auxiliary signal line 36 from pulling on the voltage on the first data line 11.

[0113] The orthographic projection of the auxiliary signal line 36 on the substrate 101 partially coincides with the orthographic projection of the second data line 12 on the substrate 101, thus forming a capacitance between the auxiliary signal line 36 and the second data line 12. Furthermore, the capacitance formed between at least one second data line 12 and both the second control signal line 32 and the auxiliary signal line 36 is equal. Based on this, after the second data line 12 completes data signal transmission (at the second time node), the voltages of the second control signal line 32 and the auxiliary signal line 36 simultaneously undergo a jump, with one voltage decreasing and the other increasing. This reduces or completely cancels out the combined voltage pull of the second control signal line 32 and the auxiliary signal line 36 on the second data line 12, which helps to reduce voltage fluctuations on the second data line 12, thereby reducing or eliminating voltage fluctuations on the sub-pixel P electrically connected to the second data line 12.

[0114] For example, by setting the driving method of the array substrate, the second data line 12 can be controlled to transmit data signals first. In this way, the voltage fluctuation on the pixel electrode of the sub-pixel P (second sub-pixel P2) electrically connected to the second data line 12 can be reduced, and the voltage change generated by the pixel electrode of the second sub-pixel P2 at the first time node can be reduced or eliminated. This is beneficial to reduce the voltage difference on the pixel electrode of different sub-pixels P when displaying the same gray level, and reduce the risk of flickering of the display module when displaying at low frequency.

[0115] Referring again to Figure 9, the array substrate 110 further includes multiple third transistors T3 and multiple fourth transistors T4. The multiple third transistors T3 are disposed in the second peripheral region BB2 and arranged in a row along the first direction X. A first data line 11 is electrically connected to one of the third transistors T3. The multiple fourth transistors T4 are disposed in the second peripheral region BB2 and are located on the side of the multiple first transistors away from the display area AA. A second data line 12 is electrically connected to one of the fourth transistors T4. An auxiliary signal line 36 is disposed between the third transistors T3 and the fourth transistors T4. In this way, the orthographic projection of the auxiliary signal line 36 on the substrate 101 can coincide only with the orthographic projection of the second data line 12 on the substrate 101, and not with the orthographic projection of the first data line 11 on the substrate 101.

[0116] In the embodiments of this disclosure, the first data line 11 refers to the portion between the first transistor T1 and the third transistor T3, and the second data line 12 refers to the portion between the second transistor T2 and the fourth transistor T4. The array substrate 110 may further include multiple output signal lines 16, which are disposed within the second peripheral region BB2 and electrically connected to a data line 10 via the third transistor T3 / fourth transistor T4. At the second time node, the third transistor T3 may be in a turned-off state, thus preventing voltage fluctuations on the first data line 11 and preventing voltage fluctuations on the auxiliary signal line 36 from affecting the first data line 11.

[0117] It should be noted that the embodiment of the array substrate described in FIG. 9 can be implemented alone, or it can be combined with any of the embodiments in FIG. 4, 6, 7, and 8. When the embodiment of the array substrate described in FIG. 9 is implemented alone, the array substrate can employ a Z-shaped drive. However, unlike the driving method shown in FIG. 4, in the first stage H1 of each scan cycle H, the multiplexing circuit 20 transmits a data signal to the second data line 12, and in the second stage H2 of each scan cycle H, the multiplexing circuit 20 transmits a data signal to the first data line 11. When the embodiment of the array substrate described in FIG. 9 is combined with any of the embodiments in FIG. 6, 7, and 8, the array substrate can employ a Z-shaped drive, and can transmit a data signal to one of the first data line 11 and the second data line 12 in the first stage H1 of each scan cycle H, and transmit a data signal to the other of the first data line 11 and the second data line 12 in the second stage H2.

[0118] In some embodiments, when the array substrate described in FIG9 is combined with any of the embodiments in FIG6, 7 and 8, referring to FIG10, a scan cycle H is configured to transmit data signals to a row of sub-pixels P, and the scan cycle H includes a first stage H1 and a second stage H2 arranged sequentially. The multiplexing circuit 20 is configured to: transmit data signals to the first data line 11 and the second data line 12 respectively in the first stage H1 and the second stage H2 of the same scan cycle H; and transmit data signals to the first data line 11 and the second data line 12 respectively in the first stage H1 or the second stage H2 of two adjacent scan cycles H.

[0119] For example, in the first stage H1 of the Nth scan cycle H, the multiplexing circuit 20 transmits a data signal to the first data line 11; in the second stage H2 of the Nth scan cycle H, the multiplexing circuit 20 transmits a data signal to the second data line 12; in the first stage H1 of the (N+1)th scan cycle H, the multiplexing circuit 20 transmits a data signal to the second data line 12; ..., and transmits data signals to the first data line 11 and the second data line 12 in this order. The order in which the data signals are written provided in this embodiment can also be called bow-shaped drive.

[0120] In summary, when the array substrate embodiment shown in Figure 9 is combined with any of the embodiments in Figures 4, 6, 7 and 8, the array substrate can be driven not only in a Z-shape but also in a bow-shaped shape.

[0121] Exemplary embodiments of this disclosure also provide a driving method for an array substrate, which can be used to drive an array substrate 110 formed as described in any combination of the embodiments in FIG9, 4, 6, 7, and 8. In this case, the capacitance formed between the first data line 11 of the array substrate 110 and the first control signal line 31 and the second control signal line 32 is equal, and the capacitance formed between the second data line 12 and the second control signal line 32 and the auxiliary signal line 36 is equal. Referring to FIG10, a scan cycle H may include a first stage H1 and a second stage H2 sequentially configured. The driving method may include:

[0122] In the first stage H1 of the Nth scan cycle, the first scan signal line 14(N) connected to the Nth row sub-pixel P transmits the working voltage, and the data writing transistor T20 of the Nth row sub-pixel P is turned on; the first control signal line 31 outputs the working voltage, and the second control signal line 32 outputs the non-working voltage. The first transistor T1 of the multiplexing circuit 20 is turned on, and the second transistor T2 is turned off. The multiplexing circuit 20 electrically connects the input signal line 15 to the first data line 11 and transmits the data signal to the first data line 11. The first data line 11 transmits the data signal to the pixel electrode of the first sub-pixel through the data writing transistor T20.

[0123] In the second stage H2 of the Nth scan cycle, the first scan signal line 14(N) connected to the Nth row sub-pixel P continues to transmit the operating voltage, and the data writing transistor T20 of the Nth row sub-pixel P is turned on. The first control signal line 31 outputs a non-operating voltage, and the second control signal line 32 outputs an operating voltage. The first transistor T1 of the multiplexing circuit 20 is turned off, and the second transistor T2 is turned on. The multiplexing circuit 20 electrically connects the input signal line 15 to the second data line 12 and transmits the data signal to the second data line 12. The second data line 12 transmits the data signal to the pixel electrode of the second sub-pixel through the data writing transistor T20.

[0124] In the first stage H1 of the (N+1)th scan cycle, the second scan signal line 14(N+1), connected to the (N+1)th row sub-pixel P, transmits the working voltage, and the data writing transistor T20 of the (N+1)th row sub-pixel P is turned on; the second control signal line 32 outputs the working voltage, and the first control signal line 31 outputs the non-working voltage. The first transistor T1 of the multiplexing circuit 20 is turned off, and the second transistor T2 is turned on. The multiplexing circuit 20 electrically connects the input signal line 15 to the second data line 12 and transmits the data signal to the second data line 12. The second data line 12 transmits the data signal to the pixel electrode of the second sub-pixel through the data writing transistor T20.

[0125] Continuing in the above order, data signals are written to multiple rows of sub-pixels P sequentially. In the first stage H1 and the second stage H2 of each scan cycle H, the multiplexing sub-circuit 20 transmits data signals to the first data line 11 and the second data line 12 respectively. In the first stage H1 of two adjacent scan cycles, data signals are transmitted to the first data line 11 and the second data line 12 respectively, and in the second stage H2 of two adjacent scan cycles, data signals are transmitted to the first data line 11 and the second data line 12 respectively.

[0126] Specifically, at the first time point, the pull exerted on the first data line 11 by the first control signal line 31 and the second control signal line 32 can cancel each other out, reducing voltage fluctuations on the first data line 11, and thus reducing or eliminating voltage fluctuations on the pixel electrode of the first sub-pixel P. At the second time point, the pull exerted on the second data line 12 by the second control signal line 32 and the auxiliary signal line 36 can cancel each other out, reducing voltage fluctuations on the second data line 12, and thus reducing or eliminating voltage fluctuations on the pixel electrode of the second sub-pixel P.

[0127] In some embodiments, referring to FIG11, the array substrate 110 further includes a plurality of first scan signal lines 14, one of which is electrically connected to a row of sub-pixels P. The first scan signal lines 14 are configured to control the plurality of (all) data lines 10 to transmit data signals to the row of sub-pixels P. The plurality of sub-pixels P includes a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2. The first sub-pixels P1 include a first pixel electrode PX1, and the second sub-pixels P2 include a second pixel electrode PX2. A scan cycle is configured to transmit data signals to a row of sub-pixels P, and the scan cycle includes a first stage and a second stage configured sequentially. In the first stage, the multiplexing circuit 20 transmits data signals to the first pixel electrode PX1, and in the second stage, the multiplexing circuit 20 transmits data signals to the second pixel electrode PX2. The capacitances formed between the first scan signal lines 14 and the first pixel electrode PX1 and the second pixel electrode PX2 are not equal.

[0128] As described above, the voltage on the pixel electrode of sub-pixel P is affected not only by the voltage fluctuations of the control signal line 30, but also by the voltage fluctuations of the first scan signal line 14. In the embodiments of this disclosure, the capacitance (Cgs) formed between the first scan signal line 14 and the first pixel electrode PX1 and the second pixel electrode PX2 can be set to be unequal, so that the pull ΔVP2 of the first pixel electrode PX1 and the second pixel electrode PX2 on the first scan signal line 14 at the second time node is different, thereby balancing the difference in the pull ΔVP1 of the control signal line 30 on the first pixel electrode PX1 and the second pixel electrode PX2 at the first time node. For example, the pull of the first pixel electrode PX1 on the first scan signal line 14 is denoted as ΔVP21, and the pull of the second pixel electrode PX2 on the first scan signal line 14 is denoted as ΔVP22. For the first pixel electrode PX1, the voltage pull it receives is ΔVP1 + ΔVP21, and for the second pixel electrode PX2, the voltage pull it receives is ΔVP22. By calculation, the difference between (ΔVP1 + ΔVP21) and ΔVP22 can be minimized to reduce the voltage difference between the first pixel electrode PX1 and the second pixel electrode PX2 when the first sub-pixel P1 and the second sub-pixel P2 display the same grayscale. This also reduces the risk of flickering in the display module during low-frequency display.

[0129] In some embodiments, the capacitance Cgs formed between the first scan signal line 14 and the first pixel electrode PX1 is smaller than the capacitance Cgs formed between the first scan signal line 14 and the second pixel electrode PX2. Thus, the voltage pull ΔVP21 generated by the first scan signal line 14 on the first pixel electrode PX1 is less than the voltage pull ΔVP22 generated on the second pixel electrode PX2. This helps to balance the difference between (ΔVP1 + ΔVP21) and ΔVP22, reducing the voltage difference between the first pixel electrode PX1 and the second pixel electrode PX2 when the first sub-pixel P1 and the second sub-pixel P2 display the same grayscale, and also reduces the risk of flickering in the display module during low-frequency display.

[0130] In some embodiments, as shown in FIG11, the first sub-pixel P1 includes a fifth transistor T5, or in other words, the data writing transistor T20 of the first sub-pixel P1 is the fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first scan signal line 14, the first source pattern S1 is electrically connected to the data line 10, and the first drain pattern D1 is electrically connected to the first pixel electrode PX1. The second sub-pixel P2 includes a sixth transistor T6, or in other words, the data writing transistor T20 of the second sub-pixel P2 is the sixth transistor T6. The control electrode of the sixth transistor T6 is electrically connected to the first scan signal line 14, the second source pattern S2 is electrically connected to the data line 11, and the second drain pattern D2 is electrically connected to the second pixel electrode PX2.

[0131] In the orthographic projection of the first scan signal line 14, the first drain pattern D1, and the second drain pattern D2 onto the substrate 101, the area of ​​the second drain pattern D2 is larger than the area of ​​the first drain pattern D1, and the area of ​​the second drain pattern D2 overlapping with the first scan signal line 14 is larger than the area of ​​the first drain pattern D1 overlapping with the first scan signal line 14. This ensures that the capacitance Cgs1 formed between the first scan signal line 14 and the first pixel electrode PX1 is smaller than the capacitance Cgs2 formed between the first scan signal line 14 and the second pixel electrode PX2.

[0132] In some embodiments, referring to FIG12, the display module 1100 may include a driving circuit board, which may include a data processing unit 40. The data processing unit 40 is electrically connected to the multiplexing circuit 20 and is configured to transmit data signals to the multiplexing circuit 20, and to compensate for different voltage values ​​of a first data signal and / or a second data signal used to make the first sub-pixel P1 and the second sub-pixel P2 display the same gray level. In this way, the difference ΔVP1 in the pull of the control signal line 30 on the first pixel electrode PX1 and the second pixel electrode PX2 at the first time node can be compensated directly by changing the voltage value of the data signals written to the first sub-pixel P1 and the second sub-pixel P2, thereby reducing the voltage difference on the first pixel electrode PX1 and the second pixel electrode PX2 when the first sub-pixel P1 and the second sub-pixel P2 display the same gray level, and reducing the risk of flickering of the display module during low-frequency display.

[0133] For example, as shown in FIG12, the data processing unit 40 may include, but is not limited to, a data receiving subunit Data1, a buffer subunit Latch, a voltage amplification subunit Level Shift, a digital-to-analog converter subunit DAC, a gamma compensation subunit Gamma, a data compensation subunit Source, and an amplifier subunit OP. The data receiving subunit Data1 can receive display data signals from the interface, and the data signals are sequentially processed by the buffer subunit Latch, the voltage amplification subunit Level Shift, the digital-to-analog converter subunit DAC, the gamma compensation subunit, the data compensation subunit Source, and the amplifier subunit OP before being transmitted to the input signal line, and further transmitted to the multiplexing circuit 20.

[0134] For example, the data processing unit 40 may perform compensation in the gamma compensation subunit Gamma and / or the data compensation subunit Source. For instance, different voltage values ​​can be compensated for by the gamma compensation subunit Gamma for the first data signal and / or the second data signal. Alternatively, different voltage values ​​can be compensated for by the data compensation subunit Source for the first data signal and / or the second data signal. Alternatively, different voltage values ​​can be compensated for by the gamma compensation subunit Gamma first, and then by the compensation subunit Source for the first data signal and / or the second data signal.

[0135] It should be noted that the data processing unit 40 can adjust the compensation of the first data signal and / or the second data signal within a certain range, and has a minimum adjustment range. For example, the data processing unit 40 adjusts the first data signal and / or the second data signal in 10mV increments, and adjusts the positive and negative data signals in the same direction, such as compensating both the positive and negative data signals with +10mV voltage, or compensating both with -10mV voltage.

[0136] In some embodiments, referring to FIG13, the data processing unit 40 is configured to compensate a positive voltage for a first data signal (the data signal output by the first stage H1). Exemplarily, the compensation value for the first data signal by the data processing unit 40 is +ΔVP1, and the compensation voltage for the second data signal remains unchanged. This balances the downward pull ΔVP1 exerted by the control signal line 30 on the pixel electrode (first data signal) of the first sub-pixel. For example, the voltage of the second data signal is a reference voltage ±V1, and the compensated voltages of the first data line signal are V1+ΔVP1 and -V1+ΔVP1, respectively; where the positive (+) and negative (-) signs only represent the polarity of the voltage.

[0137] In some embodiments, referring to FIG14, the data processing unit 40 is configured to compensate for a negative voltage on the second data signal (the data signal transmitted in the second stage H2). Exemplarily, the compensation value for the second data signal by the data processing unit 40 is -ΔVP1, while the compensation voltage for the first data signal remains unchanged. This balances the downward pull ΔVP1 exerted by the control signal line 30 on the pixel electrode (first data signal) of the first sub-pixel. For example, the voltage of the first data signal is a reference voltage ±V2, and the compensated voltages of the second data line signal are V2-ΔVP1 and -V2-ΔVP1, respectively.

[0138] In some other embodiments, referring to FIG15, the data processing unit 40 is configured to compensate for a positive voltage on the first data signal and a negative voltage on the second data signal. Exemplarily, the compensation value for the first data signal by the data processing unit 40 is +1 / 2ΔVP1, and the compensation value for the second data signal is -1 / 2ΔVP1. For example, the initial reference voltages of the first and second data signals are ±V3. The compensated voltages of the first data signal are +V3+1 / 2ΔVP1 and -V3+1 / 2ΔVP1, respectively; the compensated voltages of the second data signal are +V3-1 / 2ΔVP1 and -V3-1 / 2ΔVP1, respectively.

[0139] The inventors' research also revealed that the first and second transistors included in the multiplexing circuit 20 may experience reliability drift after prolonged operation, leading to issues such as vertical lines, image retention, and LPWG (Last-Level Graphics) artifacts in the displayed image. The larger the source-drain voltage difference Vgs between the first and second transistors, the greater the bias of the first and second transistors, and the more severe the threshold voltage drift. To address this problem, related technologies typically reduce the bias effect on the first transistor T1 and the second transistor T2 by increasing the number of control signal lines 30 or decreasing the voltage on the control signal lines 30. However, increasing the number of control signal lines 30 results in the multiplexing circuit 20 occupying more space and shortening the charging time of the sub-pixel data signal, while decreasing the voltage on the control signal lines 30 may reduce the charging efficiency of the first and second transistors.

[0140] To address the aforementioned technical problems, the embodiments of this disclosure provide an array substrate, as shown in Figures 4 and 6. When the first control signal line 31 includes two first sub-lines 33 and the second control signal line 32 includes two second sub-lines 34, the multiplexing circuit 20 is electrically connected to the two data lines 10. The multiplexing circuits 20 include multiple first multiplexing circuits 21 and multiple second multiplexing circuits 22, with each multiplexing circuit 21 and 22 electrically connected to a first sub-line 33 and a second sub-line 34, respectively. The data lines 11, electrically connected to the first multiplexing circuits 21 and 22, transmit data signals of opposite polarity in the same frame. For example, the first multiplexing circuit 21 transmits a negative polarity data signal, and the second multiplexing circuit 22 transmits a positive polarity data signal. Each data line 10 transmits data signals of opposite polarity in adjacent frames; that is, the array substrate 110 employs a column-to-column reversal driving method.

[0141] Referring to Figure 16, the two first sub-lines 33 are configured to transmit control signals of the same polarity but different magnitudes. And / or, the two second sub-lines 34 are configured to transmit control signals of the same polarity but different magnitudes. Exemplarily, the two first sub-lines 33 and the two second sub-lines 34 can select control signals of different magnitudes in different frames according to the polarity of the data signals transmitted by the multiplexing circuit 20.

[0142] For example, the operating voltage of the first sub-line 33 and the second sub-line 34, which are electrically connected to the multiplexing circuit 20 transmitting negative polarity data signals, can be reduced. In this case, the gate-source voltage difference Vgs of the first and second transistors is large, so even if the operating voltage of the first sub-line 33 and the second sub-line 34 is reduced, the charging efficiency of the first and second transistors will not be reduced. The non-operating voltage remains unchanged, which reduces the leakage current of the first and second transistors when they are off. Similarly, the non-operating voltage of the first sub-line 33 and the second sub-line 34, which are electrically connected to the multiplexing circuit 20 transmitting positive polarity data signals, can also be reduced, while the operating voltage remains unchanged. In this way, without reducing the charging efficiency of the first and second transistors in the multiplexing circuit 20, the voltage of the control signals of the first and second transistors can be reduced, thereby reducing the bias voltage of the first and second transistors and reducing the risk of reliability drift.

[0143] In some embodiments, of the two first sub-lines 33, one controlling the transmission of negative polarity data signals by the first multiplexing circuit 21 and the second multiplexing circuit 22 is designated as the first target sub-line 33A, and the other as the second target sub-line 33B. Of the two second sub-lines 34, one controlling the transmission of negative polarity data signals by the first multiplexing circuit 21 and the second multiplexing circuit 22 is designated as the third target sub-line 34A, and the other as the fourth target sub-line 34B. That is, the first target sub-line 33A and the third target sub-line 34A are electrically connected to the multiplexing circuit 20 transmitting negative polarity data signals, while the first target sub-line 33B and the third target sub-line 34B are electrically connected to the multiplexing circuit 20 transmitting positive polarity data signals.

[0144] Referring to Figure 16, the voltage of the control signal transmitted by the first target sub-line 33A is less than the voltage of the control signal transmitted by the second target sub-line 33B. And / or, the voltage of the control signal transmitted by the third target sub-line 34A is less than the voltage of the control signal transmitted by the fourth target sub-line 34B.

[0145] For example, the operating voltage VGH1 of the control signal transmitted by the first target sub-line 33A is less than the operating voltage VGH2 of the control signal transmitted by the second target sub-line 33B; and the non-operating voltage VGL1 of the control signal transmitted by the first target sub-line 33A is less than the non-operating voltage VGL2 of the control signal transmitted by the second target sub-line 33B.

[0146] Referring again to Figure 16, in some embodiments, the difference between the operating voltage and non-operating voltage (VGH1-VGL1) of the control signal transmitted by the first target sub-line 33A is equal to the difference between the operating voltage and non-operating voltage (VGH2-VGL2) of the control signal transmitted by the second target sub-line 33B. And / or, the difference between the operating voltage and non-operating voltage (VGH1-VGL1) of the control signal transmitted by the third target sub-line 34A is equal to the difference between the operating voltage and non-operating voltage (VGH2-VGL2) of the control signal transmitted by the fourth target sub-line 34B.

[0147] Referring again to Figure 16, the first target sub-line 33A and the third target sub-line 34A transmit control signals of equal magnitude but opposite polarity. And / or, the second target sub-line 33B and the fourth target sub-line 34B transmit control signals of equal magnitude but opposite polarity.

[0148] The above embodiments will be illustrated below through two specific examples.

[0149] Example 1: In related technologies, the operating voltages VGH transmitted by the two first sub-lines 33 and the two second sub-lines 34 are all equal and both are +18V, while the non-operating voltages VGL transmitted by the two first sub-lines 33 and the two second sub-lines 34 are both -12V. In this case, the voltage difference ΔVG between each first sub-line 33 and the second sub-line 34 is 30V. Taking a maximum voltage of +5V for positive data signals and -5V for negative data signals as an example, see Table 1 below.

[0150] Table 1:

[0151] Here, Vgs refers to the voltage difference between the gate and source of the first transistor / second transistor (hereinafter referred to as the gate-source voltage difference), that is, the voltage difference between the first sub-line 33 and the two second sub-lines 34 and the data signal on the input signal line 15. As shown in Table 1, in Example 1, when the first transistor / second transistor is turned on, the largest gate-source voltage difference Vgs occurs when the maximum voltage for transmitting a negative data signal is reached, at which point Vgs = 18V - (-5V) = 23V. The smallest gate-source voltage difference Vgs occurs when the maximum voltage for transmitting a positive data signal is reached, at which point Vgs = 18V - 5V = 13V. In other words, as long as Vgs is greater than 13V, the first transistor / second transistor can be fully turned on, ensuring the charging efficiency of the first transistor / second transistor.

[0152] When the first transistor / second transistor is off, the maximum gate-source voltage difference Vgs occurs when the maximum voltage for transmitting negative polarity data signals is reached. At this time, Vgs = -12V - (-5V) = -7V. In other words, as long as the maximum gate-source voltage difference Vgs is less than -7V, the first transistor / second transistor can meet the conditions for non-leakage operation.

[0153] Example 2: The operating voltage of the first target sub-line 33A and the third target sub-line 34A is 13V, and the non-operating voltage is -12V. The operating voltage of the second target sub-line 33B and the fourth target sub-line 34B is 18V, and the non-operating voltage is -7V. That is, when transmitting negative polarity data signals, the operating voltage of the first sub-line 33 and the second sub-line 34 is 13V, and the non-operating voltage is -12V; when transmitting negative polarity data signals, the operating voltage of the first sub-line 33 and the second sub-line 34 is 18V, and the non-operating voltage is -7V. At this time, the voltage difference between each of the first sub-line 33 and the second sub-line 34 is 25V. For example, if the maximum voltage of the positive polarity data signal is +5V and the maximum voltage of the negative polarity data signal is -5V, see Table 2 below.

[0154] Table 2:

[0155] As shown in Table 2 above, when the first transistor / second transistor is turned on, the minimum gate-source voltage difference Vgs occurs when the voltage for transmitting positive data signals is at its maximum, at which point Vgs = 18V - 5V = 13V, and when the voltage for transmitting negative data signals is at its minimum (0V), at which point Vgs = 13V - 0V = 13V. Therefore, reducing the operating voltage of the first target sub-line 33A and the third target sub-line 34A will not reduce the charging efficiency of the first transistor / second transistor.

[0156] When the first transistor / second transistor is off, the maximum gate-source voltage difference Vgs occurs when the voltage for transmitting negative data signals is at its maximum, at which point Vgs = -12V - (-5V) = -7V, and also when the voltage for transmitting positive data signals is at its minimum, at which point Vgs = -7V - 0V = -7V. In other words, reducing the non-operating voltage of the second target sub-line 33B and the fourth target sub-line 34B will not cause the first transistor / second transistor to leak current.

[0157] In summary, the embodiments of this disclosure reduce the operating voltage of the first sub-line 33 and the second sub-line 34 electrically connected to the multiplexing circuit 20 for transmitting negative polarity data signals, and reduce the non-operating voltage (regardless of voltage polarity) of the first sub-line 33 and the second sub-line 34 electrically connected to the multiplexing circuit 20 for transmitting positive polarity data signals. This reduces the gate voltage of the first transistor and the second transistor without reducing their charging efficiency or increasing the leakage risk of the multiplexing circuit 20. Consequently, it reduces the bias of the first transistor and the second transistor and lowers the risk of reliability drift.

[0158] In some embodiments, the first control signal line 31 of the array substrate includes two first sub-lines 33, and the second control signal line 32 includes two second sub-lines 34. A multiplexing circuit 20 is electrically connected to the two data lines 10, and the multiplexing circuits 20 include multiple first multiplexing circuits 21 and multiple second multiplexing circuits 22. The first multiplexing circuits 21 and 22 are electrically connected to one first sub-line 33 and one second sub-line 34, respectively. The data lines 10, which are electrically connected to the first multiplexing circuits 21 and 22, transmit data signals of opposite polarity in the same frame, and each data line 10 transmits data signals of opposite polarity in two adjacent frames.

[0159] Referring to Figures 17 and 18, the drive circuit board also includes a power supply unit 50, a timing controller (such as a TCON chip) 60, and a power output circuit 70.

[0160] The power supply unit 50 is configured to provide a first set of voltage signals 51 and a second set of voltage signals 52. The first set of voltage signals includes a first operating voltage VGH1 and a first non-operating voltage VGL1, and the second set of voltage signals 52 includes a second operating voltage VGH2 and a second non-operating voltage VGL2. The first operating voltage VGH1 is less than the second operating voltage VGH2, and the first non-operating voltage VGL1 is less than the second non-operating voltage VGL2.

[0161] The timing controller 60 is configured to output a first set of selection signals Ti1 based on the polarity of the data signal transmitted to the first multiplexing circuit 21, and to output a second set of selection signals Ti2 based on the polarity of the data signal transmitted to the second multiplexing circuit 22.

[0162] The power output circuit 70 is electrically connected to the timing controller 60, the power supply unit 50, the two first sub-lines 33, and the two second sub-lines 34.

[0163] The power output circuit is configured to: transmit one of a first group voltage signal 51 and a second group voltage signal 52 to a first sub-line 33 and a second sub-line 34 electrically connected to the first multiplexing circuit 21 according to a first group selection signal Ti1; and transmit the other of the first group voltage signal 51 and the second group voltage signal 52 to a first sub-line 33 and a second sub-line 34 electrically connected to the second multiplexing circuit 22 according to a second group selection signal Ti2.

[0164] For example, as shown in FIG18, the first set of selection signals Ti1 output by the timing controller 60 may include a first signal Ti11 and a second signal Ti12; the second set of selection signals Ti2 may include a third signal Ti21 and a fourth signal Ti22.

[0165] The power output circuit 70 may include two selection sub-units 33 / 34IN, a first gating circuit, a second gating circuit, and two level conversion sub-units (L / S sub-units). The selection sub-units 33 / 34IN are used to select one first sub-line 33 and one second sub-line 34 that require the output signal, for example, selecting one first sub-line 33 and one second sub-line 34 electrically connected to the first multiplexing circuit 21, or selecting one first sub-line 33 and one second sub-line 34 electrically connected to the second multiplexing circuit 21. The first gating circuit may include a first selection transistor T31, a second selection transistor T32, a third selection transistor T33, and a fourth selection transistor T34. The second gating circuit may include a fifth selection transistor T35, a sixth selection transistor T36, a seventh selection transistor T37, and an eighth selection transistor T38.

[0166] Specifically, the first selection transistor T31 and the second selection transistor T32 are controlled by the first signal Ti11, and selectively transmit one of the first operating voltage VGH1 and the second operating voltage VGH2 to the level conversion subunit. The third selection transistor T33 and the fourth selection transistor T34 are controlled by the second signal Ti12, and selectively transmit one of the first non-operating voltage VGL1 and the second non-operating voltage VGL2 to the level conversion subunit. The fifth selection transistor T35 and the sixth selection transistor T36 are controlled by the third signal Ti21, and selectively transmit one of the first operating voltage VGH1 and the second operating voltage VGH2 to the level conversion subunit. The seventh selection transistor T37 and the eighth selection transistor T38 are controlled by the fourth signal Ti22, and selectively transmit one of the first non-operating voltage VGL1 and the second non-operating voltage VGL2 to the level conversion subunit.

[0167] For example, the process by which the power output circuit transmits the first set of voltage signals 51 and 52 to the first sub-line 33 and the second sub-line 34 electrically connected to the first multiplexing circuit 21 according to the first set of selection signals Ti1 includes: when transmitting a negative polarity data signal to the first multiplexing circuit 21, the first selection transistor T31 and the third selection transistor T33 are turned on under the first signal Ti11 and the second signal Ti12, respectively. The first selection circuit transmits the first set of voltage signals 51 provided by the power supply unit 50 to the level conversion sub-unit, and the level conversion sub-unit transmits it to a first sub-line 33 and a second sub-line 34 electrically connected to the first multiplexing circuit 21. The process by which the power output circuit transmits the first set of voltage signals 51 and 52 to the first sub-line 33 and the second sub-line 34 electrically connected to the second multiplexing circuit 22 according to the second set of selection signals Ti2 is similar to the above process and will not be described again here.

[0168] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

An array substrate, comprising: The substrate includes a display area and a first peripheral area adjacent to one side of the display area; Multiple sub-pixels are disposed in the display area, and the multiple sub-pixels are arranged in multiple rows and multiple columns. Each row includes multiple sub-pixels arranged along a first direction, and each column includes multiple sub-pixels arranged along a second direction. The first direction and the second direction intersect. Multiple data lines pass through the display area and extend to the first peripheral area, and one of the data lines is electrically connected to a column of the sub-pixels; Multiple multiplexing circuits are disposed in the first peripheral area, and each multiplexing circuit is electrically connected to at least two data lines; A first control signal line and a second control signal line are disposed in the first peripheral area and are both electrically connected to the multiplexing circuit. The first control signal line and the second control signal line are configured to transmit voltage signals with opposite polarities. The first control signal line and the second control signal line are configured to control the multiplexing circuit to transmit data signals to at least two data lines connected to the multiplexing circuit, respectively. The plurality of data lines include a plurality of first data lines, the orthographic projection of each first data line on the substrate partially overlaps with the first control signal line and the second control signal line, and at least one first data line has an equal capacitance with the first control signal line and the second control signal line. According to claim 1, the array substrate, wherein, The multiplexing circuit includes a first transistor and a second transistor, wherein the first transistor is located on the side of the second transistor away from the display area; The first control signal line is located on the side of the second control signal line away from the display area, the first control signal line is configured as the gate of the first transistor, and the second control signal line is configured as the gate of the second transistor; The first data line includes a first extension and a first electrode portion located in a first peripheral region. The orthographic projections of the first extension and the second control signal line on the substrate intersect each other. The orthographic projection of the first electrode portion on the substrate coincides with the orthographic projection of the first control signal line on the substrate and is configured as the first electrode of the first transistor. According to claim 2, the array substrate, wherein, The first electrode portion includes a plurality of sub-portions arranged side by side along the first direction, and the sum of the dimensions of the plurality of sub-portions along the first direction is greater than the dimension of the first extension portion along the first direction; The second control signal line includes a first extension and a second extension. The orthographic projection of the first extension on the substrate at least partially coincides with the orthographic projection of the first data line on the substrate, and the orthographic projection of the second extension on the substrate does not coincide with the orthographic projection of the first data line on the substrate. The dimension of the first extension segment along the second direction is greater than the dimension of the second extension segment along the second direction. The array substrate according to claim 2 or 3, wherein, The multiplexed circuits include multiple first transistors arranged in multiple rows along the second direction, each row including multiple first transistors arranged along the first direction; the first control signal line includes multiple first sub-lines, each first sub-line being configured as the gate of a row of first transistors; and / or, The multiplexed circuits include multiple second transistors arranged in multiple rows along the second direction, each row including multiple second transistors arranged along the first direction, the second control signal line including multiple second sub-lines, and one second sub-line configured as the gate of a row of second transistors. The array substrate according to any one of claims 1 to 4, wherein, The first control signal line includes two first sub-lines, and the second control signal line includes two second sub-lines; The multiplexing circuit is electrically connected to the two data lines, and the multiple multiplexing circuits include multiple first multiplexing circuits and multiple second multiplexing circuits, wherein the first multiplexing circuit and the second multiplexing circuit are electrically connected to a first sub-line and a second sub-line, respectively. The data lines electrically connected to the first multiplexing circuit and the second multiplexing circuit respectively transmit data signals of opposite polarity in the same frame, and each data line transmits data signals of opposite polarity in two adjacent frames; The two first sub-lines are configured to transmit control signals of the same polarity but different magnitudes; and / or, the two second sub-lines are configured to transmit control signals of the same polarity but different magnitudes. According to claim 5, the array substrate, wherein, Of the two first sub-lines, one controlling the transmission of negative polarity data signals by the first multiplexing circuit and the second multiplexing circuit is the first target sub-line, and the other is the second target sub-line; of the two second sub-lines, one controlling the transmission of negative polarity data signals by the first multiplexing circuit and the second multiplexing circuit is the third target sub-line, and the other is the fourth target sub-line. The voltage of the control signal transmitted by the first target sub-line is less than the voltage of the control signal transmitted by the second target sub-line; and / or, the voltage of the control signal transmitted by the third target sub-line is less than the voltage of the control signal transmitted by the fourth target sub-line. According to the array substrate of claim 6, wherein, The difference between the operating voltage and the non-operating voltage of the control signal transmitted by the first target sub-line is equal to the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the second target sub-line; and / or, the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the third target sub-line is equal to the difference between the operating voltage and the non-operating voltage of the control signal transmitted by the fourth target sub-line. The array substrate according to claim 6 or 7, wherein, The first target sub-line transmits control signals of equal magnitude but opposite polarity to the third target sub-line; and / or, the second target sub-line transmits control signals of equal magnitude but opposite polarity to the fourth target sub-line. The array substrate according to claim 2 or 3, wherein, The multiplexed circuits include multiple first transistors arranged in a row along the first direction, and the first control signal line is configured as the gate of the multiple first transistors; and / or, The multiplexed circuits include multiple second transistors arranged in a row along the first direction, and the second control signal line is configured as the gate of the multiple second transistors. The array substrate according to any one of claims 1 to 9, wherein, The multiple data lines also include multiple second data lines, wherein the orthographic projection of each second data line on the substrate does not coincide with the first control signal line, but partially coincides with the second control signal line; The substrate further includes a second peripheral region located in the display area away from the first peripheral region; The array substrate further includes an auxiliary signal line disposed in the second peripheral region and configured to transmit a voltage signal with the opposite polarity to the second control signal line; the orthographic projection of the auxiliary signal line on the substrate does not coincide with the orthographic projection of the first data line on the substrate, but partially coincides with the orthographic projection of the second data line on the substrate. In this configuration, at least one of the second data lines has an equal capacitance to the second control signal line and the auxiliary signal line. The array substrate according to claim 10 further comprises: Multiple third transistors are disposed in the second peripheral region and arranged in a row along the first direction; a first data line is electrically connected to one of the third transistors. A plurality of fourth transistors are disposed in the second peripheral area and located on the side of the plurality of first transistors away from the display area, and a second data line is electrically connected to one of the fourth transistors; The auxiliary signal line is located between the third transistor and the fourth transistor. The array substrate according to any one of claims 1 to 11, wherein, The multiple data lines also include multiple second data lines, wherein the orthographic projection of each second data line on the substrate does not coincide with the first control signal line, but partially coincides with the second control signal line; A scan cycle is configured to transmit data signals to a row of subpixels, and the scan cycle includes a first stage and a second stage set sequentially. The multiplexing circuit is configured to: transmit a data signal to the first data line during the first phase of each scan cycle; and transmit a data signal to the second data line during the second phase of each scan cycle. The array substrate according to claim 10 or 11, wherein, A scan cycle is configured to transmit data signals to a row of subpixels, and the scan cycle includes a first stage and a second stage set sequentially. The multiplexing circuit is configured to: transmit data signals to the first data line and the second data line respectively during the first stage and the second stage of the same scan cycle; and transmit data signals to the first data line and the second data line respectively during the first stage or the second stage of two adjacent scan cycles. The array substrate according to any one of claims 1 to 13 further includes a plurality of first scan signal lines, one of which is electrically connected to a row of sub-pixels, and the first scan signal line is configured to control the plurality of data lines to transmit data signals to the row of sub-pixels; wherein, The plurality of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, wherein the first sub-pixel includes a first pixel electrode and the second sub-pixel includes a second pixel electrode; A scan cycle is configured to transmit data signals to a row of sub-pixels, and the scan cycle includes a first stage and a second stage configured sequentially; in the first stage, the multiplexing circuit transmits data signals to the first pixel electrode, and in the second stage, the multiplexing circuit transmits data signals to the second pixel electrode. The capacitances formed between the first scan signal line and the first pixel electrode and the second pixel electrode are not equal. According to the array substrate of claim 14, wherein, The capacitance formed between the first scan signal line and the first pixel electrode is smaller than the capacitance formed between the first scan signal line and the second pixel electrode. According to the array substrate of claim 15, wherein, The first sub-pixel includes a fifth transistor, the control electrode of the fifth transistor is electrically connected to the first scan signal line, the first source pattern is electrically connected to the data line, and the first drain pattern is electrically connected to the first pixel electrode. The second sub-pixel includes a sixth transistor, the control electrode of which is electrically connected to the first scan signal line, the second source pattern is electrically connected to the data line, and the second drain pattern is electrically connected to the second pixel electrode. In the orthographic projection of the first scan signal line, the first drain pattern, and the second drain pattern onto the substrate, the area of ​​the second drain pattern is larger than the area of ​​the first drain pattern, and the area of ​​the second drain pattern overlapping with the first scan signal line is larger than the area of ​​the first drain pattern overlapping with the first scan signal line. A display module, comprising: The array substrate as described in any one of claims 1 to 16 includes a plurality of first sub-pixels and a plurality of second sub-pixels, a scan cycle is configured to transmit a data signal to a row of sub-pixels, and the scan cycle includes a first stage and a second stage arranged sequentially; in the first stage, a multiplexing circuit transmits a first data signal to the first sub-pixel, and in the second stage, the multiplexing circuit transmits a second data signal to the second sub-pixel. The driving circuit board includes a data processing unit electrically connected to the multiplexing circuit and configured to transmit data signals to the multiplexing circuit, and to compensate for different voltage values ​​for a first data signal and / or a second data signal used to make a first sub-pixel and a second sub-pixel display the same gray level. The display module according to claim 17, wherein, The data processing unit is configured to compensate the first data signal with a positive voltage. The display module according to claim 17, wherein, The data processing unit is configured to compensate for negative voltage in the second data signal. The display module according to claim 17, wherein, The data processing unit is configured to compensate the first data signal with a positive voltage and the second data signal with a negative voltage. The display module according to any one of claims 17 to 20, wherein, The data processing unit includes a gamma compensation subunit and / or a data compensation subunit. The display module according to any one of claims 17 to 21, wherein, The first control signal line of the array substrate includes two first sub-lines, and the second control signal line includes two second sub-lines. The plurality of multiplexing circuits include a plurality of first multiplexing circuits and a plurality of second multiplexing circuits, wherein the first multiplexing circuits and the second multiplexing circuits are electrically connected to a first sub-line and a second sub-line, respectively. The data lines electrically connected to the first multiplexing circuit and the second multiplexing circuit respectively transmit data signals of opposite polarity in the same frame, and each data line transmits data signals of opposite polarity in two adjacent frames; The driver circuit board also includes: A power supply unit is configured to provide a first set of voltage signals and a second set of voltage signals, wherein the first set of voltage signals includes a first operating voltage and a first non-operating voltage, and the second set of voltage signals includes a second operating voltage and a second non-operating voltage; wherein the first operating voltage is less than the second operating voltage, and the first non-operating voltage is less than the second non-operating voltage. The timing controller is configured to output a first set of selection signals based on the polarity of the data signals transmitted to the first multiplexing circuit, and to output a second set of selection signals based on the polarity of the data signals transmitted to the second multiplexing circuit. A power output circuit is electrically connected to the timing controller, the power supply unit, the two first sub-lines, and the two second sub-lines. The power output circuit is configured to: transmit one of the first set of voltage signals and the second set of voltage signals to a first sub-line and a second sub-line electrically connected to the first multiplexing circuit according to the first set of selection signals; and transmit the other of the first set of voltage signals and the second set of voltage signals to a first sub-line and a second sub-line electrically connected to the second multiplexing circuit according to the second set of selection signals. A display device, comprising: The array substrate as described in any one of claims 1 to 16; Alternatively, the display module as described in any one of claims 17 to 22.

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