Display panel and display apparatus

Abstract

The present application belongs to the technical field of display. Disclosed are a display panel and a display apparatus. The display panel provided in the present application comprises: a substrate, a first electrode layer, a pixel definition layer, a light-emitting layer, a second electrode layer and a peripheral trace. Since the side of the second electrode layer that faces a first trace portion in the peripheral trace does not protrude beyond the side of the pixel definition layer that faces the first trace portion, in a first sub-region of the display panel, the second electrode layer no longer overlaps a transfer portion in the first electrode layer, thereby ensuring that it is unnecessary to reserve in the first sub-region a region where the second electrode layer overlaps the transfer portion. Thus, the width of the first sub-region can be reduced, such that the width of an upper bezel of the display panel is relatively small, thereby effectively improving the screen-to-body ratio of the display panel.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411718606.9, filed on November 27, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] Display panels that use organic light-emitting diodes (OLEDs) to achieve display functions are called OLED display panels. Due to their high color gamut, thinness, and flexibility, they have become the mainstream display structure.

[0004] However, the bezels of current OLED display panels are relatively wide, resulting in a relatively low screen-to-body ratio. Summary of the Invention

[0005] This application provides a display panel and a display device. It can solve the problem of low screen-to-body ratio in existing display panels. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel having a display area and a non-display area located around the display area, the non-display area including: a bent area and a first sub-region disposed opposite each other in a first direction, and two second sub-regions disposed opposite each other in a second direction; the first direction and the second direction intersect; the display area is located between the bent area and the first sub-region in the first direction, and between the two second sub-regions in the second direction; the display panel includes: a substrate, a first electrode layer, a pixel definition layer, a light-emitting layer, a second electrode layer, and peripheral wiring;

[0007] The first electrode layer, the pixel definition layer, the light-emitting layer, and the second electrode layer are stacked on one side of the substrate in a direction away from the substrate, and the first electrode layer, the pixel definition layer, the light-emitting layer, and the second electrode layer are located at least within the display area;

[0008] The peripheral traces are distributed within the non-display area. The peripheral traces include: a first trace portion located within the first sub-region, and two second trace portions located within the two second sub-regions respectively. The two ends of the first trace portion are respectively connected to the ends of the two second trace portions.

[0009] Wherein, the side of the second electrode layer facing the first trace does not protrude from the side of the pixel definition layer facing the first trace, and the two sides of the second electrode layer that are disposed opposite to each other in the second direction are electrically connected to the two second traces respectively.

[0010] Optionally, the pixel definition layer protrudes from the side of the first trace portion onto the side of the second electrode layer facing the first trace portion;

[0011] Alternatively, the side of the pixel definition layer facing the first trace portion is flush with the side of the second electrode layer facing the first trace portion.

[0012] Optionally, the side of the second electrode layer facing the first trace portion protrudes beyond the side of the light-emitting layer facing the first trace portion.

[0013] Optionally, the side of the light-emitting layer facing the first trace portion protrudes beyond the side of the second electrode layer facing the first trace portion, and the side of the light-emitting layer facing the first trace portion does not protrude beyond the side of the pixel definition layer facing the first trace portion.

[0014] Optionally, the pixel definition layer protrudes from the side of the first trace portion onto the side of the light-emitting layer facing the first trace portion;

[0015] Alternatively, the side of the pixel definition layer facing the first trace is flush with the side of the light-emitting layer facing the first trace.

[0016] Optionally, the side of the light-emitting layer facing the first trace portion is flush with the side of the second electrode layer facing the first trace portion.

[0017] Optionally, the second electrode layer includes: a main body portion located within the display area, and a first protrusion portion located within the first sub-region, the first protrusion portion being connected to the main body portion;

[0018] Wherein, the orthographic projection of the first protrusion on the substrate is located within the orthographic projection of the pixel definition layer on the substrate.

[0019] Optionally, the second electrode layer further includes two second protrusions located in the two second sub-regions respectively, and both second protrusions are connected to the main body.

[0020] The two second protrusions are electrically connected to the two second wiring sections, respectively.

[0021] Optionally, the first electrode layer includes: a plurality of separately disposed electrode blocks located within the display area, and two first transition portions located within the two second sub-regions respectively, wherein the first transition portions are separately disposed from the electrode blocks;

[0022] The two first transition portions facing the substrate are respectively in contact with the two second trace portions away from the substrate, and the two first transition portions away from the substrate are respectively in contact with the two second protrusions facing the substrate.

[0023] Optionally, the first electrode layer further includes: a second transition portion located within the first sub-region, the second transition portion being separately disposed from the electrode block;

[0024] The side of the second adapter facing the substrate contacts the side of the first trace away from the substrate.

[0025] Optionally, the display panel further includes: a first planarization layer, the first planarization layer being located on the side of the first electrode layer facing the substrate;

[0026] Wherein, the side of the first electrode layer facing the first trace portion does not protrude from the side of the first planarization layer facing the first trace portion.

[0027] Optionally, the display panel further includes: a plurality of parallel first signal lines, the first signal lines being distributed at least within the display area, the extension direction of the first signal lines being parallel to the second direction, and the two ends of the first signal lines being electrically connected to the two second wiring portions respectively.

[0028] Optionally, the display panel further includes: a plurality of parallel second signal lines, the second signal lines being distributed at least within the display area, the extension direction of the second signal lines being parallel to the first direction, and the ends of the second signal lines being electrically connected to the first wiring portion, and the second signal lines also being electrically connected to the first signal lines at their intersections.

[0029] Optionally, the second signal line is disposed on the same layer as at least a portion of the peripheral traces and is made of the same material.

[0030] On the other hand, a display device is provided, the display device comprising: a driver chip, and a display panel electrically connected to the driver chip, the display panel being any of the aforementioned display panels.

[0031] The beneficial effects of the technical solutions provided in this application include at least the following:

[0032] Since the second electrode layer faces the side of the first trace in the peripheral trace and does not protrude from the side of the pixel definition layer facing the first trace, the second electrode layer no longer overlaps with the transition part in the first electrode layer in the first sub-region of the display panel. This ensures that there is no need to reserve an area for the second electrode layer to overlap with the transition part in the first sub-region, thereby reducing the width of the first sub-region and making the top bezel of the display panel smaller, effectively improving the screen ratio of the display panel. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 is a top view of the structure of a display panel;

[0035] Figure 2 is a schematic diagram of the film structure of the display panel at AA' shown in Figure 1;

[0036] Figure 3 is a schematic diagram of the film structure of the display panel at BB' shown in Figure 1;

[0037] Figure 4 is a top view of a display panel provided in an embodiment of this application;

[0038] Figure 5 is a schematic diagram of a film structure of the display panel shown in Figure 4 at CC';

[0039] Figure 6 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0040] Figure 7 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0041] Figure 8 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0042] Figure 9 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0043] Figure 10 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0044] Figure 11 is a schematic diagram of a film structure of the display panel at EE' shown in Figure 4;

[0045] Figure 12 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0046] Figure 13 is a schematic diagram of another film layer structure of the display panel at CC' shown in Figure 4;

[0047] Figure 14 is a top view of another display panel provided in an embodiment of this application;

[0048] Figure 15 is a schematic diagram of a film structure at DD' of the display panel shown in Figure 4. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] Please refer to Figure 1, which is a top view of a display panel. The display panel 000 may have a display area 001 and a non-display area 002. The non-display area 002 is located around the display area 001 and has a bent area 002a and a first sub-area 002b disposed opposite each other in a first direction X, and two second sub-areas 002c disposed opposite each other in a second direction Y. The display area 001 is located between the bent area 002a and the first sub-area 002b in the first direction, and between the two second sub-areas 002c in the second direction. Here, the first direction X intersects the second direction Y. For example, the first direction X may be perpendicular to the second direction Y.

[0051] It should be noted that the portion of the display panel 000 containing the bent area 002a can usually be referred to as the bottom border of the display panel 000; the portion of the display panel 000 containing the first sub-region 002b can usually be referred to as the top border of the display panel 000; and the portion of the display panel 000 containing the two second sub-regions 002c can usually be referred to as the left border and right border of the display panel 000, respectively.

[0052] Please refer to Figure 2, which is a schematic diagram of the film layer structure of the display panel at AA' shown in Figure 1. The display panel 000 may include: a substrate 100, a first electrode layer 200, a pixel definition layer 300, a light-emitting layer 400, and a second electrode layer 500.

[0053] The first electrode layer 200, the pixel definition layer 300, the light-emitting layer 400, and the second electrode layer 500 are stacked on one side of the substrate 100 in a direction away from the substrate 100, and the first electrode layer 200, the pixel definition layer 300, the light-emitting layer 400, and the second electrode layer 500 are located at least within the display area 001.

[0054] The first electrode layer 200 may include a plurality of separately arranged electrode blocks 200a located within the display area 001.

[0055] The pixel definition layer 300 has multiple pixel openings K in the display area 001. These multiple pixel openings K can correspond one-to-one with multiple electrode blocks 200a in the first electrode layer 200. Therefore, the portion of the light-emitting layer 400 distributed in each pixel opening K can contact the corresponding electrode block 200a.

[0056] As shown in Figure 2, for any pixel opening K in the display area 001, the electrode block 200a corresponding to this pixel opening K, and the portions of the light-emitting layer 400 and the second electrode layer 500 located within this pixel opening K, can form a light-emitting device L. It should be noted that the electrode block 200a corresponding to the pixel opening K can serve as the anode in the light-emitting device, and the portion of the second electrode layer 500 located within the pixel opening K can serve as the cathode in the light-emitting device L.

[0057] It should be noted that the second electrode layer 500 in the display panel 000 is a single-layer film structure, which can serve as the common electrode for multiple light-emitting devices L. Therefore, as shown in Figure 1, a peripheral trace 600 is typically provided in the non-display area 002, and the peripheral trace 600 is electrically connected to the second electrode layer 500, allowing the second electrode layer 500 to receive signals through the peripheral trace. For example, the peripheral trace 600 can be a low-level power signal line, providing a low-level power signal to the second electrode layer 500.

[0058] It should also be noted that, in order to ensure the effectiveness of the low-level power signal applied to the second electrode layer 500, which is arranged throughout the entire layer, the second electrode layer 500 typically needs to be connected to the power signal provided by the peripheral traces 600 simultaneously on the top, left, and right edges of the display panel 000. Therefore, the peripheral traces 600 need to be distributed within the first sub-region 002b and the two second sub-regions 002c of the display panel 000. Since the second electrode layer 500 in the display panel 000 is relatively far from the peripheral traces 600, the first electrode layer 200 can be used as a transition structure to connect the two.

[0059] For example, as shown in Figure 1, the first electrode layer 200 may further include a transition portion 200b, which may be distributed within the first sub-region 002b and two second sub-regions 002c of the display panel 000, and the transition portion 200b may be separately disposed from each electrode block 200a in the first electrode layer 200. Thus, after the transition portion 200b overlaps with the peripheral trace 600, the peripheral trace 600 will not apply signals to each electrode block 200a, ensuring that there is no short circuit between the anode and cathode in the light-emitting device 200. Furthermore, the portion of the second electrode layer 500 located within the first sub-region 002b and the two second sub-regions 002c may overlap with the transition portion 200b. In this way, the electrical connection between the peripheral trace 600 and the second electrode layer 500 can be achieved through the transition portion 200b.

[0060] However, as shown in Figure 3, which is a schematic diagram of the film layer structure at BB' of the display panel shown in Figure 1, within the first sub-region 002b of the display panel 000, the second electrode layer 500 needs to be electrically connected to the adapter 200b via an overlap, and the adapter 200b also needs to be electrically connected to the peripheral trace 600 via an overlap. Furthermore, the overlap width between the second electrode layer 500 and the adapter 200b is typically large. Therefore, the width of the first sub-region 002b is relatively large, resulting in a larger upper bezel width for the display panel 000. Consequently, the screen-to-body ratio of this display panel 000 is low.

[0061] To improve the screen-to-body ratio of the display panel 000, this application embodiment provides a display panel with a smaller upper bezel width. Please refer to Figures 4 and 5. Figure 4 is a top view of a display panel according to an embodiment of this application, and Figure 5 is a schematic diagram of a film layer structure at CC' of the display panel shown in Figure 4. The peripheral traces 600 in the display panel 000 need to be distributed within a first sub-region 002b and two second sub-regions 002c of the non-display area 002. Therefore, the peripheral traces 600 may include: a first trace portion 601 located in the first sub-region 002b, and two second trace portions 602 respectively located in the two second sub-regions 002c. The two ends of the first trace portion 601 are respectively connected to the ends of the two second trace portions 602. That is, a second trace portion 602 distributed at the left bezel position, a first trace portion 601 distributed at the top bezel position, and a second trace portion 602 distributed at the right bezel position of the display panel 000 can be sequentially connected as a single unit.

[0062] In this embodiment, as shown in FIG5, the second electrode layer 500 faces the first trace portion 601 but does not protrude from the pixel definition layer 300 facing the first trace portion 601. Furthermore, as shown in FIG4, the two sides of the second electrode layer 500, which are positioned opposite each other in the second direction Y, are electrically connected to two second trace portions 602 in the peripheral trace 600.

[0063] Specifically, when the second electrode layer 500 does not protrude beyond the pixel definition layer 300 facing the first wiring portion 601 on the side facing the first wiring portion 601, the second electrode layer 500 no longer overlaps with the transition portion 200b in the first electrode layer 200 within the first sub-region 002b of the display panel 000. This ensures that no area needs to be reserved within the first sub-region 002b for the second electrode layer 500 to overlap with the transition portion 200b, thereby reducing the width of the first sub-region 002b and making the top bezel of the display panel 000 smaller. This effectively improves the screen-to-body ratio of the display panel 000.

[0064] It should be noted that within the first sub-region 002b of the display panel 000, if the second electrode layer 500 no longer overlaps with the transition portion 200b in the first electrode layer 200, the second electrode layer 500 will not receive the low-level power signal provided by the peripheral trace 600 at the upper frame of the display panel 000. In this case, it is necessary to electrically connect the two opposite sides of the second electrode layer 500 in the second direction Y to the two second trace portions 602 in the peripheral trace 600, so as to ensure that the second electrode layer 500 can normally receive the low-level power signal provided by the peripheral trace 600 at the left and right frames of the display panel 000.

[0065] It should also be noted that after the driving component is bonded to the bending area of ​​the display panel 000, the ends of the two second traces 602 that are away from the first trace 601 can simultaneously access the low-level power signal provided by the driving component 002a through the traces arranged within the bending area 002a. Since the two second traces 602 in the peripheral trace 600 can be connected as one unit through the first trace 601, after the two second traces 602 are simultaneously connected to the low-level power signal, the first trace 601 can better balance the low-level power signals connected to the two second traces 602, so that the two second traces 602 can better provide a low-level power signal with a balanced potential to the second electrode layer 500.

[0066] In summary, the display panel provided in this application includes: a substrate, a first electrode layer, a pixel definition layer, a light-emitting layer, a second electrode layer, and peripheral wiring. Since the side of the second electrode layer facing the first wiring portion in the peripheral wiring does not protrude from the side of the pixel definition layer facing the first wiring portion, the second electrode layer no longer overlaps with the transition portion in the first sub-region of the display panel. This ensures that no area needs to be reserved in the first sub-region for the second electrode layer to overlap with the transition portion, thereby reducing the width of the first sub-region and making the top bezel of the display panel smaller, effectively improving the screen-to-body ratio of the display panel.

[0067] In this application, the positional relationship between the second electrode layer 200 and the pixel definition layer 300 in the display panel 000 can be implemented in various ways. For example, the side of the pixel definition layer 300 facing the first wiring portion 601 can protrude beyond the side of the second electrode layer 500 facing the first wiring portion 601. Alternatively, the side of the pixel definition layer 300 facing the first wiring portion 601 can be flush with the side of the second electrode layer 500 facing the first wiring portion 601. Furthermore, the positional relationship between the second electrode layer 200 and the light-emitting layer 400 in the display panel 000 can also be implemented in various ways. Therefore, this application will illustrate the following three possible implementations as examples:

[0068] In the first possible implementation, as shown in Figures 5 and 6, the side of the second electrode layer 500 facing the first trace portion 601 can protrude from the side of the light-emitting layer 400 facing the first trace portion 601.

[0069] In this case, as shown in Figure 5, the side of the pixel definition layer 300 facing the first trace portion 601 can protrude beyond the side of the second electrode layer 500 facing the first trace portion 601. Alternatively, as shown in Figure 6, the side of the pixel definition layer 300 facing the first trace portion 601 can also be flush with the side of the second electrode layer 500 facing the first trace portion 601.

[0070] In a second possible implementation, as shown in Figures 7 and 8, the side of the light-emitting layer 400 facing the first trace 601 can protrude beyond the side of the second electrode layer 500 facing the first trace 601, while the side of the light-emitting layer 400 facing the first trace 601 does not protrude beyond the side of the pixel definition layer 300 facing the first trace 601. Here, the situation where the side of the light-emitting layer 400 facing the first trace 601 does not protrude beyond the side of the pixel definition layer 300 facing the first trace 601 can also have two possible scenarios.

[0071] In the first possible scenario, as shown in Figure 7, the side of the light-emitting layer 400 facing the first trace portion 601 can be flush with the side of the pixel definition layer 300 facing the first trace portion 601.

[0072] In the second possible case, as shown in Figure 8, the side of the pixel definition layer 300 facing the first trace portion 601 may protrude from the side of the light-emitting layer 400 facing the first trace portion 601.

[0073] It should be noted that when the side of the light-emitting layer 400 facing the first trace portion 601 protrudes beyond the side of the second electrode layer 500 facing the first trace portion 601, the side of the pixel definition layer 300 facing the first trace portion 601 will also protrude beyond the side of the second electrode layer 500 facing the first trace portion 601.

[0074] In a third possible implementation, as shown in Figures 9 and 10, the side of the second electrode layer 500 facing the first trace portion 601 can also be flush with the side of the light-emitting layer 400 facing the first trace portion 601.

[0075] In this case, as shown in Figure 9, the side of the pixel definition layer 300 facing the first wiring portion 601 can protrude beyond the side of the second electrode layer 500 facing the first wiring portion 601, and can also protrude beyond the side of the light-emitting layer 400 facing the first wiring portion 601. Alternatively, as shown in Figure 10, the side of the pixel definition layer 300 facing the first wiring portion 601 can be flush with the side of the second electrode layer 500 facing the first wiring portion 601, and can also be flush with the side of the light-emitting layer 400 facing the first wiring portion 601.

[0076] It should be noted that, in any embodiment of this application, the second electrode layer 500 may include: a main body portion 500a located within the display area 001, and a first protrusion portion 501 located within the first sub-region 002b. The first protrusion portion 501 is connected to the main body portion 500a. Since the side of the second electrode layer 500 facing the first trace portion 601 does not protrude beyond the side of the pixel definition layer 300 facing the first trace portion 601, the orthographic projection of the first protrusion portion 501 onto the substrate 100 can be located within the orthographic projection of the pixel definition layer 300 onto the substrate 100, thereby ensuring that there is no electrical connection between the first protrusion portion 501 and the first trace portion 601 in the peripheral trace 600.

[0077] In this embodiment of the application, as shown in FIG11, FIG11 is a schematic diagram of a film layer structure of the display panel at EE' shown in FIG4. The second electrode layer 500 may further include two second protrusions 502 located in two second sub-regions 002c respectively. The second protrusions 502 are also connected to the main body portion 500a. And the two second protrusions 502 are electrically connected to two second trace portions 602 in the peripheral traces 600 respectively.

[0078] For example, the two second protrusions 502 can be electrically connected to the two second traces 602 respectively through the transition portion 200b of the first electrode layer 200. For example, the transition portion 200b of the first electrode layer 200 may include two first transition portions 201 located in the two second sub-regions 002c respectively, and the two first transition portions 201 are respectively disposed separately from each electrode block 200a in the first electrode layer 200.

[0079] The side of the second protrusion 502 facing the substrate 100 contacts the side of the first adapter 201 away from the substrate 100, and the side of the first adapter 201 facing the substrate 100 contacts the side of the second trace 602 away from the substrate 100, thereby realizing the electrical connection between the two second protrusions 502 and the two second traces 602.

[0080] In this embodiment, the transition portion 200b of the first electrode layer 200 may further include a second transition portion 202 located within the first sub-region 002b. The second transition portion 202 is also separately disposed from each electrode block 200a in the first electrode layer 200. Here, the two ends of the second transition portion 202 may be connected to the ends of the two first transition portions 201 respectively. As shown in Figures 5 to 10, the second transition portion 202 may protrude from the side of the pixel defined layer 300 facing the first trace portion 601, so that the second transition portion 202 can overlap with the first trace portion 601. That is, the side of the second transition portion 202 facing the substrate 100 contacts the side of the first trace portion 601 away from the substrate 100.

[0081] It should be noted that in other possible implementations, since the second electrode layer 500 no longer overlaps with the transition portion 200b in the first electrode layer 200 within the first sub-region 002b of the display panel 000 in this application, the overlap between the first protrusion 501 and the first trace portion 601 is eliminated. Therefore, the overlap between the second transition portion 202 and the first trace portion 601 can also be eliminated. In this case, the second transition portion 202 in the second electrode layer 200 no longer contacts the first trace portion 601 in the peripheral trace 600.

[0082] For example, as shown in FIG12, the display panel 000 may further include a first planarization layer 800, which is located on the side of the first electrode layer 200 facing the substrate 100. In this case, the side of the first electrode layer 200 facing the first trace portion 601 does not protrude from the side of the first planarization layer 800 facing the first trace portion 601. That is, the orthographic projection of the second transition portion 202 on the substrate 100 is located within the orthographic projection of the first planarization layer 800 on the substrate 100.

[0083] In one possible scenario, as shown in FIG12, the side of the first electrode layer 200 facing the first trace portion 601 is flush with the side of the first planarization layer 800 facing the first trace portion 601. In another possible scenario, as shown in FIG13, the side of the first planarization layer 800 facing the first trace portion 601 protrudes beyond the side of the first electrode layer 200 facing the first trace portion 601.

[0084] When the second adapter 202 does not contact the first wiring section 601, there is no need to reserve an area in the first sub-region 002b where the second adapter 202 and the first wiring section 601 overlap. The width of the first wiring section 601 can be further reduced to further reduce the width of the upper bezel of the display panel 000, thereby further increasing the screen ratio of the display panel 000.

[0085] Please refer to Figure 14, which is a top view of another display panel provided in this embodiment. The display panel 000 may further include: multiple parallel first signal lines 603, which are at least distributed within the display area 001. The extension direction of the first signal lines 603 is parallel to the second direction Y, and both ends of the first signal lines 603 are electrically connected to two second trace portions 602 respectively. The first signal lines 603 can reduce the resistance of the peripheral traces 600, reduce the voltage drop of the peripheral traces 600, and ensure the uniformity of the power signal transmitted from the second trace portion 602 to the second protrusion 502 through the first adapter portion 201, thereby ensuring the light-emitting effect of the light-emitting device L and improving the display effect of the display panel 000.

[0086] The display panel 000 may further include: multiple parallel second signal lines 604, which are at least distributed within the display area 001. The extension direction of the second signal lines 604 is parallel to the first direction X, and the ends of the second signal lines 604 are electrically connected to the first trace portion 601. The second signal lines 604 are also electrically connected to the first signal lines 603 at their intersections. These second signal lines 604 can further reduce the resistance of the peripheral traces 600, reduce the voltage drop of the peripheral traces 600, and ensure the uniformity of the power signal transmitted from the second trace portion 602 to the second protrusion 502 through the first adapter portion 201, thereby ensuring the light-emitting effect of the light-emitting device L and improving the display effect of the display panel 000.

[0087] As shown in Figure 15, Figure 15 is a schematic diagram of a film layer structure at DD' of the display panel shown in Figure 4. The display panel 000 may further include: a buffer layer 101, an active layer 102, a first gate insulating layer 103, a first gate layer 104, a second gate insulating layer 105, a second gate layer 106, an interlayer dielectric layer 107, a first source-drain layer 108, a second planarization layer 109, and a second source-drain layer 110, all stacked between the substrate 100 and the first planarization layer 800.

[0088] The active layer 102, the first gate layer 104, the second gate layer 106, the first source-drain layer 108, and the second source-drain layer 110 are used to form a pixel driving circuit electrically connected to the light-emitting device 200, as well as various signal lines electrically connected to the pixel driving circuit. The pixel driving circuit can be electrically connected to the electrode block 200a in the light-emitting device L.

[0089] The peripheral trace 600 in the display panel 000 can be a double-layer trace. The peripheral trace 600 can include a first sub-peripheral trace and a second sub-peripheral trace stacked along the direction away from the substrate 100. The first sub-peripheral trace can be a part of the first source-drain layer 108, and the second sub-peripheral trace can be a part of the second source-drain layer 110.

[0090] In one possible embodiment of this application, the first source-drain layer 108 can also be used to form a first signal line 603, and the second source-drain layer 110 can also be used to form a second signal line 604. In this case, the first signal line 603 is disposed on the same layer as the first sub-peripheral trace and is made of the same material, and the second signal line 604 is disposed on the same layer as the second sub-peripheral trace and is made of the same material.

[0091] In another possible embodiment of this application, the first gate layer 104 and / or the second gate layer 106 may also be used to form the first signal line 603, and the first source-drain layer 108 and / or the second source-drain layer 110 may also be used to form the second signal line 604. In this case, the second signal line 604 may be disposed on the same layer as the first sub-peripheral trace or the second sub-peripheral trace and made of the same material.

[0092] It should be noted that, due to the high resistance and significant voltage drop of the second electrode layer 500, the display panel 000 may further include multiple auxiliary electrodes. Here, all auxiliary electrodes may be located within the display area 001, with one auxiliary electrode positioned between two adjacent light-emitting devices L. The main body 500a of the second electrode layer 500 may contact the multiple auxiliary electrodes, and each auxiliary electrode may be electrically connected to the first signal line 603 and / or the second signal line 604. Since the two ends of the first signal line 603 are electrically connected to the two second traces 602 respectively, and the end of the second signal line 604 is electrically connected to the first trace 601, the power signal provided by the auxiliary electrode to the main body 500a inside the display area 001 and the power signal provided to the second protrusion 502 at the peripheral trace 600 are relatively balanced. Through multiple auxiliary electrodes, the voltage at each position in the second electrode layer 500 can be balanced, effectively solving the problem of power signal imbalance caused by severe voltage drop in the second electrode layer 500, ensuring the light-emitting effect of the light-emitting device L, and thus improving the display effect of the display panel 000.

[0093] In this embodiment of the application, as shown in Figures 3 and 5 to 13, the display panel 000 may further include an encapsulation layer 700. The encapsulation layer 700 is located on the side of the second electrode layer 500 facing away from the substrate 100, and the encapsulation layer 700 can be used to encapsulate each light-emitting device L, so that water and oxygen in the external environment are not easily corroded into the interior of the light-emitting device L, thus preventing damage to the light-emitting device L. The encapsulation layer 700 includes at least one organic encapsulation layer and multiple inorganic encapsulation layers.

[0094] Because organic materials have high fluidity and strong water absorption, to prevent the intrusion of external water and oxygen, the display panel 000 also includes a baffle 900. The baffle 900 can be located within the non-display area 002 and can be distributed around the display area 001. Here, the number of baffles 900 is usually at least one. If there are multiple baffles 900, they can be nested sequentially within the non-display area 002. For example, the display panel 000 has one baffle 900, distributed around the display area 001. The baffle 900 can effectively block the flow of the organic encapsulation layer, preventing the organic encapsulation layer from entering the side of the baffle 900 away from the display area 001 and affecting the encapsulation effect.

[0095] In the display panel 000, since the second electrode layer 500 is formed by a vapor deposition process, a shadow effect exists during the vapor deposition process. Therefore, a shadow area exists when the second electrode layer 500 is formed, which includes an inner shadow area and an outer shadow area.

[0096] The outer shadow area causes the actual formed second electrode layer 500 to extend beyond the designed vapor deposition area. Therefore, a certain distance needs to be maintained between the side of the second electrode layer 500 facing away from the display area 001 and the barrier 900. For example, the side of the first protrusion 501 in the second electrode layer 500 facing the first trace 601 does not protrude beyond the side of the pixel definition layer 300 facing the first trace 601, while the side of the second protrusion 502 in the second electrode layer 500 facing the second trace 602 does protrude beyond the side of the pixel definition layer 300 facing the second trace 602. Therefore, it is necessary to ensure that there is a certain distance between the side of the second protrusion 502 facing away from the main body 500a and the barrier walls 900 distributed around the display area 001. This distance should take into account the mask manufacturing accuracy, process alignment accuracy, and the area of ​​the outer shadow region during the manufacturing process. This is to prevent the outer shadow region of the second electrode layer 500 from entering the barrier walls 900 and the area of ​​the barrier walls 900 facing away from the display area 001, which would affect the blocking effect of the barrier walls 900 on the organic encapsulation layer and lead to encapsulation failure. When there are multiple barrier walls, the barrier wall 900 refers to the one closest to the display area 001.

[0097] The inner shadow area results in the second electrode layer 500 being deposited in the vapor deposition area, but the thickness of the second electrode layer 500 in the inner shadow area is thin and uneven, affecting the transmission of power signals and thus affecting the light emission effect of the light-emitting device L in the display area 001. Therefore, there needs to be a certain distance between the side of the second electrode layer 500 away from the display area 001 and the boundary of the display area 001. For example, the first protrusion 501 and the second protrusion 502 of the second electrode layer 500 need to have a certain width between the side away from the main body 500a and the boundary of the display area 001. The setting of this width should take into account the manufacturing accuracy of the mask, the process alignment accuracy and the area of ​​the inner shadow area during the process, so that the thickness of the main body 500a of the second electrode layer 500 is uniform, thereby ensuring the display effect of the display panel 000.

[0098] In summary, the display panel provided in this application includes: a substrate, a first electrode layer, a pixel definition layer, a light-emitting layer, a second electrode layer, and peripheral wiring. Since the side of the second electrode layer facing the first wiring portion in the peripheral wiring does not protrude from the side of the pixel definition layer facing the first wiring portion, the second electrode layer no longer overlaps with the transition portion in the first sub-region of the display panel. This ensures that no area needs to be reserved in the first sub-region for the second electrode layer to overlap with the transition portion, thereby reducing the width of the first sub-region and making the top bezel of the display panel smaller, effectively improving the screen-to-body ratio of the display panel.

[0099] This application also provides a display device, which includes: a driver chip and a display panel 000 electrically connected to the driver chip. The display panel 000 may include any of the display panels 000 given above. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, advertising machine, display screen, digital photo frame, etc.

[0100] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0101] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0102] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area located around the display area. The non-display area includes: a bent area and a first sub-region disposed opposite each other in a first direction, and two second sub-regions disposed opposite each other in a second direction; the first direction and the second direction intersect; the display area is located between the bent area and the first sub-region in the first direction, and between the two second sub-regions in the second direction; the display panel includes: a substrate, a first electrode layer, a pixel definition layer, a light-emitting layer, a second electrode layer, and peripheral wiring. The first electrode layer, the pixel definition layer, the light-emitting layer, and the second electrode layer are stacked on one side of the substrate in a direction away from the substrate, and the first electrode layer, the pixel definition layer, the light-emitting layer, and the second electrode layer are located at least within the display area; The peripheral traces are distributed within the non-display area. The peripheral traces include: a first trace portion located within the first sub-region, and two second trace portions located within the two second sub-regions respectively. The two ends of the first trace portion are respectively connected to the ends of the two second trace portions. Wherein, the side of the second electrode layer facing the first trace does not protrude from the side of the pixel definition layer facing the first trace, and the two sides of the second electrode layer that are disposed opposite to each other in the second direction are electrically connected to the two second traces respectively.

2. The display panel according to claim 1, characterized in that, The pixel definition layer protrudes from the side of the first trace portion onto the side of the second electrode layer facing the first trace portion; Alternatively, the side of the pixel definition layer facing the first trace portion is flush with the side of the second electrode layer facing the first trace portion.

3. The display panel according to claim 2, characterized in that, The second electrode layer protrudes from the side of the light-emitting layer facing the first trace portion.

4. The display panel according to claim 2, characterized in that, The side of the light-emitting layer facing the first trace portion protrudes beyond the side of the second electrode layer facing the first trace portion, and the side of the light-emitting layer facing the first trace portion does not protrude beyond the side of the pixel definition layer facing the first trace portion.

5. The display panel according to claim 4, characterized in that, The pixel definition layer protrudes from the side of the first wiring portion on the side of the light-emitting layer facing the first wiring portion; Alternatively, the side of the pixel definition layer facing the first trace is flush with the side of the light-emitting layer facing the first trace.

6. The display panel according to claim 2, characterized in that, The side of the light-emitting layer facing the first trace is flush with the side of the second electrode layer facing the first trace.

7. The display panel according to any one of claims 1 to 6, characterized in that, The second electrode layer includes: a main body portion located within the display area, and a first protrusion portion located within the first sub-region, the first protrusion portion being connected to the main body portion; Wherein, the orthographic projection of the first protrusion on the substrate is located within the orthographic projection of the pixel definition layer on the substrate.

8. The display panel according to claim 7, characterized in that, The second electrode layer further includes two second protrusions located in the two second sub-regions respectively, and both second protrusions are connected to the main body. The two second protrusions are electrically connected to the two second wiring sections, respectively.

9. The display panel according to claim 8, characterized in that, The first electrode layer includes: a plurality of separately disposed electrode blocks located within the display area, and two first transition portions located within the two second sub-regions respectively, wherein the first transition portions are separately disposed from the electrode blocks; The two first transition portions facing the substrate are respectively in contact with the two second trace portions away from the substrate, and the two first transition portions away from the substrate are respectively in contact with the two second protrusions facing the substrate.

10. The display panel according to claim 9, characterized in that, The first electrode layer further includes: a second transition portion located within the first sub-region, the second transition portion being separately disposed from the electrode block; The side of the second adapter facing the substrate contacts the side of the first trace away from the substrate.

11. The display panel according to any one of claims 1 to 6, 8 to 9, characterized in that, The display panel further includes: a first planarization layer, the first planarization layer being located on the side of the first electrode layer facing the substrate; Wherein, the side of the first electrode layer facing the first trace portion does not protrude from the side of the first planarization layer facing the first trace portion.

12. The display panel according to any one of claims 1 to 6, 8 to 10, characterized in that, The display panel further includes: a plurality of parallel first signal lines, the first signal lines being distributed at least within the display area, the extension direction of the first signal lines being parallel to the second direction, and the two ends of the first signal lines being electrically connected to the two second wiring portions respectively.

13. The display panel according to claim 12, characterized in that, The display panel further includes: a plurality of parallel second signal lines, the second signal lines being distributed at least within the display area, the extension direction of the second signal lines being parallel to the first direction, and the ends of the second signal lines being electrically connected to the first wiring portion, and the second signal lines also being electrically connected to the first signal lines at their intersections.

14. The display panel according to claim 13, characterized in that, The second signal line is disposed on the same layer as at least a portion of the peripheral traces and is made of the same material.

15. A display device, characterized in that, include: A driver chip, and a display panel electrically connected to the driver chip, wherein the display panel is the display panel according to any one of claims 1 to 14.

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