Message processing method and apparatus

Abstract

Disclosed are an information processing method and apparatus. Every n columns of an LDPC base matrix correspond to one sub-matrix group, each sub-matrix group comprises W sub-matrices, and the W sub-matrices can be obtained from a first matrix, that is, the LDPC base matrix can be obtained from the first matrix. In this way, the LDPC base matrix may not be stored, but the first matrix is stored. The size of the first matrix is much smaller than that of the LDPC base matrix, thereby reducing the occupied storage space. As the LDPC base matrix may be obtained from the first matrix, during matrix construction, the first matrix may be obtained in a small search space, and then the LDPC base matrix is obtained on the basis of the first matrix, thereby reducing the difficulty of matrix construction.

Description

An information processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202411751516.X, filed on November 29, 2024, entitled "An Information Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more specifically, to an information processing method and apparatus. Background Technology

[0003] Channel coding is one of the core technologies in the field of wireless communication. The complete channel coding process includes: adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is a crucial part. The purpose of error correction coding is to ensure that the receiving device can automatically correct errors that occur during data transmission with as little redundancy overhead as possible. At the same bit error rate, the smaller the redundancy overhead, the higher the coding efficiency.

[0004] Low-density parity check (LDPC) codes are among the most mature and widely used coding schemes. LDPC codes are a channel coding scheme very close to Shannon lines, characterized by good performance and low complexity. LDPC codes have been adopted by the 3rd Generation Partnership Project (3GPP) as a data channel coding scheme. Spatially coupled-low-density parity check (SC-LDPC) codes are a widely used type of LDPC code, which can be constructed by coupling multiple disjoint LDPC subcodes.

[0005] Currently, the matrix construction of SC-LDPC codes is complex, and the stored matrix is ​​relatively large. Summary of the Invention

[0006] This application provides an information processing method and apparatus to reduce the construction complexity of LDPC codes and reduce the storage resources occupied.

[0007] In a first aspect, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (such as modem chips, also known as baseband chips, or system-on-chip (SoC) chips containing modem cores or system-in-package (SIP) chips)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or network device.

[0008] The method includes: acquiring information to be encoded; encoding the information according to an M-row, N-column LDPC base matrix; and outputting the encoded information. The LDPC base matrix comprises multiple sub-matrix groups, with each n-column of the N columns of the LDPC base matrix corresponding to a sub-matrix group. Each sub-matrix group comprises W sub-matrices, all of which are of the same size and non-zero. The first row of the first sub-matrix in each of the multiple sub-matrix groups has a different row number. The W sub-matrices are determined based on a first matrix, where M, N, and n are positive integers, and W is an integer greater than 1.

[0009] Based on the above method, W submatrices can be obtained from the first matrix, that is, the LDPC basis matrix can be obtained from the first matrix. In this way, the encoding device does not need to store the LDPC basis matrix, but instead stores the first matrix, which is much smaller than the LDPC basis matrix, thus reducing the storage space required. Furthermore, since the LDPC basis matrix can be obtained from the first matrix, the first matrix can be obtained in a smaller search space during matrix construction, and then the LDPC basis matrix can be obtained from the first matrix, thus reducing the difficulty of matrix construction.

[0010] In conjunction with the first aspect, in some implementations, the first position of the first matrix is ​​a non-zero element, the first position corresponds to the second position of the submatrix, the second position of P submatrices out of the W submatrices is a non-zero element, the second position of the submatrices other than the P submatrices out of the W submatrices is a zero element, and P is a positive integer less than W; and / or, the third position of the first matrix is ​​a zero element, the third position corresponds to the fourth position of the submatrix, the fourth position of each of the W submatrices is a zero element; and / or, the fifth position of the first matrix is ​​a non-zero element, the fifth position corresponds to the sixth position of the submatrix, the sixth position of each of the W submatrices is a non-zero element.

[0011] The first matrix may include one or more first positions, one or more third positions, and one or more fifth positions.

[0012] Based on the above implementation, the first matrix can be decomposed into W sub-matrices, which helps reduce storage overhead and matrix construction difficulty. When P is greater than 1, the element at the first position of the first matrix is ​​a polygon, meaning that the above implementation also applies to the case where the first matrix is ​​a polygonal matrix. This increases the design space of the LDPC code and improves matrix performance.

[0013] In conjunction with the first aspect or any of its implementations, in some other implementations, the first position of the first matrix corresponds to P first translation values, the first translation values ​​correspond to the promoted cyclic shift matrix, the translation values ​​corresponding to the second positions of the P sub-matrices correspond one-to-one with the P first translation values, the translation values ​​corresponding to the second positions of the sub-matrices other than the P sub-matrices in the W sub-matrices are second translation values, the second translation values ​​correspond to the promoted all-zero matrix, and P is a positive integer; and / or, the translation value corresponding to the fifth position of the first matrix is ​​the same as the translation value corresponding to the sixth position of each of the W sub-matrices.

[0014] In conjunction with the first aspect or any of its implementations, in some other implementations, each of the W submatrices includes a first region, the first matrix includes a second region, the second region being the same size as the first region, and the first region being determined based on the second region.

[0015] In the above implementation, the size of the second region can be less than or equal to the size of the first matrix, meaning that some or all of the regions of the first matrix can be split. This provides greater flexibility.

[0016] In conjunction with the first aspect or any of its implementations, in some other implementations, each of the W sub-matrices further includes a third region, and the first matrix further includes a fourth region, which is the region other than the second region of the first matrix, and the values ​​of the elements in the third region are the same as the values ​​of the corresponding elements in the fourth region.

[0017] In conjunction with the first aspect or any of its implementations, in some other implementations, the W submatrices and the first matrix adopt a raptor-like structure. This implementation supports flexible bitrates.

[0018] In conjunction with the first aspect or any of its implementations, in some other implementations, each of the W submatrices includes a first core portion, a first all-zero portion, a first extended portion below the first core portion, and a second extended portion below the first all-zero portion, wherein the second extended portion of the first submatrix of the W submatrices is a lower triangular matrix.

[0019] In conjunction with the first aspect or any of its implementations, in some other implementations, the first region includes a first sub-region, a second sub-region, and a third sub-region, where the first sub-region belongs to the first core part, the second sub-region belongs to the first extended part, and the third sub-region belongs to the second extended part. This implementation is more flexible.

[0020] In conjunction with the first aspect or any of its implementations, in other implementations, the first sub-region, the second sub-region, and the third sub-region may be the same or different in size. This implementation is more flexible.

[0021] In conjunction with the first aspect or any of its implementations, in some other implementations, the row weight of the j-th row of the first submatrix among the W submatrixes is not less than the row weight of the j-th row of the submatrixes other than the first submatrix among the W submatrixes, where j is a non-negative integer.

[0022] That is, the first submatrix among the W submatrixes has the largest row weight.

[0023] In conjunction with the first aspect or any implementation thereof, in other implementations, the W sub-matrices are determined based on the first information and the first matrix, wherein the first information is used to indicate the splitting method of each element in the first matrix. In this way, the encoding device can obtain the LDPC basis matrix for encoding by storing the first matrix and the first information, which helps to reduce storage overhead.

[0024] In conjunction with the first aspect or any of its implementations, in some other implementations, the first information takes the form of any of the following: matrix, list, or sequence.

[0025] In conjunction with the first aspect or any of its implementations, in some other implementations, the elements in every n columns of the N columns of the LDPC basis matrix, excluding the W submatrices, are zero elements.

[0026] Secondly, embodiments of this application provide an information processing method that can be applied to a decoding side, such as a decoding device, a module within the decoding device (e.g., a circuit, chip, or chip system (such as a modem chip, or a SoC chip or SIP chip containing a modem core)), or a logical node, logical module, or software capable of implementing all or part of the decoding device. The decoding device can be a network device or a terminal. This second aspect corresponds to the decoding side of the first aspect. Terms or features identical to those in the second aspect or implementations of the first aspect can be referenced to the first aspect or its implementations. The technical effects of the second aspect can be referenced to the first aspect or its implementations, and will not be repeated here.

[0027] The method includes: acquiring information to be decoded; decoding the information according to an M-row, N-column LDPC base matrix to obtain decoded information, wherein the LDPC base matrix includes multiple sub-matrix groups, each n-column of the N columns of the LDPC base matrix corresponds to a sub-matrix group, each sub-matrix group includes W sub-matrices, the W sub-matrices are of the same size and are non-zero matrices, the row numbers of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups are different, the W sub-matrices are determined based on a first matrix, M, N, and n are positive integers, and W is an integer greater than 1.

[0028] In conjunction with the second aspect, in some implementations, the first position of the first matrix is ​​a non-zero element, the first position corresponds to the second position of the submatrix, the second position of P submatrices out of the W submatrices is a non-zero element, the second position of the submatrices other than the P submatrices out of the W submatrices is a zero element, and P is a positive integer less than W; and / or, the third position of the first matrix is ​​a zero element, the third position corresponds to the fourth position of the submatrix, the fourth position of each of the W submatrices is a zero element; and / or, the fifth position of the first matrix is ​​a non-zero element, the fifth position corresponds to the sixth position of the submatrix, the sixth position of each of the W submatrices is a non-zero element.

[0029] In conjunction with the second aspect or any of its implementations, in some other implementations, the first position of the first matrix corresponds to P first translation values, the first translation values ​​correspond to the boosted cyclic shift matrix, the translation values ​​corresponding to the second positions of the P sub-matrices correspond one-to-one with the P first translation values, the translation values ​​corresponding to the second positions of the sub-matrices other than the P sub-matrices in the W sub-matrices are second translation values, the second translation values ​​correspond to the boosted all-zero matrix, and P is a positive integer; and / or, the translation value corresponding to the fifth position of the first matrix is ​​the same as the translation value corresponding to the sixth position of each of the W sub-matrices.

[0030] In conjunction with the second aspect or any of its implementations, in some other implementations, each of the W submatrices includes a first region, the first matrix includes a second region, the second region being the same size as the first region, and the first region being determined based on the second region.

[0031] In conjunction with the second aspect or any of its implementations, in some other implementations, each of the W sub-matrices further includes a third region, and the first matrix further includes a fourth region, which is the region other than the second region of the first matrix, and the values ​​of the elements in the third region are the same as the values ​​of the corresponding elements in the fourth region.

[0032] In conjunction with the second aspect or any of its implementations, in some other implementations, the W submatrices and the first matrix adopt a raptor-like structure.

[0033] In conjunction with the second aspect or any of its implementations, in some other implementations, each of the W submatrices includes a first core portion, a first all-zero portion, a first extended portion below the first core portion, and a second extended portion below the first all-zero portion, wherein the second extended portion of the first submatrix of the W submatrices is a lower triangular matrix.

[0034] In conjunction with the second aspect or any of its implementations, in some other implementations, the first region includes a first sub-region, a second sub-region, and a third sub-region, wherein the first sub-region belongs to the first core part, the second sub-region belongs to the first extended part, and the third sub-region belongs to the second extended part.

[0035] In conjunction with the second aspect or any of its implementations, in some other implementations, the first sub-region, the second sub-region, and the third sub-region may be the same or different in size.

[0036] In conjunction with the second aspect or any of its implementations, in some other implementations, the row weight of the j-th row of the first submatrix among the W submatrixes is not less than the row weight of the j-th row of the submatrixes other than the first submatrix among the W submatrixes, where j is a non-negative integer.

[0037] In conjunction with the second aspect or any of its implementations, in some other implementations, the W submatrices are determined based on first information and the first matrix, wherein the first information is used to indicate the splitting method of each element in the first matrix.

[0038] In conjunction with the second aspect or any of its implementations, in some other implementations, the first information takes the form of any of the following: a matrix, a list, or a sequence.

[0039] In conjunction with the second aspect or any of its implementations, in some other implementations, the elements in every n columns of the N columns of the LDPC basis matrix, excluding the W submatrices, are zero elements.

[0040] Thirdly, embodiments of this application provide an information processing method that can be applied to the encoding side, such as an encoding device, modules within the encoding device (e.g., circuits, chips, or chip systems (such as modem chips, or SoC chips or SIP chips containing modem cores)), or logical nodes, logical modules, or software that can implement all or part of the encoding device. The encoding device can be a terminal or a network device.

[0041] The method includes: acquiring information to be encoded; encoding the information according to an M-row, N-column LDPC base matrix; and outputting the encoded information; wherein the LDPC base matrix comprises multiple sub-matrix groups, each n-column of the N columns of the LDPC base matrix corresponds to a sub-matrix group, each sub-matrix group comprises W sub-matrices, the W sub-matrices are of the same size and are non-zero matrices, and the row numbers of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups are different; the first position of the first matrix is ​​a non-zero element, the first position corresponds to the second position of the sub-matrix, and P elements in the W sub-matrices... The second position of the matrix is ​​a non-zero element and the second position of the submatrices other than the P submatrices in the W submatrices is a zero element, and / or the third position of the first matrix is ​​a zero element, the third position corresponding to the fourth position of the submatrices, the fourth position of each of the W submatrices is a zero element, and / or the fifth position of the first matrix is ​​a non-zero element, the fifth position corresponding to the sixth position of the submatrices, the sixth position of each of the W submatrices is a non-zero element; M, N, n are positive integers, W is an integer greater than 1, and P is a positive integer less than W.

[0042] It should be noted that the steps performed by the encoding device in the third aspect can refer to the first aspect or its implementation. The terms or features in the third aspect that are the same as those in the first aspect or its implementation can refer to the first aspect or its implementation. The technical effects of the third aspect can refer to the technical effects in the first aspect or its implementation, and will not be repeated here.

[0043] Fourthly, embodiments of this application provide an information processing method that can be applied to a decoding side, such as a decoding device, a module (e.g., a circuit, chip, or chip system (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core) within the decoding device, or a logical node, logical module, or software that can implement all or part of the decoding device. The decoding device can be a network device or a terminal.

[0044] The method includes: acquiring information to be decoded; decoding the information according to an M-row, N-column LDPC basis matrix to obtain decoded information; wherein, the LDPC basis matrix includes multiple sub-matrix groups, each n columns of the N columns of the LDPC basis matrix corresponds to a sub-matrix group, each sub-matrix group includes W sub-matrices, the W sub-matrices are of the same size and are non-zero matrices, and the row numbers of the first row of the first sub-matrix corresponding to each of the multiple sub-matrix groups are different; the first position of the first matrix is ​​a non-zero element, the first position corresponds to the second position of the sub-matrix, and P elements in the W sub-matrices are... The second position of the matrix is ​​a non-zero element and the second position of the submatrices other than the P submatrices in the W submatrices is a zero element, and / or the third position of the first matrix is ​​a zero element, the third position corresponding to the fourth position of the submatrices, the fourth position of each of the W submatrices is a zero element, and / or the fifth position of the first matrix is ​​a non-zero element, the fifth position corresponding to the sixth position of the submatrices, the sixth position of each of the W submatrices is a non-zero element; M, N, n are positive integers, W is an integer greater than 1, and P is a positive integer less than W.

[0045] It should be noted that the steps performed by the decoding device in the fourth aspect can refer to the second aspect or its implementation. The same terms or features in the fourth aspect as those in the second aspect or its implementation can refer to the second aspect or its implementation. The technical effects of the fourth aspect can refer to the technical effects in the second aspect or its implementation. They will not be repeated here.

[0046] Fifthly, embodiments of this application provide a communication device that has the function of implementing any of the above aspects or any possible implementation methods. For example, the communication device includes modules, units, or means corresponding to the operations involved in performing any of the above aspects or any possible implementation methods. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0047] Sixthly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in any of the above aspects or any possible implementations thereof. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in any of the above aspects or any possible implementations thereof when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0048] In one possible implementation, the processor is used to communicate with other devices or components through the interface circuit.

[0049] In one possible implementation, the communication device may also include the memory.

[0050] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0051] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0052] In a seventh aspect, embodiments of this application provide a communication system including at least one of the encoding or decoding devices described above.

[0053] Eighthly, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause the computer to perform any of the above aspects or any possible implementation thereof.

[0054] Ninthly, embodiments of this application provide a computer program product that, when read and executed by a computer, causes the computer to perform any of the above aspects or any possible implementation thereof.

[0055] In a tenth aspect, embodiments of this application provide a computer program that, when run on a computer, causes the methods provided in any of the foregoing aspects or any possible implementation thereof to be executed. Attached Figure Description

[0056] Figure 1 is a schematic diagram of a network architecture applicable to embodiments of this application.

[0057] Figure 2 is a schematic diagram of a communication scenario applicable to embodiments of this application.

[0058] Figure 3 is a schematic architecture diagram of a mobile communication chip system applicable to embodiments of this application.

[0059] Figure 4 is a schematic architecture diagram of an encoder chip applicable to embodiments of this application.

[0060] Figure 5 is a schematic architecture diagram of a decoder chip applicable to embodiments of this application.

[0061] Figure 6 is the Tanner plot of the parity-check matrix H.

[0062] Figure 7 is a schematic diagram of the matrix structure of the base graph (BG) of the 5th generation (5G) LDPC code.

[0063] Figure 8 is a schematic diagram of 5G LDPC code.

[0064] Figure 9 is an example of a Tanner diagram for SC-LDPC codes.

[0065] Figure 10 is a schematic diagram of sliding window decoding of SC-LDPC code.

[0066] Figure 11 is a schematic flowchart of the information processing method 1100 provided in this application.

[0067] Figure 12 is a schematic diagram of the overlapping part.

[0068] Figure 13 is another schematic diagram of the overlapping part.

[0069] Figure 14 is a schematic diagram of the verification matrix before and after splitting.

[0070] Figure 15 is an example of how B0 and B1 are obtained from B.

[0071] Figure 16 is another example of how B0 and B1 are derived from B.

[0072] Figure 17 is another schematic diagram of the verification matrix before and after splitting.

[0073] Figure 18 is another example of how B0 and B1 are derived from B.

[0074] Figure 19 is another example of how B0 and B1 are derived from B.

[0075] Figure 20 is an example of a first matrix containing multiple sub-regions and W sub-matrices.

[0076] Figure 21 is an example of splitting that supports variable rates.

[0077] Figure 22 is an example of how B0 to B3 are derived from B.

[0078] Figure 23 is a schematic diagram of matrix T.

[0079] Figure 24 is a schematic diagram of a device provided in an embodiment of this application.

[0080] Figure 25 is another structural schematic diagram of the device provided in an embodiment of this application.

[0081] Figure 26 is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0082] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0083] "System" and "network" can be used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC. "At least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC, where A, B, and C can be single or multiple. And, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects. The term "protocol" may refer to standard protocols in the field of communications, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as (another) example" are used to indicate that something is being described as an example, illustration, or description. Any embodiment or design described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0084] In this application, "sending information" can be understood as one device sending information to another device, or it can also be understood as one logic module within a device sending information to another logic module. For example, "the encoding device sending information" can be understood as the encoding device sending information to another device (such as a decoding device), or it can be understood as logic module 1 in the encoding device sending information to logic module 2 in the encoding device.

[0085] In this application, "receiving information" can be understood as one device receiving information from another device, or it can also be understood as a logic module within a device receiving information from another logic module. For example, "decoding device receiving information" can be understood as the decoding device receiving information from another device (such as an encoding device), or it can be understood as logic module 1 in the decoding device receiving information from logic module 2 in the decoding device.

[0086] In this application, the phrase "sending information to... (e.g., a decoding device)" or the related illustrations in the accompanying drawings can be understood as the destination of the information being a decoding device. This can include sending information directly or indirectly to a terminal. Similarly, the phrases "receiving information from... (e.g., an encoding device)," "receiving information from... (e.g., an encoding device)," or "receiving information sent (e.g., by an encoding device)," or the related illustrations in the accompanying drawings, can be understood as the source of the information being an encoding device. This can include receiving information directly or indirectly from an encoding device. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly, and will not be elaborated further here.

[0087] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0088] The following describes a communication system to which embodiments of this application can be applied.

[0089] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, long term evolution-vehicle (LTE-V) communication, long term evolution-machine (LTE-M) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. The embodiments of this application can also be applied to satellite communication systems, high altitude platform station (HAPS) communications, unmanned aerial vehicles (UAVs), and other non-terrestrial network (NTN) systems, such as integrated communication and navigation (ICAN) systems, global navigation satellite systems (GNSS), and ultra-dense low-Earth orbit (LEO) satellite communication systems. Furthermore, it can be extended to similar wireless communication systems, such as wireless local area networks (WLANs), wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and other communication systems related to the 3rd generation partnership project (3GPP).

[0090] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminals. Optionally, both the transmitting device and the receiving device may be network devices.

[0091] In this application, the transmitting device can be understood as a device that transmits data or information, and can also be called an encoding device. The receiving device can be understood as a device that receives data or information, and can also be called a decoding device. The following uses the terms encoding device and decoding device to describe the scheme of this application.

[0092] For example, Figure 1 shows a schematic diagram of a network architecture to which embodiments of this application may be applied.

[0093] Figure 1 illustrates a possible, non-limiting system diagram. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0094] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0095] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0096] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0097] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0098] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0099] In the embodiments of this application, the access network device may also be simply referred to as a network device.

[0100] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0101] The embodiments of this application can be applied to various mobile communication scenarios, such as multi-hop or multi-relay transmission between network devices and terminal devices, dual connectivity (DC) or multiple connectivity between multiple network devices and terminal devices, etc.

[0102] Figure 2 is a schematic diagram of a communication scenario applicable to embodiments of this application.

[0103] Figure 2(a) shows a point-to-point single connection between a network device and a terminal device; Figure 2(b) shows a multi-hop single connection between a network device and a terminal device; Figure 2(c) shows a DC dual connection between a network device and a terminal device; and Figure 2(d) shows a multi-hop multi-connection between a network device and a terminal device.

[0104] It should be noted that Figure 2 is merely exemplary and does not limit the network architecture applicable to this application. Any network architecture in a cellular network where one device charges other devices is applicable to this application. Communication scenarios applicable to this application include, but are not limited to: network devices charging terminal devices, network devices charging network devices, network devices charging relays, relay network devices charging terminal devices, multiple network devices charging one terminal device, multiple network devices charging multiple terminal devices, and any scenario where one or more devices charge one or more other devices.

[0105] Unless otherwise specified, the means for implementing the functions of a terminal or network device in this application can refer to the terminal or network device itself, or it can refer to a means that enables the terminal or network device to implement the function, such as a system-on-a-chip (SoC) or a chip, specifically a SoC or a modem. This means can be installed in the terminal or network device. In the embodiments of this application, the SoC can be composed of chips, or it can include chips and other discrete devices.

[0106] It should also be noted that some embodiments in this article use a 5G system as an example to illustrate specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0107] The technical solutions provided in the embodiments of this application can be applied to channel coding / decoding between communication devices. Channel coding / decoding between communication devices can include: channel coding / decoding between network devices and terminal devices, channel coding / decoding between network devices, and channel coding / decoding between terminal devices. The term channel coding can also be referred to as coding, network coding, source-channel joint coding, etc., and the term channel decoding can also be referred to as decoding, network decoding, source-channel joint decoding, etc. The coding structures applicable to the embodiments of this application include, but are not limited to: concatenated codes, layered codes, coupled codes, outer codes, sliding window codes, product codes, or ladder codes. The term coding structure can also be referred to as code type, code design, etc.

[0108] Figure 3 is a schematic architecture diagram of a mobile communication chip system applicable to embodiments of this application.

[0109] As shown in Figure 3, the mobile communication chip system is divided into downlink processing and uplink processing. In downlink processing, layer 2 (L2) data is encoded, modulated, layer mapped, precoded, framed, and subjected to inverse fast Fourier transform (IFFT), and finally processed into an over-the-air signal by the intermediate radio frequency (IRF) module. In uplink processing, the received signal is processed by the IRF module to obtain baseband data, and physical layer signal processing is completed through fast Fourier transform (FFT), deframing, equalization, de-mapping, demodulation, and decoding. The embodiments of this application are applied to the encoding and decoding modules in the mobile communication chip system architecture and are important components of the baseband processing system. Exemplarily, the encoding module can be an encoder chip, and the decoding module can be a decoder chip.

[0110] Figure 4 is a schematic architecture diagram of an encoder chip applicable to embodiments of this application.

[0111] The encoder chip architecture, as shown in Figure 4, consists of three main components: a computing unit, a control unit, and a storage unit. These three components are coupled together. The computing unit is responsible for processing the encoder's logical operations, the storage unit is responsible for storing the data generated during the computation process, and the control unit is responsible for scheduling and controlling the computing unit and storage resources. Taking LDPC encoding as an example, the encoder's computation is completed through transport block (TB) cyclic redundancy check (CRC) calculation, BG selection, code block segmentation, code block (CB) CRC calculation, LDPC encoding, and code block concatenation. The encoder chip can perform corresponding encoding according to the LDPC check matrix structure provided in the embodiments of this application.

[0112] Figure 5 is a schematic architecture diagram of a decoder chip applicable to embodiments of this application.

[0113] The decoder chip architecture, as shown in Figure 5, consists of three main components: a computing unit, a control unit, and a storage unit. These three components are coupled together. The computing unit is responsible for handling the decoder's logical operations, the storage unit is responsible for storing data generated during the computation process, and the control unit is responsible for scheduling and controlling the computing unit and storage resources. Taking LDPC decoding as an example, the decoding process is completed through rate matching, hybrid automatic repeat-request (HARQ) merging, LDPC decoding, CB CRC check, and TB CRC check. The decoder chip can perform corresponding decoding according to the structure of the LDPC check matrix provided in the embodiments of this application.

[0114] The encoding and / or decoding shown in Figures 3 to 5 can be implemented in hardware or software. When the throughput requirement for encoding / decoding is high, a hardware accelerator (HAC) can be used.

[0115] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application will be briefly explained.

[0116] The concepts and terms described below are based on those specified in the agreement, but do not imply that the embodiments of this application can only be applied to existing systems. The concepts and terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms related to functional descriptions) may be adjusted as future systems develop.

[0117] 1. LDPC code

[0118] LDPC codes are linear block codes with sparse parity-check matrices. The proportion of non-zero elements in the parity-check matrix of an LDPC code is extremely small; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with K information bits and a code length of N, its parity-check matrix H has dimensions (NK) × N, and the corresponding codeword c can be defined by the parity-check matrix H as: c = {c|Hc} T =0, c∈{0,1} N}

[0119] .

[0120] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and the NK parity-check equations correspond to the NK parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0121] Where v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0122] LDPC codes can be represented using graph models. Commonly used graph models include Tanner graphs, factor graphs, and tree graphs, among which Tanner graphs offer the most concise and intuitive representation. The Tanner graph of the parity-check matrix H is shown in Figure 6. The degree in Figure 6 corresponds to the definition of degree in the parity-check matrix H, where the degree of a node can be defined as the number of edges connected to it.

[0123] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0124] The parity-check matrix of QC-LDPC code has quasi-cyclic properties, and the parity-check matrix can be simplified according to the quasi-cyclic structure.

[0125] For a (N, K) QC-LDPC code, the number of check bits (or check nodes, rows) is M = NK, and the check matrix H can be represented as:

[0126] Where N = n b ×Z, M=m b ×Z, Z≥1, P i,j This represents a Z×Z cyclic shift matrix or a Z×Z all-zero matrix, which can be represented by the corresponding cyclic shift coefficient p. i,j To simplify the representation, Z represents the lifting size, also known as the expansion factor, expansion value, expansion coefficient, or lifting dimension. Here, the cyclic shift matrix is ​​defined as a cyclic right shift matrix of an identity matrix. The shift factor is determined by the number of bits shifted to the right of the first element, and its value ranges from p. i,j ∈[-1,Z max -1], where Z max It is the maximum value of Z, Z≤Z max p i,j =-1 represents a matrix of all zeros, p i,j =0 represents the identity matrix, 1≤p i,j ≤Z max -1 indicates that each element of the identity matrix is ​​cyclically shifted right by 1 by p. i,j The matrix obtained by the bit transformation function g(p) i,j (Z) usually has the following form:

[0127] Where % represents the modulo operation, with Z=4, Z max For example, with a value of 8, the p of LDPC i,j The corresponding matrix is:

[0128] The matrix obtained by simplifying the parity-check matrix based on a quasi-cyclic structure can be called the basis matrix. Based on the basis matrix and the boost value Z, the basis matrix H can be expanded into a complete parity-check matrix for encoding or decoding. The basis matrix is ​​sometimes also called the base graph (BG). The base graph can also be called the basic pattern graph, protograph, etc.

[0129] 3. Base map of 5G LDPC code

[0130] The base map of 5G LDPC code includes BG1 and BG2, which share a common matrix structure.

[0131] Figure 7 is a schematic diagram of the matrix structure of the 5G LDPC code basemap. The 5G LDPC code basemap adopts a raptor-like structure, which can be divided into five regions: A, B, C, D, and E. Regions A and B are high-rate regions; region A corresponds to the information column region at high code rates, and region B corresponds to the core check region at high code rates. Region C is an all-zero region, which is a zero matrix. Region D is an incremental redundancy region, an extended region corresponding to low code rates. Region E is an extended region whose diagonal positions, when expanded, do not contain a zero matrix (i.e., the translation value corresponding to its diagonal position is not -1).

[0132] The elements in the base graph take values ​​of 0 or 1, where 0 represents an empty element or zero element, and 1 represents an edge present at that position in the base graph or an association between the corresponding check node and the variable node. The translation value corresponding to 0 in the base graph can be represented by "-1", other numerical values ​​or symbols, or an empty value; there are no restrictions.

[0133] In 5G LDPC codes, the protocol specifies storing the largest possible base map. In practical applications, different matrix regions are selected based on the code rate. Specifically, rows 1 to M0 and columns 1 to N0 are selected. As the code rate decreases, M0 and N0 gradually increase, and the area of ​​the matrix used also gradually expands. For example, the dashed boxes in Figure 8 that contain high code rate regions correspond to different code rates.

[0134] The base map of 5G LDPC code has a nested characteristic, meaning that low code rate regions contain high code rate regions.

[0135] 4. SC-LDPC code

[0136] Due to the presence of trap sets, LDPC codes exhibit error planes, which degrade system performance in regions with high signal-to-noise ratios. Furthermore, when LDPC codes are long, the encoding and decoding processes become computationally complex and time-consuming, making it difficult for existing standards to support applications with extremely long codes. SC-LDPC codes, as a type of coupled code, can be used to address this problem.

[0137] The parity-check matrix of SC-LDPC codes can be obtained by coupling the parity-check matrix of traditional LDPC codes. SC-LDPC codes couple adjacent LDPC block codes together, which can be regarded as a local coupling relationship. Compared with traditional LDPC codes, SC-LDPC codes not only have better decoding performance, but also have a relatively simple coding structure. Furthermore, SC-LDPC codes employ a unique parity-preceding coding scheme and a unique sliding window decoding scheme, which effectively reduces decoding latency, and are considered a very promising coding scheme.

[0138] SC-LDPC codes are a class of finite-length LDPC convolutional codes, whose parity-check matrix is ​​composed of multiple coupled submatrices. The basis matrix B of a graph-based SC-LDPC code... SC It can be represented as:

[0139] Where L represents the coupling length, m s Indicates the coupling depth. B SC Each column contains m s +1 submatrix, i.e. Each submatrix has a size of m0 × n0. If B SC Satisfy B i (i)=B i (i+1)=…=B i (i+L), i=0,1,….,m s If the code is invariant, it is called a time-invariant SC-LDPC code; otherwise, it is called a time-varying SC-LDPC code. For ease of explanation, the following text will use time-invariant SC-LDPC codes.

[0140] Similar to QC-LDPC codes, the parity-check matrix can be obtained by expanding the basis matrix of the SC-LDPC code by querying the offset matrix. The expanded parity-check matrix is ​​denoted as H. SC H SC The size is [m0(m s +L)·Z]×(n0L·Z). B SC The corresponding translation matrix can be denoted as: P SC Each element p in i,j To satisfy p i,j Integers ≥-1. If p i,j =-1, it can be expanded into a zero matrix of size Z×Z; otherwise, it can be expanded into a cyclic shift matrix of size Z×Z identity matrix, p i,j This indicates the amount of cyclic displacement to the right.

[0141] Time-invariant SC-LDPC codes can also be represented by a Tanner diagram, let m s=1, select a subset of variable nodes on the uncoupled Tanner graph at time t and connect them to the next m. s Verification nodes on a Tanner graph.

[0142] Figure 9 is an example of a Tanner diagram for an SC-LDPC code. 91 in Figure 9 represents the LDPC code used for coupling, and 92 in Figure 9 represents the SC-LDPC code generated by copying the Tanner diagram of 91 in Figure 9 L times and coupling them together.

[0143] When time-invariant SC-LDPC codes undergo L-column truncation, additional check nodes are added and connected to the variable nodes from the previous time step. This results in a loss of code rate. The code rate of SC-LDPC codes is related to the coupling length L and coupling depth m. s Related, when m s When L is constant, increasing L can reduce bitrate loss. When L is infinitely large, bitrate loss is almost non-existent.

[0144] During decoding, the SC-LDPC code can be applied to the entire parity check matrix H. SC Decoding can also be performed using sliding window decoding. The process of sliding window decoding is illustrated in Figure 10. The window size remains constant, sliding sequentially to the lower right (moving from the solid-line rectangle to the dashed-line rectangle), decoding each portion of the matrix within the window. Sliding window decoding can reduce complexity and decoding latency.

[0145] The relevant terms used in the embodiments of this application have been described above, and will not be explained further below.

[0146] Currently, the system may need to support both uncoupled LDPC codes and SC-LDPC codes simultaneously. In this case, more space is required to store the matrix, and the basis matrix of SC-LDPC codes has a large search space during construction. For example, when m s When = 1, let the dimensions of B0 and B1 be m×n. Then, when searching the matrix, it is necessary to search on at least 2m×2n dimensions, which results in a large search space and increases the difficulty of matrix construction.

[0147] To address the aforementioned problems, this application provides an information processing method and apparatus to reduce storage space usage and simplify matrix construction.

[0148] The method embodiments of this application are described below with reference to the accompanying drawings.

[0149] Figure 11 is a schematic flowchart of the information processing method 1100 provided in this application.

[0150] It is understood that this application uses encoding and decoding devices as examples to illustrate the execution of the interaction, but this application does not limit the execution entities of the interaction. For example, the method executed by the encoding device in this application can also be implemented by modules in the encoding device, or by logical nodes, logical modules, or software that can implement all or part of the functions of the encoding device; similarly, the method executed by the decoding device in this application can also be implemented by modules in the decoding device, or by logical nodes, logical modules, or software that can implement all or part of the functions of the decoding device. Modules in the encoding device and / or decoding device can be, for example, circuits, chips, or chip systems (such as modem chips, also known as baseband chips, or SoC chips or SIP chips containing modem cores, etc.). The encoding device can be a terminal device or a network device, and the decoding device can be a network device or a terminal device.

[0151] Method 1100 may include at least a portion of the following:

[0152] Step 1101: The encoding device acquires the information to be encoded.

[0153] In other words, if the encoding device needs to communicate with the decoding device, that is, if the encoding device needs to send a signal to the decoding device, the encoding device needs to first obtain the information corresponding to the signal to be sent to the decoding device.

[0154] The phrase "the encoding device acquires the information to be encoded" can refer to: the encoding device performing source encoding on source symbols to generate an information bit sequence. Alternatively, it can refer to: the encoding device receiving an information bit sequence from other communication devices.

[0155] Step 1102: The encoding device encodes the information according to the LDPC base matrix and outputs the encoded information.

[0156] In one implementation, the encoding device can expand the LDPC base matrix into a parity-check matrix based on a boost value, and then use the expanded parity-check matrix to encode the information to be encoded, obtaining the encoded information. The boost value can be determined based on the system-supported code block size and / or the size of the information data, etc.

[0157] In step 1103, the encoding device sends a symbol sequence to the decoding device based on the encoded information. Accordingly, the decoding device receives the symbol sequence from the encoding device.

[0158] The symbol sequence can be the sequence of encoded information after operations such as rate matching and modulation. For example, the encoding device performs rate matching on the encoded information, then modulates the rate-matched sequence to obtain the symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0159] Understandably, since channel noise signals may be introduced during the transmission of the symbol sequence, the symbol sequence sent by the encoding device and the symbol sequence received by the decoding device may be different.

[0160] Step 1104: The decoding device decodes the information to be decoded based on the LDPC basis matrix to obtain the decoded information.

[0161] For example, the information to be decoded can be a sequence of symbols.

[0162] For example, the information to be decoded can also be based on information obtained from a symbol sequence. In other words, the decoding device can process the received symbol sequence to obtain the information to be decoded. For instance, the information to be decoded can be information obtained after demodulation of the symbol sequence. As another example, the information to be decoded can be information obtained after demodulation and distribution matching processing.

[0163] In one implementation, the decoding device can expand the LDPC basis matrix into a parity check matrix based on a boost value, and then use the expanded parity check matrix to decode the information to be decoded, obtaining the decoded information. The boost value can be determined based on the system-supported code block size and / or the size of the information data, etc.

[0164] In the embodiments of this application, the LDPC base matrix is ​​an M-row, N-column matrix, where M and N are positive integers. The LDPC base matrix comprises multiple submatrix groups. Each n-column of the N columns of the LDPC base matrix corresponds to a submatrix group. Each submatrix group comprises W submatrices of the same size, meaning each submatrix in each submatrix group comprises n columns, where n is a positive integer and W is an integer greater than 1. The W submatrices in different submatrix groups are identical. For example, if the LDPC base matrix includes submatrix group 1 and submatrix group 2, both submatrix group 1 and submatrix group 2 include submatrix B0 and submatrix B1. B0 in submatrix group 1 is the same as B0 in submatrix group 2, and B1 in submatrix group 1 is the same as B1 in submatrix group 2. The W submatrices in each submatrix group are not zero matrices. The row numbers of the first row of the first submatrix corresponding to each of the multiple submatrix groups are different. As an example, the row number of the first row of the first submatrix corresponding to each of the multiple submatrix groups can be increased sequentially by the same value, such as 1, or half the number of rows in each submatrix, or the number of rows in each submatrix. As another example, the row number of the first row of the first submatrix corresponding to each of the multiple submatrix groups can be decreased sequentially by the same value, such as 1, or half the number of rows in each submatrix, or the number of rows in each submatrix.

[0165] For example, the LDPC basis matrix can be the SC-LDPC basis matrix B as mentioned in the terminology explanation section. SC In this case, M = m0(m) s +L), N=n0L, the number of submatrix groups is L+1, W=m s +1, the size of each submatrix is ​​m0×n0, that is, n=n0, and the row number of the first row of the first submatrix corresponding to each of the multiple submatrix groups increases by m0 in sequence.

[0166] In the embodiments of this application, the W sub-matrices can be obtained from the first matrix, that is, the LDPC basis matrix can be obtained from the first matrix. Thus, the encoding and decoding devices do not need to store the LDPC basis matrix, but instead store the first matrix, which is much smaller than the LDPC basis matrix, thereby reducing the storage space required. Furthermore, since the LDPC basis matrix can be obtained from the first matrix, the first matrix can be obtained in a smaller search space when constructing the matrix, and then the LDPC basis matrix can be obtained from the first matrix, thus reducing the difficulty of matrix construction.

[0167] It should be noted that the embodiments of this application do not limit the values ​​of the elements other than the W submatrices in every n columns of the N columns of the LDPC base matrix. For example, all elements other than the W submatrices in every n columns of the N columns of the LDPC base matrix are zero elements.

[0168] In some implementations, the first matrix can be an NR LDPC basis matrix, or a matrix obtained using existing LDPC matrix construction techniques. It should be understood that the NR LDPC basis matrix is ​​an NR-related LDPC basis matrix, which can be the LDPC basis matrix in the NR standard protocol, or the LDPC basis matrix mentioned during the discussion of the NR standard protocol. The NR protocol can be any version of the protocol, without restriction. When the first matrix is ​​the basis matrix of the uncoupled LDPC code in the NR standard protocol, and the LDPC basis matrix in method 1100 is the basis matrix of the SC-LDPC code, in scenarios where the system simultaneously supports uncoupled LDPC codes and SC-LDPC codes, for both uncoupled LDPC codes and SC-LDPC codes, the encoding and decoding devices can store the basis matrix of the uncoupled LDPC code but not the basis matrix of the SC-LDPC code. The basis matrix of the SC-LDPC code can be obtained from the basis matrix of the uncoupled LDPC code, thus further reducing the storage space required.

[0169] In some implementations, the first matrix can be a full-column-weight LDPC basis matrix, or the first matrix can be a regular LDPC basis matrix where all rows have equal weight and all columns have equal weight.

[0170] The embodiments of this application are not limited to the implementation method of obtaining W submatrices from the first matrix. In some implementations, the W submatrices can be obtained by splitting the first matrix.

[0171] For example, a non-zero element at a certain position in the first matrix can be split into corresponding positions in W submatrices. For instance, if the first position of the first matrix is ​​a non-zero element, this first position corresponds to the second position of each of the W submatrices. The second positions of P submatrices out of the W submatrices are non-zero elements, and the second positions of the remaining submatrices out of the W submatrices are zero elements. The non-zero element at the first position of the first matrix can be a single edge, such as 1 for the first position. It can also be a multi-edge element, such as (1,1) for the first position. When the number of edges of the non-zero element at the first position of the first matrix is ​​less than W, P is a positive integer less than W. When the number of edges of the non-zero element at the first position of the first matrix is ​​greater than or equal to W, P is a positive integer equal to W. It should be understood that when the non-zero element at the first position of the first matrix is ​​a single edge, the second position of one of the W submatrices is a non-zero element, and the second positions of the remaining submatrices are all zero elements. When the non-zero element at the first position of the first matrix is ​​a multi-sided element, the second position of multiple submatrices in the W submatrices is a non-zero element. The second position of W submatrices minus the number of sides in the W submatrices is a zero element. If the number of sides of the non-zero element at the first position of the first matrix is ​​greater than or equal to W, the second position of each of the W submatrices is a non-zero zero element. It should be understood that the first matrix can include one or more of the aforementioned first positions; that is, one or more non-zero elements of the first matrix can be split as described above.

[0172] In the above scenario, the first position of the first matrix can correspond to P first translation values, each corresponding to a boosted cyclic shift matrix. The translation values ​​corresponding to the second positions of the P submatrices out of the W submatrices each correspond to one of the P first translation values. The translation values ​​corresponding to the second positions of the submatrices other than the P submatrices out of the W submatrices are second translation values, each corresponding to a boosted all-zero matrix. In other words, the P first translation values ​​corresponding to the first position of the first matrix are distributed among the P submatrices of the W submatrices, and the second positions of the remaining submatrices are the second translation values. The relationship between P and W can be found above and will not be repeated here.

[0173] Optionally, a non-zero element at a certain position in the first matrix may not be split, but instead copied to the corresponding position in each of the W submatrices. The corresponding positions in the W submatrices will have the same element as that position, meaning the corresponding positions in the W submatrices will also have non-zero elements. For example, if the fifth position of the first matrix is ​​a non-zero element, this fifth position corresponds to the sixth position in each of the W submatrices, and the sixth position in each of the W submatrices will also have a non-zero element. It should be understood that the first matrix may include one or more of the aforementioned fifth positions, meaning that one or more non-zero elements in the first matrix may not be split. It should also be understood that the first matrix may not include the fifth position.

[0174] In the above case, the translation value corresponding to the fifth position of the first matrix is ​​the same as the translation value corresponding to the sixth position of each of the W submatrices.

[0175] For example, a zero element at a certain position in the first matrix will also have zero elements at the corresponding positions in the W submatrices. This can be understood as either the zero element in the first matrix remaining zero when split across the W submatrices, or it can be understood as the zero element in the first matrix not being split, but rather copied to the corresponding positions in the W submatrices. For instance, if the third position of the first matrix is ​​zero, this third position corresponds to the fourth position in each of the W submatrices, and the fourth position in each of the W submatrices is also zero. It should be understood that the first matrix can include one or more of the aforementioned third positions; that is, one or more zero elements of the first matrix can be copied to the corresponding positions in the W submatrices or not split at all.

[0176] In the above case, the translation value corresponding to the third position of the first matrix is ​​the same as the translation value corresponding to the fourth position of each of the W submatrices, which is the second translation value. The second translation value corresponds to the lifted all-zero matrix.

[0177] The embodiments of this application do not limit the values ​​of the first translation value and the second translation value. For example, the second translation value is -1 and the first translation value is a non-negative value. Or, the second translation value is a special symbol and the first translation value is a numerical value.

[0178] In some other implementations of this application, the row weight of the j-th row of the first submatrix among the W submatrixes is no less than the row weight of the j-th row of each of the other W submatrixes, where j is a non-negative integer. That is, the row weight of each row of the first submatrix among the W submatrixes is no less than the row weight of the corresponding row of each of the other W submatrixes. In other words, the first submatrix among the W submatrixes has the largest row weight.

[0179] In embodiments of this application, a portion or all of the region of the first matrix can be split. The aforementioned one or more first positions are located within the split region of the first matrix. The aforementioned one or more third positions are located within the split region of the first matrix. The aforementioned one or more fifth positions are located within the unsplit region of the first matrix. For example, each of the W submatrices includes a first region, and the first matrix includes a second region of the same size as the first region. The first region of each of the W submatrices is determined based on the second region. The second region of the first matrix includes the aforementioned one or more first positions, a portion or all of the aforementioned one or more third positions, and a portion or all of the aforementioned one or more fifth positions (if the first matrix includes a fifth position). In other words, there exists a second region in the first matrix, and the splitting of the first matrix into the W submatrices all occurs within the second region. Elements in the second region can be all split, or some elements can remain unsplit. It should be understood that the size of the second region can be equal to or smaller than the size of the first matrix. For example, the number of columns in the second region is the same as the number of columns in the first matrix, but the number of rows in the second region is different from the number of rows in the first matrix. Or, the number of columns in the second region is the same as the number of columns in the first matrix, and the number of rows in the second region is the same as the number of rows in the first matrix. Or, the number of columns in the second region is different from the number of columns in the first matrix, and the number of rows in the second region is different from the number of rows in the first matrix.

[0180] Optionally, each of the W submatrices may further include a third region, which is not obtained by splitting the first matrix. The embodiments of this application do not limit the method for determining the elements of the third region and the corresponding translation values. In some implementations, the elements and corresponding translation values ​​of the third region of each of the W submatrices can be obtained through independent calculation or search. In other implementations, the elements and corresponding translation values ​​of the third region of each of the W submatrices can be obtained based on the fourth region of the first matrix, where the fourth region is the region other than the second region of the first matrix, and the elements and corresponding translation values ​​of the third region of each of the W submatrices are the same as the elements and translation values ​​at corresponding positions in the fourth region. For example, the third region of each of the W submatrices can be obtained by equally dividing the fourth region of the first matrix. That is, part or all of the aforementioned one or more fifth positions are located in the fourth region of the first matrix. It should be understood that when the second region does not include the fifth positions, all of the aforementioned one or more fifth positions are located in the fourth region of the first matrix; when the second region includes the fifth positions, all the remaining fifth positions are located in the fourth region of the first matrix.

[0181] The following uses the LDPC basis matrix in method 1100 as m. sThe following is a detailed description of the SC-LDPC basis matrix with a value of 1, the W submatrices obtained by splitting the first matrix, and the first matrix being a one-sided matrix.

[0182] m of the SC-LDPC basis matrix s =1, meaning the SC-LDPC basis matrix consists of submatrices B0 and B1, where B0 and B1 have the same dimension, denoted as m×n. The first matrix is ​​denoted as matrix B, with dimension m. B ×n B .

[0183] First, define the overlapping region, which can correspond to the first region and / or the second region mentioned above. The size of the overlapping region is denoted as m. overlap ×n, matrix splitting is performed on the overlapping parts. The non-overlapping parts of B0 and B1 have the same values ​​at the corresponding positions as B. The number of rows in the overlapping part is m. overlap The value m satisfies overlap ≤m B , and (m B -m overlap ) mod 2 = 0, where mod represents the modulo operation. Thus, the number of rows in B0 and B1... Number of columns n = n B .

[0184] If m overlap =m B If B0 and B1 are equal in size to B, then B0 and B1 are obtained by splitting the whole B, as shown in Case 1 of Figure 12, where the shaded part represents the overlapping part.

[0185] If m overlap <m B Then the overlapping portion of B0 and B1 corresponds to the middle part of B. Specifically, the front of B0... line and the front of B The rows are the same, and the remaining rows are obtained by splitting B; the rest of B1 After B If the rows are equal, the remaining rows are obtained by splitting B, as shown in case 2 of Figure 12.

[0186] The splitting is performed on the overlapping portion. The portion of B, B0, and B1 located in the overlapping region is denoted as B0. D B 0D and B 1D And define Γ as the number of elements that are not split. For the splitting process, B D There are Γ elements with 1s that are not split (their positions belong to the fifth position mentioned above). The remaining elements with 1s (their positions belong to the first position mentioned above) are split into B elements, one 0 and one 1 respectively. 0D and B 1D In the middle, B DThe 0 element (located in the third position mentioned above) in B 0D and B 1D The middle element is 0.

[0187] The above example assumes that the number of columns in the overlapping portion is the same as that of B, B0, and B1. However, the number of columns in the overlapping portion can also be different from that of B, B0, and B1, as shown in cases 3 and 4 of Figure 13. The following explanation will continue to use the example of the number of columns in the overlapping portion being the same as that of B, B0, and B1.

[0188] In the following text, the set of positions in the overlapping region that do not belong to the unsplit elements is called the "split region", which means that all elements in the split region must be split.

[0189] From the perspective of the splitting results, B D B 0D and B 1D Satisfy: B 0D ∨B 1D =B D

[0190] Here, ∨ represents the first operation (such as the "OR" operation) performed on the elements of the matrix, and the first operation between elements satisfies:

[0191] The number of occurrences of 1∨1=1 is Γ.

[0192] For the QC-LDPC matrix, the splitting is performed at the granularity of the base matrix to ensure that the resulting matrix is ​​still a QC matrix. For the positions where splitting has occurred (i.e., excluding the Γ elements with a translation value of -1 and those that are not split and have a translation value of not -1), the expansion form of the parity check matrix is ​​shown in Figure 14. That is, after splitting and expanding the elements at these positions, we get a matrix that is the same as the matrix after expanding the elements before splitting and a matrix of all zeros.

[0193] Figure 15 is an example of how B0 and B1 are derived from B. In this example, m overlap =m B Γ = 0, meaning that all elements in B are split. It should be noted that the blank squares in the diagram represent a translation value of -1; the meaning of blank squares in the following text is the same and will not be explained further.

[0194] Figure 16 is another example of obtaining B0 and B1 from B. In this example, m overlap =1, Γ=1, meaning the overlapping part consists of 1 row, and there exists an element in that row with a shift value other than -1 that is not split. It can be seen that, due to m overlap=1, the first row of B0 is the same as the first row of B, and the third row (last row) of B1 is the same as the third row (last row) of B. The split occurs in the second row, and one element in the second row (the element with a value of 11) is not split, and is located in both B0 and B1. The elements in the remaining positions are split into B0 and B1.

[0195] Compared to existing technologies, it is necessary to (m) s +1)×m rows, (m s A matrix search is performed in a dimension of (+1)×n columns. Embodiments of this application either only require searching in m... B row, n B Perform a matrix search within the column dimensions, or simply based on the designed m. B row, n B The matrix of columns yields the required SC-LDPC matrix, reducing the difficulty of matrix design and facilitating the representation of the SC-LDPC basis matrix based on the uncoupled LDPC basis matrix.

[0196] The above example illustrates how B0 and B1 are derived from B using a one-sided matrix B. The following example further illustrates how some or all elements of matrix B can be two-sided.

[0197] For two-sided elements that have been split, the process can be performed such that one edge corresponds to one split matrix. In this way, B0 and B1 are both single-sided elements at that position. The expanded form of the parity matrix for the split two-sided elements and B0 and B1 at that position is shown in Figure 17. That is, after splitting and expanding the two-sided elements at these positions, two single-sided elements are obtained. One of the two elements corresponds to one edge of the two-sided element, and the other of the two elements corresponds to the other edge of the two-sided element.

[0198] Figure 18 is another example of obtaining B0 and B1 from B. In this example, m overlap =m B Γ = 0, which means splitting all elements in B. In Figure 18, each element of B is a two-sided structure.

[0199] Figure 19 is another example of obtaining B0 and B1 from B. In this example, m overlap =m B Γ = 0, meaning all elements in B are split. In Figure 19, the elements in B are bilateral. The splitting method for unilateral elements is described above.

[0200] In other implementations of this application, the first matrix may include multiple sub-regions, and different sub-regions may define different overlapping portions. Correspondingly, the second region of the first matrix may also be composed of multiple sub-regions. Accordingly, the first region of W sub-matrices may also include multiple sub-regions.

[0201] For example, the W submatrices and the first matrix can adopt a raptor-like structure. A description of the raptor-like structure can be found in the terminology explanation section and will not be repeated here. Each of the W submatrices includes a first core portion, a first all-zero portion, a first extended portion below the first core portion, and a second extended portion below the first all-zero portion. The first region can include a first sub-region, a second sub-region, and a third sub-region. The first sub-region belongs to the first core portion, the second sub-region belongs to the first extended portion, and the third sub-region belongs to the second extended portion. The sizes of the first, second, and third sub-regions can be the same or different, without limitation. The first matrix includes a second core portion, a second all-zero portion, a third extended portion below the second core portion, and a fourth extended portion below the second all-zero portion. The second region of the first matrix can include a fourth, fifth, and sixth sub-region. The fourth sub-region belongs to the second core portion, the fifth sub-region belongs to the third extended portion, and the sixth sub-region belongs to the fourth extended portion. The sizes of the fourth, fifth, and sixth sub-regions can be the same or different, without limitation. Since the W submatrices and the first matrix can adopt a raptor-like structure, variable rate can be supported. The LDPC basis matrix determined by this also supports variable rate, thus enabling flexible code rate coding.

[0202] Using the LDPC basis matrix in method 1100 as m s The SC-LDPC basis matrix with a value of 1, the W submatrices, and the first matrix can adopt a raptor-like structure. Taking the first matrix as a one-sided matrix as an example, m is defined similarly. overlap And Γ, for the core part of B, the extended part below the core part (Rex1), and the extended part below the all-zero matrix (Rex2), m can be defined respectively. overlap and Γ, that is, m overlap Let Γ be a 1×3 vector. For example, m overlap When Γ = [4,5,5] and Γ = [2,7,3], it means that the middle 4 rows of the core part are split and there are 2 positions that are not -1 and are not split; the middle 5 rows of Rex1 are split and there are 7 positions that are not -1 and are not split; and the middle 5 rows of Rex2 are split and there are 3 positions that are not -1 and are not split.

[0203] Figure 20 shows an example of a first matrix and W sub-matrices containing multiple sub-regions. Here, B is the first matrix, and B0 and B1 are the W sub-matrices. B, B0, and B1 adopt a raptor-like structure.

[0204] In some implementations, the second extension of the first submatrix among the W submatrixes is a lower triangular matrix.

[0205] Figure 21 is an example of a split that supports variable rates. As shown, B, B0, and B1 adopt a raptor-like structure, and the extension below the all-zero matrix of B0 is a diagonal matrix.

[0206] It should be understood that when the W submatrices and the first matrix can adopt a raptor-like structure, the elements in the first matrix can be either single-sided or multi-sided, without restriction. For example, when m s When = 1, the elements in the first matrix can be bilateral. For details on unilateral and multilateral splitting, please refer to the above text, which will not be elaborated further.

[0207] Figure 22 is an example of how B is derived from B0 to B3. In this example, m overlap =m B Γ=0, which means splitting all elements in B. B and B0 to B3 satisfy B0∨B1∨B2∨B3=B. In Figure 22, each element of B is a single edge.

[0208] The embodiments of this application do not limit the way the elements in the first matrix are split.

[0209] In some implementations, the way the elements in the first matrix are split is predefined or protocol-defined.

[0210] In other implementations, the W submatrices are determined based on first information and a first matrix, where the first information indicates how each element in the first matrix is ​​split. The first information can be pre-stored in the encoding and / or decoding devices, or it can be determined through signaling interaction between the encoding and decoding devices, without limitation.

[0211] The embodiments of this application do not limit the form in which the first information takes. For example, the first information may take any of the following forms: matrix, list, or sequence.

[0212] Taking the first information in matrix form as an example, let's denote this matrix as T. The dimension of T is the same as the dimension of the first matrix. The value of each element in T represents the way the element at the same position in the first matrix can be split. The number of splitting methods depends on the number of edges and W of the elements in the first matrix. We can iterate through all the splitting methods, assign a number to each method, and use that number as the value of an element in T. For example, suppose there are C splitting methods. The values ​​of the elements in T are 0, 1, ..., C-1, or a special character, where a special character indicates no splitting. If no splitting is considered a splitting method, the values ​​of the elements in T are 0, 1, ..., or C-1.

[0213] For example, if the first matrix is ​​a one-sided matrix and m s If the value is 1, then "0" can be used to indicate splitting into B0, and "1" can be used to indicate splitting into B1. Alternatively, a "special character" (such as "A") can be used to indicate no splitting, which means that the element at that position will be included in both B0 and B1.

[0214] For example, if it is a two-sided matrix and m s If the value is 1, then "0" indicates that the first offset value is split into B0 and the second offset value is split into B1, and "1" indicates that the first offset value is split into B1 and the second offset value is split into B0. Optionally, a "special character" (such as "A") can be used to indicate that the element at that position is not split, which means that the element at that position will be included in both B0 and B1.

[0215] Taking the split shown in Figure 15 as an example, T can be as shown in Figure 23. Here, "0" represents splitting into B0, and "1" represents splitting into B1.

[0216] For m s When the value of T is 1 and the elements in T are either 0 or 1, since B0 usually has a larger row weight than B1, "1" represents splitting into B0 and "0" represents splitting into B1. This results in fewer "1"s in matrix T compared to "0", making T more likely to be a sparse matrix. In this case, a sparse matrix storage method can be used, storing only the positions of elements 1 to further reduce storage overhead.

[0217] In this application, if the LDPC basis matrix A or the translation value matrix D corresponding to the LDPC basis matrix A can be obtained by performing a first transformation on the LDPC basis matrix or the translation value matrix corresponding to the LDPC basis matrix provided in the embodiments of this application, then the LDPC basis matrix A or the translation value matrix D can be considered to be included within the protection scope of this application. The first transformation includes at least one of the following operations: row permutation, column permutation, or translation value transformation. Row permutation may include permuting one or more rows. Column permutation may include permuting one or more columns. Translation value transformation may include simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more rows in the basis matrix, and / or simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more columns in the basis matrix.

[0218] In other words, the LDPC basis matrix A can be obtained from the LDPC basis matrix provided in the embodiments of this application through a first transformation, the translation value matrix D can be obtained from the translation value matrix corresponding to the LDPC basis matrix provided in the embodiments of this application through a first transformation, and the parity check matrix corresponding to the LDPC basis matrix A can be obtained from the parity check matrix corresponding to the LDPC basis matrix provided in the embodiments of this application through a first transformation. Therefore, "encoding information according to the LDPC basis matrix and outputting the encoded information" can be replaced with "encoding information according to the LDPC basis matrix A and outputting the encoded information," and / or, "decoding the information to be decoded according to the LDPC basis matrix to obtain the decoded information" can be replaced with "decoding the information to be decoded according to the LDPC basis matrix A to obtain the decoded information."

[0219] Row permutations of the LDPC base matrix, its corresponding shifted value matrix, and its corresponding parity check matrix are equivalent to swapping the order of the parity check equations, without changing the required parity check relations. Column permutations or shifted value transformations of the LDPC base matrix, its corresponding shifted value matrix, and its corresponding parity check matrix are equivalent to swapping the order of the encoded bits, which can be considered as reordering the encoded result. During decoding, restoring the order first yields the same effect as the matrix before the column transformation. Therefore, the LDPC base matrix A obtained by the first transformation can be considered equivalent to the LDPC base matrix provided in the embodiments of this application, the shifted value matrix D obtained by the first transformation can be considered equivalent to the shifted value matrix corresponding to the LDPC base matrix provided in the embodiments of this application, and the parity check matrix obtained by the first transformation can be considered equivalent to the parity check matrix corresponding to the LDPC base matrix provided in the embodiments of this application.

[0220] In other words, the LDPC base matrix or the translation value matrix corresponding to the LDPC base matrix provided in the embodiments of this application can be modified to its equivalent or equivalent form. Compared with the LDPC base matrix or the translation value matrix corresponding to the LDPC base matrix provided in the embodiments of this application, the equivalent or equivalent LDPC base matrix or the translation value matrix corresponding to the LDPC base matrix provided in the embodiments of this application has a different arrangement order, and / or a different column arrangement order, and / or the translation values ​​of one or more rows are shifted, and / or the translation values ​​of one or more columns are shifted.

[0221] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 23. The device embodiments of this application will be described below with reference to Figures 24 to 26.

[0222] It is understood that, in order to achieve the functions in the above embodiments, the devices in Figures 24 to 26 include hardware structures and / or software modules corresponding to perform each function. These devices can be used to implement the functions of the encoding or decoding devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0223] Figure 24 is a schematic diagram of a device provided in an embodiment of this application.

[0224] This application embodiment can divide the encoding or decoding device into functional units according to the above method examples. For example, each function can be divided into different functional units, or two or more functions can be integrated into one unit. Each function can be implemented in hardware or as a software functional module. It should be noted that the division shown in Figure 24 is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0225] As shown in Figure 24, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0226] When device 10 is used to implement the function of the encoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the encoding device, such as step 1103, and processing unit 12 is used to execute the processing steps 1101 and 1102 of the encoding device. When device 10 is used to implement the function of the decoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the decoding device, such as step 1103, and processing unit 12 is used to execute the processing steps of the decoding device, such as step 1104.

[0227] Optionally, the device 10 also includes a storage unit 13 for storing instructions and / or data.

[0228] For a more detailed description of the transceiver unit 11 and the processing unit 12, please refer to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0229] Figure 25 is another structural schematic diagram of the device provided in an embodiment of this application.

[0230] The device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, which stores instructions. When the device 20 is used to implement the method described above, the processing circuit 21 executes the instructions in the memory 23 to implement the function of the processing unit 12 described above.

[0231] Optionally, the device 20 further includes a memory 23 for implementing the functions of the aforementioned memory unit 13.

[0232] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 can be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 executes instructions to implement the function of the processing unit 12, and the transceiver circuit 22 implements the function of the transceiver unit 11.

[0233] Optionally, device 20 can be an encoding device or a decoding device, and correspondingly, the transceiver circuit can be a transceiver.

[0234] Optionally, the device 20 can be a chip used in encoding or decoding equipment, and correspondingly, the transceiver circuit can be an input / output interface.

[0235] For example, when device 20 is a chip applied to an encoding or decoding device, the chip implements the functions of the encoding or decoding device in the above method embodiments. The chip receives information from other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to the encoding or decoding device by other devices; or, the chip sends information to other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to other devices by the encoding or decoding device.

[0236] Figure 26 is a schematic diagram of a chip system provided in an embodiment of this application. The chip system 30 (or may also be called a processing system) includes logic circuitry 31 and an input / output interface 32.

[0237] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 30 to implement the methods and functions of the embodiments of this application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting processed information from the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0238] As an alternative, the chip system 30 may also include a memory unit.

[0239] As one approach, the chip system 30 is used to implement the operations performed by the encoding or decoding device in the various method embodiments described above.

[0240] For example, logic circuit 31 is used to implement processing-related operations performed by the encoding or decoding device in the above method embodiments; input / output interface 32 is used to implement sending and / or receiving-related operations performed by the encoding or decoding device in the above method embodiments.

[0241] This application also provides a communication device including a processing circuit coupled to a memory for storing computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or to read the data stored in the memory, to perform the methods in the above-described method embodiments. Optionally, the processing circuit may be one or more. Optionally, the communication device includes a memory. Optionally, the memory may be one or more. Optionally, the memory may be integrated with the processing circuit, or may be separately disposed.

[0242] This application also provides a chip including a processing circuit coupled to a memory. The memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the encoding or decoding device in the above-described method embodiments. The memory may be located within the chip or independently of the chip, located outside the chip; this is not limited thereto.

[0243] This application also provides a computer-readable storage medium having stored thereon computer instructions for implementing the methods executed by an encoding device or a decoding device in the above-described method embodiments.

[0244] This application also provides a computer program product comprising instructions which, when executed by a computer, implement the methods performed by an encoding or decoding device in the above-described method embodiments.

[0245] This application also provides a computer program that, when executed by a computer, implements the methods performed by the encoding or decoding device in the above-described method embodiments.

[0246] This application also provides a communication system that includes at least one of the encoding or decoding devices described in the above embodiments.

[0247] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0248] It is understood that the processing circuit in the embodiments of this application may be a processor or a circuit in a processor for performing processing operations. The processor may include one or more of the following: a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0249] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored in non-volatile memory, such as the aforementioned memory 23 or at least a portion of the storage cells (e.g., one or more of ROM, flash memory, EPROM, or hard disk).

[0250] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Furthermore, the ASIC can reside in an encoding or decoding device. Alternatively, the processor and storage medium can exist as discrete components in the encoding or decoding device.

[0251] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive.

[0252] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0253] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

Claims

1. An information processing method, characterized in that, The method includes: Obtain the information to be encoded; The information is encoded using a low-density parity-check (LDPC) basis matrix with M rows and N columns, and the encoded information is output. The LDPC basis matrix includes multiple sub-matrix groups, and each n columns of the N columns of the LDPC basis matrix corresponds to a sub-matrix group. Each sub-matrix group includes W sub-matrices. The W sub-matrices are of the same size and are non-zero matrices. The row numbers of the first row of the first sub-matrix of each of the multiple sub-matrix groups are different. The W sub-matrices are determined based on the first matrix. M, N, and n are positive integers, and W is an integer greater than 1.

2. The method according to claim 1, characterized in that, The first position of the first matrix is ​​a non-zero element, which corresponds to the second position of the submatrix. The second positions of P submatrices out of the W submatrices are non-zero elements, and the second positions of the submatrices other than the P submatrices out of the W submatrices are zero elements, where P is a positive integer less than W; and / or, The third position of the first matrix is ​​a zero element, and the third position corresponds to the fourth position of the sub-matrix. The fourth position of each of the W sub-matrixes is a zero element. And / or, The fifth position of the first matrix is ​​a non-zero element, and the fifth position corresponds to the sixth position of the submatrix. The sixth position of each of the W submatrixes is a non-zero element.

3. The method according to claim 2, characterized in that, The first position of the first matrix corresponds to P first translation values, each corresponding to a boosted cyclic shift matrix. The translation values ​​corresponding to the second positions of the P sub-matrices correspond one-to-one with the P first translation values. The translation values ​​corresponding to the second positions of the W sub-matrices other than the P sub-matrices are second translation values, each corresponding to a boosted all-zero matrix. P is a positive integer; and / or, The translation value corresponding to the fifth position of the first matrix is ​​the same as the translation value corresponding to the sixth position of each of the W sub-matrices.

4. The method according to any one of claims 1 to 3, characterized in that, Each of the W submatrices includes a first region, the first matrix includes a second region, the second region being the same size as the first region, and the first region being determined based on the second region.

5. The method according to claim 4, characterized in that, Each of the W submatrices further includes a third region, and the first matrix further includes a fourth region, which is the region other than the second region of the first matrix. The values ​​of the elements in the third region are the same as the values ​​of the corresponding elements in the fourth region.

6. The method according to any one of claims 1 to 5, characterized in that, Each of the W submatrices includes a first core portion, a first all-zero portion, a first extended portion below the first core portion, and a second extended portion below the first all-zero portion. The second extended portion of the first submatrix of the W submatrices is a lower triangular matrix.

7. The method according to claim 6, characterized in that, The first region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region belongs to the first core part, the second sub-region belongs to the first extended part, and the third sub-region belongs to the second extended part.

8. The method according to any one of claims 1 to 7, characterized in that, The row weight of the j-th row of the first submatrix among the W submatrixes is not less than the row weight of the j-th row of the submatrixes other than the first submatrix among the W submatrixes, where j is a non-negative integer.

9. The method according to any one of claims 1 to 8, characterized in that, The W submatrices are determined based on the first information and the first matrix, wherein the first information is used to indicate the splitting method of each element in the first matrix.

10. The method according to any one of claims 1 to 9, characterized in that, In the N columns of the LDPC basis matrix, each n column contains zero elements except for the W submatrices.

11. An information processing method, characterized in that, The method includes: Obtain the information to be decoded; The information is decoded using a low-density parity-check (LDPC) basis matrix with M rows and N columns to obtain the decoded information. The LDPC basis matrix includes multiple sub-matrix groups, with each n columns of the N columns of the LDPC basis matrix corresponding to a sub-matrix group. Each sub-matrix group includes W sub-matrices, which are all of the same size and are non-zero matrices. The row numbers of the first row of the first sub-matrix of each of the multiple sub-matrix groups are different. The W sub-matrices are determined based on the first matrix, where M, N, and n are positive integers, and W is an integer greater than 1.

12. The method according to claim 11, characterized in that, The first position of the first matrix is ​​a non-zero element, which corresponds to the second position of the submatrix. The second positions of P submatrices out of the W submatrices are non-zero elements, and the second positions of the submatrices other than the P submatrices out of the W submatrices are zero elements, where P is a positive integer less than W; and / or, The third position of the first matrix is ​​a zero element, and the third position corresponds to the fourth position of the sub-matrix. The fourth position of each of the W sub-matrixes is a zero element. And / or, The fifth position of the first matrix is ​​a non-zero element, and the fifth position corresponds to the sixth position of the submatrix. The sixth position of each of the W submatrixes is a non-zero element.

13. The method according to claim 12, characterized in that, The first position of the first matrix corresponds to P first translation values, each corresponding to a boosted cyclic shift matrix. The translation values ​​corresponding to the second positions of the P sub-matrices correspond one-to-one with the P first translation values. The translation values ​​corresponding to the second positions of the W sub-matrices other than the P sub-matrices are second translation values, each corresponding to a boosted all-zero matrix. P is a positive integer; and / or, The translation value corresponding to the fifth position of the first matrix is ​​the same as the translation value corresponding to the sixth position of each of the W sub-matrices.

14. The method according to any one of claims 11 to 13, characterized in that, Each of the W submatrices includes a first region, the first matrix includes a second region, the second region being the same size as the first region, and the first region being determined based on the second region.

15. The method according to claim 14, characterized in that, Each of the W submatrices further includes a third region, and the first matrix further includes a fourth region, which is the region other than the second region of the first matrix. The values ​​of the elements in the third region are the same as the values ​​of the corresponding elements in the fourth region.

16. The method according to any one of claims 11 to 15, characterized in that, Each of the W submatrices includes a first core portion, a first all-zero portion, a first extended portion below the first core portion, and a second extended portion below the first all-zero portion. The second extended portion of the first submatrix of the W submatrices is a lower triangular matrix.

17. The method according to claim 16, characterized in that, The first region includes a first sub-region, a second sub-region, and a third sub-region. The first sub-region belongs to the first core part, the second sub-region belongs to the first extended part, and the third sub-region belongs to the second extended part.

18. The method according to any one of claims 11 to 17, characterized in that, The row weight of the j-th row of the first submatrix among the W submatrixes is not less than the row weight of the j-th row of the submatrixes other than the first submatrix among the W submatrixes, where j is a non-negative integer.

19. The method according to any one of claims 11 to 18, characterized in that, The W submatrices are determined based on the first information and the first matrix, wherein the first information is used to indicate the splitting method of each element in the first matrix.

20. The method according to any one of claims 11 to 19, characterized in that, In the N columns of the LDPC basis matrix, each n column contains zero elements except for the W submatrices.

21. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1 to 20.

22. A communication device, characterized in that, The device includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, and the processor is used to implement the method as described in any one of claims 1 to 20 through logic circuits or execution code instructions.

23. The communication device according to claim 22, characterized in that, The communication device is a terminal device, network device, chip, or chip system.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1 to 20.

25. A computer program product, characterized in that, Includes a computer program that, when run, implements the method as described in any one of claims 1 to 20.

26. A communication system, characterized in that, include: An encoding device for performing the method as described in any one of claims 1 to 10, and a decoding device for performing the method as described in any one of claims 11 to 20.

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