LDPC-based encoding method and LDPC-based decoding method

Abstract

Provided in the present application are an LDPC-based encoding method and an LDPC-based decoding method. In the encoding / decoding method, a plurality of intervals may be obtained by means of performing division on the basis of lengths of information bits, and each of the plurality of intervals may be associated with one lifting size and one group of information columns of a base matrix, an encoding apparatus may determine a target lifting size and a target information column on the basis of the lengths of information bits to be encoded; or, a decoding apparatus may determine the target lifting size and the target information column on the basis of the lengths of information bits to be decoded, so as to construct a check matrix for encoding or decoding. By means of the encoding method and the decoding method provided in the embodiments of the present application, a lifting size can be flexibly selected, thereby ensuring that hardware resources are fully utilized.

Description

An LDPC-based encoding and decoding method

[0001] This application claims priority to Chinese Patent Application No. 202411718756.X, filed on November 26, 2024, entitled "An Encoding and Decoding Method Based on LDPC", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to an LDPC-based coding and decoding method. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0004] Currently, the base graphs (BGs) of QC-LDPC codes described in the standard include BG1 and BG2. The parity-check matrix of QC-LDPC can be formed based on the base graph of the QC-LDPC code and the lifting size. The larger the lifting size, the higher the decoding parallelism. To support the maximum decoding parallelism, hardware resources are configured to run at the maximum possible parallelism. However, during rate matching, the lifting size is determined according to the information length. For example, a larger lifting size is used when the information length is long, and a smaller lifting size is used when the information length is short, resulting in low utilization of hardware resources. Summary of the Invention

[0005] This application provides an LDPC-based encoding and decoding method to improve the utilization of hardware resources.

[0006] Firstly, an LDPC-based encoding method is provided, which can be executed by an encoding device or a module applied to the encoding device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the encoding device). The method may include: the encoding device determining a first interval among multiple intervals based on the length of the information bits to be encoded, the first interval being associated with a first boost value and a first set of information columns, the multiple intervals being intervals relating to the length of the information bits, the first boost value being used to boost elements in a first base matrix into a matrix; the encoding device obtaining a first parity check matrix based on the first base matrix and the first boost value; and the encoding device performing LDPC encoding on the information bits to be encoded based on the first parity check matrix and the first set of information columns to obtain an encoded sequence.

[0007] The above encoding method allows for flexible selection of boost values ​​based on the length of the information bits to be encoded, thus ensuring full utilization of hardware resources.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the above method further includes: the encoding device determines the first boost value and the first set of information columns based on a first rule, a boost value set, and an information column set, wherein the first rule is a rule corresponding to a first interval, the boost value set includes N boost values, the information column set includes the number of columns of M sets of information columns of the first base matrix, the first boost value belongs to the N boost values, and the first set of information columns belongs to the M sets of information columns, where M and N are positive integers.

[0009] Specifically, each of the aforementioned intervals corresponds to one rule. For example, the rules corresponding to each of the aforementioned intervals may be all the same, partially the same, or all different; this application does not impose any limitations on this.

[0010] For example, the aforementioned set of promotion values ​​and the aforementioned set of information columns may be predefined.

[0011] Using the above encoding method, a target boost value can be selected from a predefined set of boost values, and a target information column can be selected from a predefined set of information columns. This not only achieves rate matching but also ensures the encoding performance of the selected target boost value and target information column.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the first rule is as follows: the first boost value is one of the N boost values ​​that satisfies the first condition, and the first set of information columns is determined based on the length of the information bits to be encoded and the determined first boost value.

[0013] Specifically, the first condition mentioned above can be any of the following:

[0014] The first indicator belongs to the aforementioned set of information columns; or, the first indicator is greater than or equal to the smallest element in the aforementioned set of information columns; or, the first indicator is less than or equal to the largest element in the aforementioned set of information columns.

[0015] Among them, the first indicator mentioned above is or Any item in Z, ceil() represents rounding up, floor() represents rounding down, Z i Let be the i-th boost value among the above N boost values, where 1 ≤ i ≤ N, and K is the length of the information bits to be encoded.

[0016] The above method first determines the target boost value and then determines the target information column, which increases the selection space for the target boost value, thereby prioritizing the utilization of hardware resources.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the first boost value is one of the N boost values ​​that satisfies the first condition, including: the first boost value is the largest boost value among the N boost values ​​that satisfies the first condition.

[0018] The above method determines the target improvement value as the maximum improvement value among the improvement values ​​that meet certain conditions, which can maximize the utilization of hardware resources.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, if at least two of the aforementioned N improvement values ​​correspond to the same first indicator, the aforementioned first improvement value is the minimum improvement value among the at least two improvement values.

[0020] For example, in the first indicator is or When any one of the following is true, there may be at least two improvement values ​​that correspond to the same first indicator.

[0021] The above method determines the minimum boost value among multiple boost values ​​with the same first index as the target boost value, which can reduce the number of shortened bits, reduce the code distance between the encoded codeword and the mother code, and make the encoding performance more stable.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, if the minimum endpoint value of the first interval is greater than or equal to the first threshold, the first rule is: the first boost value is the largest element in the set of boost values, and the first set of information columns is determined based on the length of the information bits to be encoded and the determined first boost value; if the maximum endpoint value of the first interval is less than or equal to the first threshold, the first rule is: the first set of information columns is a set of information columns corresponding to the smallest element in the set of information columns, and the first boost value is determined based on the length of the information bits to be encoded and the determined first set of information columns.

[0023] For example, the first threshold is the product of the largest element in the set of boost values ​​and the smallest element in the set of information columns.

[0024] The above method can be used to design different methods for determining the target boost value and target information column for information bits of different lengths. For example, for longer information bits, the largest boost value in the boost value set can be selected as the target boost value, thereby maximizing the utilization of hardware resources; for shorter information bits, the set of information columns with the fewest columns in the information column set can be selected as the target information column, thereby maximizing the boost value and improving the utilization of hardware resources to some extent.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, each of the aforementioned intervals is associated with a boost value and / or a set of information columns associated with the first base matrix.

[0026] For example, a boost value associated with each of the multiple intervals and / or a set of information columns of the associated first base matrix can be stored on the encoding device side.

[0027] The above method can directly store the boost value and / or information column associated with each segment interval, and the check matrix can be constructed by direct query without calculation, which can simplify the processing complexity of the encoding device.

[0028] In conjunction with the first aspect, in some implementations of the first aspect, each of the aforementioned multiple intervals is associated with a boost value, and the first set of information columns can be determined based on the length of the information bits to be encoded and the first boost value associated with the first interval; or, each of the aforementioned multiple intervals is associated with a set of information columns of the first base matrix, and the first boost value can be determined based on the length of the information bits to be encoded and the first set of information columns associated with the first interval.

[0029] The above method can store the boost value or information column associated with each segment interval, and determine the information column associated with each segment interval based on the stored boost value associated with each segment interval, or determine the boost value associated with each segment interval based on the stored information column associated with each segment interval, thereby saving storage resources.

[0030] In conjunction with the first aspect, in some implementations of the first aspect, the endpoint values ​​of the aforementioned multiple intervals are determined based on elements in the information column set and elements in the promotion value set.

[0031] For example, the endpoint values ​​of the above intervals are: kb i ×Z max Among them, Z maxkb is the largest element in the aforementioned set of boost values. i Let i be the i-th element in the above information column set, where i takes values ​​from 1 to M.

[0032] The above method allows the maximum boost value in the boost value set to be used as the target boost value, regardless of which interval the length of the information bit to be encoded falls into, thereby maximizing the utilization of hardware resources.

[0033] Alternatively, the length of the information bits corresponding to each of the above intervals satisfies: kb j ×Z i-1 ≤K i ≤kb j ×Z i+1 , where K i Z is the length of the information bits of the i-th interval among the above multiple intervals. i-1 Z is the boost value associated with the (i-1)th interval among the above intervals. i+1 kb is the boost value associated with the (i+1)th interval among the above intervals. j For the j-th element in the above information column set, j takes values ​​from 1 to N, or kb j The smallest element in the above set of information columns, or kb j It is the smallest or second smallest element in the above set of information columns.

[0034] The above method can minimize the number of columns of information associated with each segment interval, thereby allowing the selection of a larger improvement value as the target improvement value, which can improve the utilization rate of hardware resources to a certain extent.

[0035] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned set of information columns is {5,6,7,8,9,10} or a subset of {5,6,7,8,9,10}.

[0036] The set of information columns included in the above method indicates a set of information columns that are information columns of the base matrix supported by existing protocols, thereby making the technical solution of this application compatible with current encoding schemes.

[0037] Secondly, an LDPC-based decoding method is provided, which can be executed by a decoding device or a module applied to the decoding device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the decoding device). The method may include: the decoding device acquiring a sequence to be decoded; the decoding device determining the length of the information bits corresponding to the sequence to be decoded; the decoding device determining a first interval among multiple intervals based on the length of the information bits corresponding to the sequence to be decoded, the first interval being associated with a first boost value and a first set of information columns, the multiple intervals being intervals relating to the length of the information bits, the first boost value being used to boost the elements in a first base matrix to a matrix; the decoding device acquiring a first parity check matrix based on the first base matrix and the first boost value; and the decoding device performing LDPC decoding on the sequence to be decoded based on the first parity check matrix and the first set of information columns to obtain a decoded sequence.

[0038] The above decoding method allows for flexible selection of boost values ​​based on the length of the information bits corresponding to the sequence to be decoded, thereby ensuring full utilization of hardware resources.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the above method further includes: the decoding device determines the first boost value and the first set of information columns based on a first rule, a boost value set, and an information column set. The first rule is the rule corresponding to the first interval. The boost value set includes N boost values. The information column set includes the number of columns of the M sets of information columns of the first base matrix. The first boost value belongs to the N boost values, and the first set of information columns belongs to the M sets of information columns, where M and N are positive integers.

[0040] Specifically, each of the aforementioned intervals corresponds to one rule. For example, the rules corresponding to each of the aforementioned intervals may be all the same, partially the same, or all different; this application does not impose any limitations on this.

[0041] For example, the aforementioned set of promotion values ​​and the aforementioned set of information columns may be predefined.

[0042] The above decoding method allows for the selection of target boost values ​​from a predefined boost value set and target information columns from a predefined information column set, ensuring the decoding performance of the selected target boost values ​​and target information columns.

[0043] In conjunction with the second aspect, in some implementations of the second aspect, the first rule mentioned above is: the first boost value is one of the N boost values ​​that satisfies the first condition, and the first set of information columns is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first boost value.

[0044] Specifically, the first condition mentioned above can be any of the following:

[0045] The first indicator belongs to the aforementioned set of information columns; or, the first indicator is greater than or equal to the smallest element in the aforementioned set of information columns; or, the first indicator is less than or equal to the largest element in the aforementioned set of information columns.

[0046] Among them, the first indicator mentioned above is or Any item in Z, ceil() represents rounding up, floor() represents rounding down, Z i Let be the i-th boost value among the above N boost values, 1≤i≤N, and K be the length of the information bits corresponding to the sequence to be decoded.

[0047] The above method first determines the target boost value and then determines the target information column, which increases the selection space for the target boost value, thereby prioritizing the utilization of hardware resources.

[0048] In conjunction with the second aspect, in some implementations of the second aspect, the first boost value is one of the N boost values ​​that satisfies the first condition, including: the first boost value is the largest boost value among the N boost values ​​that satisfies the first condition.

[0049] The above method determines the target boost value as the maximum boost value among boost values ​​that meet certain conditions, which can maximize the utilization of hardware resources and increase the parallelism of decoding.

[0050] In conjunction with the second aspect, in some implementations of the second aspect, if at least two of the above N improvement values ​​correspond to the same first indicator, the above first improvement value is the minimum improvement value among the at least two improvement values.

[0051] For example, in the first indicator is or When any one of the following is true, there may be at least two improvement values ​​that correspond to the same first indicator.

[0052] The above method determines the minimum boost value among multiple boost values ​​with the same first index as the target boost value, which can reduce the number of shortened bits and make the decoding performance more stable.

[0053] In conjunction with the second aspect, in some implementations of the second aspect, if the minimum endpoint value of the first interval is greater than or equal to the first threshold, the first rule is: the first boost value is the largest element in the set of boost values, and the first set of information columns is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first boost value; if the maximum endpoint value of the first interval is less than or equal to the first threshold, the first rule is: the first set of information columns is a set of information columns corresponding to the smallest element in the set of information columns, and the first boost value is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first set of information columns.

[0054] For example, the first threshold is the product of the largest element in the set of boost values ​​and the smallest element in the set of information columns.

[0055] The above method can design different methods for determining the target boost value and target information column for information bits of different lengths. For example, for longer information bits, the largest boost value in the boost value set can be selected as the target boost value, thereby maximizing the utilization of hardware resources; for shorter information bits, the set of information columns with the fewest columns in the information column set can be selected as the target information column, thereby maximizing the boost value as possible, which can improve the utilization of hardware resources and increase the parallelism of decoding to a certain extent.

[0056] In conjunction with the second aspect, in some implementations of the second aspect, each of the aforementioned intervals is associated with a boost value and / or a set of information columns associated with the first base matrix.

[0057] For example, a boost value associated with each of the multiple intervals and / or a set of information columns of the associated first basis matrix can be stored on the decoding device side.

[0058] The above method can directly store the boost value and / or information column associated with each segment interval, and the check matrix can be constructed by direct query without calculation, which can simplify the processing complexity of the decoding device.

[0059] In conjunction with the second aspect, in some implementations of the second aspect, each of the above-mentioned multiple intervals is associated with a boost value, and the first set of information columns can be determined based on the length of the information bits corresponding to the above-mentioned sequence to be decoded and the first boost value associated with the first interval; or, each of the above-mentioned multiple intervals is associated with a set of information columns of the first base matrix, and the first boost value can be determined based on the length of the information bits corresponding to the above-mentioned sequence to be decoded and the first set of information columns associated with the first interval.

[0060] The above method can store the boost value or information column associated with each segment interval, and determine the information column associated with each segment interval based on the stored boost value associated with each segment interval, or determine the boost value associated with each segment interval based on the stored information column associated with each segment interval, thereby saving storage resources.

[0061] In conjunction with the second aspect, in some implementations of the second aspect, the endpoint values ​​of the aforementioned multiple intervals are determined based on elements in the information column set and elements in the promotion value set.

[0062] For example, the endpoint values ​​of the above intervals are: kb i ×Z max Among them, Z max kb is the largest element in the aforementioned set of boost values. i Let i be the i-th element in the above information column set, where i takes values ​​from 1 to M.

[0063] The above method allows the maximum boost value in the boost value set to be used as the target boost value, regardless of which interval the length of the information bit to be decoded falls into, thereby maximizing the utilization of hardware resources and the parallelism of decoding.

[0064] Alternatively, the length of the information bits corresponding to each of the above intervals satisfies: kb j ×Z i-1 ≤K i ≤kb j ×Z i+1 , where K i Z is the length of the information bits of the i-th interval among the above multiple intervals. i-1 Z is the boost value associated with the (i-1)th interval among the above intervals. i+1 kb is the boost value associated with the (i+1)th interval among the above intervals. j For the j-th element in the above information column set, j takes values ​​from 1 to N, or kb j The smallest element in the above set of information columns, or kb j It is the smallest or second smallest element in the above set of information columns.

[0065] The above method can minimize the number of columns of information associated with each segment interval, thereby allowing the selection of a larger improvement value as the target improvement value. This can improve the utilization of hardware resources and increase the parallelism of decoding to a certain extent.

[0066] In conjunction with the second aspect, in some implementations of the second aspect, the aforementioned information column set is {5,6,7,8,9,10} or a subset of {5,6,7,8,9,10}.

[0067] The set of information columns included in the above method indicates a set of information columns that are information columns of the basis matrix supported by existing protocols, thereby making the technical solution of this application compatible with current decoding schemes.

[0068] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0069] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0070] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0071] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0072] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0073] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0074] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0075] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0076] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0077] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0078] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0079] Figure 5 is a schematic diagram of the information transmission process.

[0080] Figure 6 is a schematic flowchart of a communication method 600 provided in this application.

[0081] Figure 7 is a performance simulation diagram provided in the embodiment of this application.

[0082] Figure 8 is a schematic structural diagram of the communication device 1000 provided in this application.

[0083] Figure 9 is a schematic structural diagram of another communication device 1100 provided in this application.

[0084] Figure 10 is a schematic structural diagram of the chip provided in this application. Detailed Implementation

[0085] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0086] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction of A or an indirect instruction of A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements. The various numerical designations such as "first," "second," etc., are only for descriptive convenience and are not used to limit the scope of the embodiments of this application, such as distinguishing different messages, different information, different parameters, different ranges, etc. "Predefined" can be achieved by pre-saving corresponding codes, tables, or other methods that can be used to instruct relevant information in the device; this application does not limit its specific implementation. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words “exemplary,” “for example,” and “an example” are used to indicate that something is an example, illustration, or description. Any embodiment or design described as an “example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms “comprising,” “including,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized. “At least one” means one or more, and “more than one” means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. “At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Where a, b, and c can be single or multiple. Descriptions relating to device A sending messages, information, or data to device B, and device B receiving messages, information, or data from device A, aim to specify which device the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other devices. Descriptions such as "when," "under," "if," and "if" indicate that the device will take appropriate action under certain objective circumstances, not a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0087] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0088] The following describes a communication system to which embodiments of this application can be applied.

[0089] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0090] A communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices. Exemplarily, the transmitting device may be an encoding device, and the receiving device may be a decoding device.

[0091] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the encoding device is the terminal device and the decoding device is the network device; conversely, in downlink data transmission, the encoding device is the network device and the decoding device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0092] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0093] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, or equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies, without limitation.

[0094] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0095] For example, some embodiments in this document use a 5G system as an example to illustrate specific solution details. When this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0096] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0097] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0098] 1. LDPC code

[0099] LDPC codes are a type of linear block code. A linear block code divides the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, a decoding device decodes the received signal to determine the original information bits.

[0100] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0101] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0102] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0103] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0104] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0105] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of the cycle is defined as the number of edges it contains, while the perimeter of the graph is defined as the minimum cycle length. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in a Tanner graph, a cycle is a closed loop formed by connecting variable nodes, check nodes, and edges end-to-end.

[0106] 2. QC-LDPC code

[0107] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented by BG, where elements are either 0 or 1. Expanding the 1s and 0s in BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, BG can be written in matrix form, referred to as the base matrix H in this application. BG Basis matrix H BG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The following section discusses the base matrix H. BGThe expansion process is described.

[0108] Based on the basis matrix H BG And the lifting size Z, can be used to transform the basis matrix H BG The matrix is ​​expanded into a complete parity-check matrix for encoding or decoding. In this application, Z can also be referred to as the expansion factor, boosting factor, expansion value, expansion coefficient, boosting size, etc. The expansion process involves boosting all elements of the base matrix into a Z×Z square matrix, where 0 is boosted to a Z×Z 0 matrix, and 1 is boosted to an identity matrix and cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, and this application does not limit this. It can be understood that each 1 in the base matrix corresponds to a shifting value. For example, boosting 1 to a 4×4 identity matrix with shifting values ​​of 0, 1, 2, and 3, and cyclically shifting to the right, is illustrated below:

[0109] (1) When the translation value is 0 (i.e., remains unchanged), the matrix after right circular shift is:

[0110] (2) When the translation value is 1, the matrix after the right circular shift is:

[0111] (3) When the translation value is 2, the matrix after the right circular shift is:

[0112] (4) When the translation value is 3, the matrix after the right circular shift is:

[0113] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Z×Z submatrix, and each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0114] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0115] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Z. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... bIn this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0116] For example, As shown below:

[0117] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0118] It is understandable that the above exponent matrix H... b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0119] 3. Lifting size (Z) and shifting value (Z)

[0120] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0121] For example, the list of promotion values ​​is shown in Table 1.

[0122] Table 1

[0123] The j-th row of the boost value list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; The row indices of the lift value list correspond one-to-one with the column indices of the shift value list, that is, the lift size in each row of the lift value list corresponds to a set of shift values.

[0124] For example, the list of translation values ​​is shown in Table 2.

[0125] Table 2

[0126] For an index of a set of lift values, the basis matrix H BG A non-zero position corresponds to one translation value. For example, the basis matrix H... BG The translation value corresponding to the 0th row and 0th column of the matrix H when the lifting index is 0 is 211. BGThe translation value corresponding to the 6th column of the 1st row in the matrix H is 66 when the lifting index is 3. BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0127] It's understandable that during LDPC encoding, the lift value is first determined, and then the corresponding shift value is determined based on the selected lift value to construct the parity check matrix. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0128] 4. Column weight and row weight

[0129] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0130] 5. Structure of the parity check matrix

[0131] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0132] As shown in Figure 4(a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or a parity with a degree greater than or equal to 2, or a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0133] The parity-check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 4(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0134] The parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0135] 6. Information column and validation column

[0136] The columns of the LDPC base matrix consist of information columns and check columns.

[0137] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0138] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0139] 7. Message length, code length, and code rate

[0140] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0141] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0142] Bitrate refers to the ratio of information length to bit length.

[0143] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0144] 8. Information Transmission Process

[0145] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the coding device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the decoding device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0146] To facilitate understanding of the embodiments of this application, the existing rate matching process is briefly described. It mainly includes the following steps:

[0147] (1) Based on the given target code length, code rate, and communication scenario, determine the required base matrix and boost value Z.

[0148] For example, the required base matrix can be determined based on the target code length, code rate, and scenario.

[0149] For example, the boost value Z can be determined from the boost value list above based on the information length and the total number of information columns Kb of the base matrix. The determined boost value Z satisfies the following conditions: the product of the boost value Z and the total number of information columns Kb of the base matrix is ​​greater than the information length, and the boost value Z is the smallest boost value in the boost value set that satisfies the condition.

[0150] (2) Determine the information bit sequence c based on the base matrix and the determined lifting value Z, where the length of the information bit sequence c is K, K = Kb × Z, where Kb is the number of all information columns corresponding to the base matrix.

[0151] Specifically, if the base matrix is ​​BG1, then K = 22 × Z; if the base matrix is ​​BG2, then K = 10 × Z.

[0152] It can be understood that each column in the information column of the base matrix corresponds to Z consecutive bits in the information bit sequence c.

[0153] It can also be understood that the length of the information bit sequence c is not equal to the information length.

[0154] (3) Punch holes in the information bit sequence c according to the punch column of the basis matrix to obtain sequence #1.

[0155] As can be seen from the above, the punched columns of the basis matrix can be the first two columns. Therefore, the punched positions (or punched bits) corresponding to the information bit sequence c are the first 2 × Z bits of the information bit sequence c.

[0156] It can be understood that the bit sequence d to be sent consists of two parts: one part is sequence #1, and the other part is bit #2 determined in step (4). Sequence #1 is the part of the bit sequence d to be sent that is related to the information bits, and bit #2 determined in step (4) is the part of the bit sequence d to be sent that is related to the check bits.

[0157] The pseudocode for determining sequence #1 from the information bit sequence c in the current protocol is shown below:

[0158] Among them, c k =Null means that this position is a shortened bit, with a default sign, such as 0 by default. In other words, the pseudocode means: if c k Not equal to Null, c k The value assigned to d k-2*Zc If c k Equals null, assign 0 to c k And assign Null to d k-2*Zc In the pseudocode, Zc is the boost value Z determined in step (1) above.

[0159] (4) Encode according to the base matrix and sequence c to obtain sequence #2, which is the part of the bit sequence d to be sent that is related to the check bit.

[0160] The parity bits are w = [w0, ..., wN + 2 * Zc - K - 1] T The encoding process is solving equations. The process of obtaining w involves writing w into the sequence d in order, where H is the parity check matrix.

[0161] (5) Based on sequence #1 and sequence #2, the bit sequence to be sent is obtained as d.

[0162] It can be seen that the boost value determined in the current rate matching process is based on the information length and the complete information column of the basis matrix, resulting in a relatively small boost value. However, to support maximum decoding parallelism, hardware resources are configured to run at the maximum possible parallelism. A small boost value cannot meet the requirements of high decoding parallelism and will lead to low utilization of hardware resources. In view of this, this application proposes an LDPC-based encoding and decoding method, which can effectively solve the above-mentioned technical problems.

[0163] Figure 6 is a schematic flowchart of a method 600 provided in this application. The method includes the following steps.

[0164] It is understood that method 600 can be executed by an encoding device and a decoding device. Unless otherwise specified, "encoding device" or "decoding device" can refer to the encoding device or decoding device itself, or it can refer to a device that enables the encoding device or decoding device to perform this function. For ease of description, the terms "encoding device" and "decoding device" will be used uniformly below. Among them, the encoding device can be a terminal device or a network device, and the decoding device can be a terminal device or a network device.

[0165] S610, the encoding device acquires the information bits to be encoded.

[0166] For example, the information bits to be encoded can be a sequence of information bits to be transmitted. The sequence of information bits to be transmitted can be payload information bits, or payload information bits with CRC bits added. This application does not impose any specific restrictions.

[0167] S612, the encoding device determines a first interval among a plurality of intervals based on the length of the information bits to be encoded, the first interval being associated with a first boost value and a first set of information columns.

[0168] For example, the length of the information bits to be encoded can be the aforementioned information length.

[0169] Specifically, the aforementioned intervals are intervals relating to the length of information bits. For example, these intervals can be divided according to the length of the information bits, and can be denoted as (a1, a2], (a2, a3], (a3, a4], ..., (a... ... k-1 ,a k ], where a1, a2, a3, a4, ..., a k-1 a k These are the endpoint values ​​of the multiple intervals. This application describes an embodiment using the example of the first interval whose length of the information bits to be encoded falls within the multiple intervals. This first interval can be any one of the multiple intervals, and this application does not limit it.

[0170] For example, each of the above intervals can correspond to a rule, and the first boost value and the first set of information columns associated with the first interval can be obtained through the first rule corresponding to the first interval.

[0171] For example, the rules corresponding to each of the above intervals can be the same or different, and this application does not limit this.

[0172] For example, the encoding device can determine the first lift value and the first set of information columns associated with the first interval based on the first rule, the lift value set, and the information column set.

[0173] Specifically, the aforementioned boosting value set includes N boosting values. For example, the boosting value set may include all boosting values ​​in the boosting value list shown in Table 1 above; or, the boosting value set may include the maximum boosting value in each row of the boosting value list shown in Table 1 above, where each row of boosting values ​​in Table 1 corresponds to the same boosting value set index or the same boosting value identifier (ID), for example, the boosting value set is {256,384,320,224,288,352,208,240}; or, the boosting value set may include the maximum and second-largest boosting values ​​in each row of the boosting value list shown in Table 1 above, for example, the boosting value set is {256,128,384,192,320,160,224,112,288,144,352,176,208,104,240,120}; or, the boosting value set may include values ​​greater than or equal to Z. max All the boost values ​​of / 2, the Z max The Z value is the maximum boost value in the boost value list shown in Table 1 above. For example, the boost value set is {256,384,192,320,224,288,352,208,240}. max The value is 384, and this Z... max It can also be other values, such as Z. max It could also be 768 (384*2), and correspondingly, Z max Each element in the set of boost values ​​when the value is 768 can be obtained from Z. max It is obtained by multiplying the corresponding element in the set of promotion values ​​when the value is 384 by 2, for example, Z. max When the value is 768, the set of promotion values ​​is {256*2,384*2,192*2,320*2,224*2,288*2,352*2,208*2,240*2}. This application does not limit the specific elements included in the set of promotion values.

[0174] Specifically, the aforementioned information column set includes the number of columns of the M groups of information columns of the first base matrix. That is, the information column set includes M elements, each element being the number of columns of a group of information columns, and each element can indicate a group of information columns. Specifically, the encoding device determines the required base matrix to be used as the first base matrix based on the given target code length, code rate, and communication scenario. The elements included in the information column set are the number of columns of information columns supported by the first base matrix. For example, the first base matrix is ​​BG2, and the information column set is {5,6,7,8,9,10} or a subset of {5,6,7,8,9,10}, such as {6,7,8,9,10}, {6,7,8,9}, {6,8,9,10}, or {6,8,10}, etc.

[0175] For example, if the information column set is {6,8,9,10}, the information column set includes the number of columns of the four sets of information columns of BG2. The first element "6" in the information column set indicates a set of information columns that are columns 1 to 6 of BG2 or any 6 columns of BG2. The second element "8" in the information column set indicates a set of information columns that are columns 1 to 8 of BG2 or any 8 columns of BG2. The third element "9" in the information column set indicates a set of information columns that are columns 1 to 9 of BG2 or any 9 columns of BG2. The fourth element "10" in the information column set indicates a set of information columns that are columns 1 to 10 of BG2 or any 10 columns of BG2. This application does not limit this.

[0176] For example, the elements included in the information column set can be integers with intervals of 1 within a certain range, such as the information column sets {5,6,7,8,9,10}, {6,7,8,9,10}, and {6,7,8,9} shown above; or, for example, the elements in the information column set can be integers with intervals of 2 within a certain range, such as the information column set {6,8,10} shown above. For example, the maximum element and the minimum element in the information column set can also satisfy a certain relationship, for example, the maximum element in the information column set is 3 / 2 × the minimum element, such as the information column set {6,7,8,9} shown above; or, for example, the maximum element in the information column set can be 2 × the minimum element, such as the information column set {5,6,7,8,9,10} shown above.

[0177] In one example, the first rule mentioned above can be: the first boost value is one of the N boost values ​​that satisfies the first condition, and the first set of information columns is determined based on the length of the information bits to be encoded and the determined first boost value.

[0178] For example, the first condition is any one of the following:

[0179] The first indicator belongs to the set of information columns; or, the first indicator is greater than or equal to the smallest element in the set of information columns; or, the first indicator is less than or equal to the largest element in the set of information columns.

[0180] Among them, the first indicator mentioned above is or Any item in Z, ceil() represents rounding up, floor() represents rounding down, Z i Let be the i-th lift value among N lift values, where 1 ≤ i ≤ N, and K is the length of the information bits to be encoded.

[0181] For example, Z iValues ​​can be selected from the N lift values ​​in the aforementioned lift value set, or from a subset of the aforementioned lift value set. Values ​​for Z can be pre-selected from the information column set. i The subset of values ​​is not limited in this application.

[0182] With K=2000, the set of boost values ​​is {256,384,320,224,288,352,208,240}, the set of information columns is {6,7,8,9}, and the first indicator is... The first condition is that the first indicator belongs to the information column set. For example: After calculation, the first indicator of the first boost value "256" in the boost value set is 8. 8 belongs to the information column set, therefore the first boost value "256" in the boost value set satisfies the first condition. The first indicator of the second boost value "384" in the boost value set is 6. 6 belongs to the information column set, therefore the second boost value "384" in the boost value set satisfies the first condition. The first indicator of the third boost value "320" in the boost value set is 7. 7 belongs to the information column set, therefore the third boost value "320" in the boost value set satisfies the first condition. The first indicator of the fourth boost value "224" in the boost value set is 9. 9 belongs to the information column set, therefore the fourth boost value "224" in the boost value set satisfies the first condition. 224” satisfies the first condition; the first indicator of the 5th boost value “288” in the boost value set is 7, and 7 does not belong to the information column set, therefore the 5th boost value “288” in the boost value set satisfies the first condition; the first indicator of the 6th boost value “352” in the boost value set is 6, and 6 belongs to the information column set, therefore the 6th boost value “352” in the boost value set satisfies the first condition; the first indicator of the 7th boost value “208” in the boost value set is 10, and 10 does not belong to the information column set, therefore the 7th boost value “208” in the boost value set does not satisfy the first condition; the first indicator of the 8th boost value “240” in the boost value set is 9, and 9 belongs to the information column set, therefore the 8th boost value “240” in the boost value set satisfies the first condition.

[0183] As can be seen from the examples above, the promotion values ​​that satisfy the first condition are 384, 352, 320, 288, 256, 240, and 224. One way is to determine any one of the promotion values ​​that satisfy the first condition as the first promotion value. For example, the first promotion value can be any value among 384, 352, 320, 288, 256, 240, and 224. Another way is to determine the first promotion value as the largest promotion value among the above N promotion values ​​that satisfy the first condition. For example, the largest promotion value among the promotion values ​​that satisfy the first condition, "384", can be determined as the first promotion value.

[0184] For example, among the N lift values ​​mentioned above, at least two lift values ​​may correspond to the same first indicator. For instance, in the example above, the first indicator corresponding to lift values ​​"384" and "352" is 6. If it is necessary to select one lift value from these two lift values ​​as the first lift value, the first lift value can be determined as the smallest lift value among the two. For example, the lift value "352" from the lift values ​​"384" and "352" with the same first indicator can be determined as the first lift value. As another example, in the example above, the first indicator corresponding to lift values ​​"320" and "288" is 7. If it is necessary to select one lift value from these two lift values ​​as the first lift value, the first lift value can be determined as the smallest lift value among the two. For example, the lift value "288" from the lift values ​​"320" and "288" with the same first indicator can be determined as the first lift value. For example, in the above example, the first indicator corresponding to the improvement value "240" and the improvement value "224" is 9. If it is necessary to select one of these two improvement values ​​as the first improvement value, the first improvement value can be determined as the smallest improvement value among the two improvement values. For example, the improvement value "224" can be determined as the first improvement value among the improvement values ​​"240" and "224" with the same first indicator.

[0185] Alternatively, the first indicator for each boost value can be calculated by ordering the elements in the boost value set from largest to smallest, and the first boost value that satisfies the first condition can be determined as the first boost value. Here, we still use K = 2000, the boost value set as {256, 384, 320, 224, 288, 352, 208, 240}, the information column set as {6, 7, 8, 9}, and the first indicator as... The first condition is that the first indicator belongs to the information column set. For example: First, calculate the first indicator of the largest increase value "384" in the increase value set. The first indicator is 6. 6 belongs to the information column set. Therefore, the largest increase value "384" in the increase value set satisfies the first condition, so the calculation can be stopped, and the first increase value "384" that satisfies the first condition is determined as the first increase value.

[0186] Specifically, the first boost value is first determined using the method shown in Example 1 above, and then the first set of information columns is determined based on the length of the information bits to be encoded and the determined first boost value.

[0187] For example, if the above first indicator is It can be done To determine the first set of information columns. The value should belong to the information column set, and the information column set should include the values ​​that are related to the information column set. The set of information columns indicated by elements with equal values ​​is determined as the first set of information columns. For example, if the aforementioned first indicator is... It can be done To determine the first set of information columns. The value should belong to the information column set, and the information column set should include the values ​​that are related to the information column set. The set of information columns indicated by elements with equal values ​​is determined as the first set of information columns.

[0188] In another example, if the minimum endpoint value of the first interval is greater than or equal to the first threshold, the first rule can be: the first boost value is the largest element in the set of boost values, and the first set of information columns is determined based on the length of the information bits to be encoded and the determined first boost value; if the maximum endpoint value of the first interval is less than or equal to the first threshold, the first rule can be: the first set of information columns is a set of information columns corresponding to the smallest element in the set of information columns, and the first boost value is determined based on the length of the information bits to be encoded and the determined first set of information columns.

[0189] To illustrate this, consider two intervals as two separate intervals: denote these two intervals as (a1, a2] and (a2, a3], where a1 < a2 < a3, and a1, a2, and a3 are the three endpoints of these two intervals.

[0190] If the length of the information bit to be encoded falls within the interval (a1, a2), it indicates that the length of the information bit to be encoded is relatively short. The first set of information columns can be determined as the set of information columns corresponding to the smallest element in the above set of information columns. Then, the first boost value can be determined based on the length of the information bit to be encoded and the determined first set of information columns.

[0191] Taking K=2000, the lift value set as {256,384,320,224,288,352,208,240}, and the information column set as {6,7,8,9} as an example: the first set of information columns corresponds to the smallest element "6" in the information column set, and the first lift value can be greater than or equal to a value in the lift value set. Minimum lift value, kb min It is the smallest element in the set of information columns. The value is 333, so the first promotion value can be "352" in the promotion set.

[0192] If the length of the information bit to be encoded falls within the interval (a2, a3), it indicates that the length of the information bit to be encoded is relatively long. The first lift value can be determined as the largest element in the lift value set, and then the first group of information columns can be determined based on the length of the information bit to be encoded and the determined first lift value.

[0193] Taking K=2000, the lift value set as {256,384,320,224,288,352,208,240}, and the information column set as {6,7,8,9} as an example: the first lift value set is the largest element in the lift value set, "384", and the first set of information columns can be the elements in the information column set that are equal to or greater than the maximum value in the lift value set. Z represents a set of information columns indicated by elements with equal values. max To promote the largest element in the set of values, The value is 6, so the first set of information columns can be the set of information columns indicated by the element "6" in the information column set.

[0194] For example, the first threshold mentioned above can be the product of the largest element in the set of boosted values ​​and the smallest element in the set of information columns. Taking the two intervals (a1, a2] and (a2, a3] as an example, the first threshold can be considered as a2, that is, the endpoint value a2 = kb. min *Z max If the boost value set is {256,384,320,224,288,352,208,240} and the information column set is {6,7,8,9}, then a2 = 2304. The first rule can be determined based on whether the length of the information bit to be encoded falls within the interval (a1,a2] or (a2,a3].

[0195] Using the method described in the other example above, when the length of the information bits to be encoded is long (greater than or equal to the first threshold), the maximum boost value can be used, thereby maximizing the utilization of hardware resources; when the length of the information bits to be encoded is short (less than or equal to the first threshold), although the maximum boost value cannot be achieved, using the maximum boost value as much as possible can improve the utilization of hardware resources.

[0196] Specifically, each of the aforementioned intervals can also be associated with a boost value and / or a set of information columns of the first base matrix, wherein the first interval is associated with a first boost value and / or a first set of information columns. The boost value and / or the set of information columns of the first base matrix associated with each of the aforementioned intervals can be stored. If the length of the information bit to be encoded falls within the first interval, the first boost value and the first set of information columns associated with the first interval are directly used for LDPC encoding or LDPC decoding.

[0197] For example, each of the aforementioned multiple intervals is associated with a boost value and / or a set of information columns of a first base matrix, including: each of the aforementioned multiple intervals is associated with a set of boost values ​​and / or a set of information columns, the boost value set associated with each interval includes a boost value, and the set of information columns associated with each interval includes the number of columns of the set of information columns of the first base matrix. For example, the aforementioned first rule can be: the first boost value is a boost value in the boost value set associated with the first interval, or the first boost value is determined based on the length of the information bits to be encoded and the first set of information columns, the first set of information columns is a set of information columns in the set of information columns associated with each interval, or the first set of information columns is determined based on the length of the information bits to be encoded and the first boost value.

[0198] The embodiments of this application do not limit each of the multiple intervals to being associated with only one lifting value and / or a set of information columns of the first basis matrix. Each of the multiple intervals may also be associated with at least one lifting value and / or at least one set of information columns of the first basis matrix.

[0199] In one example, each of the aforementioned intervals is associated with a boost value, and the first set of information columns can be determined based on the length of the information bits to be encoded and the first boost value associated with the first interval. For example, the first interval is associated with the first boost value, and the number of columns in the first set of information columns can be...

[0200] In another example, each of the aforementioned intervals is associated with a set of information columns of the first base matrix. The first boost value can be determined based on the length of the information bits to be encoded and the first set of information columns associated with the first interval. For example, the first boost value associated with the first set of information columns could be...

[0201] In another example, each of the above intervals is associated with a lifting value and a set of information columns of the first base matrix. The lifting value and the set of information columns of the first base matrix associated with the first interval are the first lifting value and the first set of information columns.

[0202] For example, the endpoint values ​​of the aforementioned multiple intervals can be determined based on N elements in the information column set and M elements in the lift value set. For instance, the endpoint values ​​of the aforementioned multiple intervals can be determined using the following two methods:

[0203] Method 1: The endpoint values ​​of multiple intervals are: kb i ×Z max Among them, Z max To promote the largest element in the set of values, kb i Let i be the i-th element in the information column set, where i takes values ​​from 1 to M.

[0204] For example, the above multiple intervals can be denoted as (a1, a2], (a2, a3], (a3, a4], ..., (a... k-1 ,a k ], where a1, a2, a3, a4, ..., a k-1 a k These are the endpoint values ​​of the multiple intervals. Here, we take the set of boost values ​​as {256,384,320,224,288,352,208,240} and the set of information columns as {6,7,8,9} to illustrate the endpoint values ​​of the multiple intervals: the endpoint values ​​of the multiple intervals are 6×384, 7×384, 8×384, and 9×384, that is, a1=2304, a2=2688, a3=3072, a4=3456, and the multiple intervals can be (2304,2688], (2688,3072], and (3072,3456).

[0205] Method 2: The length of the information bits corresponding to each of the multiple intervals satisfies: kb j ×Z i-1 ≤K i ≤kb j ×Z i+1 , where K i Z is the length of the information bits of the i-th interval among multiple intervals. i-1 Z is the boost value associated with the (i-1)th interval among multiple intervals. i+1 kb is the boost value associated with the (i+1)th interval among multiple intervals. j For the j-th element in the information column set, j takes values ​​from 1 to N, or kb j The smallest element in the set of information columns, or kb j It is the smallest or second smallest element in the set of information columns.

[0206] For example, the above multiple intervals can be denoted as (a1, a2], (a2, a3], (a3, a4], ..., (a... k-1 ,a k ], where a1, a2, a3, a4, ..., a k-1 a k These are the endpoint values ​​of these multiple intervals. Here, the set of boost values ​​is {256,384,320,224,288,352,208,240}, the set of information columns is {6,7,8,9}, and kb... jTo illustrate the endpoint values ​​of the i-th interval among multiple intervals, consider the j-th element in the information column set: Assume the lift value associated with the (i-1)-th interval is 240 and the lift value associated with the (i+1)-th interval is 384. Then, the length of the information bits in the i-th interval must be greater than or equal to the maximum value among 6×240, 7×240, 8×240, and 9×240, and the length of the information bits in the i-th interval must be less than or equal to the minimum value among 6×384, 7×384, 8×384, and 9×384. Therefore, the first interval can be defined as: 9×240 ≤ K. i ≤6×384, that is: 2160≤K i ≤2304. The method for determining the endpoint values ​​of each interval in multiple intervals can refer to the method for determining the endpoint values ​​of the i-th interval, and will not be repeated here.

[0207] S614, the encoding device obtains the first parity check matrix based on the first base matrix and the aforementioned first boost value.

[0208] For example, the encoding device can promote each element in the first base matrix to a square matrix of first promotion value × first promotion value, wherein 0 in the first base matrix is ​​promoted to a 0 matrix of first promotion value × first promotion value, 1 is promoted to an identity matrix of first promotion value × first promotion value, and the identity matrix is ​​cyclically shifted based on the translation value corresponding to 1, thereby obtaining the first parity check matrix.

[0209] S616, the encoding device performs LDPC encoding on the information bits to be encoded based on the first parity check matrix and the first set of information columns to obtain the encoded sequence.

[0210] One implementation is as follows: the encoding device can delete unused information columns in the first check matrix according to the first set of information columns, and the position of the deleted information columns is 0 during encoding, thus performing a shortening process.

[0211] Another implementation is that the encoding device can delete the unused information columns in the first check matrix according to the first set of information columns, and reassemble the remaining columns in the first check matrix into a new check matrix, and use the new check matrix for encoding.

[0212] For example, the encoding device can divide the information sequence to be encoded into groups of q bits each, and then the encoder performs linear operations on these q information bits to obtain m parity bits. These q information bits and m parity bits are then combined to obtain an encoded sequence of length n = q + m. The mapping relationship from q-bit information bits to n-bit codewords can be represented by the first parity check matrix or the new parity check matrix described above. Based on the first parity check matrix or the new parity check matrix, an encoded sequence can be generated accordingly to complete the encoding process.

[0213] In step S618, the encoding device sends the encoded sequence to the decoding device. Correspondingly, in step S620, the decoding device receives the sequence to be decoded from the encoding device.

[0214] Specifically, the decoding device can determine the length of the information bits corresponding to the received sequence to be decoded.

[0215] S622, the decoding device determines a first interval among multiple intervals based on the length of the information bits corresponding to the sequence to be decoded, the first interval being associated with a first boost value and a first set of information columns.

[0216] Specifically, the decoding device in step S622 determines the first interval among multiple intervals based on the length of the information bits corresponding to the sequence to be decoded, which can be referred to as the encoding device in step S612 above determining the first interval among multiple intervals based on the length of the information bits to be decoded, and will not be repeated here.

[0217] S624, the decoding device obtains the first parity check matrix based on the first base matrix and the first lift value.

[0218] Specifically, step S624 can refer to step S614 above, and will not be repeated here.

[0219] S626, the decoding device performs LDPC decoding on the sequence to be decoded based on the first parity check matrix and the first set of information columns to obtain the decoded sequence.

[0220] One implementation is as follows: the decoding device can delete unused information columns in the first parity check matrix according to the first set of information columns, and the position of the deleted information columns is 0 during decoding, thus performing a shortening process.

[0221] Another implementation is that the decoding device can delete the unused information columns in the first parity check matrix according to the first set of information columns, and reassemble the remaining columns in the first parity check matrix into a new parity check matrix, and use the new parity check matrix for decoding.

[0222] The LDPC-based encoding and decoding methods provided in the embodiments of this application can not only improve the utilization of hardware resources, but also achieve better decoding performance.

[0223] Figure 7 is a performance simulation diagram provided by an embodiment of this application. The horizontal axis of Figure 7 represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error rate (BLER). Figures 7(a) and (b) respectively show a comparison of the decoding performance using the existing BG2 and the decoding performance using the parity-check matrix obtained by the scheme of this application when the length of the information bits to be encoded is K = 1920 and the code rate is 1 / 2 and 1 / 5. In Figures 7(a) and (b), the upper performance curve represents the decoding performance using the existing BG2, and the lower performance curve represents the decoding performance using the parity-check matrix obtained by the scheme of this application. It can be seen from the figures that, at various code rates, the decoding performance using the parity-check matrix obtained by the scheme of this application is superior to the decoding performance using the existing BG2.

[0224] The communication device provided in this application is described below.

[0225] Figure 8 is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 can be an encoding-side device, or a device applied to the encoding-side device and capable of implementing the corresponding functions of the encoding-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 1000 can be a decoding-side device, or a device applied to the decoding-side device and capable of implementing the corresponding functions of the decoding-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0226] Optionally, the communication device 1000 includes a processing module 1001, which can be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the processing module 1001 is used to determine a first interval among multiple intervals based on the length of the information bits to be encoded, to obtain a first parity check matrix based on a first base matrix and a first boost value, and to perform LDPC encoding on the information bits to be encoded based on the first parity check matrix and a first set of information columns, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the processing module 1001 is used to determine a first interval among multiple intervals based on the length of the information bits to be decoded, to obtain a first parity check matrix based on a first base matrix and a first boost value, and to perform LDPC decoding on the information bits to be decoded based on the first parity check matrix and a first set of information columns, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0227] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the communication module 1002 can be used to acquire information bits to be encoded and transmit the information bits to be encoded to the processing module 1001; and output the encoded sequence obtained by the processing module 1001. Similarly, when the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the communication module 1002 can be used to receive an encoded sequence and send the encoded sequence to the processing module 1001; and output the decoded sequence obtained by the processing module 1001 after decoding the encoded sequence. Furthermore, the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through a software functional unit or a virtual device, and the communication module can be implemented through a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0228] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0229] Figure 9 is a schematic structural diagram of another communication device 1100 provided in this application. The communication device 1100 can be used to implement the functions of any communication device (e.g., a terminal device or a network device) in the communication system described in the foregoing examples. The communication device 1100 may include at least one processor 1110. Optionally, the processor 1110 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the corresponding functions of the encoding-side device or decoding-side device in any of the above embodiments.

[0230] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 1100 is a chip-type device or circuit, the communication interface 1130 in the device 1100 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0231] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0232] Figure 10 is a schematic structural diagram of the chip 30 provided in this application. The chip 30 includes a circuit 31 and a communication interface 32. The circuit 31 can be a logic circuit, an integrated circuit, etc., and the communication interface 32 can also be called an input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). The chip 30 can execute the methods executed by the encoding-side device or the decoding-side device in the various embodiments of this application.

[0233] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding-side device or a decoding-side device in the various method embodiments of this application to be executed.

[0234] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding-side device or decoding-side device in the various method embodiments of this application are executed.

[0235] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding-side device or a decoding-side device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0236] This application provides a communication system, including the encoding-side device and decoding-side device in the above method embodiments.

[0237] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0238] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly embodied in the execution of the hardware processor, or executed by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0239] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0240] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0241] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0242] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0243] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0244] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0245] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0246] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0247] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A coding method based on Low-Density Parity-Check Code (LDPC), characterized in that, include: Based on the length of the information bits to be encoded, a first interval is determined among multiple intervals. The first interval is associated with a first boosting value and a first set of information columns. The multiple intervals are intervals related to the length of the information bits. The first boosting value is used to boost the elements in the first base matrix into a matrix. The first verification matrix is ​​obtained based on the first base matrix and the first lift value; The information bits to be encoded are subjected to LDPC encoding based on the first parity check matrix and the first set of information columns to obtain an encoded sequence.

2. The method according to claim 1, characterized in that, The method further includes: Based on the first rule, the boost value set, and the information column set, the first boost value and the first group of information columns are determined. The first rule is the rule corresponding to the first interval. The boost value set includes N boost values. The information column set includes the number of columns in the M groups of information columns of the first base matrix. The first boost value belongs to the N boost values, and the first group of information columns belongs to the M groups of information columns. M and N are positive integers.

3. The method according to claim 2, characterized in that, The first rule is: the first boost value is one of the N boost values ​​that satisfies the first condition, and the first group of information columns is determined based on the length of the information bits to be encoded and the determined first boost value; The first condition is any one of the following: The first indicator belongs to the set of information columns; or... The first indicator is greater than or equal to the smallest element in the set of information columns; or, The first indicator is less than or equal to the largest element in the set of information columns; The first indicator is or Any item in Z, ceil() represents rounding up, floor() represents rounding down, Z i Let be the i-th boost value among the N boost values, 1≤i≤N, and K be the length of the information bits to be encoded.

4. The method according to claim 3, characterized in that, The first boost value is one of the N boost values ​​that satisfies the first condition, including: the first boost value is the largest boost value among the N boost values ​​that satisfies the first condition.

5. The method according to claim 3, characterized in that, If at least two of the N improvement values ​​correspond to the same first indicator, the first improvement value is the minimum improvement value among the at least two improvement values.

6. The method according to claim 2, characterized in that, If the minimum endpoint value of the first interval is greater than or equal to the first threshold, the first rule is: the first boost value is the largest element in the boost value set, and the first group of information columns is determined based on the length of the information bit to be encoded and the determined first boost value; If the maximum endpoint value of the first interval is less than or equal to the first threshold, the first rule is: the first set of information columns is a set of information columns corresponding to the smallest element in the set of information columns, and the first boost value is determined based on the length of the information bit to be encoded and the determined first set of information columns.

7. The method according to claim 6, characterized in that, The first threshold is the product of the largest element in the set of boost values ​​and the smallest element in the set of information columns.

8. The method according to any one of claims 1 to 7, characterized in that, Each of the plurality of intervals is associated with a boost value and / or with a set of information columns of the first base matrix.

9. The method according to claim 1 or 8, characterized in that, Each of the plurality of intervals is associated with a boost value, and the first set of information columns is determined based on the length of the information bits to be encoded and the first boost value associated with the first interval; or, Each of the plurality of intervals is associated with a set of information columns of the first base matrix, and the first boost value is determined based on the length of the information bit to be encoded and the first set of information columns associated with the first interval.

10. The method according to any one of claims 2 to 9, characterized in that, The endpoint values ​​of the multiple intervals are determined based on the elements in the information column set and the elements in the boost value set.

11. The method according to claim 10, characterized in that, The endpoint values ​​of the multiple intervals are determined based on elements in the information column set and elements in the boost value set, including: The endpoint values ​​of the multiple intervals are: kb i ×Z max Among them, Z max kb is the largest element in the set of boosted values. i Let i be the i-th element in the set of information columns, where i takes values ​​from 1 to M. or, The length of the information bits corresponding to each of the plurality of intervals satisfies: kb j ×Z i-1 ≤K i ≤kb j ×Z i+1 , where K i Z is the length of the information bits of the i-th interval among the plurality of intervals. i-1 Z is the boost value associated with the (i-1)th interval among the plurality of intervals. i+1 kb is the boost value associated with the (i+1)th interval among the plurality of intervals. j For the j-th element in the information column set, j takes values ​​from 1 to N, or kb j The smallest element in the set of information columns, or kb j It is the smallest or second smallest element in the set of information columns.

12. The method according to any one of claims 2 to 11, characterized in that, The information column set is {5,6,7,8,9,10} or a subset of {5,6,7,8,9,10}.

13. A decoding method based on low-density parity-check codes (LDPC), characterized in that, include: Obtain the sequence to be decoded and determine the length of the information bits corresponding to the sequence to be decoded; Based on the length of the information bits corresponding to the sequence to be decoded, a first interval is determined among multiple intervals. The first interval is associated with a first boost value and a first set of information columns. The multiple intervals are intervals related to the length of the information bits. The first boost value is used to boost the elements in the first base matrix into a matrix. The first verification matrix is ​​obtained based on the first base matrix and the first lift value; The sequence to be decoded is subjected to LDPC decoding based on the first parity check matrix and the first set of information columns to obtain the decoded sequence.

14. The method according to claim 13, characterized in that, The method further includes: Based on the first rule, the boost value set, and the information column set, the first boost value and the first group of information columns are determined. The first rule is the rule corresponding to the first interval. The boost value set includes N boost values. The information column set includes the number of columns in the M groups of information columns of the first base matrix. The first boost value belongs to the N boost values, and the first group of information columns belongs to the M groups of information columns. M and N are positive integers.

15. The method according to claim 14, characterized in that, The first rule is: the first boost value is one of the N boost values ​​that satisfies the first condition, and the first group of information columns is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first boost value; The first condition is any one of the following: The first indicator belongs to the set of information columns; or... The first indicator is greater than or equal to the smallest element in the set of information columns; or, The first indicator is less than or equal to the largest element in the set of information columns; The first indicator is or Any item in Z, ceil() represents rounding up, floor() represents rounding down, Z i Let be the i-th boost value among the N boost values, 1≤i≤N, and K be the length of the information bits corresponding to the sequence to be decoded.

16. The method according to claim 15, characterized in that, The first boost value is one of the N boost values ​​that satisfies the first condition, including: the first boost value is the largest boost value among the N boost values ​​that satisfies the first condition.

17. The method according to claim 15, characterized in that, If at least two of the N improvement values ​​correspond to the same first indicator, the first improvement value is the minimum improvement value among the at least two improvement values.

18. The method according to claim 14, characterized in that, If the minimum endpoint value of the first interval is greater than or equal to the first threshold, the first rule is: the first boost value is the largest element in the boost value set, and the first group of information columns is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first boost value; If the maximum endpoint value of the first interval is less than or equal to the first threshold, the first rule is: the first set of information columns is a set of information columns corresponding to the smallest element in the set of information columns, and the first boost value is determined based on the length of the information bits corresponding to the sequence to be decoded and the determined first set of information columns.

19. The method according to claim 18, characterized in that, The first threshold is the product of the largest element in the set of boost values ​​and the smallest element in the set of information columns.

20. The method according to any one of claims 13 to 19, characterized in that, Each of the plurality of intervals is associated with a boost value and / or with a set of information columns of the first base matrix.

21. The method according to claim 13 or 20, characterized in that, Each of the plurality of intervals is associated with a boost value, and the first set of information columns is determined based on the length of the information bits corresponding to the sequence to be decoded and the first boost value associated with the first interval; or, Each of the plurality of intervals is associated with a set of information columns of the first base matrix, and the first boost value is determined based on the length of the information bits corresponding to the sequence to be decoded and the first set of information columns associated with the first interval.

22. The method according to any one of claims 14 to 21, characterized in that, The endpoint values ​​of the multiple intervals are determined based on the elements in the information column set and the elements in the boost value set.

23. The method according to claim 22, characterized in that, The endpoint values ​​of the multiple intervals are determined based on elements in the information column set and elements in the boost value set, including: The endpoint values ​​of the multiple intervals are: kb i ×Z max Among them, Z max kb is the largest element in the set of boosted values. i Let i be the i-th element in the set of information columns, where i takes values ​​from 1 to M. or, The length of the information bits corresponding to each of the plurality of intervals satisfies: kb j ×Z i-1 ≤K i ≤kb j ×Z i+1 , where K i Z is the length of the information bits of the i-th interval among the plurality of intervals. i-1 Z is the boost value associated with the (i-1)th interval among the plurality of intervals. i+1 kb is the boost value associated with the (i+1)th interval among the plurality of intervals. j For the j-th element in the information column set, j takes values ​​from 1 to N, or kb j The smallest element in the set of information columns, or kb j It is the smallest or second smallest element in the set of information columns.

24. The method according to any one of claims 14 to 23, characterized in that, The information column set is {5,6,7,8,9,10} or a subset of {5,6,7,8,9,10}.

25. A communication device, characterized in that, The system includes a communication interface and circuitry. The communication interface is used to acquire information required to perform the method as described in any one of claims 1-12, and to send the information to the circuitry, which is used to perform the method as described in any one of claims 1-12 based on the received information; or... The communication interface is used to acquire information required to perform the method as described in any one of claims 13-24, and to send the information to the circuit, which is used to perform the method as described in any one of claims 13-24 based on the received information.

26. A communication device, characterized in that, It includes at least one processor, said at least one processor being configured to execute a computer program or instructions to cause the communication device to perform the method as described in any one of claims 1-24.

27. The communication device according to claim 26, characterized in that, The communication device further includes a memory for storing the computer program or instructions.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-24.

29. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when the computer program or instructions are run on a computer, implement the method as described in any one of claims 1-24.

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