LDPC multi-bit quantization hardware decoding method suitable for high-speed communication

Abstract

The application discloses a kind of LDPC multi-bit quantization hardware decoding method suitable for high-speed communication, it is related to the field of communication physical layer digital signal transmission, including the steps 1) reset decoding module, from channel obtains the information sequence to be decoded and carries out suitable bit quantization extension;2) to meet the engineering demand of super high speed, low resource consumption, low latency, the application adopts a kind of full parallel decoding structure, the full parallel decoding structure can realize all check nodes update simultaneously and provide to all variable nodes.3) check node update is carried out by 6 parallel ways, the normalization factor used in the application check node update is obtained by adaptive mode;4) the check node information obtained in step 3 is as the input of variable node update module, variable node update is carried out by 6 parallel ways, the input in the application variable node update module is improved by expanding the number of bit quantization to improve the decoding ability of decoder.

Description

Technical Field

[0001] This invention relates to a hardware decoding method for LDPC multi-bit quantization suitable for high-speed communication in the field of digital signal transmission at the physical layer of communication. More specifically, it is a hardware channel decoding method that employs a fully parallel structure, improves decoding capability by modifying the normalization factor in the normalized minimum sum decoding algorithm and the multi-bit quantization method, and is suitable for high-speed digital signal communication in practical engineering. Background Technology

[0002] With the advent of the 5G and 6G era, high-speed communication has always been a hot research topic in the field of communications, particularly in modern digital signal transmission and storage systems. Due to the presence of noise in the communication transmission channel, errors in digital signal transmission are an unavoidable problem. Therefore, effectively improving the transmission reliability of high-speed digital signal transmission systems has become a crucial research area in communications. Channel coding and decoding technology is an important solution to the transmission reliability problem.

[0003] Shannon's channel coding theorem, a fundamental theorem for all communication transmission systems, proposes the maximum average information rate that a channel can transmit, also known as channel capacity. Researchers in the field of communication have dedicated themselves to increasing channel transmission rates to match channel capacity. Currently, LDPC, Turbo, and Polar codes theoretically approach the Shannon limit in performance. Compared to the other two coding methods, LDPC codes have lower decoding complexity, support parallel decoding, and are error-detectable. Most importantly, LDPC codes perform better with medium- to long codes. Therefore, LDPC codes have become one of the important channel coding schemes in high-speed communication systems.

[0004] LDPC decoding is crucial for improving the reliability of digital signal transmission. However, in practical communication engineering applications, decoding algorithms with excessive complexity often require significant logic resources in hardware implementation. Therefore, it is necessary to balance decoding performance with actual resource consumption. Normalized minimum sum decoding algorithms, which belong to belief propagation, have the characteristics of low decoding complexity and good decoding performance. Thus, this method is often used in practical engineering implementations for LDPC decoding schemes. Improving the selection of the normalization factor in the hardware decoding algorithm implementation and using multi-bit quantization decoding are feasible directions for effectively improving decoding capabilities. Summary of the Invention

[0005] This invention aims to reduce hardware resource consumption and improve the decoding capability of channel decoding modules in high-speed communication engineering hardware implementation. To achieve the above objectives, this invention adopts the following technical solution:

[0006] A hardware decoding method for LDPC multi-bit quantization suitable for high-speed communication includes the following steps:

[0007] (1) Reset the decoding module, obtain the message sequence of length len from the channel, perform k-bit quantization expansion, and store the quantization result in a register, denoted as message. q , awaiting input as variable node information for calculation; where k is 3;

[0008] (2) Initialize the decoding module; the decoding module includes a fully parallel check node update module, a fully parallel node information calculation and transmission module, a memory module, and a fully parallel variable node update module.

[0009] (3) Use the parity check coefficient matrix of the LDPC code to expand the quantization result obtained in step (1) into a message. q The variable node information v is calculated using a fully parallel structure. mess ;

[0010] (4) Transfer the variable node information v obtained in step (3) mess As input to the fully parallel check node update module, the check node is updated in a 6-way fully parallel manner to obtain the check node update value; wherein, the normalization factor used by the fully parallel check node update module is obtained in an adaptive manner.

[0011] (5) Based on the updated value of the verification node obtained in step (4), the verification node information c is calculated using a 6-way parallel method. mess ;

[0012] (6) Transfer the verification node information c obtained in step (5) mess The bit quantization bit is increased, and then used as input to the fully parallel variable node update module. The variable node is updated in a 6-way fully parallel manner, and the highest bit of the update result is used as the decoding decision value.

[0013] (7) Use the decoding decision value obtained in step (6) as the input to check whether the decoding was successful. If the verification result is an all-zero vector: that is, H·dout T =0 indicates successful decoding and the decoding process ends; otherwise, determine whether the maximum number of iterations has been reached. If the maximum number of iterations has not been reached, return to step (2). If the maximum number of iterations has been reached, declare that the decoding has failed and the decoding process ends.

[0014] Specifically, step (3) is as follows:

[0015] v mess [k*(row_i)-1:k*(row_i-1)]=

[0016] message q[(len*k-1)-(R i -1)*k:(len*k-1)-(R i -1)*k-(k-1)]

[0017] In this matrix, the parity check coefficient matrix H of the LDPC code has a dimension of m×n, with row weight 'row' and column weight 'col'; row_i = 1, 2, ..., row; R i This represents the index of the position of "1" in each row of H, where i = 1, 2, ..., row;

[0018] The entire computation is completed simultaneously in parallel. The information sequence to be decoded is obtained from the channel during the first iteration, and from the second iteration onwards, it is obtained from the output of the fully parallel variable node update module.

[0019] Specifically, step (4) involves: obtaining the variable node information v from step 3. mess As input to the check node update module, for each check node, a binary search method is used to obtain the maximum and second-largest values ​​(Max and SMax) of the variable node information connected to it. The check node update is performed in a 6-way parallel manner. The normalization factor used for the check node update is obtained adaptively. The update result is denoted as cnode, and all updated cnode information is used as the check node update value C. cnodes The calculation method for updating the result, denoted as cnode, is shown in the following formula:

[0020] cnode=Max-floor(Max / 2)+floor(Max / 4) or

[0021] cnode=SMax-floor(SMax / 2)+floor(SMax / 4)

[0022] Here, floor is the floor function.

[0023] Specifically, step (5) is as follows:

[0024] c mess [k*(col_i)-1:k*(col_i-1)]=

[0025] C cnodes [(len*k-1)-(Q i -1)*k:(len*k-1)-(Q i -1)*k-(k-1)]

[0026] in, Q i This represents the index of the "1" position in the parity check coefficient matrix H of the LDPC code.

[0027] Specifically, step (6) involves: verifying the node information c mess As input to the variable node update module, variable node updates are performed in a 6-way parallel manner. The decoding capability of the decoder is improved by increasing the number of bits in the bit quantization of the input to the variable node update module. The k-bit input is first mapped to K bits, denoted as c. messK Using C messK To update the variable node, the following formula gives the update method for the j-th variable node:

[0028]

[0029] Where p represents the index of the check node connected to variable node j, j = 1, 2, ..., len, the highest bit of the update result is used as the decoding decision value, that is, the decoding decision value dou[j] = v j [K]

[0030] The present invention has the following advantages due to the adoption of the above technical solutions:

[0031] 1. In order to meet the engineering requirements of ultra-high speed and low resource consumption in actual communication engineering, this invention adopts a fully parallel decoding structure and an adaptive normalization factor to optimize the LDPC hardware decoding algorithm in high-speed communication engineering. This makes the optimized LDPC channel decoding algorithm more robust, reduces hardware resource consumption and improves decoding performance in actual engineering communication without increasing decoding complexity.

[0032] 2. When updating variable nodes, this invention performs amplified bit quantization on the input verification node information, uses a soft decision method to obtain the decoding result during the decision-making process, and adopts a parallel algorithm structure throughout the process. This can achieve a practical communication effect where the bit error rate is reduced to below 1e-6 when the encoding and decoding throughput exceeds 25Gbps. Attached Figure Description

[0033] Figure 1 This is a flowchart of the present invention;

[0034] Figure 2 This invention employs a fully parallel decoding structure diagram;

[0035] Figure 3 This is a schematic diagram of the fully parallel LDPC decoder of this invention;

[0036] Figure 4 This is a hardware resource report diagram of an example of the present invention;

[0037] Figure 5 This is a timing report diagram of an example of the present invention. Detailed Implementation

[0038] To clearly illustrate the technical features of this solution, specific implementation methods are described below, along with their appendices. Figure 1-5 The present invention will be described in detail below. Specific examples are provided below to implement the present invention.

[0039] A hardware decoding method for LDPC multi-bit quantization suitable for high-speed communication includes the following steps:

[0040] (1) Reset the decoding module, obtain the message sequence of length len from the channel, perform k-bit quantization expansion, and store the quantization result in a register, denoted as message. q , awaiting input as variable node information for calculation; where k is 3;

[0041] This example uses 1723_2048 LDPC encoding with a code rate of 0.8413 under the IEEE 802.3an standard as an example to illustrate the present invention. Information on the standard and check matrix H used in this example can be found in 802.3-2005 / Cor 1-2006-IEEE Standard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA / CD) Access Method and Physical Layer Specifications-Corrigendum 1|IEEE Standard|IEEE Xplore. A 2048-bit sequence of information to be decoded is obtained from the channel, extended by 5 bits, then transmitted and mapped back to 3 bits for quantization. The quantization result is stored in a register and denoted as the message. q Then message q It consists of 2048*3 bits, which are used as input to the variable node information calculation module. The expansion rules are shown in the table below.

[0042] Before expansion After expansion 0 01110 1 10001

[0043] To simulate the impact of channel noise on transmitted information bits, the expanded information bits are adjusted during algorithm design. The transmitted 5 bits of information will change, spreading to any 5 bits, and then undergo 3-bit quantization. The specific mapping quantization rules are shown in the table below:

[0044]

[0045] (2) Initialize the decoding module; the decoding module includes a fully parallel check node update module, a fully parallel node information calculation and transmission module, a memory module, and a fully parallel variable node update module.

[0046] To meet the engineering requirements of ultra-high speed, low resource consumption, and low latency, this invention adopts a fully parallel decoding structure, the diagram of which is attached. Figure 2 The fully parallel decoding structure enables all check nodes to update simultaneously and provide information to all variable nodes. The fully parallel decoding structure mainly includes a fully parallel check node update module, a fully parallel node information calculation and transmission module, a memory module, and a fully parallel variable node update module. In engineering implementation, the fully parallel decoding structure consumes fewer hardware resources while ensuring a higher transmission rate. A schematic diagram of the fully parallel LDPC decoder is attached. Figure 3 ;

[0047] (3) Use the parity check coefficient matrix of the LDPC code to expand the quantization result obtained in step (1) into a message. q The variable node information v is calculated using a fully parallel structure. mess ;

[0048] Step (3) specifically involves:

[0049] Fully parallel computation of variable node information v mess The parity check coefficient matrix H of the LDPC code is decoded in a 6-way parallel manner (see attached diagram of the parallel decoding structure). Figure 2 ) Calculate the variable node information sent to the verification node update module, v mess The first 96 bits are calculated using the following formula.

[0050] v mess [k*(row_i)-1:k*(row_i-1)]=

[0051] message q [(len*k-1)-(R i -1)*k:(len*k-1)-(R i -1)*k-(k-1)]

[0052] The parity check matrix H of the LDPC code has a dimension of 384×2048, a row weight of 32, and a column weight of 6; where row_i = 1, 2, ..., 32; R i This represents the index of the position of "1" in each row of H, i = 1, 2, ..., 32, k = 3.

[0053] The entire computation is completed simultaneously in parallel. The information sequence to be decoded is obtained from the channel during the first iteration, and from the second iteration onwards, it is obtained from the output of the fully parallel variable node update module.

[0054] (4) Transfer the variable node information v obtained in step (3) mess As input to the fully parallel check node update module, the check node is updated in a 6-way fully parallel manner to obtain the check node update value; wherein, the normalization factor used by the fully parallel check node update module is obtained in an adaptive manner.

[0055] Step (4) specifically involves: obtaining the variable node information v from step 3. mess As input to the check node update module, for each check node, a binary search method is used to obtain the maximum and second-largest values ​​(Max and SMax) of the variable node information connected to it. The check node update is performed in a 6-way parallel manner. The normalization factor used for the check node update is obtained adaptively. The update result is denoted as cnode, and all updated cnode information is used as the check node update value C. cnodes The calculation method for updating the result, denoted as cnode, is shown in the following formula:

[0056] cnode=Max-floor(Max / 2)+floor(Max / 4) or

[0057] cnode=SMax-floor(SMax / 2)+floor(SMax / 4)

[0058] Here, `floor` refers to the `floor` function. In hardware implementation, the `floor` function can be implemented using a shift and truncation operation. This results in a normalization factor that is not a constant but dynamically changing, making the update results of the verification nodes more robust. The information passed to the variable nodes in each iteration is also different, effectively avoiding invalid iterations. All updated cnode information is denoted as `Ccnodes`.

[0059] (5) Based on the updated value of the verification node obtained in step (4), the verification node information c is calculated using a 6-way parallel method. mess ;

[0060] Step (5) specifically involves:

[0061] c mess [k*(col_i)-1:k*(col_i-1)]=

[0062] C cnodes [(len*k-1)-(Q i -1)*k:(len*k-1)-(Q i -1)*k-(k-1)]

[0063] Where col_i = 1, 2, ..., 64; Q i This represents the index of the "1" position in the LDPC code parity check coefficient matrix H, where i = 1, 2, ..., 64, k = 3, and len = 2048. The fully parallel structure can simultaneously calculate all check node information transmitted to all variable nodes, thereby achieving ultra-high-speed communication decoding and transmission, and improving the transmission rate of the entire hardware decoding project.

[0064] (6) Transfer the verification node information c obtained in step (5) mess The bit quantization bit is increased, and then used as input to the fully parallel variable node update module. The variable node is updated in a 6-way fully parallel manner, and the highest bit of the update result is used as the decoding decision value.

[0065] Step (6) specifically involves: verifying the node information c mess As input to the variable node update module, variable node updates are performed in a 6-way parallel manner. The decoding capability of the decoder is improved by increasing the number of bits in the bit quantization of the input to the variable node update module. The k-bit input is first mapped to K bits, denoted as c. messK Using C messK Update the variable node.

[0066] This invention improves the decoding capability of the decoder by increasing the number of bits in the bit quantization of the input in the variable node update module. The 3-bit input is first mapped to 8 bits, denoted as c. messK This expands the scope of node information, thereby improving the stability of the decision-making stage. The specific mapping rules are shown in the table below.

[0067] 3 bits (before mapping) 8 bits (after mapping) 0(000) 8(00001000) 1(001) 5(00000101) 2(010) 2(00000010) 3(011) 1(00000001) 4(100) 255(11111111) 5(101) 254(11111110) 6(110) 251(11111011) 7(111) 248(11111000)

[0068] The following formula gives the update method for the j-th variable node:

[0069]

[0070] Where p represents the index of the check node connected to variable node j, j = 1, 2, ..., 2048, and the highest bit of the update result is used as the decoding decision value, that is, the decoding decision value dou[j] = v j[K], where K = 8.

[0071] (7) Use the decoding decision value obtained in step (6) as the input to check whether the decoding was successful. If the verification result is an all-zero vector: that is, H·dout T = 0, indicating successful decoding and the decoding process ends; otherwise, check if the maximum number of iterations has been reached. If the maximum number of iterations has not been reached, return to step (2); if the maximum number of iterations has been reached, declare decoding failure and the decoding process ends. Use the decoding decision value dou[1:2048] obtained in step (6) as the input of the decoding success verification module. If the verification result is an all-zero vector: that is, H·dout T =0 indicates successful decoding, outputs the decoding result dout[1:1723], and the decoding process ends; otherwise, it checks whether the maximum number of iterations has been reached (the maximum number of iterations is set to 8 in this example). If not, the iteration count is incremented by 1 and the process returns to step 2; otherwise, it declares decoding failure and the decoding process ends.

[0072] This example, following the above implementation steps, can achieve a coding gain of over 5dB and a bit error rate below 1e-6 at a decoder throughput exceeding 25Gbps. Figure 4 and attached Figure 5 These are the hardware resource report diagram and timing report diagram for this example.

Claims

1. A hardware decoding method for LDPC multi-bit quantization suitable for high-speed communication, characterized in that, Includes the following steps: (1) Reset the decoding module, obtain the message sequence of length len from the channel, perform k-bit quantization expansion, and store the quantization result in the register as message. q , awaiting input as variable node information for calculation; where k is 3; (2) Initialize the decoding module; wherein the decoding module includes a fully parallel check node update module, a fully parallel node information calculation and transmission module, a memory module, and a fully parallel variable node update module; (3) Use the LDPC code parity check coefficient matrix to expand the quantization result obtained in step (1) into a message. q The variable node information v is calculated using a fully parallel structure. mess ; (4) The variable node information v obtained in step (3) mess As input to the fully parallel check node update module, the check node is updated in a 6-way fully parallel manner to obtain the check node update value; wherein, the normalization factor used by the fully parallel check node update module is obtained in an adaptive manner. (5) The check node information c is calculated using a 6-way parallel method based on the check node update value obtained in step (4). mess ; (6) The verification node information c obtained in step (5) mess The bit quantization bit is increased, and then used as input to the fully parallel variable node update module. The variable node is updated in a 6-way fully parallel manner, and the highest bit of the update result is used as the decoding decision value. (7) Use the decoding decision value obtained in step (6) as the input to check whether the decoding was successful. If the verification result is a vector of all zeros: that is If the decoding is successful, the decoding process ends; otherwise, it is determined whether the maximum number of iterations has been reached. If the maximum number of iterations has not been reached, the process returns to step (2). If the maximum number of iterations has been reached, the decoding is declared to have failed and the decoding process ends. Step (4) specifically involves: obtaining the variable node information v from step 3. mess As input to the check node update module, for each check node, a binary search method is used to obtain the maximum and second-largest values ​​(Max and SMax) of the variable node information connected to it. The check node update is performed in a 6-way parallel manner. The normalization factor used for the check node update is obtained adaptively. The update result is denoted as cnode, and all updated cnode information is used as the check node update value C. cnodes The calculation method for updating the result, denoted as cnode, is shown in the following formula: or Here, floor is the floor function.

2. The LDPC multi-bit quantization hardware decoding method for high-speed communication according to claim 1, characterized in that, Step (3) is as follows: Wherein, the dimension of the parity check coefficient matrix H of the LDPC code is... Row weight is 'row', column weight is 'col'; row_i = 1, 2, ..., row; R i This represents the index of the position of "1" in each row of H, i = 1, 2, ..., row; The entire computation is completed simultaneously in parallel. The information sequence to be decoded is obtained from the channel during the first iteration, and from the second iteration onwards, it is obtained from the output of the fully parallel variable node update module.

3. The LDPC multi-bit quantization hardware decoding method for high-speed communication as described in claim 1, characterized in that, Step (5) is as follows: Where, col_i = 1, 2, ..., Q i This represents the index of the "1" in the parity check coefficient matrix H of the LDPC code, i = 1, 2, ... .

4. The LDPC multi-bit quantization hardware decoding method for high-speed communication as described in claim 1, characterized in that, Step (6) specifically involves: verifying the node information c mess As input to the variable node update module, variable node updates are performed in a 6-way parallel manner. The decoding capability of the decoder is improved by increasing the number of bits in the bit quantization of the input to the variable node update module. The k-bit input is first mapped to K bits, denoted as c. messK Using C messK To update the variable node, the following formula gives the update method for the j-th variable node: Where p represents the index of the check node connected to the variable node j, j = 1, 2, ..., len, the highest bit of the update result is used as the decoding decision value, i.e., the decoding decision value. .

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