Decoder, decoding method, memory controller and memory system

Abstract

The embodiment of the present disclosure provides a decoder, a decoding method, a memory controller and a memory system. The decoder comprises a cache module and a flip indication module. The cache module is configured to cache soft data related to a to-be-decoded codeword. The flip indication module is configured to obtain the soft data from the cache module, and use the soft data to assist in determining the number of bits in the to-be-decoded codeword that do not satisfy a check when performing hard decision decoding on the to-be-decoded codeword for the first time.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a decoder, decoding method, memory controller, and memory system. Background Technology

[0002] With the development of storage technology, 3D NAND flash memory has evolved from single-level cells (SLC) capable of storing 1 bit of information, to double-level cells (DLC) capable of storing 2 bits of information, to triple-level cells (TLC) capable of storing 3 bits of information, and even quadruple-level cells (QLC) capable of storing 4 bits of information; the number of stacked layers is also increasing. Faced with memory devices with increasingly more layers and storage bits, low-density parity code (LDPC) is typically used for error correction during data retrieval to enhance the reliability of the stored data. However, as the structure of 3D NAND flash becomes more complex and it stores more data, the types of errors it contains become increasingly complex. Using current error correction methods results in slow error correction speeds, reduced efficiency, and a significant impact on read speeds. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a decoder, a decoding method, a memory controller, and a memory system.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a decoder comprising: a buffer module and a toggle indicator module, wherein;

[0006] The caching module is configured to cache soft data related to the codeword to be decoded;

[0007] The flip indication module is configured to: obtain the soft data from the cache module; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine the number of bits in the codeword to be decoded that do not meet the check.

[0008] In the above scheme, the flip indicator module is further configured as follows:

[0009] Determine the initial error bit indication vector corresponding to the codeword to be decoded;

[0010] The soft data is used to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0011] In the above scheme, the decoder further includes: a variable node module and a check node module, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein,

[0012] The variable node module is configured to: receive hard read data and generate the codeword to be decoded based on the hard read data; send the codeword to be decoded to the verification node module; and send the codeword to be decoded and the hard read data to the flip indicator module.

[0013] The verification node module is configured to: receive the codeword to be decoded; determine a checksum vector based on the codeword to be decoded and the check matrix; and send the checksum vector to the flip indication module.

[0014] The flip indicator module is further configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

[0015] In the above scheme, the flip indicator module is further configured as follows:

[0016] Determine the soft data vector corresponding to the soft data;

[0017] The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector.

[0018] The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit vector.

[0019] Each element in the target error bit vector corresponds to the number of non-compliance checks for one bit.

[0020] In the above scheme, the flip indicator module is further configured as follows:

[0021] The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation.

[0022] Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector;

[0023] The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

[0024] In the above scheme, the flip indicator module is further configured as follows:

[0025] Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped.

[0026] The variable node module is further configured to: receive the flip instruction vector, and flip the bits that need to be flipped in the codeword to be decoded according to the flip instruction vector.

[0027] In the above scheme, the flipping criterion includes:

[0028] Flip the bit with the largest number of non-checking bits in the codeword to be decoded.

[0029] Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

[0030] In the above scheme, the decoder further includes: a counting module and a termination decision module, wherein,

[0031] The counting module is configured to: count the number of iterations for performing hard decision on the codeword to be decoded;

[0032] The termination decision module is configured to: determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate that the hard-decision decoding of the codeword to be decoded has failed.

[0033] In the above scheme, the decoder further includes: a rearrangement module;

[0034] The termination decision module is further configured to: output a second stop decoding signal when the checksum vector is determined to be a zero vector;

[0035] The rearrangement module is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in the correct order.

[0036] In the above scheme, the termination decision module is further configured to: output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indicator module to continue to perform hard decision decoding operation on the codeword to be decoded.

[0037] Secondly, embodiments of this disclosure provide a decoding method, including:

[0038] Obtain the soft data corresponding to the codeword to be decoded;

[0039] When performing hard-decision decoding on the codeword to be decoded, the number of bits in the codeword to be decoded that do not meet the check is determined using the soft data assistance at least in the first flip iteration.

[0040] In the above scheme, the step of using the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes:

[0041] Determine the initial error bit indication vector corresponding to the codeword to be decoded;

[0042] The soft data is used to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0043] In the above scheme, the step of using the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes:

[0044] Determine the soft data vector corresponding to the soft data;

[0045] The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector.

[0046] The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit vector.

[0047] Each element in the target error bit vector corresponds to the number of non-compliance checks for one bit.

[0048] In the above scheme, determining the initial error bit indication vector corresponding to the codeword to be decoded includes:

[0049] Receive hard read data and generate the codeword to be decoded based on the hard read data;

[0050] The checksum vector is determined based on the codeword to be decoded and the pre-constructed check matrix;

[0051] The initial error bit indication vector corresponding to the codeword to be decoded is determined based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0052] In the above scheme, determining the initial error bit indication vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix includes:

[0053] The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation.

[0054] Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector;

[0055] The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

[0056] In the above scheme, the method further includes:

[0057] Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped.

[0058] The bits that need to be flipped in the codeword to be decoded are flipped according to the flipping indicator vector.

[0059] In the above scheme, the method further includes:

[0060] Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped.

[0061] The bits that need to be flipped in the codeword to be decoded are flipped according to the flipping indicator vector.

[0062] In the above scheme, the flipping criterion includes:

[0063] Flip the bit with the largest number of non-checking bits in the codeword to be decoded.

[0064] Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

[0065] In the above scheme, the method further includes:

[0066] The number of iterations for performing hard decision on the codeword to be decoded is counted;

[0067] Determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector;

[0068] When the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, a first stop decoding signal is output; the first stop decoding signal is configured to indicate that the hard-decision decoding of the codeword to be decoded has failed.

[0069] In the above scheme, the method further includes:

[0070] Determine whether the checksum vector is a zero vector; if the checksum vector is determined to be a zero vector, output a second stop decoding signal;

[0071] In response to the second stop decoding signal, the codewords to be decoded are rearranged, and the codewords to be decoded in the correct order are output.

[0072] In the above scheme, the method further includes:

[0073] When the checksum vector is not zero and the number of iterations has not reached the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to indicate that a hard decision decoding operation is performed on the codeword to be decoded.

[0074] Thirdly, embodiments of this disclosure also provide a memory controller, including a processor and a decoder as described above, wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device;

[0075] The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine, at least in the first flip iteration, the number of bits in the codeword to be decoded that do not meet the check.

[0076] Fourthly, embodiments of this disclosure provide a memory system, including:

[0077] A memory device configured to store data;

[0078] A memory controller, coupled to the memory device, includes a processor and a decoder; wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device;

[0079] The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine, at least in the first flip iteration, the number of bits in the codeword to be decoded that do not meet the check.

[0080] In the above scheme, the processor is further configured to: read hard read data from the memory device; and send the hard read data to the decoder.

[0081] The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded based on the hard read data.

[0082] In the above scheme, the decoder includes: a buffer module, a variable node module, a check node module, and a flip indicator module, wherein;

[0083] The cache module is configured to cache the soft data read by the processor;

[0084] The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded based on the hard read data; and send the codeword to be decoded to the verification node module.

[0085] The verification node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector based on the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indicator module.

[0086] The flip indicator module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0087] This disclosure provides a decoder, a decoding method, a memory controller, and a memory system. The decoder includes a cache module and a flip indicator module. The cache module is configured to cache soft data related to the codeword to be decoded. The flip indicator module is configured to retrieve the soft data from the cache module. When performing hard-decision decoding on the codeword to be decoded, the soft data is used at least in the first flip iteration to help determine the number of bits in the codeword that do not meet the parity check. The decoder provided by this disclosure caches the soft data related to the codeword to be decoded through the cache module. Then, when performing hard-decision decoding on the codeword to be decoded, the flip indicator module uses the soft data in one or more iterations to help determine the number of bits in the codeword that do not meet the parity check. Thus, by using soft data to assist the flip decision in hard-decision decoding, the high throughput and low power consumption characteristics of hard-decision decoding are achieved, greatly improving the error correction capability of hard-decision decoding. Attached Figure Description

[0088] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0089] Figure 1 A schematic diagram of an exemplary system having a memory system provided in an embodiment of this disclosure;

[0090] Figure 2a A schematic diagram of an exemplary memory card with a memory system provided according to an embodiment of this disclosure;

[0091] Figure 2b A schematic diagram of an exemplary solid-state drive with a memory system provided according to an embodiment of this disclosure;

[0092] Figure 3 This is a schematic diagram of the structure of a memory controller provided in an embodiment of the present disclosure;

[0093] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuitry provided for an embodiment of this disclosure;

[0094] Figure 5 This is a schematic cross-sectional view of a memory array containing NAND-type memory strings according to an embodiment of the present disclosure.

[0095] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuitry provided for embodiments of this disclosure;

[0096] Figure 7This is a schematic diagram of the structure of a decoder provided in one embodiment of the present disclosure;

[0097] Figure 8 This is an exemplary schematic diagram illustrating the acquisition of soft data and the reading of hard data according to an embodiment of the present disclosure;

[0098] Figure 9 This is a schematic diagram of the structure of a decoder provided in another embodiment of the present disclosure;

[0099] Figure 10 A schematic diagram of a Tanner diagram provided in an embodiment of this disclosure;

[0100] Figure 11 Tanner provided as an embodiment of this disclosure Figure 1 One example;

[0101] Figure 12 This is a schematic diagram of the structure of a decoder provided in another embodiment of the present disclosure;

[0102] Figure 13 A schematic diagram of the structure of a decoder is provided for another embodiment of this disclosure;

[0103] Figure 14 This is a schematic diagram of the working process of a decoder provided in one embodiment of the present disclosure;

[0104] Figure 15 A schematic flowchart illustrating a decoding method provided in an embodiment of this disclosure;

[0105] Figure 16 This is a schematic diagram of the structure of a memory controller provided in an embodiment of the present disclosure. Detailed Implementation

[0106] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. Other embodiments, variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of the present disclosure. Therefore, the embodiments of the present disclosure are not limited to those set forth herein. Rather, the described embodiments are provided so that the embodiments of the present disclosure are thorough and complete, and fully convey the scope of the embodiments of the present disclosure to those skilled in the art to which the embodiments of the present disclosure pertain. It should be noted that references to “embodiment,” “another embodiment,” etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, a first element in one embodiment may also be referred to as a second or third element in another embodiment without departing from the spirit and scope of the embodiments of the present disclosure.

[0107] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0108] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. Singular forms as used herein are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” as used in embodiments of this disclosure and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in embodiments of this disclosure specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in embodiments of this disclosure includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in embodiments of this disclosure, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains in light of embodiments of this disclosure. It should be further understood that unless explicitly defined in embodiments of this disclosure, terms such as “classified” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of embodiments of this disclosure and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0109] In the following description, numerous specific details are set forth to provide a thorough understanding of this disclosure, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail to avoid unnecessarily obscuring this disclosure. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of this disclosure are described in detail below with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of embodiments of this disclosure. Well-known technical details may have been omitted to avoid obscuring the features and aspects of embodiments of this disclosure.

[0110] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0111] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile memory device, 3D NAND (Not-And) memory devices have become the mainstream product in the storage market due to their high storage density, controllable production costs, suitable programming and erasing speeds, and retention characteristics. With the increase in the number of bits per memory cell and the number of stacked layers, the types of errors that occur during read operations on memory devices become increasingly complex. In this situation, using LDPC hard-decision decoding in a decoder to decode the codeword (data read from the memory device) results in long decoding times and weak error correction capabilities, severely impacting the read speed.

[0112] To address one or more of the aforementioned problems, embodiments of this disclosure provide a decoder that utilizes soft data to assist in the flip decision of hard decision decoding, thereby achieving high throughput and low power consumption characteristics of hard decision decoding and greatly improving the error correction capability of hard decision decoding.

[0113] The embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific examples.

[0114] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided according to an embodiment of the present disclosure. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory system therein. For example... Figure 1As shown, system 100 may include host 108 and memory system 102. Host 108 may include a processor, such as a central processing unit (CPU) or a system-on-chip (SoC), where the SoC may be, for example, an application processor (AP). Host 108 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed in host 108. The OS enables interoperability between host 108 coupled to memory system 102 and users who need and use memory system 102. The OS may support functions and operations corresponding to user requests. For example, and not limited to, depending on whether host 108 is a removable host, OS may be classified as a general-purpose operating system and a mobile operating system. The general-purpose operating system may include personal operating systems and enterprise operating systems. The personal operating system may be an operating system, including Windows and Chrome, used for general purposes to support services; the enterprise operating system may be an operating system, including Windows Server, Linux, Unix, etc., dedicated to ensuring and supporting higher performance. The mobile operating system can refer to an operating system for services or functions related to mobility (such as power saving). Generally, a mobile operating system can be an operating system such as Android, iOS, or Windows Mobile. In some embodiments, the host 108 may include multiple OSes; correspondingly, the host 108 may run multiple operating systems associated with the memory system 102. In other embodiments, the host 108 translates a user's request into one or more commands and transmits the one or more commands to the memory system 102 so that the memory system 102 performs operations related to the one or more commands.

[0115] The memory system 102 is capable of responding to requests from the host 108, performing specific functions, or executing various internal operations. In some embodiments, the memory system 102 can store data accessed by the host 108. The memory system 102 can serve as the main memory system or auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically connected and communicate according to corresponding protocols. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, but not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RSMMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, and memory sticks, etc.

[0116] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0117] Return as Figure 1 As shown, the memory system 102 may include one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and control the memory devices 104. For example, the memory controller 106 can read data from the memory devices 104 and transfer the read data to the host 108; it can also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. In other words, the memory controller 106 can control the write (or programming) operations, read operations, erase operations, and background operations of the memory devices 104, etc. Furthermore, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0118] Among them, such as Figure 3 As shown, the memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and memory 304. The aforementioned components 301, 302, 303, and 304 within the memory controller 106 can share internal transmission signals via an internal bus. In some embodiments, the host I / F 301 may interface with the memory system 102 in response to a protocol of the host 108, and the host I / F 301 may exchange transmission commands and data operations between the host 108 and the memory system 102. The host I / F 301 may process commands and data sent by the host 108 and may include at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE). In some embodiments, the host I / F301 is a component of the memory system 102 used to exchange data with the host 108, and can be implemented through firmware known as the host interface layer (HIL).

[0119] Memory I / F 302 can serve as an interface for transmitting commands and data between memory controller 106 and memory device 104, allowing memory controller 106 to control memory device 104 in response to requests transmitted from host 108. Memory I / F 302 can generate control signals for controlling memory device 104. In some embodiments, if memory device 104 is NAND flash memory, memory I / F 302 can write data to or read data from memory device 104 under the control of processor 303. Memory I / F 302 can process commands and data between memory controller 106 and memory device 104, such as operations of the NAND flash interface, particularly operations between memory controller 106 and memory device 104. According to embodiments, memory I / F 302 can be implemented as a component for exchanging data with memory device 104 via firmware referred to as the Flash Interface Layer (FIL).

[0120] Processor 303 may be implemented as a microprocessor or a central processing unit (CPU). Memory system 102 may include one or more processors 303. Processor 303 may control all operations of memory system 102. By way of example and not limitation, processor 303 may control programming or reading operations of memory device 104 in response to write or read requests from host 108. According to embodiments, processor 303 may use or run firmware to control all operations of memory system 102. In this disclosure, firmware may be referred to as a flash translation layer (FTL). FTL may act as an interface between host 108 and memory device 104. Host 108 may transmit requests related to write and read operations to memory device 104 via FTL. For example, memory controller 106 uses processor 303 when performing an operation requested from host 108 in memory device 104. Processor 303 coupled to memory device 104 may process instructions or commands related to commands from host 108. The memory controller 106 can perform foreground operations such as command operations corresponding to commands input from the host 108, such as programming operations corresponding to write commands, reading operations corresponding to read commands, erasing / discarding operations corresponding to erase / discard commands, and parameter setting operations corresponding to setting parameter commands or setting feature commands with setting commands.

[0121] In another example, memory controller 106 may perform background operations on memory device 104 via processor 303. By way of example and not limitation, these background operations may include garbage collection (GC) operations, wear leveling (WL) operations, map sweeping operations, and bad block management operations that check or search for bad blocks. Garbage collection operations may include copying and processing data stored in one memory block of memory device 104 to another memory block. Wear leveling operations may include exchanging and processing stored data between memory blocks of memory device 104. Map sweeping operations may include storing mapped data stored in memory controller 106 in memory blocks of memory device 104. Bad block management operations may include checking and processing bad blocks in memory blocks of memory device 104. Memory controller 106 may respond to operations that access memory blocks of memory device 104, wherein accessing memory blocks of memory device 104 may include foreground or background operations performed on memory blocks of memory device 104.

[0122] Memory 304 may be the working memory of memory controller 106, configured to store data used to drive memory controller 106. More specifically, memory 304 may store firmware driven by processor 303 and data (e.g., metadata) required to drive the firmware when memory controller 106 controls memory device 104 in response to a request from host 108. Memory 304 may also be a buffer memory of memory controller 106, configured to temporarily store write data transferred from host 108 to memory device 104 and read data transferred from memory device 104 to host 108. Memory 304 may include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapped buffer / cache for storing write and read data. Memory 304 may be implemented using volatile memory. Memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0123] Although Figure 3 The diagram shows that memory 304 is included in memory controller 106, but this disclosure is not limited thereto. In embodiments, memory 304 may be included outside of memory controller 106, and memory controller 106 may input and output data to memory 304 via a separate memory interface (not shown).

[0124] The error correction (ECC) module 305 includes an encoding unit 3051 and a decoding unit 3052. The encoding unit 3051 performs an encoding operation, such as LDPC, on the data to be programmed into the semiconductor memory device 104 and outputs data including additional parity bits. The parity bits can be stored in the semiconductor memory device 104. The decoding unit 3052 performs error correction decoding on data read from the semiconductor memory device 104; it can also determine whether the error correction decoding was successful and output a command signal based on the determination result; it can also use the parity bits generated by the LDPC encoding operation to correct erroneous bits in the data.

[0125] Here, although Figure 3 The error correction module 305 is shown to be included in the memory controller 106, but this disclosure is not limited thereto. In an embodiment, the error correction module 305 may be included outside the memory controller 106, and the memory controller 106 may communicate with the error correction module 305 via a separate interface (not shown).

[0126] See back Figure 1 The memory device 104 may include non-volatile memory, which retains stored data even when no power is supplied. The memory device 104 may also include volatile memory. The device 104 can store data provided from the host 108 via write operations; the memory device 104 can also provide the stored data to the host 108 via read operations. In embodiments of this disclosure, the memory device 104 may include any disclosed memory, such as volatile memory devices of dynamic random access memory (DRAM) and static RAM (SRAM), or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory (e.g., three-dimensional NAND flash memory).

[0127] To illustrate memory devices using 3D NAND flash memory as an example, see [link to documentation]. Figure 4 The diagram illustrates a schematic circuit diagram of an exemplary memory device 400 including peripheral circuitry according to some aspects of this disclosure. The memory device 400 may be... Figure 1An example of memory device 104 is provided. Memory device 400 may include memory array 401 and peripheral circuitry 402 coupled to memory array 401. Taking memory array 401 as an example of a three-dimensional NAND-type memory array, memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0128] In some implementations, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 406 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-bit cell (TLC), a four-bit cell (QLC), or five bits per cell (also known as a five-bit cell (PLC)). Each MLC may be programmed to take a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0129] like Figure 4As shown, each NAND memory string 408 may include a lower select gate (BSG) 410 at its source end and an upper select gate (TSG) 412 at its drain end. BSG 410 and TSG 412 can be configured to activate the selected NAND memory string 408 during read and program operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled via a common source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the TSG 412 of each NAND memory string 408 is coupled to a corresponding bit line (BL) 416, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 412) or a deselection voltage (e.g., 0V) to the corresponding TSG 412 via one or more TSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 410) or a deselection voltage (e.g., 0V) to the corresponding BSG 410 via one or more BSG lines 415.

[0130] like Figure 4 As shown, NAND memory strings 408 can be organized into multiple memory blocks 404, each of which may have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase memory cells 406 in a selected memory block 404, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 414 of the selected memory block 404 and the unselected memory blocks 404 on the same plane as the selected memory block 404. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 is affected by read and program operations.

[0131] Figure 5 A schematic cross-sectional view of an exemplary memory array 401 including NAND memory strings 408 is shown according to some aspects of this disclosure. Figure 5As shown, the NAND memory string 408 may include a stacked structure 510, which includes multiple gate layers 511 and multiple insulating layers 512 stacked alternately in sequence, and a memory string 408 perpendicularly penetrating the gate layers 511 and insulating layers 512. The gate layers 511 and insulating layers 512 may be stacked alternately, with adjacent gate layers 511 separated by an insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 determines the number of memory cells included in the memory array 401.

[0132] The constituent materials of the gate layer 511 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper select gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower select gate line 514, and the gate layer 511 extending laterally between the upper and lower select gate lines may serve as a word line layer 503.

[0133] In some embodiments, the stacked structure 510 may be disposed on the substrate 501. The substrate 501 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0134] In some embodiments, the NAND memory string 408 includes a channel structure extending vertically through the stacked structure 510. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0135] Return to reference Figure 4 The peripheral circuitry 402 can be coupled to the memory array 401 via bit line 416, word line 418, source line 414, BSG line 415, and TSG line 413. The peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, BSG line 415, and TSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. The peripheral circuitry 402 can include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0136] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic 612. In one example, page buffer / sensor amplifier 604 can store programming data (write data) to be programmed into memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0137] The row decoder / word line driver 608 can be configured to be controlled by control logic 612 and to select / deselect memory blocks 404 of memory array 401 and select / deselect word lines 418 of memory blocks 404. The row decoder / word line driver 608 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive BSG lines 415 and TSG lines 413. The row decoder / word line driver 608 can be configured to perform programming operations on memory cells 406 coupled to one or more selected word lines 418. The voltage generator 610 can be configured to be controlled by control logic 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 401.

[0138] Control logic 612 can be coupled to various circuits in the peripheral circuitry described above, such as voltage generator 610, row decoder / word line driver 608, etc., and is configured to control the operation of each circuit. Register 614 can be coupled to control logic 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 612, as well as to buffer status information received from control logic 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0139] In 3D NAND memory devices, single-cell memory (SLC) holds a certain share of the memory market due to its advantages such as fast read / write speed, high reliability, and long lifespan; while double-cell memory (MLC), triple-cell memory (TLC), and quad-cell memory (QLC) are becoming the development trend of the memory market due to their higher storage density and larger storage capacity.

[0140] However, as the number of bits in a memory cell and the number of stacking layers increase, the types of errors it contains become more and more complex. When performing read operations on a memory device, using LDPC hard decision decoding to decode the codeword to be decoded results in a long decoding time and weak error correction capability, which seriously affects the read speed.

[0141] Based on the memory device and memory system described above, in order to solve one or more of the problems mentioned above, see [reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the structure of a decoder provided in one embodiment of the present disclosure.

[0142] Specifically, the decoder 700 includes: a buffer module 701 and a toggle indicator module 702, wherein;

[0143] The cache module 701 is configured to cache soft data related to the codeword to be decoded;

[0144] The flip indication module 702 is configured to: obtain the soft data from the cache module 701; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine the number of bits in the codeword to be decoded that do not meet the check.

[0145] It should be noted that the decoder provided in this embodiment can be applied to memory systems such as those described above, and the decoder 700 can be configured as follows: Figure 3 The decoding unit within the illustrated memory controller is configured to perform a decoding operation on the codeword to be decoded. The codeword to be decoded can refer to hard-read data, which can be read from the memory device by the memory controller according to a hard-read voltage, or it can be the codeword after a certain iteration flip during the decoding process. Whether the codeword to be decoded is hard-read data or the codeword after a certain iteration flip will be explained in detail later and will not be repeated here.

[0146] Here, the hard read voltage can be the initial read voltage (which is the default read voltage preset by the memory system, and can be the same as or have a certain offset from the reference voltage in the Read Retry Table (RRT). This offset is included in the RRT); or, the hard read voltage can be the optimal read voltage. The optimal read voltage can be obtained in ways including, but not limited to, the optimal read voltage determined based on the usage of the memory device and the RRT. Specifically, this process includes: traversing the RRT, determining the voltage offset in the RRT that minimizes errors when reading the memory device under the given usage conditions, and then obtaining the optimal read voltage based on the reference voltage and the determined voltage offset.

[0147] It should be noted that the RRT is a table containing multiple voltage offsets, each of which is relative to a reference voltage. These voltage offsets are implemented by the hardware circuitry within the memory, for example, by setting these voltage offsets through registers included in the memory. In other words, all read voltages are obtained by deriving the required voltage offset from this RRT table, then superimposing it on the reference voltage (including the sign of the superposition; that is, if the voltage offset is negative, the final read voltage will be less than the reference voltage) to obtain the desired voltage value, which is then applied to the corresponding word line.

[0148] For example, Table 1 shows the RRT corresponding to a TLC type memory cell provided in this embodiment of the present disclosure. Each column in Table 1 represents a set of voltage offsets, i.e., Rd1 to Rd7, that distinguishes adjacent programming states relative to the corresponding reference voltage. It should be noted that since a TLC type memory cell has 8 data states, it can be distinguished using 7 read voltages, hence Table 1 has 7 columns.

[0149] The set of voltage offsets described above can include positive offsets that increase in the direction of being greater than the reference voltage, and negative offsets that decrease in the direction of being less than the reference voltage. For example, for Rd7, +V1, +V2, +V3, and +V4 are positive offsets, where the values ​​of V1, V2, V3, and V4 increase sequentially; while -V5 to -V11 are negative offsets, where the values ​​of V5 to V11 decrease sequentially.

[0150] Table 1 RRT

[0151]

[0152] return Figure 7 The decoder shown uses soft data, which can be a type of probabilistic information used to measure the reliability of a given read (such as the hard read data in the embodiments of this disclosure), and can be represented by the log-likelihood ratio (LLR). Therefore, there is a read as a baseline, and the soft data is used to measure its reliability.

[0153] For soft data, please refer to [link / reference]. Figure 8 As shown. In Figure 8 In this context, assume the hard read data read using the optimal read voltage is 1100; the data read using the first reread voltage is 1000, where the first reread voltage is to the left of the optimal read voltage and has a certain offset from it, denoted as -Δ; the data read using the second reread voltage is 1110, where the second reread voltage is to the right of the optimal read voltage and has a certain offset from it, denoted as +Δ. Correspondingly, the soft data can be 0110. In this case, the soft data can be used to determine the reliability of the hard read data 1100 / 1000 / 1110. Specifically, the reliability of the hard read data is determined using the soft data. A bit in the soft data that is "0" indicates that the reliability of that bit in the hard read data is relatively high; in other words, that bit is judged to be relatively close to the truth. A bit in the soft data that is "1" indicates that the reliability of that bit in the hard read data is relatively weak. For example, in... Figure 8 In this example, the reliability of the hard read data 1100 is determined by the soft data 0110. If the leftmost bit of the soft data 0110 is "1", and the corresponding bit in the soft data is "0", then the reliability of that bit is relatively high, i.e., a strong "1". Similarly, if the middle two bits of the hard read data 1100 correspond to "1" in the soft data, then the reliability of the middle two bits is weak, i.e., weak '1' or '0'; the rightmost bit of the hard read data 1100 is a strong "0".

[0154] In some implementations, the method of acquiring the soft data may include: Figure 8As shown, the soft data is read directly from a NAND-type memory device. Specifically, the memory controller can send a command to the memory device to read the soft data, and the memory device can return the soft data to the memory controller. In other embodiments, the soft data can also be based on the XOR result of two consecutive hard reads pre-cached in the memory controller's memory.

[0155] The decoder provided in this disclosure, when performing hard-decision decoding on the codeword to be decoded, uses soft data cached in the decoder's buffer module related to the codeword to be decoded, and then uses this soft data to help determine the number of bits in the codeword that do not meet the check. The hard-decision decoding can be LDPC bit-flip decoding. In LDPC bit-flip decoding, at least in the first flip iteration, fast-read soft data is used to assist in LDPC bit-flip decoding, greatly improving the correction capability of LDPC bit-flip decoding. The phrase "at least in the first flip iteration, soft data is used to assist in bit-flip judgment" can mean that it is used only in the first flip iteration; or in the first flip iteration, the second flip iteration; or, similarly, in multiple flip iterations.

[0156] Here, the "failure to satisfy the check" refers to the equation in the checksum vector generated after a single check of the codeword to be decoded using the check matrix, where each non-zero element corresponds to a bit in the codeword to be decoded that participates in the check. The "number of bits in the codeword to be decoded that fail to satisfy the check" refers to the number of non-zero elements in the check equations that the bits in the codeword participate in.

[0157] For example, suppose the codeword to be decoded is: C1C2C3C4C5C6C8C9C10C11C12; the checksum vector it satisfies in a single check is as follows:

[0158]

[0159]

[0160]

[0161]

[0162]

[0163]

[0164]

[0165]

[0166]

[0167] In this case, the number of bits in the codeword to be decoded that do not meet the check is as follows: C1: 2; C2: 2; C3: 0; C4: 1; C5: 2; C6: 1; C7: 1; C8: 0; C9: 0; C10: 1; C11: 0; C12: 1.

[0168] In some embodiments, the flip indicator module 702 may also be configured to:

[0169] Determine the initial error bit indication vector corresponding to the codeword to be decoded;

[0170] The soft data is used to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0171] It should be noted that this step specifically describes how to use soft data assistance to determine the number of bits in the codeword to be decoded that do not meet the parity check. Specifically, first, an initial error bit indicator vector is determined for the codeword to be decoded. This initial error bit indicator vector can be the one that indicates the number of bits in the codeword to be decoded that do not meet the parity check when only LDPC bit-flipping decoding is performed without soft data assistance. Then, soft data assistance is used to determine the number of bits in the codeword to be decoded that do not meet the parity check using this initial error bit vector.

[0172] Specifically, in some embodiments, the flip indicator module 702 is further configured to:

[0173] Determine the soft data vector corresponding to the soft data;

[0174] The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector.

[0175] The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit indication vector.

[0176] Each element in the target error bit vector corresponds to the number of non-compliance checks for one bit.

[0177] It should be noted that the soft data is used to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check. Specifically, the soft data is first represented as a soft data vector. Then, the soft data vector is summed with the aforementioned initial error bit indicator vector to obtain the target error bit indicator vector. Each element in the target error bit indicator vector corresponds to the number of bits that do not meet the check.

[0178] For example, suppose the initial error bit vector is {0, 1, 1, 0}; the soft data vector corresponding to the soft data is {0, 1, 1, 0}; then the target error bit vector is {0, 2, 2, 0}. Here, the number of non-checked values ​​corresponding to the first bit of the codeword to be decoded is 0; the number of non-checked values ​​corresponding to the second bit of the codeword to be decoded is 2; the number of non-checked values ​​corresponding to the third bit of the codeword to be decoded is 2; and the number of non-checked values ​​corresponding to the fourth bit of the codeword to be decoded is 0.

[0179] In some embodiments of this disclosure, the initial error bit indication vector is obtained as follows: Figure 9 As shown, the decoder 700 further includes a variable node module 703 and a check node module 704, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein,

[0180] The variable node module 703 is configured to: receive hard read data and generate the codeword to be decoded based on the hard read data; send the codeword to be decoded to the verification node module; and send the codeword to be decoded and the hard read data to the flip indicator module.

[0181] The verification node module 704 is configured to: receive the codeword to be decoded; determine a checksum vector based on the codeword to be decoded and the verification matrix; and send the checksum vector to the flip indication module.

[0182] The flip indicator module 702 is further configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

[0183] It should be noted that, Figure 7 The decoder shown only includes the main structures relevant to the inventive concept of this disclosure. In LDPC bit-flip decoding, the decoder may further include a variable node module and a check node module, and the variable node module may include multiple variable node units; the check node module may include multiple check node units; the multiple variable node units and the multiple check node units are connected according to a pre-constructed check matrix to form a variable-check connection network. Here, the pre-constructed check matrix may refer to the LDPC check matrix, also known as the H matrix.

[0184] In practical applications, the aforementioned variable-verification connection network can also be called a Tanner graph, as shown below. Figure 10 As shown. In Figure 10 In the Tanner graph, there are verification nodes 1001, variable nodes 1002, and edges 1003 connecting the verification nodes and variable nodes. The value transmitted from the verification node to the variable node after processing by the verification node is called verification node information 1004A; the value transmitted from the variable node to the verification node after processing by the variable node is called variable node information 1004B.

[0185] One example, see Figure 11 The Tanner graph includes five check nodes 1001 representing the parity equation of the H matrix, ten variable nodes 1002 representing code symbols, and edges 1003 representing the relationships between the check nodes and the variable nodes. Edges 1003 connect each check node to a variable node corresponding to a code symbol included in the parity equation represented by the check node. Figure 11 A Tanner graph formed by an H matrix is ​​shown, where the number of variable nodes connected to each check node is fixed at 4, and the number of check nodes connected to each variable node is fixed at 2. The initial values ​​of the variable nodes can be hard-read data.

[0186] In such Figure 9 In the decoder structure shown, the variable node module can receive hard read data and generate a codeword to be decoded based on the hard read data; and send the codeword to be decoded to the check node module; send the codeword to be decoded and the hard read data to the flip indicator module; the check node module can receive the codeword to be decoded and determine the checksum vector based on the codeword to be decoded and the aforementioned check matrix, and send the checksum vector to the flip indicator module; the flip indicator module can receive the aforementioned codeword to be decoded, hard read data, check vector sum, and obtain the check matrix, and then use the codeword to be decoded, hard read data, check vector sum, and check matrix to obtain the initial error bit indicator vector.

[0187] It should be noted that, based on the preceding description, the decoder can be located in the decoding section of the memory controller. Therefore, the hard read data received by the variable node module can be either read data fed back from the memory device via the memory I / F in response to the processor's read command, directly transmitted to the variable node module via the bus; or read data fed back from the memory device via the memory I / F in response to the processor's read command, temporarily stored in memory, and then retrieved by the processor from memory before being transmitted to the variable node module; or any other process that allows the acquisition of hard read data. In general, the decoder is internal to the memory controller and coupled to the processor and other components via the bus; therefore, the variable node module can receive hard read data from outside the decoder. After receiving the hard read data, the variable node module assigns the value of each bit of the hard read data to the corresponding variable node unit, generating the codeword to be decoded.

[0188] To determine the checksum vector based on the codeword to be decoded and the aforementioned check matrix, one can multiply the aforementioned check matrix with the transpose of the codeword to be decoded to obtain the checksum vector.

[0189] For the initial error bit indication vector obtained using the codeword to be decoded, hard-read data, check vector, and check matrix, in some embodiments, the flip indication module 702 is further configured to:

[0190] The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation.

[0191] Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector;

[0192] The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

[0193] It should be noted that this description outlines the specific steps for obtaining the initial error bit indicator vector using the codeword to be decoded, hard read data, a check vector, and a check matrix. Specifically, the hard read data (the codeword to be decoded during the first iteration's flip) is first summed with the codeword to be decoded, followed by a modulo operation to obtain the first bit vector. Then, the transpose of the check vector is multiplied by the check matrix to obtain the second bit vector. Finally, the first bit vector and the second bit vector are summed to obtain the aforementioned initial error bit indicator vector. Here, the number of elements in the first and second bit vectors is the same as the number of bits in the codeword to be decoded.

[0194] Specifically, the calculation process described above can be described by the following formula:

[0195] f1=(y+y0)mod2+s′H

[0196] Where f1 is the initial error bit indicator vector, each element of which corresponds to a bit in the codeword to be decoded; y is the codeword to be decoded; y0 is the hard read data; s' is the transpose of the checksum vector; and H is the check matrix.

[0197] It should be noted that in the first flip iteration, y = y0, that is, in the first flip iteration, the codeword to be decoded is the hard read data; in the remaining flip iterations, the codeword to be decoded is the hard read data after bit flipping.

[0198] Based on this, in the embodiments of this disclosure, the target error bit indication vector can be represented by the following formula:

[0199] f2=(y+y0)mod2+s′H+R

[0200] Where f2 is the target error bit indicator vector; R is soft data.

[0201] In some embodiments, the flip indicator module 702 is further configured to:

[0202] Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped.

[0203] The variable node module 703 is further configured to: receive the flip instruction vector and flip the bits that need to be flipped in the codeword to be decoded according to the flip instruction vector.

[0204] The flipping criteria may include:

[0205] Flip the bit with the largest number of non-checking bits in the codeword to be decoded.

[0206] Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

[0207] It should be noted that after obtaining the target error bit indication vector, the number of bits in the codeword to be decoded that do not meet the check is obtained. Then, the flip indication module obtains a flip indication vector based on the number of bits that meet the check and the flip criterion for each bit. Subsequently, the variable node module flips the bits in the codeword to be decoded that need to be flipped according to this flip indication vector. The flip criterion here includes, but is not limited to, flipping the bit with the largest number of bits that do not meet the check, and flipping the bits with a number of bits that do not meet the check greater than or equal to a preset threshold. In other words, only the bit corresponding to the largest data in f2 is flipped; or, bits in f2 that are greater than or equal to T (i.e., the preset threshold) are flipped.

[0208] In some embodiments, such as Figure 12 As shown, the decoder 700 further includes: a counting module 704 and a termination decision module 705, wherein,

[0209] The counting module 704 is configured to count the number of iterations for performing hard decision on the codeword to be decoded;

[0210] The termination decision module 705 is configured to: determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate that the hard decision decoding of the codeword to be decoded has failed.

[0211] It should be noted that the number of flip iterations is finite in hard-decision decoding. This number of flip iterations can be counted by the counting module 704, i.e., the counting module counts the number of iterations. Then, the termination decision module 705 determines whether the counted number of iterations has reached the maximum number of iterations and whether the checksum vector is zero. When the maximum number of iterations is reached and the checksum vector is non-zero, a first stop decoding signal is output. This first stop decoding signal indicates that the hard-decision decoding of the codeword to be decoded has failed.

[0212] In some embodiments, the decoder 700 further includes a rearrangement module 706;

[0213] The termination decision module 705 is further configured to: output a second stop decoding signal when the checksum vector is determined to be a zero vector; the second stop decoding signal is configured to indicate that the hard decision decoding of the codeword to be decoded was successful;

[0214] The rearrangement module 706 is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in the correct order.

[0215] It should be noted that when the termination decision module 705 outputs a second stop decoding signal, the rearrangement module responds to the second stop decoding signal by rearranging the codewords to be decoded and outputting the codewords to be decoded in the correct order, thereby completing the decoding of the hard read data.

[0216] In some embodiments, the termination decision module 705 is further configured to: output a continue decoding signal when the checksum vector is not a zero vector and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indicator module to continue performing hard decision decoding operation on the codeword to be decoded.

[0217] It should be noted that the steps here may refer to the termination decision module outputting a continue decoding signal when the checksum vector is not zero and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the aforementioned variable node module, check node module and flip indicator module to continue to perform hard decision decoding operation on the codeword to be decoded, so as to determine whether the codeword to be decoded is successfully decoded or fails to decode.

[0218] Based on the above description, such as Figure 13 As shown, it illustrates a schematic diagram of the decoder provided in an embodiment of this disclosure. It should be noted that... Figure 13 In this context, d represents hard read data; v represents the codeword to be decoded; S represents the checksum vector; I represents the toggle indicator vector; and Stop is the stop decoding signal, including the first and second stop decoding signals described above. Here, the first and second sub-connection networks together form the variable-check node connection network.

[0219] based on Figure 13 The decoder shown in this disclosure, and the decoding workflow provided in this embodiment, can be as follows: Figure 14 As shown. Specifically, an implementable decoding workflow can be as follows:

[0220] S1401: Obtain hard read data y0 and soft data R; assign the hard read data to the codeword to be decoded y (y = y0); and buffer the soft data; the iteration count is 0; here, y0 is... Figure 13 In this context, d and y are equivalent to v in 13.

[0221] S1402: Generate a checksum vector using the parity-check matrix and the codeword to be decoded; and determine whether the checksum vector is a zero vector (i.e., H*y). T=0?); If yes, execute S1403; if no, execute S1404;

[0222] S1403: Output the codeword to be decoded after successful decoding, and end the process;

[0223] S1404: Determine if the number of iterations has reached the maximum number of iterations; if yes, proceed to S1305; if no, proceed to S1406.

[0224] S1405: Outputs a decoding failure indication signal; for example, a first stop decoding signal.

[0225] S1406: Calculate the number of bits in the codeword to be decoded that do not meet the check criteria using the f2 formula;

[0226] S1407: Determine the features in the codeword to be decoded that need to be flipped based on the number of non-compliant check items and the flipping criteria;

[0227] S1408: Increment the iteration count by 1 and proceed to the next iteration. Continue executing S1402 to S1408 in sequence until decoding is successful or fails, then end the process.

[0228] It should be noted that the methods for obtaining hard read data and soft data in step S1401 have already been described above. That is, hard read data can be directly received from the feedback of the memory device or obtained from the memory of the memory controller; soft data can be cached in the decoder's cache module and then obtained from the cache module. The above steps are only one implementation of this decoding workflow. The execution order of each step can be adjusted according to the actual situation. For example, S1404 can be performed before S1402, first determining whether the number of iterations has reached the maximum number of iterations. If the maximum number of iterations has not been reached, then a checksum vector is generated using the check matrix and the codeword to be decoded; otherwise, a decoding failure indication signal is output, and the process ends.

[0229] The decoder provided in this embodiment applies soft data to LDPC bit-flipping (i.e., hard decision) decoding, and utilizes the strong error correction capability of soft data to speed up LDPC bit-flipping decoding, so as to reduce the power consumed by LDPC bit-flipping decoding and improve the error correction throughput of the decoder.

[0230] This disclosure also provides a decoding method, such as... Figure 15 As shown, it includes:

[0231] S1501: Obtain the soft data corresponding to the codeword to be decoded;

[0232] S502: When performing hard-decision decoding on the codeword to be decoded, the number of bits in the codeword to be decoded that do not meet the check is determined using the soft data assistance at least in the first flip iteration.

[0233] In some embodiments, the step of using the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes:

[0234] Determine the initial error bit indication vector corresponding to the codeword to be decoded;

[0235] The soft data is used to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0236] In some embodiments, the step of using the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes:

[0237] Determine the soft data vector corresponding to the soft data;

[0238] The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector.

[0239] The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit vector.

[0240] Each element in the target error bit vector corresponds to the number of non-compliance checks for one bit.

[0241] In some embodiments, determining the initial error bit indication vector corresponding to the codeword to be decoded includes:

[0242] Receive hard read data and generate the codeword to be decoded based on the hard read data;

[0243] The checksum vector is determined based on the codeword to be decoded and the pre-constructed check matrix;

[0244] The initial error bit indication vector corresponding to the codeword to be decoded is determined based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

[0245] In some embodiments, determining the initial error bit indication vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix includes:

[0246] The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation.

[0247] Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector;

[0248] The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

[0249] In some embodiments, the method further includes:

[0250] Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped.

[0251] The bits that need to be flipped in the codeword to be decoded are flipped according to the flipping indicator vector.

[0252] In some embodiments, the flipping criterion includes:

[0253] Flip the bit with the largest number of non-checking bits in the codeword to be decoded.

[0254] Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

[0255] In some embodiments, the method further includes:

[0256] The number of iterations for performing hard decision on the codeword to be decoded is counted;

[0257] Determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector;

[0258] When the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, a first stop decoding signal is output; the first stop decoding signal is configured to indicate that the hard-decision decoding of the codeword to be decoded has failed.

[0259] In some embodiments, the method further includes:

[0260] Determine whether the checksum vector is a zero vector; if the checksum vector is determined to be a zero vector, output a second stop decoding signal;

[0261] In response to the second stop decoding signal, the codewords to be decoded are rearranged, and the codewords to be decoded in the correct order are output.

[0262] In some embodiments, the method further includes:

[0263] When the checksum vector is not zero and the number of iterations has not reached the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to indicate that a hard decision decoding operation is performed on the codeword to be decoded.

[0264] It should be noted that the decoding method provided in this embodiment is actually the workflow of the decoder described above. The workflow of the decoder has already been described in detail above; the terms and features mentioned herein can be found in the foregoing description and will not be repeated here.

[0265] This disclosure also provides a memory controller 1600, such as... Figure 16 As shown, it includes: a processor 1601 and a decoder 700 as described in any of the above claims, wherein the processor 1601 is configured to: read soft data corresponding to the codeword to be decoded from the memory device;

[0266] The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine, at least in the first flip iteration, the number of bits in the codeword to be decoded that do not meet the check.

[0267] It should be noted that the memory controller provided in this embodiment includes the aforementioned decoder. Therefore, the terms and features of the decoder have been described in detail above and will not be repeated here.

[0268] This disclosure also provides a memory system, including:

[0269] A memory device configured to store data;

[0270] A memory controller, coupled to the memory device, includes a processor and a decoder; wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device;

[0271] The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine, at least in the first flip iteration, the number of bits in the codeword to be decoded that do not meet the check.

[0272] In some embodiments, the processor is further configured to: read hard read data from the memory device; and send the hard read data to the decoder.

[0273] The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded based on the hard read data.

[0274] In some embodiments, the decoder includes: a buffer module, a variable node module, a check node module, and a flip indicator module, wherein;

[0275] The cache module is configured to cache the soft data read by the processor;

[0276] The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded based on the hard read data; and send the codeword to be decoded to the verification node module.

[0277] The verification node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector based on the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indicator module.

[0278] The flip indicator module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit vector in determining the number of bits in the codeword to be decoded that do not meet the check.

[0279] It should be noted that the memory system provided in the embodiments of this disclosure includes the memory controller and the decoder included in the memory controller described above. Therefore, the various related terms and features described herein can be referred to in the foregoing description, and will not be repeated here.

[0280] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A decoder, characterized in that, include: The cache module and the flip indicator module, wherein; The caching module is configured to cache soft data related to the codeword to be decoded; The flip indication module is configured to: obtain the soft data from the cache module; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine the number of bits in the codeword to be decoded that do not meet the check. The number of bits in the decoded codeword that do not meet the check is calculated based on the hard read data and the soft data.

2. The decoder according to claim 1, characterized in that, The flip indicator module is further configured to: Determine the initial error bit indication vector corresponding to the codeword to be decoded; The soft data is used to assist the initial error bit indication vector in determining the number of bits in the codeword to be decoded that do not meet the check.

3. The decoder according to claim 2, characterized in that, The decoder further includes a variable node module and a check node module, wherein the variable node module and the check node module are connected according to a pre-constructed check matrix to form a variable-check connection network; wherein, The variable node module is configured to: receive the hard read data and generate the codeword to be decoded based on the hard read data; send the codeword to be decoded to the verification node module; and send the codeword to be decoded and the hard read data to the flip indicator module. The verification node module is configured to: receive the codeword to be decoded; determine a checksum vector based on the codeword to be decoded and the check matrix; and send the checksum vector to the flip indication module. The flip indicator module is further configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; and determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix.

4. The decoder according to claim 2, characterized in that, The flip indicator module is further configured to: Determine the soft data vector corresponding to the soft data; The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector. The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit indication vector. Each element in the target error bit indication vector corresponds to the number of non-compliance checks for one bit.

5. The decoder according to claim 3, characterized in that, The flip indicator module is further configured to: The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation. Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector; The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

6. The decoder according to claim 3, characterized in that, The flip indicator module is further configured to: Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped. The variable node module is further configured to: receive the flip instruction vector, and flip the bits that need to be flipped in the codeword to be decoded according to the flip instruction vector.

7. The decoder according to claim 6, characterized in that, The flipping criteria include: Flip the bit with the largest number of non-checking bits in the codeword to be decoded. Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

8. The decoder according to claim 3, wherein, The decoder further includes: a counting module and a termination decision module, wherein, The counting module is configured to: count the number of iterations for performing hard decision on the codeword to be decoded; The termination decision module is configured to: determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector; when the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, output a first stop decoding signal; the first stop decoding signal is configured to indicate that the hard-decision decoding of the codeword to be decoded has failed.

9. The decoder according to claim 8, characterized in that, The decoder further includes: a rearrangement module; The termination decision module is further configured to: output a second stop decoding signal when the checksum vector is determined to be a zero vector; The rearrangement module is configured to: in response to the second stop decoding signal, rearrange the codewords to be decoded; and output the codewords to be decoded in the correct order.

10. The decoder according to claim 9, characterized in that, The termination decision module is further configured to output a continue decoding signal when the checksum vector is not zero and the number of iterations has not reached the maximum number of iterations; the continue decoding signal is configured to instruct the variable node module, the check node module and the flip indicator module to continue performing hard decision decoding on the codeword to be decoded.

11. A decoding method, characterized in that, include: Obtain the soft data corresponding to the codeword to be decoded; When performing hard-decision decoding on the codeword to be decoded, the number of bits in the codeword to be decoded that do not meet the check is determined using the soft data at least in the first flip iteration; the number of bits in the decoded codeword that do not meet the check is calculated based on the hard read data and the soft data.

12. The decoding method according to claim 11, characterized in that, The step of using the soft data to assist in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes: Determine the initial error bit indication vector corresponding to the codeword to be decoded; The soft data is used to assist the initial error bit indication vector in determining the number of bits in the codeword to be decoded that do not meet the check.

13. The decoding method according to claim 12, characterized in that, The step of using the soft data to assist the initial error bit indication vector in determining the number of bits in the codeword to be decoded that do not meet the check criteria includes: Determine the soft data vector corresponding to the soft data; The soft data vector is summed with the initial error bit indicator vector to obtain the target error bit indicator vector. The number of bits in the codeword to be decoded that do not meet the check is determined based on the target error bit indication vector. Each element in the target error bit indication vector corresponds to the number of non-compliance checks for one bit.

14. The decoding method according to claim 12, characterized in that, Determining the initial error bit indication vector corresponding to the codeword to be decoded includes: Receive the hard read data and generate the codeword to be decoded based on the hard read data; The checksum vector is determined based on the codeword to be decoded and the pre-constructed check matrix; The initial error bit indication vector corresponding to the codeword to be decoded is determined based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix.

15. The decoding method according to claim 14, characterized in that, The step of determining the initial error bit indication vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector, and the check matrix includes: The first bit vector is obtained by performing a summation operation between the hard read data and the codeword to be decoded, followed by taking the modulo operation. Multiply the transpose of the checksum vector by the check matrix to obtain the second bit vector; The first bit vector and the second bit vector are summed to obtain the initial error bit indicator vector.

16. The decoding method according to claim 11, characterized in that, The method further includes: Based on the number of non-compliant checks and the flipping criterion, a flipping indication vector is generated; the flipping indication vector contains the bits in the codeword to be decoded that need to be flipped. The bits that need to be flipped in the codeword to be decoded are flipped according to the flipping indicator vector.

17. The decoding method according to claim 16, characterized in that, The flipping criteria include: Flip the bit with the largest number of non-checking bits in the codeword to be decoded. Alternatively, the bits in the codeword to be decoded that do not meet the verification check if the number is greater than or equal to a preset threshold are flipped.

18. The decoding method according to claim 13, characterized in that, The method further includes: The number of iterations for performing hard decision on the codeword to be decoded is counted; Determine whether the number of iterations has reached the maximum number of iterations and whether the checksum vector is a zero vector; When the number of iterations reaches the maximum number of iterations and the checksum vector is a non-zero vector, a first stop decoding signal is output; the first stop decoding signal is configured to indicate that the hard-decision decoding of the codeword to be decoded has failed.

19. The decoding method according to claim 18, characterized in that, The method further includes: Determine whether the checksum vector is a zero vector; if the checksum vector is determined to be a zero vector, output a second stop decoding signal; In response to the second stop decoding signal, the codewords to be decoded are rearranged, and the codewords to be decoded in the correct order are output.

20. The decoding method according to claim 19, characterized in that, The method further includes: When the checksum vector is not zero and the number of iterations has not reached the maximum number of iterations, a continue decoding signal is output; the continue decoding signal is configured to indicate that a hard decision decoding operation is performed on the codeword to be decoded.

21. A memory controller, characterized in that, include: The processor and the decoder according to any one of claims 1 to 10, wherein the processor is configured to read soft data corresponding to the codeword to be decoded from a memory device; The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine the number of bits in the codeword to be decoded that do not meet the check; The number of bits in the decoded codeword that do not meet the check is calculated based on the hard read data and the soft data.

22. A memory system, characterized in that, include: A memory device configured to store data; A memory controller, coupled to the memory device, includes a processor and a decoder; wherein the processor is configured to read soft data corresponding to a codeword to be decoded from the memory device; The decoder is configured to: cache the soft data; and, when performing hard-decision decoding on the codeword to be decoded, use the soft data to help determine the number of bits in the codeword to be decoded that do not meet the check, at least in the first flip iteration; the number of bits in the decoded codeword that do not meet the check is calculated based on the hard read data and the soft data.

23. The memory system according to claim 22, characterized in that, The processor is further configured to: read the hard read data from the memory device; and send the hard read data to the decoder. The decoder is further configured to: receive the hard read data; and generate the codeword to be decoded based on the hard read data.

24. The memory system according to claim 23, characterized in that, The decoder includes: a buffer module, a variable node module, a check node module, and a flip indicator module, wherein; The cache module is configured to cache the soft data read by the processor; The variable node module is configured to: receive the hard read data read by the processor; generate the codeword to be decoded based on the hard read data; and send the codeword to be decoded to the verification node module. The verification node module is configured to: receive the codeword to be decoded sent by the variable node module; determine a checksum vector based on the codeword to be decoded and a pre-constructed check matrix; and send the checksum vector to the flip indicator module. The flip indicator module is configured to: receive the codeword to be decoded and the hard read data sent by the variable node module; and receive the checksum vector sent by the check node module; obtain the check matrix and the soft data; determine the initial error bit indicator vector corresponding to the codeword to be decoded based on the hard read data, the codeword to be decoded, the checksum vector and the check matrix; and use the soft data to assist the initial error bit indicator vector in determining the number of bits in the codeword to be decoded that do not meet the check.

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