Information processing method based on coupled code, and communication apparatus

Abstract

The present application provides an information processing method based on a coupled code, and a communication apparatus. The method comprises: dividing first information bits into C first blocks, the C first blocks having the same length; and performing coupled encoding on the basis of the C first blocks to obtain a codeword sequence, wherein a parity bit corresponding to an i-th first block among the C first blocks is obtained on the basis of information bits of the i-th first block and information bits of a first blocks, i being an integer greater than or equal to 2, a being an integer greater than or equal to 1, and C being an integer greater than or equal to 2. In the method, coupled encoding is performed on the C first blocks obtained by dividing the first information bits, thereby filling the gap for the first information bits in a coupled encoding scheme; moreover, by using the characteristics of coupled encoding, the i-th first block and the a first blocks are encoded on the basis of a coupling relationship, thereby improving the encoding and decoding performance of each first block.

Description

A method and communication device for information processing based on coupling codes

[0001] This application claims priority to Chinese Patent Application No. 202411752530.1, filed on November 30, 2024, entitled "An Information Processing Method and Communication Device Based on Coupled Code", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding. More specifically, it relates to an information processing method and communication apparatus based on coupling codes. Background Technology

[0003] In the field of channel coding, low-density parity-check (LDPC) codes and polar codes are mature and widely used channel coding schemes, theoretically approaching the Shannon limit and with decoding performance very close to the Shannon line. However, due to non-ideal factors such as implementation complexity, achieving higher throughput and better performance in encoding and decoding remains a hot research topic. Among these, coupled codes, as a coding technique, have advantages over independent codes in terms of throughput, decoding, and other aspects. Summary of the Invention

[0004] This application provides an information processing method based on coupling codes, aiming to improve the encoding and decoding performance of transport blocks.

[0005] In the first aspect, a coupling code-based encoding method is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0006] The method includes: dividing the first information bit into C first blocks, all of which have the same length; performing coupled encoding based on the C first blocks to obtain a codeword sequence, wherein the check bit corresponding to the i-th first block in the C first blocks is obtained based on the information bit of the i-th first block and the information bits corresponding to a first blocks, i is an integer greater than or equal to 2, a is an integer greater than or equal to 1, and C is an integer greater than or equal to 2.

[0007] For example, the first information bit is a transport block (TB) level information bit.

[0008] For example, the first block can be a code block or a spatially coupled block.

[0009] It should be understood that the partitioning in this application can be direct or indirect. One implementation of direct partitioning is to divide the bits in the first information bit or read the bits in the first information bit to obtain C first code blocks; another implementation of indirect partitioning is to first divide the first information bit into other blocks (e.g., S second blocks), and then divide the other blocks to obtain C first blocks.

[0010] It should also be understood that the method provided in this application is adapted to coupled codes such as coupled LDPC codes and coupled polar codes.

[0011] According to the method provided in this application, by coupling and encoding the C first blocks obtained by dividing the first information bits, the blanks of the first information bits in the coupling encoding scheme are filled. At the same time, by utilizing the characteristics of coupling encoding, the i-th first block and a first blocks are no longer encoded independently, but are encoded according to the coupling relationship, thereby further improving the encoding and decoding performance of each first block.

[0012] In conjunction with the first aspect, in some possible implementations, dividing the first information bit into C first blocks includes: dividing the first information bit into S second blocks, where the lengths of the S second blocks are all the same and S is a positive integer; and dividing the S second blocks into C first blocks, where each of the C first blocks includes a CRC bit.

[0013] For example, when the first information bit is divided into C first blocks, it can be an indirect division. The first information bit can first be divided into S second blocks, and then the S second blocks can be divided into C first blocks.

[0014] In conjunction with the first aspect, in some possible implementations, under the condition of satisfying the first condition, the S second blocks are divided into C first blocks, wherein the i-th second block is divided into s iThe first condition is determined based on a first value, a first expansion factor, and the length of the i-th second block. The first value is the number of non-parity columns in the base matrix corresponding to each first block (predefined). The first expansion factor belongs to at least one predefined expansion factor. Each expansion factor corresponds to a number of padding bits. The number of padding bits corresponding to the first expansion factor is the minimum of the number of padding bits corresponding to each expansion factor among the at least one expansion factor. The first padding bits are used to pad the i-th second block so that the length of the padded i-th second block is divisible by si, and to pad each of the si first blocks so that the padded first block is divisible by the first expansion factor.

[0015] For example, the number of first blocks in each of the S second blocks can be the same.

[0016] Based on the above scheme, the first condition is that the expansion factor can be determined to be a large value, thereby reducing the number of padding blocks in the first block and improving decoding performance.

[0017] In conjunction with the first aspect, in some possible implementations, the first condition satisfies: P2≤k·P1, where P2 is the number of the first padding bits determined based on the first expansion factor and the length of the i-th second block, P1 is the number of the second padding bits determined based on the length of the first information bit and the second expansion factor, the second expansion factor is determined based on the length of the first information bit, the number of information columns included in the base matrix corresponding to the coupling code, and the first expansion factor, k is a positive number less than 1, and P1 and P2 are both positive integers.

[0018] It should be understood that P1 refers to the number of bits padded in a single second block, and correspondingly, P2 refers to the number of bits padded in all first blocks within a single second block; that is, both P1 and P2 refer to the number of padded bits in a single second block. Alternatively, P1 refers to the number of bits padded in all second blocks, and correspondingly, P2 refers to the number of bits padded in all first blocks within all second blocks; that is, both P1 and P2 refer to the number of padded bits in all second blocks.

[0019] In conjunction with the first aspect, in some possible implementations, C is based on the length of the first information bit and the maximum length supported by the code block. The length of the first information bit, the K CB,MAX The L represents the maximum length supported by the code block, si represents the number of first blocks included in the i-th second block, and L represents the maximum length supported by the code block. CB,CRCLet si, K represent the number of CRC bits included in the first block (C blocks). TB,CRC K CB,MAX All are positive integers.

[0020] In conjunction with the first aspect, in some possible implementations, the first information bit includes a Cyclic Redundancy Check (CRC) bit.

[0021] For example, the CRC bit in the first information bit can be located at any position at the beginning, end, or middle of the first information bit.

[0022] For example, the CRC bits in the first information bit can be at the code block (CB) level or at the scblock level.

[0023] In conjunction with the first aspect, in some possible implementations, when the first information bit cannot be evenly divided into S second blocks, L1 bits are padded to the first information bit to obtain a second information bit, the information bit length of the second information bit being divisible by S, where L1 is an integer; the second information bit is then divided into S second blocks.

[0024] In conjunction with the first aspect, in some possible implementations, L1 is determined based on the length of the first information bit and S.

[0025] In conjunction with the first aspect, in some possible implementations, L1 satisfies: L1 = S - mod(K) TBCRC ,S),K TB,CRC This indicates the length of the first information bit.

[0026] In conjunction with the first aspect, in some possible implementations, the L1 bits are located at any position at the beginning, end, or middle of the second information bits.

[0027] In conjunction with the first aspect, in some possible implementations, when the first information bit cannot be evenly divided into C first blocks, dividing the first information bit into C first blocks includes: filling the first information bit with L2 bits to obtain a third information bit, wherein the information bit length of the third information bit is divisible by C, and L2 is an integer; and dividing the third information bit into C first blocks.

[0028] In conjunction with the first aspect, in some possible implementations, the L2 is determined based on the length of the first information bit and C.

[0029] In conjunction with the first aspect, in some possible implementations, L2 = C - mod (K) TBCRC C), KTB,CRC This indicates the length of the first information bit.

[0030] In conjunction with the first aspect, in some possible implementations, the L2 bits are located at any position at the beginning, end, or middle of the third information bit.

[0031] In conjunction with the first aspect, in some possible implementations, the coupled encoding based on C first blocks to obtain a codeword sequence includes: determining the size L3 of the padding bits according to the information bit length and the second value of the first block, where L3 is an integer, the second value is determined according to a first expansion factor and a first value, and the first value is a predefined number of non-parity columns in the base matrix corresponding to each first block; and padding each of the C first blocks according to the L3 to obtain C fourth blocks.

[0032] In conjunction with the first aspect, in some possible implementations, L3 satisfies: L3 = b * ZK SCB#1 K SCB#1 b*Z represents the current information bit length of the first block, b*Z represents the second value, and Z represents the first expansion factor.

[0033] In conjunction with the first aspect, in some possible implementations, the L3 padding bits are located at any position at the beginning, end, or middle of each of the C fourth blocks.

[0034] In conjunction with the first aspect, in some possible implementations, the C fourth blocks include the nth fourth block and the mth fourth block, where m and n are both integers. The coupling encoding based on the C fourth blocks to obtain the codeword sequence includes: coupling encoding based on the information bits of the nth fourth block and the corresponding information bits and check bits of the N fourth blocks to obtain the check bit corresponding to the nth fourth block; and / or coupling encoding based on the information bits of the mth fourth block and the corresponding information bits of the M fourth blocks to obtain the check bit corresponding to the mth fourth block, where N and M are both integers.

[0035] In conjunction with the first aspect, in some possible implementations, each of the C first blocks is used to determine at least one CRC check bit.

[0036] In conjunction with the first aspect, in some possible implementations, C fifth blocks are obtained by coupling encoding C first blocks, the number of holes in the b-th fifth block in the codeword sequence is different from the number of holes in the c-th fifth block, where b and c are both integers, and the fifth block is obtained by coupling encoding the first block.

[0037] Based on the above scheme, the punching method provided in this application is for the fifth block. The number of punches corresponding to each fifth block is different, that is, the punching position corresponding to each fifth block is different. By punching the fifth block, the encoding performance of the coupling code can be improved.

[0038] In conjunction with the first aspect, in some possible implementations, C fifth blocks are obtained by coupling encoding C first blocks, with each of the C fifth blocks serving as input for bit interleaving; or, the first bit sequence is obtained by coupling encoding the first information bits, with the first bit sequence serving as input for bit interleaving; or, S sixth blocks are obtained by coupling encoding S second blocks, with each of the S sixth blocks serving as input for bit interleaving, and the S second blocks comprising C first blocks.

[0039] In conjunction with the first aspect, in some possible implementations, the coupling encoding based on C first blocks to obtain a codeword sequence includes: coupling encoding based on C first blocks and a third block, wherein the third block consists of parity bits, the parity bits of the third block are obtained based on the information bits and parity bits corresponding to d fifth blocks out of C fifth blocks, and / or, the parity bits of the third block are obtained based on the information bits corresponding to d fifth blocks out of C fifth blocks, the length of the third block is determined according to the encoding coupling degree, where d is a positive integer, and wherein C fifth blocks are obtained by coupling encoding C first blocks.

[0040] In a second aspect, a communication apparatus is provided for performing the method provided in the first aspect or its implementation. Specifically, the apparatus may include units and / or modules for performing the method provided in the first aspect or its implementation, such as processing units and / or transceiver units.

[0041] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0042] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0043] Thirdly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in the first aspect or its implementation.

[0044] In one implementation, the device is either a transmitting device or a receiving device.

[0045] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0046] Fourthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in the first aspect or its implementation thereof. The communication interface may be implemented in hardware or software.

[0047] In one implementation, the device further includes the memory.

[0048] Fifthly, a processor is provided for executing the methods provided in the above aspects.

[0049] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0050] In a sixth aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing the methods provided in the first aspect or its implementations described above.

[0051] In a seventh aspect, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in the first aspect or its implementation.

[0052] Eighthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the method provided in the first aspect or its implementation thereof. The communication interface can be implemented in hardware or software.

[0053] Optionally, as one implementation, the chip also includes a memory storing computer programs or instructions, and a processor for executing the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the method provided by the first aspect or its implementation described above.

[0054] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0055] Ninthly, a computer program is provided that, when run on a computer, causes the method provided in the first aspect or its implementation to be executed.

[0056] In a tenth aspect, a communication system is provided, including the transmitting end device described above. Attached Figure Description

[0057] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0058] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0059] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0060] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0061] Figure 5 is a schematic diagram of the information transmission process.

[0062] Figure 6 is a schematic flowchart of LDPC encoding.

[0063] Figure 7 is a schematic flowchart of an information processing method based on a coupling code provided in an embodiment of this application.

[0064] Figure 8 is a schematic diagram of a coupling method provided in an embodiment of this application.

[0065] Figure 9 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application.

[0066] Figure 10 is a schematic block diagram of the communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0067] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0068] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0069] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0070] The following describes a communication system to which embodiments of this application can be applied.

[0071] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0072] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0073] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0074] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0075] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication networks. A base station may support networks with the same or different access technologies, without limitation.

[0076] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0077] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0078] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0079] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0080] To facilitate understanding of the solutions in this application, the terminology used in this application will be introduced first.

[0081] 1. LDPC code

[0082] LDPC codes are linear block codes with a sparse parity-check matrix. When the code length is long, the number of zero elements in the LDPC parity-check matrix far exceeds the number of non-zero elements; in other words, the row and column weights of the parity-check matrix are very small compared to the LDPC code length. Specifically, an LDPC code with an information bit sequence of length k and a code length of n can be uniquely determined by its parity-check matrix or generator matrix. This information bit sequence can be the payload bit sequence or a bit sequence with added cyclic redundancy check (CRC) bits; this application does not impose any limitation on this.

[0083] In 1981, Tanner represented the codewords of LDPC using a graph, now known as a Tanner graph. Tanner graphs correspond one-to-one with parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity-check nodes, representing parity-check constraints. Each parity-check node represents a parity-check constraint, which will be explained below with reference to Figures 1 and 2.

[0084] Figure 2 is a schematic diagram of the parity check matrix H of LDPC.

[0085] In Figure 2, {Vi} represents the set of variable nodes, and {Ci} represents the set of parity nodes. Each row of the parity-check matrix H represents a parity-check equation, and each parity-check equation corresponds to a parity-check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 1, there are 8 variable nodes and 4 parity nodes. If a codeword bit is included in the corresponding parity-check equation, a line is used to connect the involved variable nodes and parity nodes to obtain the Tanner graph.

[0086] Figure 3 is a Tanner plot of the parity-check matrix H of LDPC.

[0087] As shown in Figure 3, the Tanner graph represents the parity check matrix of the LDPC. For example, for a parity check matrix H of size M rows and N columns, the Tanner graph contains two types of nodes: N variable nodes and M parity nodes. The N variable nodes correspond to the N columns of the parity check matrix H, and the M parity nodes correspond to the M rows of the parity check matrix H. The loops in the Tanner graph consist of interconnected vertices, with one vertex serving as both the start and end point, and each loop traversing each node only once. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which is equivalent to each codeword bit in the LDPC; the parity nodes in the Tanner graph correspond to each row of the parity check matrix H, which is equivalent to each parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. For example, if there is a connection between the i-th parity node and the j-th variable node, the element (i,j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between the variable nodes and the parity nodes can also be called an edge. There is a connection between the verification node and the variable node, which can also be described as: there is a connection relationship between the verification node and the variable node.

[0088] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0089] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC. When the code length is long, the parity-check matrix H of an LDPC can be very large; therefore, H is usually represented in blocks: the complete parity-check matrix H is considered as multiple Z... c ×Z c The complete parity check matrix H is generated from a submatrix. Specifically, the complete parity check matrix H can be generated from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrices, each of which can be represented by a single cyclically shifted bit, greatly reduce the storage space required for the complete parity check matrix H. The exponential matrix H... b The elements in it can also be called quasi-cyclic (QC) blocks.

[0090] Based on the exponential matrix H b And increase size Z c (lifting size) can be used to transform the exponential matrix H b Expanded into a complete parity-check matrix H for encoding or decoding. Zc (lifting size) can also be called expansion factor, lifting factor, lifting value, expansion value, expansion coefficient, etc. In this application, the lifting value is used as the description.

[0091] For example, the exponent matrix H of a QC-LDPC of size m*n b As shown below:

[0092] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, with elements Let Z represent the cyclic permutation matrix, where i represents the cyclic shift value, and 0 ≤ i ≤ Z. c -1, where i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0093] Here, Z is used. c =4. Taking i=0 / 1 / 2 / 3 as an example, let's illustrate circular shift. They are shown below:

[0094] For example, the exponent matrix H b In addition to using "-1" to represent zero elements, there are other ways to represent them, such as using "-" or null values ​​to represent a matrix of all zeros.

[0095] 3. Spatially Coupled Low Density Parity Check (SC-LDPC) Code

[0096] The parity check matrix H of SC-LDPC sc As shown below:

[0097] Among them, H sc It is constructed by coupling L groups of sub-codes (sub-codes or sub-matrices). Each group of sub-codes in the L groups is identical, and each group of sub-codes in the L groups includes w+1 sub-codes, which can be represented as H0, H1, ..., H w Each subcode H i Given an M*N matrix, we can derive H from this. sc The size of the matrix is ​​[M*(w+L)]*(N*L). Here, L is called the coupling length, and w is called the coupling width (or coupling depth).

[0098] For example, each subcode H i The construction can be referenced to the parity matrix H shown in Figure 1.

[0099] Specifically, if the w+1 subcodes in each group of L subcodes are the same, it is called a time-invariant SC-LDPC code; if the w+1 subcodes in each group of L submatrices are different, it is called a time-varying SC-LDPC code.

[0100] It should be understood that the parity-check matrix of the above SC-LDPC code, when expanded, yields matrix H. SC-LDPC H SC-LDPC The size is [M(w+L)·Z]×(NL·Z), and the corresponding offset matrix can be denoted as... P SC Each element p in i,j To satisfy p i,j Integers ≥-1. If p i,j =-1, it can be expanded into a zero matrix of size Z×Z; otherwise, it can be expanded into a cyclic shift matrix of size Z×Z identity matrix, p i,j This indicates the amount of cyclic displacement to the right.

[0101] To ensure H SC-LDPC The decoding performance is usually in this H sc A tail check matrix I is introduced in the lower right corner of the matrix, where I is an m0×m0 square matrix. Matrix I can be an identity matrix or a lower triangular matrix, and can be represented as:

[0102] 4. Quasi-cyclic spatially-coupled low-density parity check (QC SC-LDPC) code

[0103] The QC SC-LDPC verification matrix B is shown below:

[0104] Here, B is constructed by coupling L groups of sub-codes. Each group of sub-codes in the L groups of sub-matrices is identical, and each group of sub-codes in the L groups of sub-codes includes w+1 sub-codes, which can be represented as B0, B1, ..., B w Each subcode B i Given an m*n matrix, we can derive H from this. sc The size of the matrix is ​​[m*(w+L)]*(n*L). Here, L is called the coupling length, and w is called the coupling width (or coupling depth).

[0105] In the verification matrix B, each column B0, B1, ..., B w Or it can be expressed as Where t = 0, 1, ..., L represents w+1 sub-BG blocks of size m*n at time t, and all BG blocks at time t can be considered as one SC block.

[0106] For example, each subcode B i The construction can refer to the exponential matrix H of QC-LDPC of size m*n shown above. b .

[0107] Specifically, if the w+1 subcodes in each group of L subcodes are the same, it is called a time-invariant QC SC-LDPC code; if the w+1 subcodes in each group of L subcodes are different, it is called a time-varying QC SC-LDPC code.

[0108] It should be understood that the matrix obtained after expanding the QC SC-LDPC code is similar to the SC-LDPC code described above, as detailed in the above description.

[0109] It should also be understood that SC-LDPC codes, QC SC-LDPC codes, globally coupled (GC)-LDPC codes, and coupled polar codes, etc., are all coupled codes and are applicable to the methods provided in this application.

[0110] 5. Non-zero elements and zero elements

[0111] In this application, zero elements in the check matrix indicate that there is no connection between the variable node and the check node. Non-zero elements in the check matrix indicate that there is a connection between the variable node and the check node.

[0112] This application does not limit the specific representation of zero and non-zero elements. For example, in the exponential matrix H b In a matrix, "-1" can be used to represent zero elements, and "non-negative value" can be used to represent non-zero elements. Similarly, in a parity check matrix H, "0" can be used to represent zero elements, and "1" can be used to represent non-zero elements.

[0113] For ease of description, the following text will use "0" to represent zero elements and "1" to represent non-zero elements.

[0114] 6. Column weight and row weight

[0115] For a column of a matrix, column weight refers to the number of non-zero elements in that column. For a row of a matrix, row weight refers to the number of non-zero elements in that row. For example, as shown in Figure 1, the column weight of the first column of the parity matrix H is 2, and the row weight of the first row is 4. Another example is the exponent matrix H mentioned above. b The column weight of the first column is 4, and the row weight of the first row is 20.

[0116] 7. Basic Structure of the Check Matrix

[0117] As shown in Figure 4(1), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(1), where part A corresponds to information bits (or information digits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). Part B can also be the region corresponding to parity columns with a column weight greater than 1. The all-zero region can correspond to part C in Figure 4(2) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(2). The raptor-like region can correspond to part E in Figure 4(2) and can be an identity matrix or a lower triangular matrix, corresponding to the parity bits of the low-rate extension.

[0118] The LDPC code shown in Figure 4 uses a "raptor-like" base matrix, which can be gradually extended from a high-rate kernel matrix to a low-rate matrix, thus flexibly supporting encoding at various rates. In practical use, as shown in (1) of Figure 4, the first X rows and the first Y columns of the parity check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. The difference between X and Y is the number of information columns.

[0119] 8. Information Transmission Process

[0120] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is sent from the source and undergoes processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Specifically, the processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the sending end (i.e., the coding device described below), while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end (i.e., the decoding device described below).

[0121] The embodiments of this application mainly involve source coding, channel coding, channel decoding, and source recovery as shown in Figure 5.

[0122] 9. LDPC code encoding process

[0123] Figure 6 shows an encoding rule for an LDPC code. The method shown in Figure 6 can be applied to an encoding-side device or a chip, functional unit, or circuit within that device. This encoding-side device can be considered a transmitting device, which can be a network device or a terminal device. The method shown in Figure 6 uses an encoding-side device as an example.

[0124] As shown in Figure 6, the encoding process may include the following steps:

[0125] Step 6-1: The encoding-side device performs TB-CRC addition on the acquired information bit k to be encoded;

[0126] For example, the encoding-side device receives information bit k and adds a length of L to information bit k. TBCRC The padding bits, which can be understood as cyclic redundancy check (CRC) bits, are added to the information bit k after TB-CRC to obtain a length of K. TBCRC Total information bits.

[0127] For example, the K TBCRC This can be understood as the length of the current transport block (TB).

[0128] Step 6-2: The encoding-side device performs code block segmentation on the information bits;

[0129] For example, after adding TB-CRC to the information bits k to be encoded in step 6-1 above, the total information bits K are obtained. TBCRC The encoding device is based on the K TBCRC With the length of the maximum information bits supported by each code block (K) CB,max The size relationship between the bits determines whether the total information bits need to be divided into code blocks.

[0130] As an example, suppose K TBCRC ≤K CB,max Then the encoding-side device does not need to perform code block segmentation on the total information bits, that is, it does not need to execute step 6-2. The encoding-side device will divide the total information bits K TBCRC Treat it as a CB and proceed to step 6-5 to encode it using an LDPC parity-check matrix.

[0131] As another example, suppose K TBCRC >K CB,max Then the encoding device has a total of K information bits. TBCRC Perform code block segmentation.

[0132] Specifically, the encoding-side device will use the total information bits K TBCRC The code is uniformly divided into A code blocks (CBs), where the sum of the information bits corresponding to the A CBs equals K. TBCRCIn the A CBs, each CB contains the same number of information bits, where A is an integer greater than or equal to 2. Specifically, in K... TBCRC If the value is not divisible by A, step 6-3 must be executed before step 6-2.

[0133] For example, the value of A could be: Where L CB,CCRC This indicates the number of CRC bits that will be filled in each code block, such as 16 information bits or 24 information bits. Wherein, this L... CB,CCRC The size can be predetermined by the system or protocol, or pre-configured.

[0134] Step 6-3: The encoding side device processes the total information bits K TBCRC Perform bit stuffing (or TB stuffing).

[0135] For example, the encoding-side device determines the total information bits K. TBCRC It cannot be uniformly divided into A code blocks CB, i.e., K TBCRC If it is not divisible by A, then the encoding device has a different value for K. TBCRC Perform TB filling so that K after TB filling TBCRC It is divisible by A. Therefore, K after being filled with TB... TBCRC It can be evenly divided into A CBs. In step 6-3, the number of information bits for which the encoding-side device performs TB padding on the total information bits is A - mod (K). TBCRC A).

[0136] Step 6-4: The encoding-side device adds CB-CRC to each of the A CBs.

[0137] For example, suppose the encoding-side device determines K TBCRC ≤K CB,max The encoding-side device does not need to perform step 6-4.

[0138] For example, suppose the encoding-side device determines K TBCRC >K CB,max The total information bits are divided into A CBs, and the encoding device adds a CRC of 16 or 24 information bits to each of the A CBs.

[0139] Optionally, the CB-CRC can be added to the end of each CB.

[0140] Step 6-5: The encoding side device performs bit stuffing on each CB.

[0141] For example, the encoding-side device determines K. TBCRC ≤K CB,max The encoding side device for the total information bits KTBCRC Bit stuffing is performed, wherein the encoding-side device stuffs the total information bits K TBCRC Consider it as a CB. The encoding-side device processes the total information bits K in step 6-5. TBCRC The bit stuffing process can be performed by traversing the lookup table of the expansion factor Z and performing bit stuffing on the total information bits K. TBCRC Bit stuffing continues until the length of the current stuffed information bits is divisible by an expansion factor in the expansion factor Z lookup table, at which point stuffing stops.

[0142] For example, the encoding-side device determines K. TBCRC >K CB,max The encoding device performs bit stuffing on each CB by executing steps 6-2 to 6-4 above. The bit stuffing process for each CB in step 6-5 can be achieved by traversing the lookup table of the expansion factor Z and stuffing bits on the CB until the length of the currently stuffed CB is divisible by an expansion factor in the lookup table of expansion factor Z, at which point stuffing stops.

[0143] Step 6-6: The encoding side device performs independent LDPC encoding on each CB to obtain the codeword sequence.

[0144] For example, on the encoding side device, the total information bits K TBCRC Or, after bit stuffing each of the A CBs, the information bit stuffed K TBCRC Alternatively, the length of each CB after information bit stuffing can be extended by an integer factor Z. The encoding device performs independent LDPC encoding on the total stuffed information bits / A CBs to obtain a codeword sequence.

[0145] It should be understood that the process of performing independent LDPC encoding for each CB can be found in the description of existing schemes, and will not be described in detail here.

[0146] Based on the method shown in Figure 6 above, it can be seen that in the encoding scheme, the encoding-side device uses independent LDPC encoding for each independent CB.

[0147] This application provides a coupling code-based encoding and decoding method that can improve the encoding and decoding characteristics of transport block (TB).

[0148] Figure 7 is a schematic flowchart of a coupled code-based encoding / decoding method 700 provided in this application. The method includes the following steps.

[0149] It is understood that method 700 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0150] 710, The sending device obtains the information bit sequence.

[0151] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0152] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0153] For example, the information bit sequence can be understood as the information bit sequence to be encoded, for example, the length of the information bit sequence to be encoded is k.

[0154] 720, The transmitting device determines the matrix corresponding to the coupling code.

[0155] For example, assuming the coupled code is a coupled LDPC code, the matrix corresponding to this coupled code can be a coupled LDPC matrix, such as the parity check matrix H of an SC-LDPC code. sc The parity-check matrix B of the QC-LDPC code, or the exponent matrix H of the QC-LDPC code. b However, this application does not limit this.

[0156] It should also be understood that this application does not impose any restrictions on the specific structural design of the matrix corresponding to the coupling code.

[0157] 730. The transmitting device performs coupling encoding on the information bit sequence according to the matrix corresponding to the coupling code to determine the codeword sequence.

[0158] It should be understood that after the transmitting device determines the matrix corresponding to the coupling code, it performs coupling encoding on the information bit sequence based on the matrix corresponding to the coupling code to obtain the codeword sequence.

[0159] For example, during the process of coupling and encoding the information bit sequence according to the matrix corresponding to the coupling code, the transmitting device can perform the following corresponding operations on the information bit sequence to be encoded obtained in step 710.

[0160] As an example, the transmitting device determines the first information bit based on the information bit sequence to be encoded. The transmitting device divides this first information bit into C first blocks, each of which is of equal length. The transmitting device then performs coupled encoding based on these C first blocks to obtain a codeword sequence. Here, C is an integer greater than or equal to 2.

[0161] It should be understood that the transmitting device can determine the first information bit in the following way:

[0162] Suppose that the length of the information bit sequence obtained by the transmitting device is greater than the maximum total information bit length supported by the coupling code, the first information bit determined by the transmitting device can be any one of the multiple first information bits obtained by uniformly dividing the third information bit.

[0163] The third information bit can be an information bit sequence obtained by padding the information bit sequence to be encoded with q padding bits. For example, if the information bit sequence to be encoded can be evenly divided into multiple first information bits, then the length of the third information bit sequence is the length of the information bit sequence to be encoded; or, if the information bit sequence to be encoded cannot be evenly divided into multiple first information bits, then q padding bits are added to the information bit sequence to be encoded to obtain the third information bit sequence, which can be evenly divided into multiple first information bits.

[0164] Where q = K SC,max -mod(K TBCRC K SC,max K SC,max K represents the maximum total information length supported by the coupled code. TB,CRC Indicates the length of the first information bit.

[0165] Furthermore, assuming that the length of the information bit sequence acquired by the transmitting device is less than or equal to the total length of information bits supported by the coupling code, the first information bit determined by the transmitting device can be the information bit sequence k acquired by the transmitting device with L added to it. TBCRC 1 bit (or padding bit), the L TBCRC Each bit can be understood as a TB-level CRC bit (or TB-CRC).

[0166] In this process, the transmitting device performs TB-CRC bit stuffing on the acquired bit sequence k to be encoded to obtain a sequence of length K. TBCRC The first information bit. For example, KTBCRC =k+L TBCRC L TBCRC It is an integer greater than or equal to 1.

[0167] For example, the K TBCRC This can be understood as the length of the current transport block (TB).

[0168] Example, added L TBCRC The specific positions of the bits and the information bits k to be encoded are not limited. For example, the L TBCRC One bit can be added to the end, the beginning, or any position in the middle of k information bits. Alternatively, it can be understood as the added L... TBCRC The position of each bit within the first information bit is not specified. For example, the L TBCRC The first bit can be located at the tail, head, or any position in the middle of the first information bit.

[0169] It should be understood that after the sending device determines the first information bit, it divides the first information bit into C first blocks, and the length of each of the C first blocks is the same.

[0170] In this application, the partitioning involved in the embodiments can be direct partitioning or indirect partitioning. One implementation of direct partitioning is to divide the bits in the first information bits or read the bits in the first information bits in this way to obtain C first code blocks; another implementation of indirect partitioning is to first divide the first information bits into other blocks (e.g., S second blocks), and then divide the S second blocks to obtain C first blocks.

[0171] For example, the first block could be a spatially coupled block (sc block).

[0172] It should be understood that the transmitting device performs coupled encoding based on C first blocks to obtain the codeword sequence.

[0173] For example, the transmitting device performs coupled encoding based on the C first blocks to obtain a codeword sequence. The parity bit corresponding to the i-th first block in the C first blocks is obtained based on the information bits of the i-th first block and the information bits corresponding to a first blocks. a is an integer greater than or equal to 1. The a first blocks can be adjacent to or not adjacent to the i-th first block, and the first blocks included in these a first blocks can be adjacent or not adjacent.

[0174] In this context, the parity bit corresponding to the i-th first block is obtained by coupling encoding the i-th first block, and the information bit of the i-th first block is the unencoded information bit of the i-th first block. The information bits corresponding to a first blocks are the information bits obtained by coupling encoding.

[0175] It should be understood that this application does not limit how each first block is encoded.

[0176] For example, assuming the first block is an sc block, the encodings of at least two sc blocks among the C sc blocks can be correlated. The parity bit corresponding to one of these at least two sc blocks is determined based on the information bits corresponding to that sc block and the information bits corresponding to the other one or more of the at least two sc blocks; or the parity bit corresponding to one of these at least two sc blocks is determined based on the information bits of that sc block and the information bits and parity bits corresponding to the other one or more of the at least two sc blocks.

[0177] Optionally, the C first blocks can be derived from the S second blocks. For example, the transmitting device divides the first information bits into S second blocks, all of which are of equal length. The transmitting device then divides the S second blocks into C first blocks.

[0178] The second block can be understood as a code block (CB).

[0179] The number of first blocks in each second block may be different. For example, the number of first blocks in the i-th second block among S second blocks can be represented as si, where si is a positive integer and i is a positive integer less than or equal to S.

[0180] For example, assuming the first block is sc block, the transmitting device evenly divides each of the S second blocks to obtain C first blocks. For instance, the i-th second block among the S second blocks is composed of si sc blocks. si is a positive integer. If the i-th second block cannot be evenly divided into si sc blocks, the transmitting device needs to first perform bit stuffing on the i-th second block so that the stuffed i-th second block is divisible by si, and thus can be evenly divided into si sc blocks. The specific value of si can be a preset value, or it can be determined based on several parameters. See the examples in Case 1 and Case 2 below for details on how si is determined.

[0181] Assuming S = 2, the two second blocks include There are 14 sc blocks, wherein the encoding of the 14 sc blocks included in each of the two second blocks can be independent or related. The encoding of the 14 sc blocks included in each of the two second blocks... Within a given sc block, at least two sc blocks are encoded in a mutually related manner, but these at least two sc blocks do not belong to the same second block. The parity bit corresponding to one of these at least two sc blocks is determined based on the information bits of that sc block and the information bits corresponding to the other one or more of the at least two sc blocks; or the parity bit corresponding to one of these at least two sc blocks is determined based on the information bits of that sc block and the information bits and parity bits corresponding to the other one or more of the at least two sc blocks.

[0182] The following examples, using specific cases one and two, illustrate how the transmitting device obtains a codeword sequence by coupling and encoding C first blocks.

[0183] Scenario 1

[0184] It should be understood that in Case 1, the first block is introduced using the sc block as an example.

[0185] Step 7-1-1: The sending device acquires the first information bit.

[0186] It should be understood that the process of the sending device acquiring the first information bit can be found in the detailed description above, and will not be repeated here.

[0187] Step 7-1-2: The sending device divides the first information bits into C first blocks.

[0188] For example, after the sending device receives the first information bit, the length of the first information bit (K) TB,CRC ) less than or equal to the maximum length supported by CB (K) CB,max In the case of K, TB,CRC ≤K CB,max The transmitting device divides the first information bits into C first blocks. All C first blocks are of the same length.

[0189] As an example, suppose the length of the first information bit is K. TB,CRC Divisible by C, meaning the first information bit can be evenly divided into C first blocks, and the length of each of these C first blocks can be expressed as...

[0190] C is determined based on the length of the first information bit, the maximum length supported by the code block, and a preset value.

[0191] For example, si represents the preset value, LCB,CRC This represents the number of CRC bits included in the C first blocks, where si is a positive integer. The formula in this application embodiment... This indicates rounding up to the nearest integer.

[0192] It should be understood that in the formulas of this application embodiments, "·" or "*" both represent multiplication.

[0193] Optionally, the si can be indicated to the sending device via indication information, or predefined by the system / protocol, or determined based on the maximum length supported by the CB, or obtained from a predefined table or rule.

[0194] As another example, suppose the length of the first information bit is K. TB,CRC The length of the first information bit cannot be divided evenly by C, meaning it cannot be divided into C first blocks. During the process of determining the C first blocks based on the first information bit, the transmitting device first performs bit stuffing on the first information bit to obtain the second information bit, the length of which is divisible by C.

[0195] For example, the transmitting device fills the first information bit with L2 bits to obtain the second information bit. The transmitting device then divides the second information bit evenly to obtain C first blocks. The length of this second information bit is K. TBCRC +L2, where L2 is a positive integer, K TBCRC +L2 can be expressed as a C integer.

[0196] Where L2 is determined based on the length of the first information bit and C. For example, L2 = C - mod(K) TBCRC C).

[0197] It should be understood that the L2 padding bits can be located at the beginning, end, or any position in the middle of the second information bits.

[0198] Step 7-1-3: The transmitting device performs coupled encoding based on C first blocks to obtain the codeword sequence.

[0199] For example, the transmitting device performs coupled encoding on the C first blocks, wherein at least two of the C first blocks are related during the encoding process, or it can be understood that the C first blocks are not encoded independently during the encoding process, or it can be understood that at least two of the C first blocks are encoded using coupled encoding during the encoding process.

[0200] In one possible implementation, before coupling and encoding the C first blocks, the transmitting device can determine the bit padding to be performed on each of the C first blocks based on the information bit length of each first block and the size of the expansion factor in the expansion factor lookup table.

[0201] For example, the information bit length of each first block is K. SCB#1 For each first block, bit stuffing is performed. During the bit stuffing process, the expansion factor lookup table is traversed in ascending order so that the size of the information bits of the first block (or fourth block) after bit stuffing is divisible by the expansion factor in the expansion factor lookup table.

[0202] It should be understood that the transmitting device obtains C fourth blocks based on C first blocks, and the length of the information bits of each of the C fourth blocks can be divided by the same expansion factor integer.

[0203] The length of the fourth block satisfies k sub • Z, the size of the bit stuffing can be represented as L3, where L3 = K sub *ZK SCB#1 K sub *Z represents the maximum bit length of information supported by the first block (e.g., the first sc block), where Z is the expansion factor in the expansion factor lookup table, and K sub This K represents the maximum length of information bits supported by each base map block in the coupled code (e.g., BG1 or BG2 in a coupled LDPC code). sub The value can be predefined.

[0204] Optionally, the information bits in the first information bit are located at any position at the beginning, end, or middle of each of the C fourth blocks.

[0205] The transmitting device performs coupled encoding on the C fourth blocks:

[0206] As an example, suppose there are C fourth blocks, including the nth fourth block and the mth fourth block, where m and n are both positive integers.

[0207] The transmitting device performs coupled encoding based on the information bits of the nth fourth block and the corresponding information bits and check bits of the N fourth blocks to obtain the check bit corresponding to the nth fourth block; and / or, the transmitting device performs coupled encoding based on the information bits of the mth fourth block and the corresponding information bits of the M fourth blocks to obtain the check bit corresponding to the mth fourth block. M and N are integers.

[0208] For example, when N is 0, the check bit corresponding to the nth fourth block is determined based on the information bits of the nth fourth block. Alternatively, when N or M is not 0, the determination of the check bits corresponding to the nth and mth fourth blocks is related to the other fourth blocks.

[0209] It should be understood that the positional relationship between the nth fourth block and the nth fourth block is not limited in this application; the positional relationship between the mth fourth block and the mth fourth block is not limited in this application.

[0210] It should also be understood that the parity bits corresponding to some of the C fourth blocks are determined based on their own information bits and the information bits corresponding to the other fourth blocks, while the parity bits corresponding to some fourth blocks are determined based on their own information bits and the information bits and parity bits corresponding to the other fourth blocks. Alternatively, the parity bits corresponding to all of the C fourth blocks are determined based on their own information bits and the information bits and parity bits corresponding to the other fourth blocks.

[0211] It should also be understood that the transmitting device can couple and encode the C fourth blocks according to the above encoding method to obtain C fifth blocks. These C fifth blocks are obtained by coupling and encoding the C fourth blocks.

[0212] Scenario 2

[0213] It should be understood that in Case 2, the first part is introduced using CB as an example.

[0214] Step 7-2-1: The sending device acquires the first information bit.

[0215] It should be understood that a detailed description of how the sending device acquires the first information bit can be found in step 7-1-1 above.

[0216] It should also be understood that the length of the first information bit (K) TB,CRC () is greater than the maximum length supported by CB (K) CB,max ), that is, K TB,CRC >K CB,max .

[0217] Step 7-2-2: The sending device divides the first information bits into S second blocks.

[0218] Among them, the lengths of the S second blocks are all equal, and S is a positive integer.

[0219] For example, after the sending device receives the first information bit, the length of the first information bit (K) TB,CRC () is greater than the maximum length supported by CB (K) CB,max In the case of K,TB,CRC >K CB,max The transmitting device divides the first information bits into S second blocks. For example, the second block can be regarded as CB.

[0220] As an example, suppose the length of the first information bit is K. TBCRC Divisible by S, meaning the first information bit can be evenly divided into S second blocks, and the length of each of these S second blocks can be expressed as...

[0221] Wherein, S is determined based on the length of the first information bit and the maximum length supported by the code block.

[0222] For example, L CB,CRC This indicates the number of CB-CRCs subsequently added for each second block. For example, the L... CB,CRC The value of L can be 16 or 24. CB,CRC The specific value can be predefined by the system or protocol, and this application does not limit it.

[0223] As another example, suppose the length of the first information bit is K. TB,CRC The length of the first information bit cannot be divided evenly by S, meaning it cannot be divided into S second blocks. During the process of dividing the first information bit into S second blocks, the transmitting device first performs bit stuffing on the first information bit to obtain the second information bit, the length of which is divisible by S.

[0224] For example, the transmitting device fills the first information bit with L1 bits to obtain the second information bit. The transmitting device then divides the second information bit evenly to obtain S second blocks. The length of each second information bit is K. TBCRC +L1, where L1 is an integer, K TBCRC +L1 can be expressed as an integer S.

[0225] Where L1 is determined based on the length of the first information bit and S. For example, L1 = S - mod(K) TBCRC S).

[0226] It should be understood that the L1 bits can be located at the beginning, end, or any position in the middle of the second information bits.

[0227] Step 7-2-3: The sending device adds CRC bits to each of the S second blocks.

[0228] For example, after the transmitting device divides the data into S second blocks, it adds CRC bits to each of the S second blocks. Each of the S second blocks after adding the CRC includes the CRC bit.

[0229] For example, each of the S second blocks contains the same number of CB-CRCs.

[0230] It should be understood that the CRC added by the sending device to each of the S second blocks can be understood as a CB-level CRC (or CB-CRC). CB-CRC can be added at any position in the beginning, end, or middle of the second block.

[0231] Step 7-2-4: The transmitting device performs coupled encoding based on S second blocks to obtain the codeword sequence.

[0232] For example, the transmitting device performs coupled coding on the S second blocks, wherein at least two of the S second blocks are coupled together.

[0233] In one possible implementation, the transmitting device divides each of the S second blocks into C first blocks. The transmitting device then performs coupled coding based on the C first blocks to obtain a codeword sequence.

[0234] For example, if the first condition is met, the sending device divides each of the S second blocks into C first blocks.

[0235] Taking the i-th second block out of S second blocks as an example, under the condition of satisfying the first condition, the transmitting device divides the i-th second block into si first blocks, where the i-th second block is any one of the S second blocks, and this application does not make any specific limitation.

[0236] The first condition is determined based on the length of the i-th second block, a first value (e.g., b), and a first expansion factor. The first value is the number of non-parity columns in the base matrix corresponding to each first block, as defined in a predefined table. The first expansion factor belongs to at least one predefined expansion factor, or can be understood as an expansion factor in a predefined expansion factor lookup table. This predefined at least one expansion factor corresponds to the number of at least one padding bits, wherein the number of padding bits corresponding to the first expansion factor is the minimum number of padding bits corresponding to each of the at least one expansion factor.

[0237] For example, the first condition satisfies: P2 ≤ k·P1, where P2 is the number of padding bits determined by the first expansion factor and the length of the first information bit, P1 is the padding bit data determined by the length of the first information bit and the second expansion factor, and the second expansion factor is determined by the length of the first information bit, the number of information columns in the base matrix corresponding to the coupling code, and the first expansion factor, and this second expansion factor is less than or equal to the first expansion factor. k is a positive number less than 1, and P1 and P2 are both positive integers.

[0238] As an example, suppose the length of the first information bit is K. TBCRC =16981, the predefined expansion factor includes 384, and the basis matrix of the coupled code, taking the basis matrix BG1 (with 22 information columns) as an example, the first information bit can be divided into S second blocks, where It is evident that the expansion factor is 384, and this first information bit sequence needs to be divided into 3 second blocks, i.e., S = 3. Based on S = 3, the actual second expansion factor used is determined. Currently, the expansion factor that each second block can divide is calculated as follows: Since 258 is not an expansion factor in the expansion factor lookup table, the search proceeds upwards based on 258 and the expansion factor lookup table to select the expansion factor that is greater than 258 and closest to 258. The second expansion factor is then determined to be 288. Based on the second expansion factor, the number of bits P1 needed to fill the three second blocks is determined, where P1 = S * first value * second expansion factor - P1, and P1 = 3 * 22 * ​​288 - 16981 = 2027. Each of the three filled second blocks contains 22 * ​​258 = 5676 information bits.

[0239] As can be seen, the transmitting device determines three second blocks, each with an information bit length of 5676. Taking one second block as an example, the transmitting device determines the number of first blocks to divide into a second block, si, based on the first value b = 4. Here, b is less than or equal to the maximum value of the information columns supported by the first block, and b is predefined or configured by parameters.

[0240] It should be understood that the transmitting device traverses each of the expansion factors in the expansion factor lookup table from 320 to 384 (e.g., 320, 352, 384) according to the expansion factor 288 determined above and the predefined expansion factor 384, determines the padding bit P2 corresponding to each expansion factor, and selects the expansion factor corresponding to the smallest padding bit P2 as the first expansion factor.

[0241] For example, taking a predefined expansion factor of 384 as an example, the total number of information columns included in this second block is: The value of m cannot be divided by b = 4. Based on a predefined integer preset value or parameter configuration value shift (e.g., shift = 4), m is determined by iterating from 0 to shift. shift , so that (m+m shift If m is divisible by b, then the first m is determined. shift If (15+0) is not divisible by 4, but (15+1) is divisible by 4, determine m. shift =1. The transmitting device determines the value based on this m. shift m and b determine si. For example... The transmitting device determines the padding bits P2 = (m + m) based on the predefined spreading factor 384 and the length of the second block. shift )*Z-5676=(15+1)*384-5676=468.

[0242] For example, taking the predefined expansion factor of 320 as an example, the total number of information columns included in this second block is: m cannot be divided by b. Based on a predefined integer preset value or parameter configuration value shift (e.g., shift = 4), m is determined by iterating from 0 to shift. shift , so that (m+m shift If m is divisible by b, then the first m is determined. shift If (18+0) is not divisible by 4, (18+1) is not divisible by 4, and (18+2) is divisible by 4, then determine m. shift =2. The transmitting device determines the value based on this m. shift m and b determine si. For example, si = The transmitting device determines si based on m and b. For example... The transmitting device determines the padding bits P2 = (m + m) based on the predefined spreading factor 320 and the length of the second block. shift )*Z-5676=(18+2)*320-5676=724.

[0243] For example, taking the predefined expansion factor 352 as an example, the total number of information columns included in this second block is: m cannot be divided by b. Based on a predefined integer preset value or parameter configuration value shift (e.g., shift = 4), m is determined by iterating from 0 to shift. shift , so that (m+m shift If m is divisible by b, then the first m is determined. shift If (17+0) is not divisible by 4, (17+1) is not divisible by 4, (17+2) is not divisible by 4, and (17+3) is not divisible by 4, then determine m. shift =3. The transmitting device determines the value based on this m. shiftm and b determine si. For example... The transmitting device determines si based on m and b. For example... The transmitting device determines the padding bits P2 = (m + m) based on the predefined spreading factor 320 and the length of the second block. shift )*Z-5676=(17+3)*352-5676=1364.

[0244] The transmitting device determines the length of the second block and the padding bits to be 468, 724, and 1364 based on predefined spreading factors of 384, 320, and 352, respectively. The transmitting device selects the predefined spreading factor 384 as the first spreading factor.

[0245] Based on the above calculations, P1 = 2027 and P2 = 468.

[0246] The first condition is: P2 ≤ k·P1, where k is a positive number less than 1, and P1 and P2 are both positive integers. Referring to the example above, P1 = 2027, P2 = 468, and assuming k = 0.3, then 468 ≤ 0.3 * 2027. The sending device divides the S second blocks to determine C first blocks, with the first expansion factor being 384.

[0247] It should be understood that the first expansion factor corresponding to the first block is determined above, and the number of bits included in each first block is not limited in this application. For example, while ensuring that the length of the bits included in each first block does not exceed b * the first expansion factor, the number of bits included in each of the C first blocks can be the same or different, and this application does not impose any limitation.

[0248] It should also be understood that in the formulas of this application embodiments, "*", "×", or "·" all represent multiplication, and "÷" or " / " all represent division.

[0249] It should also be understood that the above example determines whether to divide the second block based on the first condition. If the first condition is met, a first expansion factor that is relatively larger than the actual expansion factor is determined based on the relevant parameters in the first condition, while reducing the number of padding elements.

[0250] For example, the transmitting device divides S second blocks into C first blocks. The i-th second block among the S second blocks is divided into si first blocks, where the specific value of si can be determined based on m and b as described above. The S second blocks are divided into C first blocks, where C is determined based on the number of second blocks and the number of first blocks that each second block is divided into. For example... or

[0251] For example, each of the C first blocks includes part or all of the CB-CRC in step 7-2-3 above. The i-th second block of the S second blocks is divided into si first blocks, wherein the CRC in the i-th second block can be distributed or uniformly distributed at any deterministic position of the information bits in the si first blocks, and the number of CB-CRCs included in each of the si first blocks can be the same or different. Each of the C first blocks participates in at least one CRC check bit calculation process.

[0252] For example, the i-th second block includes 24 CRC bits, and this i-th second block is evenly divided into 3 first blocks. Assume that each of the 3 first blocks includes the 24 CRC bits of the i-th second block, meaning that the CRC check bits of the 3 first blocks can be calculated independently. Alternatively, assume that each of the 3 first blocks includes the 8 CRC bits of the i-th second block, meaning that the 3 first blocks need to be combined and participate together in the CRC check bit calculation process.

[0253] The following example uses the i-th second block out of S second blocks. The transmitting device divides the i-th second block into s... i Let's introduce the first block. The i-th second block can be any one of the S second blocks.

[0254] For example, suppose that the i-th second block can be uniformly divided into s i The first block (or the first sc block), the s i The information bits in each of the first blocks have the same length.

[0255] For example, suppose that the i-th second block cannot be uniformly divided into s i The first block (or the first sc block), that is, the s i The information bit lengths of the first blocks are not the same. Before performing coupling encoding, the transmitting device needs to perform bit padding (e.g., padding with L4 bits) on the i-th second block so that the information bit length of the padded i-th second block can be evenly divided into s. i The first piece, the s i The information bits in each of the first blocks have the same length.

[0256] For example, the L4 is based on the information bit length of the i-th second block and s i It's confirmed.

[0257] For example, L4 = s i -mod(K CB s i ), KCB This represents the length of the information bits in the i-th second block.

[0258] It should be understood that the transmitting device receives information bits of the same length as s. i The first block, and before performing coupled coding, can also be based on this s i The information bit length of each first block in the first block is determined by the size of the expansion factor in the expansion factor lookup table, which determines the value of the first block. i Each first block in the first block is bit-stuffed.

[0259] For example, s i The information bit length of each first block in the first block is K. SCB#1 By using the ascending rule in the expansion factor lookup table, each first block is bit-padded so that the size of the information bits of the first block (or fourth block) after bit-padded can be determined by the expansion factor integer in the expansion factor lookup table.

[0260] The size of the bit stuffing can be represented as L3, where L3 = K. sub *ZK SCB#1 K sub *Z represents a second value, which is determined based on a first expansion factor (e.g., Z) and a first value (e.g., b).

[0261] Optionally, the information bits in the i-th second block are located in s. i The head, tail, or any middle position of each fourth block.

[0262] It should be understood that the transmitting device obtains C fourth blocks based on C first blocks, and the length of the information bits in each of these C fourth blocks can be divided by the same expansion factor integer. The transmitting device then performs coupled encoding on these C fourth blocks:

[0263] As an example, suppose there are C fourth blocks, including the nth fourth block and the mth fourth block, where m and n are both positive integers.

[0264] The transmitting device performs coupled encoding based on the information bits of the nth fourth block and the corresponding information bits and check bits of the N fourth blocks to obtain the check bit corresponding to the nth fourth block; and / or, the transmitting device performs coupled encoding based on the information bits of the mth fourth block and the corresponding information bits of the M fourth blocks to obtain the check bit corresponding to the mth fourth block. M and N are integers.

[0265] For example, when N is 0, the check bit corresponding to the nth fourth block is determined based on the information bits of the nth fourth block. Alternatively, when N or M is not 0, the determination of the check bits corresponding to the nth and mth fourth blocks is related to the other fourth blocks.

[0266] It should be understood that the positional relationship between the nth fourth block and the nth fourth block is not limited in this application; the positional relationship between the mth fourth block and the mth fourth block is not limited in this application.

[0267] It should also be understood that the parity bits corresponding to some of the C fourth blocks are determined based on their own information bits and the information bits corresponding to the other fourth blocks, while the parity bits corresponding to some fourth blocks are determined based on their own information bits and the information bits and parity bits corresponding to the other fourth blocks. Alternatively, the parity bits corresponding to all of the C fourth blocks are determined based on their own information bits and the information bits and parity bits corresponding to the other fourth blocks.

[0268] It should also be understood that the transmitting device can couple and encode the C fourth blocks according to the above encoding method to obtain C fifth blocks. These C fifth blocks are obtained by coupling and encoding the C fourth blocks.

[0269] It should also be understood that the number of information bits included in the first and fourth blocks mentioned above can be expressed as: The information bit can be located at any position in the beginning, end, or middle of the first block, or at any position in the beginning, end, or middle of the fourth block.

[0270] It should also be understood that the degree of coupling between the fourth blocks can be described by the coupling depth w or the coupling degree α. The coupling degree can be defined by the proportion of the number of sub-blocks coupled with other fourth blocks in the current fourth block to the total number of blocks in the current fourth block. As shown in Figure 8(1), the sub-blocks coupled between sc block#1 and sc block#2 occupy 1 / 2 of sc block#1 and sc block#2 respectively; as shown in Figure 8(2), the sub-blocks coupled between sc block#1 and sc block#2 occupy 2 / 3 of sc block#1 and sc block#2 respectively.

[0271] It should be understood that the generator matrix corresponding to the coupled code also includes a third block, which can be located at the lower left corner, lower right corner, or any other position of the basis matrix corresponding to the coupled code, and this application does not impose any restrictions.

[0272] For example, the third block consists of check bits, which are obtained based on the information bits and check bits corresponding to d of the C first blocks, or the check bits are obtained based on the information bits corresponding to d of the C first blocks. Here, d is a positive integer. The length of the third block can be determined based on the coupling degree α_1, where α_1 ≤ α.

[0273] For example, the first information bit comprises 18 information bits and is divided into three first blocks. The transmitting device, when dividing the first blocks, evenly distributes the 18 information bits into the three first blocks, meaning each of the three first blocks comprises 6 information bits. The third block in the base matrix corresponding to the coupling code does not contain any information bits, i.e., it contains 0 information bits. The parity bit of this third block can be determined based on the parity bit and information bits corresponding to at least one of the first blocks, based on the coupling degree (e.g., w).

[0274] It should also be understood that after the transmitting device determines the codeword sequence, it needs to punch holes in the codeword sequence. This punching can be based on C fifth blocks in the codeword sequence. The C fifth blocks are obtained by coupling and encoding C first blocks. The number of holes punched in each of the C fifth blocks may be the same or different.

[0275] For example, in C fifth blocks, there may be a case where the number of holes corresponding to each fifth block is 0.

[0276] For example, among the C fifth blocks, at least two fifth blocks may have different numbers of punches. For instance, the number of punches in the b-th fifth block may differ from the number of punches in the c-th fifth block, where b and c are both positive integers. Correspondingly, since at least two fifth blocks have different numbers of punches, the punch positions of these at least two fifth blocks may also be different. Having different numbers of punches in at least two fifth blocks can achieve bitrate compatibility during encoding, improving adaptability.

[0277] It should also be understood that when bit interleaving is performed based on the encoded codeword sequence, the specific interleaving method is row-write-column-read, or column-write-row-read. Specifically, when the codeword sequence in this application is interleaved, the first bit sequence is obtained by coupling and encoding the first information bits. The first bit sequence can be used as the input of a bit interleaver, meaning the first bit sequence performs one interleaving; or, C fifth blocks are obtained by coupling and encoding C first blocks, with each of the C fifth blocks serving as the input of a bit interleaver, meaning each of the C fifth blocks is interleaved independently, with the number of interleavings being C; or, S sixth blocks are obtained by coupling and encoding S second blocks, with each of the S sixth blocks serving as the input of a bit interleaver, meaning each of the S sixth blocks is interleaved independently, with the number of interleavings being S.

[0278] 740, The transmitting device determines the symbol sequence based on the codeword sequence.

[0279] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0280] 750, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0281] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0282] 760. The receiving device decodes the symbol sequence according to the matrix corresponding to the coupling code to obtain the information bit sequence.

[0283] It should be understood that the matrix corresponding to the coupling code used for decoding by the receiving device is the same as the matrix corresponding to the coupling code used for encoding by the transmitting device.

[0284] It should be understood that the detailed processes of rate matching, bit stuffing, and decoding can be based on the above encoding process, combined with the detailed descriptions in existing schemes, and will not be elaborated upon in this application.

[0285] For example, the receiving device processes the acquired symbol sequence to obtain a codeword sequence. The receiving device then decodes the codeword sequence according to the coupling code matrix to obtain the information bit sequence. Specifically, the decoding method can refer to the existing sliding window decoding method, or other decoding methods, as described in existing schemes.

[0286] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0287] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0288] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0289] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 8. The apparatus embodiments of this application will now be described with reference to Figures 9 and 10. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 9 and 10 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0290] Figures 9 and 10 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0291] Figure 9 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. As shown in Figure 9, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0292] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0293] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0294] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0295] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0296] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG8 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0297] Figure 10 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0298] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0299] Optionally, the memory 1130 may be integrated into the processor 1110.

[0300] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0301] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0302] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0303] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0304] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0305] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0306] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0307] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0308] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0309] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0310] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0311] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0312] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0313] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0314] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0315] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0316] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0317] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. An information processing method based on coupled codes, characterized in that, The method includes: The first information bit is divided into C first blocks, and the C first blocks are all of the same length. Based on C of the first blocks, coupled coding is performed to obtain the codeword sequence. Wherein, the check bit corresponding to the i-th first block in the C first blocks is obtained based on the information bits of the i-th first block and the information bits corresponding to the a first blocks, i is an integer greater than or equal to 2, a is an integer greater than or equal to 1, and C is an integer greater than or equal to 2.

2. The method according to claim 1, characterized in that, The process of dividing the first information bits into C first blocks includes: The first information bit is divided into S second blocks, and the S second blocks are all of the same length, where S is a positive integer. The S second blocks are divided into C first blocks, and each of the C first blocks includes a cyclic redundancy check (CRC) bit.

3. The method according to claim 2, characterized in that, If the first condition is met, the S second blocks are divided into C first blocks, wherein the i-th second block is divided into s blocks. i The first block, The first condition is determined based on the first value, the first expansion factor, and the length of the i-th second block. Wherein, the first value is the number of non-parity columns of the base matrix corresponding to each first block in the predefined, the first expansion factor belongs to at least one predefined expansion factor, each of the at least one expansion factor corresponds to a number of padding bits, the number of first padding bits corresponding to the first expansion factor is the minimum value of the number of padding bits corresponding to each of the at least one expansion factor, the first padding bits are used to pad the i-th second block so that the length of the i-th second block after padding is divisible by si, and are used to pad each of the si first blocks so that the first block after padding is divisible by the first expansion factor.

4. The method according to claim 3, characterized in that, The first condition is satisfied: P2≤k·P1, Wherein, P2 is the number of the first padding bits determined according to the first expansion factor and the length of the i-th second block, P1 is the number of the second padding bits determined according to the length of the first information bit and the second expansion factor, the second expansion factor is determined according to the length of the first information bit, the number of information columns included in the base matrix corresponding to the coupling code and the first expansion factor, k is a positive number less than 1, and P1 and P2 are both positive integers.

5. The method according to any one of claims 2 to 4, characterized in that, C is determined based on the length of the first information bit, the maximum length supported by the code block, and the number of the first blocks included in each of the S second blocks.

6. The method according to claim 5, characterized in that, C satisfies: Among them, K TB,CRC K represents the length of the first information bit. CB,MAX The L represents the maximum length supported by the code block, si represents the number of first blocks included in the i-th second block, and L represents the maximum length supported by the code block. CB,CRC Let si, K represent the number of CRC bits included in the first block (C blocks). TB,CRC K CB,MAX All are positive integers.

7. The method according to any one of claims 2 to 6, characterized in that, When the first information bits cannot be evenly divided into S second blocks The first information bit is padded with L1 bits to obtain the second information bit. The length of the second information bit is divisible by S, where L1 is an integer. The second information bits are divided into S blocks.

8. The method according to claim 7, characterized in that, The L1 is determined based on the length of the first information bit and S.

9. The method according to claim 8, characterized in that, L1 satisfies: L1 = S - mod(K) TBCRC ,S),K TB,CRC This indicates the length of the first information bit.

10. The method according to claim 1, characterized in that, When the first information bits cannot be evenly divided into C first blocks The process of dividing the first information bits into C first blocks includes: The first information bit is padded with L2 bits to obtain the third information bit. The length of the third information bit is divisible by C, and L2 is an integer. The third information bits are divided into C blocks of the first block.

11. The method according to claim 10, characterized in that, The L2 is determined based on the length of the first information bit and C.

12. The method according to claim 11, characterized in that, L2 = C - mod(K) TBCRC C), K TB,CRC This indicates the length of the first information bit.

13. The method according to any one of claims 1 to 12, characterized in that, The coupling encoding based on C of the first blocks to obtain the codeword sequence includes: Based on the information bit length of the first block and the second value, the size L3 of the padding bits is determined, where L3 is an integer, the second value is determined based on the first expansion factor and the first value, and the first value is the number of non-parity columns of the base matrix corresponding to each first block (predefined). According to L3, each of the C first blocks is bit-stuffed to obtain C fourth blocks.

14. The method according to claim 13, characterized in that, L3 satisfies: L3=b*ZK SCB#1 K SCB#1 b*Z represents the current information bit length of the first block, b*Z represents the second value, and Z represents the first expansion factor.

15. The method according to claim 13 or 14, characterized in that, The C fourth blocks include the nth fourth block and the mth fourth block, where m and n are both integers. The coupled encoding based on C of the fourth blocks yields a codeword sequence, including: Based on the information bits of the nth fourth block, and the information bits and check bits corresponding to the N fourth blocks, coupling encoding is performed to obtain the check bit corresponding to the nth fourth block; And / or, Based on the information bits of the m-th fourth block and the corresponding information bits of the M fourth blocks, coupling encoding is performed to obtain the check bit corresponding to the m-th fourth block. Where N and M are both integers.

16. The method according to any one of claims 1 to 15, characterized in that, Each of the C first blocks is used to determine at least one CRC check bit calculation process.

17. The method according to any one of claims 1 to 16, characterized in that, The C fifth blocks are obtained by coupling and encoding the C first blocks as described above. The number of holes in the b-th fifth block in the codeword sequence is different from the number of holes in the c-th fifth block, where b and c are both integers.

18. The method according to any one of claims 1 to 17, characterized in that, C fifth blocks are obtained by coupling and encoding C first blocks, with each of the C fifth blocks serving as input for bit interleaving; or, The first bit sequence is obtained by coupling and encoding the first information bits, and the first bit sequence serves as the input for the bit interleaving; or, S sixth blocks are obtained by coupling and encoding S second blocks, each of the S sixth blocks serving as input for bit interleaving, and the S second blocks include C first blocks.

19. The method according to any one of claims 1 to 18, characterized in that, The coupling encoding based on C of the first blocks to obtain the codeword sequence includes: The first and third blocks are coupled and encoded based on C blocks. The third block consists of parity bits, which are obtained from the information bits and parity bits of d fifth blocks out of C blocks. Alternatively, the parity bits of the third block are obtained from the information bits of d fifth blocks out of C blocks. The length of the third block is determined by the coding coupling degree, where d is a positive integer. Among them, the C fifth blocks are obtained by coupling encoding the C first blocks.

20. A communication device, characterized in that, Including processor and interface circuitry, The interface circuit is used to receive signals and transmit the signals to the processor or send signals processed by the processor to cause the processor to perform the method as described in any one of claims 1 to 19.

21. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed by a communication device, enable the method as described in any one of claims 1 to 19 to be implemented.

22. A computer program product, characterized in that, Includes a computer program, which, when run, enables the method as described in any one of claims 1 to 19 to be implemented.

23. A chip, characterized in that, The chip includes a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface to implement the method as described in any one of claims 1 to 19.

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