Data processing method, apparatus and system

Abstract

The present application relates to the technical field of computers, and provides a data processing method, an apparatus and a system. The method comprises: reading non-zero vectors in a first matrix to obtain a plurality of first matrix blocks, and reading target vectors in a second matrix to obtain a plurality of second matrix blocks, the vector positions of the target vectors being associated with the vector positions of the non-zero vectors. Then, the method further comprises: performing matrix multiplication computation on a plurality of transposed first matrix blocks and a plurality of transposed second matrix blocks, so as to obtain a plurality of result matrix blocks; and further obtaining a target matrix on the basis of a plurality of transposed result matrix blocks. Thus, sparse computation of matrix multiplication can be successfully implemented. In addition, sparse computation of matrix multiplication can be implemented more flexibly, so as to better satisfy requirements of different services, thus accelerating the computation process during which processing devices execute matrix multiplication computation, and reducing computing resources consumed by processing devices in executing matrix multiplication computation.

Description

Data processing methods, apparatus and systems

[0001] This application claims priority to Chinese patent application filed on November 27, 2024, with application number 202411721497.6, entitled "Data Processing Method, Apparatus and System", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and more specifically to data processing methods, apparatus and systems. Background Technology

[0003] Matrix multiplication is involved in various business areas such as scientific computing and deep learning. With the development of computer technology, the scale of matrix data processed in these areas is increasing, leading to a greater computational burden on processing devices performing matrix multiplication. Consequently, the computation speed of matrix multiplication may be slow, and the computational resources consumed may be high. Therefore, accelerating the matrix multiplication process and reducing the computational resources consumed by processing devices have become important technical problems that need to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a data processing method, apparatus, and system that can solve the problem of difficulty in accelerating the matrix multiplication calculation process of processing devices and reducing the computing resources consumed by processing devices in performing matrix multiplication calculations.

[0005] In a first aspect, a data processing method is provided, comprising reading non-zero vectors from a first matrix to obtain multiple first matrix blocks, and reading target vectors from a second matrix to obtain multiple second matrix blocks; wherein the vector positions of the target vectors are associated with the vector positions of the non-zero vectors. Then, the method further comprises performing matrix multiplication calculations based on the multiple transposed first matrix blocks and the multiple transposed second matrix blocks to obtain multiple result matrix blocks, and further obtaining a target matrix based on the multiple result transposed matrix blocks.

[0006] In the data processing method provided in this application embodiment, for matrix multiplication of a first matrix containing zero vectors (e.g., the first matrix is ​​a sparse matrix), the processor (or processing unit) performs matrix multiplication on multiple first matrix blocks (e.g., the size of the first matrix block is n*k) formed by extracting non-zero vectors from the first matrix, and multiple second matrix blocks formed by target vectors corresponding to the aforementioned non-zero vector positions in the second matrix. The target matrix obtained by merging the transposes (e.g., transposes to m*n) of the multiple result matrix blocks (e.g., the result matrix is ​​n*m) obtained from the matrix multiplication is equivalent to the matrix multiplication result of the first and second matrices. That is, the method provided in this application embodiment can successfully achieve sparse computation of matrix multiplication.

[0007] Furthermore, in the sparse computation implementation of matrix multiplication, the processing power of the processor (or processing unit) may limit the matrix size of the left operand and the right operand (for example, the size is specified as m*k when the left operand is the first matrix block, and the size is specified as k*n when the right operand is the second matrix block).

[0008] The data processing method provided by the embodiments of this application enables sparse computation of matrix multiplication where the shapes of the constructed first and second matrix blocks are not limited by the processing capabilities of the processor (or processing unit) (e.g., the first matrix block size can be n*k and the second matrix block size can be k*m). Furthermore, matrix multiplication is performed on the transposed first and second matrix blocks, which are not limited by the processing capabilities of the processor (or processing unit). The target matrix obtained by merging the transposed matrix blocks resulting from the matrix multiplication is equivalent to or approximately the sparse computation result obtained using the aforementioned computation method limited by processing capabilities. Therefore, the data processing method provided by the embodiments of this application has a wide range of applications, enabling more flexible implementation of sparse computation of matrix multiplication, better meeting the needs of different business operations, accelerating the matrix multiplication computation process performed by the processing device, and reducing the computational resources consumed by the processing device in performing matrix multiplication.

[0009] In some implementations, the first matrix is ​​a sparse matrix and the second matrix is ​​a dense matrix.

[0010] In some implementations, the matrix size of the left operand of the matrix multiplication calculation is m*k, and the matrix size of the right operand is k*n. When m is not equal to n, the matrix multiplication is performed based on multiple transposed first matrix blocks and multiple transposed second matrix blocks.

[0011] In this way, it is possible to flexibly change the number of matrix multiplication calculations and the amount of data loaded during the matrix multiplication process of the first and second matrices.

[0012] In some implementations, the size of the first matrix block is n*k, and the transposed first matrix block is the right operand of the matrix multiplication calculation; and the size of the second matrix block is k*m, and the transposed second matrix block is the left operand of the matrix multiplication calculation; where n is less than m.

[0013] In this way, the number of matrix multiplication calculations and the amount of data loaded can be reduced during the matrix multiplication calculation of the first and second matrices.

[0014] In some implementations, the length of a non-zero vector satisfies at least one of the following: the length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation; or the length of the non-zero vector is less than the target dimension of the first matrix.

[0015] This optimization of the TC block shape of the sparse matrix reduces the size of the TC block compared to existing sparse matrix computation methods (such as DTC-SpMM). This reduces computational redundancy, lowers memory access costs, and improves processor speed.

[0016] In some implementations, reading non-zero vectors from a first matrix to obtain multiple first matrix blocks includes: reading non-zero vectors from the first matrix column-wise to obtain the multiple first matrix blocks. Similarly, reading target vectors from a second matrix to obtain multiple second matrix blocks includes: reading target vectors from the second matrix row-wise to obtain the multiple second matrix blocks.

[0017] In some implementations, the first matrix block includes k non-zero vectors, which are column vectors of length n; and the second matrix block includes k target vectors, which are row vectors of length m.

[0018] In some implementations, matrix multiplication involves multiple matrix multiplications, where each multiplication computes a first transposed matrix block and a second transposed matrix block, resulting in a single matrix block. The number of matrix multiplications depends on at least one of the length of the non-zero vector and the size of the matrix operands in the multiplication.

[0019] Thus, under the constraint that the left operand of the sparse operator is a matrix block of the first matrix and the size of the left operand matrix is ​​m*k, and the right operand is a matrix block of the second matrix and the size of the right operand matrix is ​​k*n, where m and n satisfy m>n, the data processing method provided by the embodiments of this application can successfully realize sparse matrix calculation, reduce computational redundancy, and reduce the number of matrix multiplication calculations during sparse matrix calculation.

[0020] Secondly, a data processing apparatus is provided, which includes a data acquisition module and a processing module.

[0021] The data acquisition module is used to read non-zero vectors from the first matrix to obtain multiple first matrix blocks. The data acquisition module is also used to read target vectors from the second matrix to obtain multiple second matrix blocks. The vector positions of the target vectors are associated with the vector positions of the non-zero vectors.

[0022] The processing module is used to transpose multiple first matrix blocks and multiple second matrix blocks to obtain multiple transposed first matrix blocks and multiple transposed second matrix blocks. The processing module is also used to perform matrix multiplication calculations based on the multiple transposed first matrix blocks and multiple transposed second matrix blocks to obtain multiple result matrix blocks. The processing module is also used to transpose multiple result matrix blocks to obtain multiple transposed result matrix blocks, which are used to obtain the target matrix.

[0023] In some implementations, the first matrix is ​​a sparse matrix and the second matrix is ​​a dense matrix.

[0024] In some implementations, the matrix size of the left operand of the matrix multiplication calculation is m*k, and the matrix size of the right operand of the matrix multiplication calculation is k*n. The processing module is also used to perform matrix multiplication calculations based on multiple transposed first matrix blocks and multiple transposed second matrix blocks when m is not equal to n.

[0025] In some implementations, the size of the first matrix block is n*k, and the transposed first matrix block is the right operand of the matrix multiplication calculation; and the size of the second matrix block is k*m, and the transposed second matrix block is the left operand of the matrix multiplication calculation; where n is less than m.

[0026] In some implementations, the length of a non-zero vector satisfies at least one of the following: the length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation; or the length of the non-zero vector is less than the target dimension of the first matrix.

[0027] In some implementations, the data acquisition module is used to read non-zero vectors from the first matrix column-by-column to obtain the plurality of first matrix blocks. And, the data acquisition module is used to read target vectors from the second matrix row-by-row to obtain the plurality of second matrix blocks.

[0028] In some implementations, the first matrix block includes k non-zero vectors, which are column vectors of length n; and the second matrix block includes k target vectors, which are row vectors of length m.

[0029] In some implementations, matrix multiplication involves multiple matrix multiplications, where each multiplication computes a first transposed matrix block and a second transposed matrix block, resulting in a single matrix block. The number of matrix multiplications depends on at least one of the length of the non-zero vector and the size of the matrix operands in the multiplication.

[0030] Thirdly, a computing device is provided, including a processor and a memory. The processor is configured to execute instructions stored in the memory, causing the computing device to perform the data processing method described in the first aspect.

[0031] Fourthly, a chip system is provided, including a processor core, the processor core being configured to execute instructions stored in a memory to cause the processor core to perform operational steps of the data processing method as described in the first aspect.

[0032] Fifthly, a computer program product containing instructions is provided, which, when executed by at least one computing device, cause the at least one computing device to perform the data processing method as described in the first aspect.

[0033] In a sixth aspect, a computer-readable storage medium is provided, comprising computer program instructions that, when executed by a computer device, perform the data processing method as described in the first aspect.

[0034] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods.

[0035] The following description includes more specific details about the implementation methods provided for the above aspects. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the sparse matrix calculation method provided in the embodiments of this application;

[0037] Figure 2 is a schematic diagram of the architecture of the data processing system provided in an embodiment of this application;

[0038] Figure 3 is a flowchart illustrating the data processing method provided in an embodiment of this application;

[0039] Figure 4 is a schematic flowchart of the data processing method provided in the embodiments of this application (II).

[0040] Figure 5 is a flowchart illustrating the data processing method provided in an embodiment of this application.

[0041] Figure 6 is a schematic diagram of the data processing device provided in an embodiment of this application;

[0042] Figure 7 is a schematic diagram of the structure of the computing device provided in the embodiment of this application. Detailed Implementation

[0043] To facilitate understanding, the terminology used in this application will be introduced first.

[0044] Matrix multiplication is involved in various business areas such as scientific computing and deep learning. For example, image data can be represented by matrices, and image data processing can include matrix multiplication of image data matrices. Similarly, in deep learning, the model parameters of machine learning models include weight matrices, and the training and application processes of machine learning models can involve matrix multiplication of these weight matrices.

[0045] With the development of computer technology, the scale of matrix data processed in various business areas is increasing, and the computational load of matrix multiplication calculations performed by processing devices is also increasing accordingly. Consequently, the calculation speed of matrix multiplication by processing devices may be slow, and the computational resources consumed may be high. How to accelerate the matrix multiplication calculation process and reduce the computational resources consumed by processing devices has become an important technical problem that needs to be solved by those skilled in the art.

[0046] A matrix can include zero elements. Depending on the proportion of zero elements in the matrix, a matrix can be classified as a sparse matrix or a dense matrix.

[0047] A sparse matrix can refer to a matrix in which the proportion of zero elements is greater than a set proportion (e.g., 50%, 60%, 70%), or in other words, a matrix in which the number of zero elements is greater than the number of non-zero elements.

[0048] A dense matrix is ​​a matrix in which the proportion of non-zero elements is greater than a set proportion (e.g., 50%, 60%, 70%). In other words, it can also refer to a matrix in which the number of non-zero elements is greater than the number of zero elements.

[0049] Based on the distribution pattern of zero elements in a sparse matrix, sparse matrices can also include structured sparse matrices and unstructured sparse matrices.

[0050] A structured sparse matrix can be a sparse matrix in which the distribution of zero elements follows a certain pattern, such as two zero elements out of every four elements in a sparse matrix.

[0051] An unstructured sparse matrix can refer to a sparse matrix in which the distribution of zero elements is irregular. For example, the positions of zero elements in a sparse matrix are random and do not follow a pattern.

[0052] Matrix multiplication of sparse matrices, or simply sparse matrix computation, can refer to matrix multiplication involving sparse matrices. Operators for sparse matrix computation are called sparse operators. Sparse matrix computation can include sparse matrix-matrix multiplication (SpMM), sparse matrix-matrix multiplication, and so on.

[0053] Sparse operators such as SpMM are important operators used in various applications, including Graph Neural Networks (GNNs) and large sparse model (Transformer architecture) computation. Several methods exist to accelerate the execution of sparse operators on processors (or processor cores). The processor (or processor core) can be a Graphics Processing Unit (GPU) or the GPU's CUDA core (Compute Unified Device Architecture Core).

[0054] For example, deploying Tensor Cores (TCs) on GPUs. Tensor Cores can also be called Tensor Processors, Tensor Processor Cores, or Tensor Core Units (TCUs). (TCs can perform dense matrix operations and matrix multiplication of structured sparse matrices, but they exhibit significant limitations when processing highly sparse, unstructured sparse matrices.) Furthermore, TCs can be used to accelerate matrix multiplication of unstructured sparse matrices.

[0055] Among them, the techniques for accelerating matrix multiplication of unstructured sparse matrices through TC include TC-GNN (TC-GNN: Bridging Sparse GNN Computation and Dense Tensor Cores on GPUs) and DTC-SpMM (DTC-SpMM: Bridging the Gap in Accelerating General Sparse Matrix Multiplication with Tensor Cores).

[0056] The approaches of TC-GNN and DTC-SpMM involve identifying non-zero column vectors in a sparse matrix, concatenating these non-zero column vectors into matrix blocks that meet the computational requirements / processing capabilities of TC, and then performing matrix multiplication on these sparse matrix blocks to obtain the computational results. TC's processing capabilities limit the left and right operands of the sparse operator and their matrix sizes (e.g., the left operand is a sparse matrix block of size m*k, and the right operand is a dense matrix block of size k*n).

[0057] By employing the aforementioned TC-GNN and DTC-SpMM methods, non-zero column vectors that meet the computational requirements of TC can be extracted to form matrix blocks. This allows for the removal of some zero elements in the matrix multiplication of sparse matrices, meaning that some zero elements do not participate in the matrix multiplication calculation. This reduces the computational load of matrix multiplication, improving the computational speed and resource utilization of sparse matrix multiplication performed by TC.

[0058] As an example, Figure 1 is a schematic diagram of a sparse matrix computation method. Figure 1 shows the algorithm implementation diagrams of the aforementioned TC-GNN and DTC-SpMM. As shown in Figure 1, the left part is the representation of the sparse matrix A (most of the sparse matrix A is empty, i.e., zero elements, with only a small number of non-zero elements distributed in the matrix), and the right part shows how to use TC to perform matrix multiplication of the sparse matrix A.

[0059] The following explanation uses an example where TC's processing power limits the sparse operator to a block of sparse matrices with a specified size of m*k and a block of dense matrices with a specified size of k*n, where m=16, n=8, and k=8. Performing a matrix multiplication of a sparse matrix A involves the following process.

[0060] First, identify the m×1 (e.g., 16×1) non-zero column vectors in the sparse matrix A. Specifically, any m×1 column vector containing at least one non-zero element is identified as an m×1 non-zero column vector. Then, compress k (e.g., 8) m×1 non-zero column vectors into m×k (e.g., 16×8) TC blocks (represented as TC block A).

[0061] Then, based on the column indices of these m×1 non-zero column vectors, access the n×1 (e.g. 8×1) row vectors of the corresponding rows in the dense matrix B. And, compress the k (e.g. 8) n×1 row vectors into k×n (e.g. 8×8) TC blocks (which can be represented as TC block B).

[0062] Then, multiple matrix multiplication accumulation (MMA) instructions are executed, such as MMA0, MMA1, MMA2, and MMA3 shown in Figure 1. Each MMA instruction is used to perform a matrix multiplication calculation between a 16×8 TC block A from a sparse matrix A and an 8×8 TC block B from a dense matrix B, to obtain the calculation result (which can be called an intermediate calculation result).

[0063] The intermediate calculation results of multiple matrix multiplications can be accumulated (for example, accumulating the outputs of MMA0 and MMA2 can be represented as MMA0+MMA2) to obtain the target calculation result, which is the output block C (also called the output dense matrix C, the result matrix block C, or TC block C). The size of the output block C is m×n (e.g., 16×8). In this way, the accumulation process integrates the calculation results obtained from multiple MMA instructions, and the resulting output block C can correctly reflect the matrix multiplication calculation result of TC block A.

[0064] However, due to the processing power limitations of TC, the sparsity pattern of the sparse matrix may not match the computational granularity of TC. Specifically, when the granularity of the non-zero column vector is too large (i.e., m is large), many elements in the m×1 non-zero column vector will still be zero, resulting in a large number of redundant zero elements. This leads to many operations in the computation process not contributing to the output but still consuming computational resources (i.e., a significant amount of computational resources are wasted), reducing computational efficiency. This mismatch becomes even more pronounced when processing large-scale sparse matrices, such as in Graph Neural Networks (GNNs) or Sparse Matrix Multiplication (SpMM) operations.

[0065] Taking the sparse matrix A in Figure 1 as an example, in the m×k TC block (such as a 16x8 matrix block) shown in the figure, many matrix elements are zero. Therefore, the hardware will perform unnecessary calculations on these zero elements, wasting computation cycles, memory bandwidth and computing resources.

[0066] Furthermore, due to hardware limitations of the processor (or processor core), it is difficult to modify inherent sparse operators (such as MMA instructions). For example, it is difficult to break down MMA instructions to perform matrix multiplication on smaller-granularity matrix blocks (e.g., this operation requires specific compiler support and is difficult to implement), or the processor (or processor core) does not provide a programmer-programmable interface for modifying inherent MMA instructions.

[0067] Thus, for sparse matrices with various sparse patterns such as unstructured and highly sparse, it is difficult to flexibly perform sparse matrix calculations on the processor (or processor core), so that more zero elements are removed during the sparse matrix calculation process to improve computing performance, such as reducing the waste of computing resources and increasing the calculation speed.

[0068] This application proposes a data processing method, which includes reading non-zero vectors from a first matrix to obtain multiple first matrix blocks, and reading target vectors from a second matrix to obtain multiple second matrix blocks; wherein the vector positions of the target vectors are associated with the vector positions of the non-zero vectors. The method then further includes performing matrix multiplication on the multiple transposed first matrix blocks and the multiple transposed second matrix blocks to obtain multiple result matrix blocks, and further obtaining a target matrix from the multiple result transposed matrix blocks.

[0069] In the data processing method provided in this application embodiment, for matrix multiplication of a first matrix containing zero vectors (e.g., the first matrix is ​​a sparse matrix), the processor (or processing unit) performs matrix multiplication on multiple first matrix blocks (e.g., the size of the first matrix block is n*k) formed by extracting non-zero vectors from the first matrix, and multiple second matrix blocks formed by target vectors corresponding to the aforementioned non-zero vector positions in the second matrix. The target matrix obtained by merging the transposes (e.g., transposes to m*n) of the multiple result matrix blocks (e.g., the result matrix is ​​n*m) obtained from the matrix multiplication is equivalent to the result after compressing (removing some zero vectors) the matrix multiplication result of the first and second matrices. That is, the method provided in this application embodiment can successfully achieve sparse computation of matrix multiplication.

[0070] Furthermore, in the sparse computation implementation of matrix multiplication, the processing power of the processor (or processing unit) may limit the matrix size of the left operand and the right operand (for example, the size is specified as m*k when the left operand is the first matrix block, and the size is specified as k*n when the right operand is the second matrix block).

[0071] The data processing method provided by the embodiments of this application enables sparse computation of matrix multiplication where the shapes of the constructed first and second matrix blocks are not limited by the processing capabilities of the processor (or processing unit) (e.g., the first matrix block size can be n*k and the second matrix block size can be k*m). Furthermore, matrix multiplication is performed on the transposed first and second matrix blocks, which are not limited by the processing capabilities of the processor (or processing unit). The target matrix obtained by merging the transposed matrix blocks resulting from the matrix multiplication is equivalent to or approximately the sparse computation result obtained using the aforementioned computation method limited by processing capabilities. Therefore, the data processing method provided by the embodiments of this application has a wide range of applications, enabling more flexible implementation of sparse computation of matrix multiplication and better meeting the needs of different business operations.

[0072] In the data processing method provided in this application embodiment, the processed matrix data (e.g., a first matrix, a second matrix) can be data from various fields or of various types. For example, it can be matrix representation data of one or more types of data such as images, text, and audio.

[0073] The data processing method provided in this application embodiment can be applied to various technical fields such as scientific computing and deep learning to realize matrix multiplication calculations involved in these technical fields.

[0074] The data processing method provided in this application is not limited to performing matrix multiplication on sparse matrices (e.g., the first matrix is ​​a sparse matrix, which can be a structured sparse matrix or an unstructured sparse matrix), but can also be applied to performing matrix multiplication on dense matrices (e.g., both the first and second matrices are dense matrices). This allows for the removal of zero elements in the dense matrix during the matrix multiplication process, thereby improving the performance of matrix multiplication on dense matrices.

[0075] The system architecture provided in the embodiments of this application is described below. Referring to Figure 2, the embodiments of this application provide a schematic diagram of the architecture of a data processing system. The data processing system 200 can be used to implement the data processing method proposed in the embodiments of this application. As shown in Figure 2, the data processing system 200 includes a processor 210 and a memory 220.

[0076] The processor 210 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0077] Processor 210 may include one or more processor cores. In other words, processor 210 may be implemented by processor cores.

[0078] The memory 220 can be any type of memory that can be used for data storage, such as RAM or cache. It can also be any type of storage medium or storage space that can be used for data storage, such as a hard disk or disk drive. The memory 220 may include one or more memories, each of which can be used to store a portion of the required data.

[0079] The memory 220 can be used to store matrix data that needs to be multiplied, such as the first matrix, the second matrix, etc.

[0080] The processor 210 can access the memory 220 to read data of the first matrix (e.g., a first matrix block) and data of the second matrix (e.g., a second matrix block). The processor 210 can also execute the data processing method provided in the embodiments of this application to perform matrix multiplication on the matrix data of the first and second matrices to obtain a target matrix. More details regarding the data processing method provided in the embodiments of this application can be found in the following description.

[0081] The memory 220 can also be used to store the calculation results obtained by the processor 210 during the matrix multiplication calculation, such as the result matrix block, the target matrix, etc.

[0082] It is worth noting that Figure 2 is merely a schematic diagram of the architecture of a data processing system provided in an embodiment of this application, and the positional relationships between the devices, components, modules, etc. shown in the figure do not constitute any limitation.

[0083] The data processing method provided in the embodiments of this application is described in detail below. The data processing provided in the embodiments of this application can be implemented on the data processing system 200 shown in FIG2, specifically, it can be executed by the processor 210.

[0084] Figure 3 is a flowchart illustrating the data processing method provided in an embodiment of this application.

[0085] In this embodiment, the first matrix can be a sparse matrix (e.g., a structured sparse matrix or an unstructured sparse matrix). Alternatively, the first matrix can also be a dense matrix that includes zero elements and can remove at least some of the zero elements. The second matrix can be either a dense matrix or a sparse matrix. This embodiment primarily uses the example of a sparse first matrix and a dense second matrix for illustration.

[0086] The embodiments of this application mainly illustrate the data processing method under the following two cases where the processor's processing limitations are as examples.

[0087] The first type of restriction is as follows: the left operand of the sparse operator (the operator for matrix multiplication of sparse matrices) is a block of the first matrix (e.g., a sparse matrix) and the size of the left operand matrix is ​​specified as m*k; the right operand is a block of the second matrix (e.g., a dense matrix) and the size of the right operand matrix is ​​specified as k*n.

[0088] The second type of restriction is as follows: the left operand of the sparse operator is restricted to a matrix block of the second matrix (e.g., a dense matrix) and the size of the left operand matrix is ​​specified as m*k; the right operand is a matrix block of the first matrix (e.g., a sparse matrix) and the size of the right operand matrix is ​​specified as k*n.

[0089] In some embodiments of this application, when m is not equal to n, steps 310-350 can be performed to perform the matrix multiplication of the first matrix and the second matrix. This reduces the number of matrix multiplication calculations and the amount of data loaded during the matrix multiplication of the first matrix and the second matrix.

[0090] As shown in Figure 3, the method includes the following steps.

[0091] Step 310: Obtain multiple first matrix blocks from the first matrix.

[0092] In step 310, the processor obtains multiple first matrix blocks by reading the non-zero vectors in the first matrix. That is, each first matrix block includes multiple non-zero vectors extracted from the first matrix.

[0093] Step 320: Obtain multiple second matrix blocks from the second matrix.

[0094] In step 320, the processor reads multiple target vectors from the second matrix to obtain multiple second matrix blocks.

[0095] In step 310, the position of the non-zero vector is associated with the position of the target vector in step 320. For example, if the non-zero vector is the column vector of the i-th column in the first matrix, then the target vector is the row vector of the i-th row in the second matrix. Or, for another example, if the non-zero vector is the row vector of the i-th row in the first matrix, then the target vector is the column vector of the i-th column in the second matrix. In this way, the first and second matrix blocks can successfully perform matrix multiplication.

[0096] In this embodiment of the application, the vector length of the non-zero vector read in step 310 and the vector length of the target vector read in step 320 satisfy the following: the vector length of the non-zero vector is related to the matrix size of the operand of the matrix multiplication calculation.

[0097] In this embodiment of the application, the vector length of the non-zero vector read in step 310 can also satisfy the following condition: the vector length of the non-zero vector is less than the target dimension of the first matrix. For example, if the non-zero vector is a row vector, then the vector length of the non-zero vector is less than the row dimension value of the first matrix; or, for example, if the non-zero vector is a column vector, then the vector length of the non-zero vector is less than the column dimension value of the first matrix.

[0098] Depending on the aforementioned processing limitations, the methods for reading the first matrix block and the second matrix block in steps 310 and 320 can include a variety of approaches.

[0099] For the first type of constraint (the left operand of the sparse operator is a block of the first matrix with a size of m*k, and the right operand is a block of the second matrix with a size of k*n, where m and n satisfy m>n):

[0100] In step 310, multiple first matrix blocks can be obtained by reading the non-zero vectors in the first matrix column by column. The vector length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation. The non-zero vector can be made into a column vector of length n.

[0101] Furthermore, the first matrix block includes k non-zero vectors (column vectors), meaning the size of the first matrix block is n*k;

[0102] In step 320, the target vector in the second matrix can be read row by row to obtain multiple second matrix blocks. The length of the target vector is related to the size of the matrix of the left operand of the matrix multiplication calculation. The target vector can be made into a row vector of length m.

[0103] Furthermore, the second matrix block includes k target vectors (row vectors), meaning the size of the second matrix block is k*m.

[0104] For the second type of processing restriction (the left operand of the sparse operator is a block of the second matrix with a specified size of m*k, and the right operand is a block of the first matrix with a specified size of k*n, where m and n satisfy n>m):

[0105] In step 310, multiple first matrix blocks can be obtained by reading non-zero vectors in the first matrix row by row. The length of the non-zero vector is related to the size of the matrix of the left operand of the matrix multiplication calculation. The non-zero vector can be made into a row vector of length m.

[0106] Furthermore, the first matrix block comprises k non-zero vectors (row vectors), meaning the size of the first matrix block is k*m;

[0107] In step 320, the target vector in the second matrix can be read column by column to obtain multiple second matrix blocks. The length of the target vector is related to the size of the matrix of the right operand of the matrix multiplication calculation. The target vector can be made into a column vector of length n.

[0108] Furthermore, the second matrix block includes k target vectors (column vectors), meaning the size of the second matrix block is n*k.

[0109] Step 330: Transpose multiple first matrix blocks and multiple second matrix blocks to obtain multiple transposed first matrix blocks and multiple transposed second matrix blocks.

[0110] For the first processing limitation: the size of the first matrix block is n*k, and the size of the first matrix block after transpose is k*n; the size of the second matrix block is k*m, and the size of the second matrix block after transpose is m*k.

[0111] For the second processing constraint: the size of the first matrix block is n*k, and the size of the first matrix block after transpose is m*k; the size of the second matrix block is k*m, and the size of the second matrix block after transpose is k*n.

[0112] Step 340: Perform matrix multiplication calculations based on the multiple transposed first matrix blocks and the multiple transposed second matrix blocks to obtain multiple result matrix blocks.

[0113] In step 340, the matrix multiplication calculation includes multiple matrix multiplication calculations, wherein each matrix multiplication calculation is used to calculate the matrix multiplication of a transposed first matrix block and a transposed second matrix block to obtain a result matrix block. Thus, by performing matrix multiplication calculations based on multiple transposed first matrix blocks and multiple transposed second matrix blocks, multiple result matrix blocks can be obtained.

[0114] In the embodiments of this application, the number of matrix multiplication calculations is related to the vector length of the non-zero vectors in the first matrix block and the matrix size of the operands of the matrix multiplication calculation.

[0115] Depending on the aforementioned processing constraints, various calculation methods may be used during the matrix multiplication process.

[0116] For the first type of constraint (the left operand of the sparse operator is a block of the first matrix with a size of m*k, and the right operand is a block of the second matrix with a size of k*n, where m and n satisfy m>n):

[0117] The size of the first matrix block after transpose is k*n, and the first matrix block after transpose is used as the right operand for matrix multiplication.

[0118] The size of the transposed second matrix block is m*k, and the transposed second matrix block is used as the left operand for matrix multiplication.

[0119] For the second type of processing restriction (the left operand of the sparse operator is a block of the second matrix with a specified size of m*k, and the right operand is a block of the first matrix with a specified size of k*n, where m and n satisfy n>m):

[0120] The size of the first matrix block after transpose is m*k, and the first matrix block after transpose is used as the left operand for matrix multiplication.

[0121] The transposed second matrix block has a size of k*n and serves as the right-hand operand for matrix multiplication.

[0122] Step 350: Transpose multiple result matrix blocks to obtain multiple transposed result matrix blocks.

[0123] Suppose that 'a' represents the first matrix block, a T b represents the first matrix block after transpose, and b represents the second matrix block. T c represents the second matrix block after transpose. T represents the result matrix block, and c represents the transposed result matrix block.

[0124] For the first processing constraint, the calculation process for any transposed result matrix block can be represented as b T ×a T =c T And for c T Transposing to obtain c is equivalent to a×b=c, that is, the transposed result matrix block obtained by steps 310-350 is equivalent to the matrix multiplication result obtained by the method specified by the sparse operator under the first processing constraint mentioned above.

[0125] For the second processing constraint, the calculation process for any transposed result matrix block can be represented as a T ×b T =c T And for c T Transposing to obtain c is equivalent to b × a = c, that is, the transposed result matrix block obtained by steps 310-350 is equivalent to the matrix multiplication result obtained by the method specified by the sparse operator under the aforementioned second processing constraint.

[0126] The target matrix can be obtained from multiple transposed result matrix blocks. For example, merging multiple transposed result matrix blocks will yield the desired target matrix. The target matrix is ​​equivalent to the matrix multiplication result of the first and second matrices.

[0127] For ease of understanding, the following uses Figures 4 and 5 to illustrate examples of the data processing method provided in the embodiments of this application.

[0128] Figure 4 is a flowchart of the data processing method provided in the embodiments of this application.

[0129] Figure 4 primarily illustrates the case where the first matrix is ​​sparse and the second matrix is ​​dense. Furthermore, Figure 4 also illustrates the first case with constraints: the left operand of the sparse operator is a block of the first matrix with a size of m*k, and the right operand is a block of the second matrix with a size of k*n, where m = 16, n = 8, and k = 8.

[0130] As shown in Figure 4, the data processing method provided in this application embodiment may further include the following steps:

[0131] First, identify the 8×1 non-zero column vectors in the sparse matrix A. Specifically, any 8×1 column vector containing at least one non-zero element is identified as an 8×1 non-zero column vector. Then, compress the eight 8×1 non-zero column vectors into an 8×8 first matrix block (i.e., the TC block).

[0132] Then, based on the column indices of these 8×1 non-zero column vectors, the corresponding 16×1 row vectors in the dense matrix B are accessed to obtain multiple 8×16 second matrix blocks.

[0133] Then, transpose each of the first matrix blocks and each of the second matrix blocks to obtain transposed first matrix blocks and transposed second matrix blocks. The transposed first matrix block has a size of 8×8, and the transposed second matrix block has a size of 16×8.

[0134] Then, multiple matrix multiplication accumulation (MMA) instructions are executed, such as MMA0 and MMA1 shown in Figure 4. Each MMA instruction performs a matrix multiplication of a 16×8 transposed second matrix block from a dense matrix B and an 8×8 transposed first matrix block, resulting in a 16×8 result matrix block. The 16×8 transposed second matrix block serves as the left operand of the MMA instruction, and the 8×8 first matrix block serves as the right operand.

[0135] Then, each result matrix block is transposed to obtain multiple transposed result matrix blocks C. These multiple transposed result matrix blocks C are then merged to obtain the desired target matrix.

[0136] Figure 5 is a flowchart illustrating the data processing method provided in the embodiments of this application.

[0137] Figure 5 primarily illustrates the case where the first matrix is ​​sparse and the second matrix is ​​dense. Additionally, Figure 5 also illustrates the second constraint case: the left operand of the sparse operator is a block of the second matrix with a specified size of m*k, and the right operand is a block of the first matrix with a specified size of k*n, where m = 8, n = 16, and k = 8.

[0138] As shown in Figure 5, the data processing method provided in this application embodiment may further include the following steps:

[0139] First, identify the 1×8 non-zero row vectors in the sparse matrix A. Specifically, a 1×8 row vector is identified as a 1×8 non-zero row vector if it contains at least one non-zero element. Then, compress the eight 1×8 non-zero row vectors into an 8×8 first matrix block (i.e., the TC block).

[0140] Then, based on the row indices of these 1×8 non-zero row vectors, the corresponding 16×1 column vectors in the dense matrix B are accessed to obtain multiple 16×8 second matrix blocks.

[0141] Then, transpose each of the first matrix blocks and each of the second matrix blocks to obtain the transposed first matrix block and the transposed second matrix block. The transposed first matrix block has a size of 8×8, and the transposed second matrix block has a size of 8×16.

[0142] Then, multiple matrix multiplication accumulation (MMA) instructions are executed, such as MMA0 and MMA1 shown in Figure 5. Each MMA instruction performs a matrix multiplication of a first transposed 8×8 matrix block and a second transposed 8×16 matrix block from a dense matrix B, resulting in a result matrix block of size 8×16. The first transposed 8×8 matrix block serves as the left operand of the MMA instruction, and the second transposed 8×16 matrix block serves as the right operand.

[0143] Then, each result matrix block is transposed to obtain multiple transposed result matrix blocks C. These multiple transposed result matrix blocks C are then merged to obtain the desired target matrix.

[0144] As can be seen from the foregoing method, the embodiments of this application optimize the shape of the TC block of the sparse matrix to 8×8 by introducing MMA calculations involving exchange and transpose. Compared with the 16×8 shape of the TC block in existing sparse matrix calculation methods (such as DTC-SpMM technology), the size of the TC block of the sparse matrix is ​​reduced. Furthermore, the embodiments of this application use an 8×1 vector granularity to partition the sparse matrix, requiring only two MMA operations to complete one SpMM calculation. In contrast, existing sparse matrix calculation methods (such as DTC-SpMM technology) using a 16×1 vector granularity require four MMA operations. This optimization significantly reduces computational redundancy, lowers memory access costs during computation, and improves processor speed.

[0145] It is understood that, in order to achieve the functions in the above embodiments, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0146] The data processing method provided according to the embodiments of this application has been described in detail above with reference to Figures 3 to 5. The apparatus provided according to this application will now be described with reference to Figure 6. These apparatuses can be used to implement the functions of the processor in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.

[0147] Figure 6 shows a data processing device provided in an embodiment of this application. As shown in Figure 6, the data processing device 600 includes a data acquisition module 610 and a processing module 620.

[0148] The data acquisition module 610 is used to read non-zero vectors from the first matrix to obtain multiple first matrix blocks. The data acquisition module 610 is also used to read target vectors from the second matrix to obtain multiple second matrix blocks. The vector positions of the target vectors are associated with the vector positions of the non-zero vectors.

[0149] Processing module 620 is used to transpose multiple first matrix blocks and multiple second matrix blocks to obtain multiple transposed first matrix blocks and multiple transposed second matrix blocks. The processing module is also used to perform matrix multiplication calculations based on the multiple transposed first matrix blocks and multiple transposed second matrix blocks to obtain multiple result matrix blocks. The processing module is also used to transpose multiple result matrix blocks to obtain multiple transposed result matrix blocks, which are used to obtain the target matrix.

[0150] In some implementations, the first matrix is ​​a sparse matrix and the second matrix is ​​a dense matrix.

[0151] In some implementations, the matrix size of the left operand of the matrix multiplication calculation is m*k, and the matrix size of the right operand of the matrix multiplication calculation is k*n. The processing module is also used to perform matrix multiplication calculations based on multiple transposed first matrix blocks and multiple transposed second matrix blocks when m is not equal to n.

[0152] In some implementations, the size of the first matrix block is n*k, and the transposed first matrix block is the right operand of the matrix multiplication calculation; and the size of the second matrix block is k*m, and the transposed second matrix block is the left operand of the matrix multiplication calculation; where n is less than m.

[0153] In some implementations, the length of a non-zero vector satisfies at least one of the following: the length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation; or the length of the non-zero vector is less than the target dimension of the first matrix.

[0154] In some implementations, the data acquisition module 610 is used to read non-zero vectors in the first matrix column-by-column to obtain the plurality of first matrix blocks. Also, the data acquisition module 610 is used to read target vectors in the second matrix row-by-row to obtain the plurality of second matrix blocks.

[0155] In some implementations, the first matrix block includes k non-zero vectors, which are column vectors of length n; and the second matrix block includes k target vectors, which are row vectors of length m.

[0156] In some implementations, matrix multiplication involves multiple matrix multiplications, where each multiplication calculates the matrix multiplication of a transposed first matrix block and a transposed second matrix block, resulting in a single matrix block. The number of matrix multiplications depends on at least one of the length of the non-zero vector and the size of the matrix operands in the multiplication.

[0157] For more details on the operations implemented by the module, please refer to Figures 3 to 5 and their related descriptions.

[0158] Optionally, the data acquisition module 610 and the processing module 620 may each include multiple sub-modules. The multiple sub-modules may be deployed separately to implement some of the functions of the corresponding module, such as implementing one or more steps in the methods of Figures 3-5 above.

[0159] All devices can be implemented in software or in hardware. For example, the implementation of data processing device 600 will be described below.

[0160] As an example of a software functional unit, the data processing device 600 may include code running on a computing instance. The computing instance may be at least one of a physical host (computing device), a virtual machine, a container, or other computing devices. Further, the aforementioned computing device may be one or more. For example, the data processing device 600 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the application may be distributed in the same region or in different regions. The multiple hosts / virtual machines / containers used to run the code may be distributed in the same Availability Zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0161] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same VPC or across multiple VPCs. Typically, a VPC is set up within a single region. Communication between two VPCs within the same region, and between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0162] As an example of a hardware functional unit, the data processing device 600 may include at least one computing device, such as a server. Alternatively, the data processing device 600 may also be a device implemented using an ASIC or a PLD. The aforementioned PLD may be implemented using a CPLD, FPGA, GAL, or any combination thereof.

[0163] The data processing device 600 includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the data processing device 600 includes multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the YY device includes multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0164] This application also provides a computing device 700. As shown in FIG7, the computing device 700 includes: a bus 702, a processor 704, a memory 706, and a communication interface 708. The processor 704, the memory 706, and the communication interface 708 communicate with each other via the bus 702. The computing device 700 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 700. Optionally, the processor 704 of the computing device 700 can be connected to a display or input device through the communication interface 708.

[0165] Bus 702 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one line is used in Figure 7, but this does not imply that there is only one bus or one type of bus. Bus 702 can include pathways for transmitting information between various components of computing device 700 (e.g., memory 706, processor 704, communication interface 708).

[0166] The processor 704 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). In the embodiments of this application, the processor 704 is used to execute the steps or operations of the data processing methods provided in Figures 3 to 5.

[0167] The memory 706 may include volatile memory, such as random access memory (RAM). The processor 704 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0168] The memory 706 stores executable program code, and the processor 704 executes the executable program code to implement the functions of the aforementioned data acquisition module 610 and processing module 620, thereby realizing the training set processing method in Embodiment 1, the model training method in Embodiment 2, and the model training method in Embodiment 3 provided in this application. That is, the memory 706 stores instructions for executing the data processing methods provided in Figures 3 to 5 of this application.

[0169] The communication interface 708 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 700 and other devices or communication networks.

[0170] The display may include various display devices capable of display functions, such as plasma displays and liquid crystal displays. The computing device 700 can implement the display functions involved in the data processing methods provided in Figures 3 to 5 of this application through the display.

[0171] Input devices can include various input devices such as keyboards, mice, and touch screens that enable user input.

[0172] This application also provides a chip system. The chip system may include a processor and a power supply circuit. The power supply circuit supplies power to the processor, which executes the steps or operations of the data processing methods provided in Figures 3 to 5.

[0173] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform the steps or operations of the data processing method provided in Figures 3-5 of this application, such as the instructions for performing the steps or operations of the data processing method provided in Figures 3-5.

[0174] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform the steps or operations of the data processing method provided in Figures 3-5 of this application, such as instructions for performing the steps or operations of the data processing method provided in Figures 3-5.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this application.

[0176] The terms “first,” “second,” “third,” and “fourth,” etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to define a specific order.

[0177] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

Claims

1. A data processing method, characterized in that, The method includes: Multiple first matrix blocks are obtained by reading the non-zero vectors in the first matrix; Multiple second matrix blocks are obtained by reading the target vector in the second matrix; wherein the vector position of the target vector is associated with the vector position of the non-zero vector; Transpose the plurality of first matrix blocks and the plurality of second matrix blocks to obtain a plurality of transposed first matrix blocks and a plurality of transposed second matrix blocks; Multiple result matrix blocks are obtained by performing matrix multiplication on the multiple transposed first matrix blocks and the multiple transposed second matrix blocks; The multiple result matrix blocks are transposed to obtain multiple transposed result matrix blocks, which are used to obtain the target matrix.

2. The method according to claim 1, characterized in that, The first matrix is ​​a sparse matrix, and the second matrix is ​​a dense matrix.

3. The method according to claim 1 or 2, characterized in that, The matrix size of the left operand in the matrix multiplication calculation is m*k, and the matrix size of the right operand in the matrix multiplication calculation is k*n. When m is not equal to n, the matrix multiplication calculation is performed based on the plurality of transposed first matrix blocks and the plurality of transposed second matrix blocks.

4. The method according to any one of claims 1-3, characterized in that, The size of the first matrix block is n*k, and the transposed first matrix block is the right operand of the matrix multiplication calculation; and, The size of the second matrix block is k*m, and the transposed second matrix block is the left operand of the matrix multiplication calculation; where n is less than m.

5. The method according to claim 4, characterized in that, The length of the non-zero vector satisfies at least one of the following: The length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation, and the length of the non-zero vector is less than the target dimension of the first matrix.

6. The method according to claim 4 or 5, characterized in that, The step of reading non-zero vectors in the first matrix to obtain multiple first matrix blocks includes: reading non-zero vectors in the first matrix column by column to obtain the multiple first matrix blocks; The step of reading the target vector in the second matrix to obtain multiple second matrix blocks includes: reading the target vector in the second matrix row by row to obtain the multiple second matrix blocks.

7. The method according to any one of claims 4-6, characterized in that, The first matrix block includes k non-zero vectors, each non-zero vector being a column vector of length n; and, The second matrix block includes k target vectors, each of which is a row vector of length m.

8. The method according to any one of claims 1-7, characterized in that, The matrix multiplication calculation includes multiple matrix multiplication calculations, wherein each matrix multiplication calculation is used to calculate the matrix multiplication of a transposed first matrix block and a transposed second matrix block to obtain a result matrix block; The number of times the matrix multiplication is performed is related to at least one of the vector length of the non-zero vector and the matrix size of the operands of the matrix multiplication.

9. A data processing apparatus, characterized in that, The device includes a data acquisition module and a processing module; The data acquisition module is used to read non-zero vectors in the first matrix to obtain multiple first matrix blocks; The data acquisition module is also used to read the target vector in the second matrix to obtain multiple second matrix blocks; wherein, the vector position of the target vector is associated with the vector position of the non-zero vector; The processing module is used to transpose the plurality of first matrix blocks and the plurality of second matrix blocks to obtain a plurality of transposed first matrix blocks and a plurality of transposed second matrix blocks; The processing module is also used to perform matrix multiplication calculations based on the plurality of transposed first matrix blocks and the plurality of transposed second matrix blocks to obtain a plurality of result matrix blocks; The processing module is also used to transpose the plurality of result matrix blocks to obtain a plurality of transposed result matrix blocks, which are used to obtain the target matrix.

10. The apparatus according to claim 9, characterized in that, The first matrix is ​​a sparse matrix, and the second matrix is ​​a dense matrix.

11. The apparatus according to claim 9 or 10, characterized in that, The matrix size of the left operand in the matrix multiplication calculation is m*k, and the matrix size of the right operand in the matrix multiplication calculation is k*n. When m is not equal to n, the matrix multiplication calculation is performed based on the plurality of transposed first matrix blocks and the plurality of transposed second matrix blocks.

12. The apparatus according to any one of claims 9-11, characterized in that, The size of the first matrix block is n*k, and the transposed first matrix block is the right operand of the matrix multiplication calculation; and, The size of the second matrix block is k*m, and the transposed second matrix block is the left operand of the matrix multiplication calculation; where n is less than m.

13. The apparatus according to claim 12, characterized in that, The length of the non-zero vector satisfies at least one of the following: The length of the non-zero vector is related to the size of the matrix of the right operand of the matrix multiplication calculation, and the length of the non-zero vector is less than the target dimension of the first matrix.

14. The apparatus according to claim 12 or 13, characterized in that, The data acquisition module is further configured to: read the non-zero vectors in the first matrix column by column to obtain the plurality of first matrix blocks; The data acquisition module is also used to: read the target vector in the second matrix row by row to obtain the plurality of second matrix blocks.

15. The apparatus according to any one of claims 12-14, characterized in that, The first matrix block includes k non-zero vectors, each non-zero vector being a column vector of length n; and, The second matrix block includes k target vectors, each of which is a row vector of length m.

16. The apparatus according to any one of claims 9-15, characterized in that, The matrix multiplication calculation includes multiple matrix multiplication calculations, wherein each matrix multiplication calculation is used to calculate the matrix multiplication of a transposed first matrix block and a transposed second matrix block to obtain a result matrix block; The number of times the matrix multiplication is performed is related to at least one of the vector length of the non-zero vector and the matrix size of the operands of the matrix multiplication.

17. A computing device, characterized in that, The computing device includes a processor and a memory; the processor is configured to execute instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1-8.

18. A chip system, characterized in that, The chip system includes a processor core for executing instructions stored in memory to cause the processor core to perform the operational steps of the method as described in any one of claims 1-8.

19. A computer program product containing instructions, characterized in that, When the instruction is executed by at least one computing device, the at least one computing device performs the method as described in any one of claims 1-8.

20. A computer-readable storage medium, characterized in that, The storage medium includes computer program instructions, which, when executed by a computing device, perform the method as described in any one of claims 1-8.

Images