In-memory computing apparatus, control method, control apparatus, in-memory computing system, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are an in-memory computing apparatus, a control method, a control apparatus, an in-memory computing system and an electronic device. The in-memory computing apparatus comprises: a storage circuit, used for performing a plurality of computations in a first pipeline cycle; a conversion circuit, connected to the storage circuit and used for performing first conversion on a plurality of signals output by the plurality of computations and outputting a plurality of conversion results; and an output circuit, connected to the conversion circuit and used for performing second conversion on the plurality of conversion results and outputting a plurality of computation results, wherein the plurality of computations comprise a first computation and a second computation, and the process of the conversion circuit performing the first conversion on a first signal output by the first computation is parallel to a running process of the second computation. The in-memory computing apparatus provided in the present application can improve the computing performance of an in-memory computing architecture.

Description

Storage devices and control methods, control devices, storage systems and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411732115.X, filed on November 28, 2024, entitled “In-memory computing device and control method, control device, in-memory computing system and electronic device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to in-memory computing devices and control methods, control devices, in-memory computing systems and electronic devices. Background Technology

[0003] In traditional computing models, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this model, data is frequently transferred between storage and computing devices, leading to data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing models unable to meet the demands of processing power.

[0004] In-memory computing (IMC) architecture physically integrates storage and computation, enabling computation through storage devices or storing data in computing devices. This reduces data transfer requirements, lowers latency and energy consumption, and significantly improves data processing efficiency. However, IMC architecture still faces challenges; for example, its computational performance needs further improvement. Summary of the Invention

[0005] This application provides a memory computing device and control method, control device, memory computing system and electronic device to improve the computing performance of the memory computing architecture.

[0006] In a first aspect, a storage computing device is provided, comprising: a storage circuit for performing multiple calculations within a first pipeline cycle; a conversion circuit connected to the storage circuit for performing a first conversion on multiple signals output from the multiple calculations and outputting multiple conversion results; and an output circuit connected to the conversion circuit for performing a second conversion on the multiple conversion results and outputting multiple calculation results; wherein the multiple calculations include a first calculation and a second calculation, and the process of the conversion circuit performing the first conversion on the first signal output from the first calculation is parallel to the process of the second calculation.

[0007] In the aforementioned in-memory computing devices, the storage circuitry can perform parallel computations within a pipeline cycle. While one computation is running, other computations can be initiated, preparing for more computational outputs in advance. Furthermore, at least some of the computations can reuse conversion circuits. When a conversion circuit converts the output of one computation, other computations sharing that conversion circuit can prepare their outputs in advance. When a conversion circuit completes the conversion of one output, it can quickly obtain the input for the next conversion, reducing waiting time and improving the overall computing power of the in-memory computing device. In addition, the computation process of the storage circuitry can be executed in parallel with the conversion process of the conversion circuitry. The runtime of the storage circuitry can be utilized to execute the conversion process in parallel, further enhancing the parallelism of the circuits in the in-memory computing device. Therefore, the circuits in the aforementioned in-memory computing devices can be more fully utilized in the time domain, thereby improving the computing power and performance of the in-memory computing device.

[0008] In conjunction with the first aspect, in some possible implementations, the conversion circuit performs a first conversion on the first signal and outputs a first conversion result, and the process of the output circuit performing a second conversion on the first conversion result is parallel to the process of the conversion circuit performing a first conversion on the second signal output by the second calculation.

[0009] Through this implementation, the in-memory computing device can not only achieve parallelism between the storage circuit and the conversion circuit, but also further achieve parallelism between the conversion circuit and the output circuit. In this way, after the conversion circuit outputs the conversion result, it can receive the next input and perform the next conversion as soon as possible. The output circuit's output of the conversion result can be parallel to the next conversion of the conversion circuit, thereby further improving the parallelism of the circuits in the in-memory computing device and greatly enhancing the computing power of the in-memory computing device.

[0010] In conjunction with the first aspect, in some possible implementations, the conversion circuit performs a first conversion on the first signal and outputs a first conversion result, and the process of the output circuit performing a second conversion on the first conversion result runs in parallel with the process of the second calculation.

[0011] Through this implementation method, the in-memory computing device can not only achieve parallelism between the storage circuit and the conversion circuit, but also further achieve parallelism between the storage circuit and the output circuit, thereby further improving the parallelism of the circuits in the in-memory computing device and thus enhancing the computing power of the in-memory computing device.

[0012] In conjunction with the first aspect, in some possible implementations, the number of calculations performed within the first pipeline cycle is related to one or more of the unit calculation time, unit conversion time, and unit output time.

[0013] The pipeline cycle of an in-memory computing device can include the time interval between two adjacent calculations performed by the same computational unit (e.g., a group of memory cells) of the storage circuit. By repeatedly running multiple pipeline cycles, the in-memory computing device can be effectively controlled to continuously perform multiple rounds of computation, continuously outputting computation results. This ensures that intermediate output results from multiple rounds of computation, such as signals output by the storage circuit during computation or conversion results output by the conversion circuit after the first conversion, can be processed in a timely manner. This allows one or more of the storage circuit, conversion circuit, and output circuit to be fully utilized in the time domain, thereby improving the computing power of the in-memory computing device. Specifically, the unit computation time of the storage circuit is the time it takes to perform one computation; this unit computation time can include the computation settling time within a single computation. The unit conversion time of the conversion circuit is the running time for one conversion (also referred to as the first conversion). The unit output time of the output circuit is the running time for one output (also referred to as the second conversion).

[0014] In conjunction with the first aspect, in some possible implementations, the storage circuit includes: N storage arrays, a conversion circuit connected to the N storage arrays, where N is a positive integer greater than 1; the N storage arrays are used to perform N calculations within a first pipeline cycle, wherein the start times of two adjacent calculations differ by a first time interval; the conversion circuit is used to perform a first serial conversion on the N signals output from the N calculations; and the output circuit is used to perform a second serial conversion on the N conversion results of the conversion circuit.

[0015] Through the technical solution of this embodiment, the computation start times of multiple storage arrays have a time difference. Utilizing this time difference, the storage arrays and conversion circuits can operate in parallel, and the conversion circuits and output circuits can further operate in parallel. This enables the in-memory computing device with multiple storage arrays to have a high degree of parallelism, with close cooperation between multiple circuits. Furthermore, the storage circuits, conversion circuits, and output circuits can all have high utilization rates in the time domain. Therefore, the in-memory computing device provided in this application embodiment can have high computing power and better computational performance.

[0016] In conjunction with the first aspect, in some possible implementations, the first time is determined based on the unit conversion time or the unit output time.

[0017] The unit conversion time of the conversion circuit and the unit output time of the output circuit can affect the overall pipeline timing of the in-memory computing device. In order to provide parallelism between the storage circuit and the conversion circuit, and / or between the conversion circuit and the output circuit, a suitable first time can be designed based on the unit conversion time of the conversion circuit and the unit output time of the output circuit, thereby improving the parallelism and computing power of the in-memory computing device.

[0018] In conjunction with the first aspect, in some possible implementations, the absolute value of the difference between unit conversion time and unit output time is less than or equal to a time threshold.

[0019] This implementation method results in a small or even zero time difference between the unit conversion time and the unit output time, which is beneficial for timing design and simplifies the timing control of the conversion and output circuits by the control circuit. Furthermore, since the unit conversion time and unit output time are essentially the same, the two circuits can have a longer parallel duration and achieve closer coordination between them. This further enhances the computing power of the in-memory computing device while reducing the complexity of the control circuit design.

[0020] In conjunction with the first aspect, in some possible implementations, the first flow cycle is determined based on unit computation time, or the first flow cycle is determined based on unit computation time and unit conversion time.

[0021] In conjunction with the first aspect, in some possible implementations, the first flow cycle includes unit calculation time and interval time, the interval time being an integer multiple of the unit conversion time.

[0022] In this embodiment, the interval between two adjacent cycles of the memory device is determined based on the unit switching time of the switching circuit, which allows for periodic preparation or adjustment of the circuits within the memory device, thereby improving the reliability of the memory device.

[0023] In conjunction with the first aspect, in some possible implementations, the memory computing device further includes: a selection circuit connected between the conversion circuit and the N memory arrays, the selection circuit being used to select multiple signals output by the N memory arrays to be sequentially input to the conversion circuit.

[0024] In conjunction with the first aspect, in some possible implementations, one of the N storage arrays includes M storage cell groups, where M is a positive integer greater than 1; a storage cell group includes multiple storage cells, which are connected to the same output terminal; the selection circuit includes M selection sub-circuits, one of which is connected to the output terminal of the N storage cell groups of the N storage arrays and is used to select the signal output of one of the storage cell groups to be input to the conversion circuit.

[0025] The above selection circuit configuration allows multiple storage arrays to reuse the same conversion and output circuits, reducing the amount of hardware circuitry required and facilitating pipeline control of the storage device.

[0026] In conjunction with the first aspect, in some possible implementations, the storage circuit includes a first storage array, which includes N1 groups of storage cells, each group of storage cells including multiple storage cells connected to the same output terminal, where N1 is a positive integer greater than 1; the N1 groups of storage cells are used to perform N1 calculations in a first pipeline cycle; the conversion circuit is used to perform a serial first conversion on the N1 signals output from the N1 calculations in the first pipeline cycle to obtain N1 conversion results; and the output circuit is used to perform a serial second conversion on the N1 conversion results.

[0027] In this embodiment, at least two memory cell groups in the same memory array can reuse conversion circuits and / or output circuits, reducing the number of conversion circuits and / or output circuits and further saving hardware resources. The conversion circuits and / or output circuits can run in parallel with the memory circuits. For example, the running time of the conversion circuits and / or output circuits can overlap with the output hold time of the memory circuits. As an example, after N1 memory cell groups in the memory circuit complete their calculations and output stable signals, these N1 memory cell groups can enter the output hold time, i.e., continuously output stable signals. Utilizing this output hold time, the conversion circuit can perform a serial first conversion on the N1 signals of the N1 memory cell groups, and / or the output circuit can perform a serial second conversion on the N1 conversion results. This improves the parallelism of the circuits in the in-memory computing device, allowing the circuits in the in-memory computing device to be fully utilized in the time domain, thereby improving the computing power and performance of the in-memory computing device.

[0028] In conjunction with the first aspect, in some possible implementations, the output circuit and the conversion circuit operate in parallel, or the output circuit and the conversion circuit operate in series.

[0029] In this embodiment, the output circuit and the conversion circuit can be selected to operate serially or in parallel according to actual needs. In the case of serial operation, it is beneficial to simplify the hardware implementation and control of the in-memory computing device and enhance the stability of the in-memory computing device. In the case of parallel operation, the pipeline cycle of the in-memory computing device can be further shortened, the operating efficiency and speed of the in-memory computing device can be improved, thereby further enhancing the computing power of the in-memory computing device.

[0030] In conjunction with the first aspect, in some possible implementations, the first pipeline cycle is determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, and the unit conversion time; or, the first pipeline cycle is determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, the unit conversion time, and the unit output time.

[0031] In conjunction with the first aspect, in some possible implementations, the output circuit and the conversion circuit operate in parallel, and the first pipeline cycle includes at least one unit of computation time and N1 times the unit conversion time.

[0032] In conjunction with the first aspect, in some possible implementations, the output circuit and the conversion circuit operate in series, and the first pipeline cycle includes at least one unit of computation time, N1 times the unit of conversion time, and (N1-1) times the unit of output time.

[0033] In conjunction with the first aspect, in some possible implementations, the N1 storage cell groups include a first storage cell group and a second storage cell group, and the storage and computing device further includes: a selection circuit connected between the conversion circuit and the first storage cell group and the second storage cell group, the selection circuit being used to time-division select the signals output by the first storage cell group and the second storage cell group to be input to the conversion circuit.

[0034] The above selection circuit configuration allows multiple memory cell groups to reuse the same conversion and output circuits, reducing the amount of hardware circuitry required and facilitating pipeline control of the storage device.

[0035] In conjunction with the first aspect, in some possible implementations, the first and second memory cell groups are computed in parallel.

[0036] In conjunction with the first aspect, in some possible implementations, the storage circuit further includes a second storage array comprising N2 groups of storage cells, where N2 is a positive integer greater than 1; the N2 groups of storage cells are used to perform N2 calculations within a second pipeline cycle; the conversion circuit is used to perform a serial first conversion on the N2 signals output from the N2 calculations within the second pipeline cycle to obtain N2 conversion results; and the output circuit is used to perform a serial second conversion on the N2 conversion results.

[0037] In conjunction with the first aspect, in some possible implementations, the first flow cycle and the second flow cycle include overlapping time.

[0038] The technical solution of this embodiment allows the first pipeline cycle of the first storage array and the second pipeline cycle of the second storage array to overlap in time, enabling the first and second storage arrays to operate in parallel. This is beneficial for improving the utilization rate of each storage array in the time domain and enhancing the computing power of the in-memory computing device.

[0039] In conjunction with the first aspect, in some possible implementations, the overlapping time includes the time it takes for the conversion circuit to serially convert the N1 signals of the N1 computed outputs.

[0040] In conjunction with the first aspect, in some possible implementations, the N1 groups of storage cells include a first group of storage cells and a second group of storage cells, and the N2 groups of storage cells include a third group of storage cells and a fourth group of storage cells. The storage device further includes a selection circuit connected between the conversion circuit and the first and second storage arrays. The selection circuit is used to select, in a time-division manner, the signals output by the first group of storage cells, the second group of storage cells, the third group of storage cells, and the fourth group of storage cells to be input to the conversion circuit.

[0041] Secondly, a control method is provided for controlling a memory computing device, the memory computing device including: a storage circuit, a conversion circuit, and an output circuit; the control method includes: controlling the storage circuit to perform multiple calculations within a first pipeline cycle; controlling the conversion circuit to perform a first conversion on multiple signals output from the multiple calculations to output multiple conversion results; controlling the output circuit to perform a second conversion on the multiple conversion results to output multiple calculation results; wherein the multiple calculations include a first calculation and a second calculation, and the control of the conversion circuit to perform the first conversion on the multiple signals to output multiple conversion results includes: the process of the control of the conversion circuit performing the first conversion on the first signal output from the first calculation running in parallel with the process of the second calculation.

[0042] In conjunction with the second aspect, in some possible implementations, the aforementioned control conversion circuit performs a first conversion on multiple signals to output multiple conversion results, including: the control conversion circuit performs a first conversion on a first signal and outputs a first conversion result; the aforementioned control output circuit performs a second conversion on multiple conversion results to output multiple calculation results, including: the process of the control output circuit performing a second conversion on the first conversion result is parallel to the process of the conversion circuit performing a first conversion on the second signal output by the second calculation.

[0043] In conjunction with the second aspect, in some possible implementations, the aforementioned control conversion circuit performs a first conversion on multiple signals to output multiple conversion results, including: the control conversion circuit performs a first conversion on a first signal and outputs a first conversion result; the aforementioned control output circuit performs a second conversion on multiple conversion results to output multiple calculation results, including: the process of the control output circuit performing a second conversion on the first conversion result is parallel to the process of the second calculation.

[0044] In conjunction with the second aspect, in some possible implementations, the number of calculations performed within the first pipeline cycle is related to one or more of the unit calculation time, unit conversion time, and unit output time.

[0045] Thirdly, a control device is provided for controlling a memory computing device, the memory computing device including: a storage circuit, a conversion circuit, and an output circuit; the control device includes: a first control module for controlling the storage circuit to perform multiple calculations in a first pipeline cycle to output multiple signals; a second control module for controlling the conversion circuit to perform a first conversion on the multiple signals to output multiple conversion results; and a third control module for controlling the output circuit to perform a second conversion on the multiple conversion results to output multiple calculation results; wherein the multiple calculations include a first calculation and a second calculation, and the second control module is used to control the process of the conversion circuit performing the first conversion on the first signal output by the first calculation to run in parallel with the process of the second calculation.

[0046] Fourthly, a control device is provided, comprising at least one processor and an interface circuit, the interface circuit being signal-connected to a memory computing device, and the at least one processor being used to execute the control method of the second aspect or any possible implementation thereof.

[0047] Fifthly, a storage computing system is provided, comprising: a storage computing device according to the first aspect or any possible embodiment of the first aspect; and a control circuit configured to control the operating state of the storage computing device.

[0048] A sixth aspect provides an electronic device, comprising: a memory computing device as described in the first aspect or any possible implementation thereof. Attached Figure Description

[0049] Figure 1 is a schematic structural diagram of a storage system provided in an embodiment of this application.

[0050] Figure 2 is a schematic structural diagram of another in-memory computing system provided in an embodiment of this application.

[0051] Figure 3 is a schematic diagram of a pipeline of a sequentially running in-memory computing device provided in an embodiment of this application.

[0052] Figure 4 is a schematic block diagram of a storage device provided in an embodiment of this application.

[0053] Figure 5 is a schematic diagram of a storage device pipeline provided in an embodiment of this application.

[0054] Figure 6 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0055] Figure 7 is a schematic diagram of the pipeline of another in-memory computing device provided in an embodiment of this application.

[0056] Figure 8 is a schematic diagram of the pipeline of another in-memory computing device provided in an embodiment of this application.

[0057] Figure 9 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0058] Figure 10 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0059] Figure 11 is a schematic diagram of the pipeline of another in-memory computing device provided in an embodiment of this application.

[0060] Figure 12 is another pipeline diagram of the in-memory computing device provided in the embodiments of this application.

[0061] Figure 13 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0062] Figure 14 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0063] Figure 15 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0064] Figure 16 is a schematic diagram of the pipeline of another in-memory computing device provided in an embodiment of this application.

[0065] Figure 17 is a schematic diagram of the pipeline of another in-memory computing device provided in an embodiment of this application.

[0066] Figure 18 is a schematic block diagram of another in-memory computing device provided in an embodiment of this application.

[0067] Figure 19 is a schematic flowchart of a control method provided in an embodiment of this application.

[0068] Figure 20 is a schematic block diagram of a control device provided in an embodiment of this application.

[0069] Figure 21 is a schematic block diagram of another control device provided in an embodiment of this application.

[0070] Figure 22 is a schematic block diagram of a storage system provided in an embodiment of this application.

[0071] Figure 23 is a schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0072] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0073] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0074] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0075] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0076] In in-memory computing technology, in-memory computing systems and devices can use memory as a carrier to perform in-memory computation (or operations). This memory can include: non-volatile memory (NVM) or volatile memory (VM). Volatile memory can include, but is not limited to: static random access memory (SRAM); non-volatile memory can include, but is not limited to: flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), or phase change memory (PCM), etc.

[0077] For ease of understanding, Figure 1 shows a schematic diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0078] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also known as weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 may include a storage cell array, which includes multiple storage cells arranged in an array.

[0079] Storage cells can utilize the conduction capability of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell may include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the electrical conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device.

[0080] The storage circuit 110 can perform calculations in groups. For example, a storage cell array may include at least one storage cell group, which includes multiple storage cells and can store multiple weight data, which can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array may include a one-dimensional array or a two-dimensional array, etc., and the storage cell group may include multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and the multiple storage cells can output their output signals collinearly.

[0081] According to some embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140, or may further include an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0082] As an example, Figure 2 shows a schematic diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0083] As shown in Figure 2, the in-memory computing system 200 includes a storage cell array 210, which includes multiple storage cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0084] According to some embodiments, the input data may include a digital input signal, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. According to some embodiments, the input signal to the memory cell array 210 may include a digital signal, which can be represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array.

[0085] According to some embodiments, the output circuit 240 may include an analog-to-digital converter (ADC) to convert the output signal of the memory cell array 210 into a digital signal and provide it to subsequent circuits. In some embodiments of this disclosure, the input signal may include a voltage signal, and the output signal may include a current signal. The memory computing system 200 may also include a conversion circuit 250 that can convert the current signal into a voltage signal and provide it to the output circuit 240 for analog-to-digital conversion. For example, the conversion circuit 250 may include a transimpedance amplifier (TIA). Additionally, in the example of FIG2, the control circuit 220 can be used to control each memory cell S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0086] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals can be connected collinearly by rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, a memory cell may include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, a memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the gate is used to store charge. Optionally, the gate may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0087] In some in-memory computing applications, the runtime (or working time) for a single output by the memory cell array, conversion circuit (e.g., TIA), and output circuit (e.g., ADC) may not be equal due to limitations in the size of the memory circuitry (e.g., the size of the memory cell array), the type of memory circuitry, or the process node. This difference in runtime can lead to underutilization of the computing power of the in-memory computing device (e.g., the in-memory chip). For example, the runtime of the memory cell array may be much longer than that of the conversion circuit and / or the output circuit. The sequential operation of the memory cell array, conversion circuit, and output circuit can result in insufficient utilization of the overall circuit capability, thus limiting the computing power of the in-memory computing device.

[0088] As an example, Figure 3 shows a schematic diagram of a pipeline for a sequentially operating in-memory computing device.

[0089] As shown in Figure 3, in a sequentially running pipeline, the memory cell array (ARRAY in the example), the conversion circuit (TIA in the example), and the output circuit (ADC in the example) operate in sequence. That is, the conversion circuit performs its conversion after the memory cell array's computation, and the output circuit's data output follows the conversion circuit's conversion. The pipeline cycle (T_Pipe) includes the sum of one run time for the memory cell array, one run time for the conversion circuit, and one run time for the output circuit. Furthermore, one run of this pipeline cannot begin until the previous run has finished.

[0090] In this example, when any one of the memory cell array, conversion circuit, and output circuit is running, the other two are idle. Therefore, in the timing of the sequential pipeline, the three-stage circuit is not fully utilized in the time domain, which is not conducive to improving the overall computing power of the in-memory computing device.

[0091] In view of this, embodiments of this application provide a memory computing device that can improve the parallelism of circuit operation in the memory computing device, thereby improving the utilization rate of the circuit and thus improving the computing power and computing performance of the memory computing device.

[0092] Figure 4 shows a schematic block diagram of a storage device 400 provided in an embodiment of this application.

[0093] As shown in Figure 4, the in-memory computing device 400 includes a storage circuit 410, a conversion circuit 420, and an output circuit 430. The storage circuit 410 performs multiple calculations within a pipeline cycle (which can be referred to as the first pipeline cycle for distinction). These multiple calculations output multiple signals, and multiple calculations can begin within the pipeline cycle, but it is not required that the multiple calculations be completed within the pipeline cycle. For example, only a portion of the calculations, such as one calculation, can be completed; or, for instance, some or all of the calculations can be completed. The conversion circuit 420 is connected to the storage circuit 410 and performs a first conversion on the multiple signals, outputting multiple conversion results. The output circuit 430 is connected to the conversion circuit 420 and performs a second conversion on the multiple conversion results, outputting multiple calculation results. The multiple calculations include the first calculation and the second calculation. The process of the conversion circuit 420 performing the first conversion on the first signal output from the first calculation runs in parallel with the process of the second calculation.

[0094] In the aforementioned in-memory computing devices, the storage circuitry can perform parallel computations within a pipeline cycle. While one computation is running, other computations can be initiated, preparing for more computational outputs in advance. Furthermore, at least some of the computations can reuse conversion circuits. When a conversion circuit converts the output of one computation, other computations sharing that conversion circuit can prepare their outputs in advance. When a conversion circuit completes the conversion of one output, it can quickly obtain the input for the next conversion, reducing waiting time and improving the overall computing power of the in-memory computing device. In addition, the computation process of the storage circuitry can be executed in parallel with the conversion process of the conversion circuitry. The runtime of the storage circuitry can be utilized to execute the conversion process in parallel, further enhancing the parallelism of the circuits in the in-memory computing device. Therefore, the circuits in the aforementioned in-memory computing devices can be more fully utilized in the time domain, thereby improving the computing power and performance of the in-memory computing device.

[0095] In this embodiment, the calculation and conversion processes of the storage circuit 410, the conversion circuit 420, and the output circuit 430 can be found in the relevant descriptions of the preceding embodiments. As an example, the conversion circuit 420 can be used to perform a first conversion from a current signal to a voltage signal, and the output circuit 430 can be used to perform a second conversion from an analog signal to a digital signal. Optionally, the conversion circuit 420 may include, for example, a TIA (Transient Analog Array), and the output circuit 430 may include, for example, an ADC (Digital Converter).

[0096] This application embodiment illustrates multiple calculations performed by the storage circuit 410, including a first calculation and a second calculation. This application does not limit the number of calculations that can be performed within a pipeline cycle. For example, the multiple calculations may also include three or more calculations. For instance, the multiple calculations may also include a third calculation, a fourth calculation, etc. In this case, the schemes for any two of the multiple calculations can be found in the relevant descriptions of the various embodiments of this application; repeated details will not be elaborated upon here. This application does not limit the completeness of the calculations within a pipeline cycle; performing multiple calculations within a pipeline cycle may include some or all of the calculations being completed within the pipeline cycle.

[0097] In this embodiment, the computation process may include a stabilization process and a holding process. The stabilization process, for example, refers to the process by which a storage circuit completes a computation from receiving an input signal to outputting a stable output signal. The holding process, for example, refers to the process by which the storage circuit maintains the output signal obtained from a computation. Taking computation on a per-storage-cell basis as an example, the stabilization process refers to the process by which the storage cell group receives an input signal and outputs a stable output signal; the holding process refers to the process by which the storage cell group maintains a stable output signal. The computation stabilization time is the time of the stabilization process, and the output holding time is the time of the holding process.

[0098] In the embodiments of this application, "parallelism" can include: different running processes overlapping in time, which can include partial or complete overlap. For example, in the above embodiments, the parallelism between the process of the conversion circuit 420 performing the first conversion on the first signal and the running process of the second calculation can include: the process of the first conversion overlapping with the running process of the second calculation in time, for example, within the time period of the running process of the storage circuit 410 performing the second calculation. Optionally, the time of the process of the conversion circuit 420 performing the first conversion on the first signal can be within the calculation stabilization time of the storage circuit 410 performing the second calculation, or within the output hold time of the storage circuit 410 performing the second calculation.

[0099] In some embodiments, the storage circuit 410 outputs a first signal through a first calculation and outputs a second signal through a second calculation. The conversion circuit 420 performs a first conversion on the first signal and outputs a first conversion result, and the output circuit 430 performs a second conversion on the first conversion result. The process of the output circuit 430 performing the second conversion on the first conversion result is parallel to the process of the conversion circuit 420 performing the first conversion on the second signal. In other words, the time for the output circuit 430 to perform the second conversion on the first conversion result may at least partially overlap with the time for the conversion circuit 420 to perform the first conversion on the second signal. Optionally, the time for the output circuit 430 to perform the second conversion on the first conversion result may completely overlap with the time for the conversion circuit 420 to perform the first conversion on the first signal.

[0100] Through this implementation, the in-memory computing device can not only achieve parallelism between the storage circuit and the conversion circuit, but also further achieve parallelism between the conversion circuit and the output circuit. In this way, after the conversion circuit outputs the conversion result, it can receive the next input and perform the next conversion as soon as possible. The output circuit's output of the conversion result can be parallel to the next conversion of the conversion circuit, thereby further improving the parallelism of the circuits in the in-memory computing device and greatly enhancing the computing power of the in-memory computing device.

[0101] In some embodiments, the storage circuit 410 outputs a first signal through a first calculation, and the conversion circuit 420 performs a first conversion on the first signal to output a first conversion result; the output circuit 430 performs a second conversion on the first conversion result, wherein the process of the output circuit 430 performing the second conversion on the first conversion result is parallel to the process of the storage circuit 410 performing the second calculation. In other words, the time for the output circuit 430 to perform the second conversion on the first conversion result may at least partially overlap with the running time of the storage circuit 410 performing the second calculation. Optionally, the time for the output circuit 430 to perform the second conversion on the first conversion result may be within the running time of the storage circuit 410 performing the second calculation. For example, the time for the output circuit 430 to perform the second conversion on the first conversion result may be within the calculation stabilization time of the storage circuit 410 performing the second calculation, or within the output hold time of the storage circuit 410 performing the second calculation.

[0102] In some implementations, the number of calculations performed by the in-memory computing device within a pipeline cycle is related to one or more of unit computation time, unit conversion time, and unit output time. That is, it can be determined based on one or more of unit computation time, unit conversion time, and unit output time. The pipeline cycle of the in-memory computing device can include the time interval between two adjacent calculations performed by the same computational unit (e.g., a group of memory cells) of the storage circuit. By repeatedly running multiple pipeline cycles, the in-memory computing device can be effectively controlled to continuously perform multiple rounds of calculations, continuously outputting calculation results, and ensuring that intermediate output results from multiple rounds of calculations, such as signals output by the storage circuit during calculations and conversion results output by the conversion circuit during the first conversion, can be processed in a timely manner. This allows one or more of the storage circuit, conversion circuit, and output circuit to be fully utilized in the time domain, thereby improving the computing power of the in-memory computing device. The unit computation time of the storage circuit is the time for the storage circuit to perform one calculation; this unit computation time can include the calculation settling time in one calculation. The unit conversion time of the conversion circuit is the running time for the conversion circuit to perform one conversion (also referred to as the first conversion above). The unit output time of the output circuit is the running time for the output circuit to perform one output (also referred to as the second conversion above).

[0103] In some implementations, for circuits with long runtimes, such as memory circuits, the output density of the circuit over a period of time can be increased by increasing the computational parallelism, so as to match the output density of circuits with shorter runtimes (e.g., conversion circuits and / or output circuits) over a period of time, thereby improving the utilization of these circuits.

[0104] For ease of understanding, Figure 5 shows a pipeline diagram of a memory computing device provided in an embodiment of this application. In Figure 5, C1 represents the time for the memory circuit to perform a first calculation, C2 represents the time for the memory circuit to perform a second calculation, T1-1 represents the time for the conversion circuit to perform a first conversion on the first signal output from the first calculation, T2-1 represents the time for the output circuit to perform a second conversion on the first conversion result of the first signal, T1-2 represents the time for the conversion circuit to perform a first conversion on the second signal output from the second calculation, and T2-2 represents the time for the output circuit to perform a second conversion on the second conversion result of the second signal.

[0105] Referring to Figure 5(a), as an example, T1-1 can be entirely located within C2, meaning the time for the conversion circuit to perform the first conversion on the first signal output from the first calculation can be entirely within the running time of the storage circuit performing the second calculation. Optionally, in some embodiments, the end times of T1-1 and C2 are the same, meaning the time interval between the two calculations can differ by a unit conversion time. This is beneficial for the conversion circuit to quickly perform the conversion on the second signal after performing the conversion on the first signal, reducing intermediate waiting time and thus improving the utilization rate of the conversion circuit to enhance the computing power of the in-memory computing device.

[0106] In some implementations, as shown in Figure 5(a), T2-1 and T1-2 can also completely overlap, meaning the time for the output circuit to perform the second conversion on the first conversion result of the first signal completely overlaps with the time for the conversion circuit to perform the first conversion on the second calculated output signal. That is, the unit conversion time and unit output time can be substantially the same, i.e., the absolute value of the difference between the unit conversion time and the unit output time is less than or equal to a time threshold, which is an error tolerance time. This embodiment does not limit its value; as long as the unit conversion time and unit output time are considered to be the same within the error tolerance range, it is acceptable. This implementation allows the conversion circuit and output circuit to have a longer parallel duration and improves the tightness of cooperation between the calculation circuit, conversion circuit, and output circuit, thereby more efficiently improving the computing power and performance of the in-memory computing device.

[0107] In other implementations, the end time of T1-1 may not be the same as the end time of C2. For example, the time interval between the two calculations may be greater than or less than the unit conversion time. T2-1 and T1-2 may also partially overlap. The duration of T2-1 may be equal to or unequal to the duration of T1-2. For example, the unit conversion time and the unit output time may be different.

[0108] Referring to Figure 5(b), as an example, T1-1 and T2-1 can both be entirely located within C2. That is, the time for the conversion circuit to perform the first conversion on the first signal output from the first calculation, and the time for the output circuit to perform the second conversion on the result of the first conversion, are both entirely within the running time of the storage circuit performing the second calculation. Optionally, in some embodiments, the end times of T2-1 and C2 are the same, that is, the time interval between the two calculations can differ by the sum of the unit conversion time and the unit output time. Similar to the above description, the unit conversion time and the unit output time can be substantially the same, allowing the conversion circuit and the output circuit to have a larger parallel duration and improving the tightness of cooperation between the calculation circuit, the conversion circuit, and the output circuit, thereby more efficiently improving the computing power and performance of the in-memory computing device.

[0109] In other implementations, the end time of T2-1 may not be the same as the end time of C2. For example, the time interval between the two calculations may be greater than or less than the sum of the unit conversion time and the unit output time. For example, the end time of C2 may lie between the start and end times of T2-1. T2-1 and T1-2 may also partially overlap. The duration of T2-1 may be equal to or unequal to the duration of T1-2. For example, the unit conversion time and the unit output time may be different.

[0110] In some other implementations, the start times of C1 and C2 can be the same, and the output hold time of the signals output by the first calculation and the second calculation can at least cover the time of the first conversion of the signals output by the first calculation and the second calculation, so as to improve the parallelism by utilizing the parallel operation of the calculation that takes a long time, and to use the output hold time to realize at least the first conversion of the parallel output signals.

[0111] In some implementations, the number of calculations performed by the in-memory computing device within a pipeline cycle can be used to characterize the parallelism of the in-memory computing device. The more calculations the in-memory computing device performs within the same pipeline cycle, the higher its parallelism.

[0112] The following describes several timing design schemes for pipelines with reference to the accompanying drawings.

[0113] Figure 6 shows a schematic block diagram of another in-memory computing device 600 provided in an embodiment of this application.

[0114] As shown in Figure 6, in this in-memory computing device 600, the storage circuit may include: an array of N storage cells (hereinafter referred to as a storage array) 610, a conversion circuit 620 connected to the N storage arrays, where N is a positive integer greater than 1; and an output circuit 630 connected to the conversion circuit 620. The storage array 610 may include a one-dimensional array or a two-dimensional array. This disclosure does not limit the structure of the storage array. For example, please refer to the description of the storage cell array in the embodiment shown in Figure 2 above. The structures of the conversion circuit 620 and the output circuit 630 can also be found in the relevant descriptions of the embodiments above.

[0115] N storage arrays 610 are used to perform N calculations within a pipeline cycle, where the start time of any two adjacent calculations differs by a first time interval. A conversion circuit 620 performs a serial first conversion on the N signals output from these N calculations. An output circuit 630 performs a serial second conversion on the N conversion results from the conversion circuit 620. As an example, as shown in Figure 6, the N storage arrays 610 can be used to receive N input data D respectively. in1 To D inN And obtain N output signals I out1 to I outN The conversion circuit 720 can perform serial conversion on the N output signals to obtain N conversion results V. out1 To V outN The output circuit 730 can serially output the N conversion results to obtain N calculation results D. out1 To D outN Different storage arrays may receive the same or different input data. Input data D in1 To D inN Any input data in the array can include multiple input signals, which can be provided to computational units (e.g., groups of memory cells) within the storage array. The computational units perform calculations on the multiple input signals based on stored weight data to obtain an output signal. Output signal I out1 to I outN Any output signal in the system may include the output signals of one or more computational units.

[0116] To facilitate understanding of the operating timing of the in-memory computing device 600 shown in Figure 6, Figure 7 shows a pipeline diagram of the in-memory computing device 600.

[0117] As shown in Figure 7, the computation time (which can be greater than or equal to the unit computation time) of the N memory arrays is represented by C1 to CN. Within one pipeline cycle (represented as T_Pipe in the figure), the computation start time interval between two adjacent memory arrays is a first time interval t1. These two adjacent memory arrays are time-adjacent arrays, not necessarily physically adjacent. If the computation time of the memory arrays is the same, the computation end time of two adjacent memory arrays also differs by a first time interval t1. Based on this time difference t1, the conversion circuit performs a serial conversion on the N signals output by the N memory arrays. The unit running time (or unit conversion time) of this conversion circuit is represented by T1-i in the figure. After the conversion circuit converts the output signals of the memory arrays to obtain the conversion results, the output circuit can perform a second serial conversion on the N conversion results. The unit running time (or unit output time) of this output circuit is represented by T2-i in the figure. Where i∈[1,N].

[0118] In some embodiments, the conversion circuit and the output circuit can perform a first conversion and a second conversion on the same calculated output signal in series. Optionally, the process of the conversion circuit performing the first conversion on the previously calculated output signal can be parallel to the current calculation process, and optionally, it can also be parallel to the process of one or more subsequent calculations. Optionally, the process of the output circuit performing the second conversion on the conversion result of the previously calculated output signal can be parallel to the process of the conversion circuit performing the first conversion on the currently calculated output signal.

[0119] Through the technical solution of the embodiments of this application, the computation start time of multiple storage arrays has a time difference. By utilizing this time difference, the storage arrays and conversion circuits can run in parallel, and the conversion circuits and output circuits can run in parallel. Thus, the in-memory computing device with multiple storage arrays has a high degree of parallelism, and the multiple circuits cooperate closely. In the time domain, the storage circuits, conversion circuits, and output circuits can all have high utilization rates. Therefore, the in-memory computing device provided by the embodiments of this application can have high computing power and better computing performance.

[0120] Furthermore, in this embodiment, multiple memory arrays can reuse conversion circuits and output circuits. For example, a memory array may include multiple memory cell groups, and the memory array can reuse conversion circuits and output circuits by memory cell group. By reusing conversion circuits and output circuits, the number of hardware circuits can be reduced, which is beneficial to reducing hardware costs and can also reduce the size of the in-memory computing device, thereby reserving more space for other circuits in the chip or reducing the chip size.

[0121] In some implementations, the aforementioned first time can be determined based on a unit conversion time or a unit output time. The unit conversion time of the conversion circuit and the unit output time of the output circuit can affect the overall pipeline timing of the in-memory computing device. In order to provide parallelism between the storage circuit and the conversion circuit, and / or between the conversion circuit and the output circuit, a suitable first time can be designed based on the unit conversion time of the conversion circuit and the unit output time of the output circuit, thereby improving the parallelism and computing power of the in-memory computing device.

[0122] Optionally, the unit conversion time and unit output time can be the same or different. For example, the unit conversion time and unit output time can be essentially the same, meaning the absolute value of the difference between the unit conversion time and unit output time is less than or equal to a time threshold. With this implementation, the time difference between the unit conversion time and unit output time is small or even zero, which is beneficial for timing design and simplifies the timing control of the conversion circuit and output circuit by the control circuit. Furthermore, having essentially the same unit conversion time and unit output time allows for greater parallelism between the two circuits and enables tighter coordination between them, further improving the computing power of the in-memory computing device while reducing the complexity of the control circuit design.

[0123] In the example shown in Figure 7, the first time t1 can be equal to the unit conversion time of the conversion circuit or the unit output time of the output circuit. In this mode, the conversion circuit can continuously convert N signals output from the N memory arrays, and the start time of the conversion of one signal is close to or equal to the end time of the corresponding calculation. This achieves close cooperation between the memory circuit and the conversion circuit, reduces waiting time, and fully utilizes the computing power of the conversion circuit. In some embodiments, the output circuit can continuously perform a second conversion on the N conversion results serially output by the conversion circuit, and the start time of the output circuit for one conversion result is close to or equal to the end time of the corresponding conversion. This also achieves close cooperation between the conversion circuit and the output circuit, reduces waiting time, and fully utilizes the computing power of the output circuit. Combining these two implementations, in some embodiments, the N memory arrays, the conversion circuit, and the output circuit can cooperate closely, and the in-memory computing device can have high computing power and superior performance.

[0124] For example, N memory arrays independently and sequentially start computation, with an interval of t1 between each start. After one memory array completes its computation, it sends its output signal to a conversion circuit. The conversion circuit receives the input from the memory array, performs a first conversion, and sends the result to the output circuit. After each conversion, the conversion circuit can immediately receive the next signal from another memory array, improving its utilization. The output circuit receives the conversion result from the conversion circuit, performs a second conversion, and then outputs the computation result to the subsequent processing system. When the operation time of the conversion circuit and the output circuit is the same, the output circuit can immediately receive the next input from the conversion circuit after each output, improving its utilization. After N memory arrays complete N rounds of computation, they can immediately enter a new round of computation, further enhancing the computing power of the in-memory computing device.

[0125] Optionally, in some embodiments, the pipeline cycle of the in-memory computing device can be determined based on the unit computation time of the memory arrays. For example, referring to Figure 7, the pipeline cycle of the in-memory computing device (shown as T_Pipe in the figure) may include one unit computation time (or unit runtime). Within this one pipeline cycle, N memory arrays in the in-memory computing device can begin computation. In some embodiments, the conversion circuit and the output circuit can also operate in parallel. Therefore, through the above embodiments of this application, compared with the sequential pipeline design, the utilization rate of the memory circuit, conversion circuit, and output circuit can be improved, effectively increasing the computation speed and operating efficiency of the in-memory computing device, and greatly enhancing computing power.

[0126] In the embodiments described above, there may be no interval between two adjacent cycles in the in-memory computing device. For example, the cycle of the in-memory computing device may be designed to include one unit of computing time. In other embodiments, an interval may be designed between two adjacent cycles. The in-memory computing device may use this interval to periodically adjust its internal circuitry or to provide preparation time for the internal circuitry, thereby improving the operational stability and reliability of the in-memory computing device.

[0127] In this case, the pipeline cycle of the in-memory computing device can be determined based on unit computation time and interval time. The interval time can be determined based on the unit conversion time of the switching circuit. In some embodiments, the pipeline cycle of the in-memory computing device can be determined based on unit computation time and unit conversion time. For example, the interval time may include an integer multiple of the unit conversion time.

[0128] As an example, Figure 8 shows another pipeline diagram of the in-memory computing device provided in an embodiment of this application.

[0129] As shown in Figure 8, in some embodiments, the pipeline cycle T_Pipe of the memory computing device may include the sum of the unit computing time and the interval time t0. In some embodiments, the interval time t0 may be determined based on the unit conversion time of the conversion circuit. For example, the interval time t0 may include an integer multiple of the unit conversion time, including 1 or more times. As an example, the interval time t0 illustrated in Figure 8 is equal to the unit conversion time of the conversion circuit.

[0130] In this embodiment, the interval between two adjacent cycles of the memory computing device is determined based on the unit conversion time of the conversion circuit. This allows for periodic preparation or adjustment of the circuitry within the memory computing device, improving its reliability. For example, an initial interval can be determined based on experience with preparation or adjustment time, and then the unit conversion time can be matched to this initial interval. For instance, if the initial interval is less than the unit conversion time, the interval can be designed to be equal to the unit conversion time. Or, if the initial interval is greater than the unit conversion time but less than twice the unit conversion time, the interval can be designed to be twice the unit conversion time, and so on.

[0131] Optionally, the number N of storage arrays in the aforementioned in-memory computing device can be designed according to the circuit structure and timing requirements of the in-memory computing device. N can be related to one or more of the following: unit computation time, unit conversion time, unit output time, and interval time.

[0132] In some implementations, N can be greater than or equal to the rounded-up ratio of the unit computation time to the unit conversion time.

[0133] Optionally, if the required interval time is 0, N can be equal to the rounded-up ratio of the unit computation time to the unit conversion time. For example, if the ratio of unit computation time to unit conversion time is 6.2, then N can be 7. When N is the rounded-up ratio of unit computation time to unit conversion time, the actual interval time can be 0 or less than 1 unit conversion time.

[0134] Optionally, if the required interval time is not zero, N can be greater than the rounded-up ratio of the unit calculation time to the unit conversion time. For example, if the required interval time is n times the unit conversion time, N is the sum of the rounded-up ratio of the unit calculation time to the unit conversion time and n, where n is a positive integer. For example, if the ratio of unit calculation time to unit conversion time is 6.2, and the required interval time is twice the unit conversion time, then N can be 9.

[0135] In this embodiment, the rounding design N based on the ratio of unit computation time to unit conversion time is beneficial to make full use of the computation time of each memory array and arrange other circuits (including at least one of other memory arrays, conversion circuits, output circuits, etc.) to run synchronously in parallel, thereby greatly improving the parallelism of the internal circuits of the in-memory computing device and thus greatly improving the computing power of the in-memory computing device.

[0136] Figure 9 shows a schematic block diagram of another in-memory computing device 900 provided in an embodiment of this application.

[0137] As shown in Figure 9, the in-memory computing device 900 includes a storage circuit 910, a selection circuit 920, a conversion circuit 930, and an output circuit 940. The selection circuit 920 is connected between the storage circuit 910 and the conversion circuit 930, and is used to select multiple signals output from the N storage arrays in the storage circuit 910 and sequentially input them to the conversion circuit 930. As an example, the selection circuit 920 may include a multiplexer (MUX) for sequentially selecting one signal from the N signals output from the N storage arrays as the input to the conversion circuit 930, thereby sequentially inputting the N signals to the subsequent conversion circuit 930.

[0138] Optionally, the storage array may include M groups of storage cells, where M is a positive integer greater than 1, and each storage cell group includes multiple storage cells connected to the same output terminal. In some embodiments, the multiple storage cells in a storage cell group may be located in the same column or row of the storage array. In other embodiments, the multiple storage cells in a storage cell group may also be located in multiple rows or columns of the storage array. The embodiments of this application do not limit the specific arrangement of the multiple storage cells in a storage cell group in the storage array.

[0139] As an example, the storage array in Figure 9 may include M output lines BL1-BL2. M The M memory cell groups in the memory array can be connected to the M output lines BL. 1- BL M The circuit provides M output terminals and outputs M output signals. The selection circuit 920 may include M selection sub-circuits, each of which is connected to the output terminals of the N memory cell groups of the N memory arrays and is used to select the signal output from one of the N memory cell groups and input it to the conversion circuit 930.

[0140] For example, selector circuit-1 in selector circuit 920 can be connected to the output line BL1 of each of the N memory arrays, thereby connecting to the first group of memory cells in each memory array; similarly, selector circuit-2 can be connected to the output line BL2 of each of the N memory arrays, thereby connecting to the second group of memory cells in each memory array. And so on, selector circuit-M can be connected to the output line BL1 of each of the N memory arrays. M Thus, they are connected to the Mth memory cell group of each memory array. Optionally, the M selection sub-circuits can each select a memory cell group of the same memory array, so that the signal calculated and output by the M memory cell groups of the same memory array is input to the conversion circuit 930. The selection of the same memory array by the M selection sub-circuits can be performed synchronously or asynchronously.

[0141] In some embodiments, the conversion circuit 930 may include M conversion sub-circuits connected to the M selection sub-circuits, each used to perform a first conversion on the M output signals of the M memory cell groups. Optionally, during the conversion process of the conversion circuit 930, the M converted output signals may be the output signals of the M memory cell groups in the same memory array. The M conversion sub-circuits may perform the conversion on the output signals of the M memory cell groups in the same memory array synchronously or asynchronously.

[0142] In some embodiments, the output circuit 940 may include M output sub-circuits connected to the M conversion sub-circuits, each used to perform a second conversion on the M conversion results of the M conversion sub-circuits. Optionally, during the conversion process of the output circuit 940, the M conversion results may originate from the output signals of M memory cell groups in the same memory array. The second conversion of the conversion results of the output signals of the M memory cell groups in the same memory array by the M output sub-circuits may be performed synchronously or asynchronously.

[0143] The above selection circuit configuration allows multiple storage arrays to reuse the same conversion and output circuits, reducing the amount of hardware circuitry required and facilitating pipeline control of the storage device.

[0144] In the embodiments shown in Figures 6 to 9 above, the storage circuit includes N storage arrays, and by controlling the time interval between the start calculations of the N storage arrays, the conversion of the conversion circuit and the calculation of the storage arrays are parallelized, thereby improving the computing power of the in-memory computing device. The embodiments below provide another circuit architecture for the in-memory computing device, which can further reduce the hardware resources of the in-memory computing device while also improving the computing power of the in-memory computing device.

[0145] Figure 10 shows a schematic block diagram of another in-memory computing device 1000 provided in an embodiment of this application.

[0146] As shown in Figure 10, in this in-memory computing device 1000, the storage circuit includes: N1 storage cell groups 1010, each storage cell group comprising multiple storage cells connected to the same output terminal, where N1 is a positive integer greater than 1. These N1 storage cell groups are used to perform N1 calculations within a pipeline cycle (e.g., the first pipeline cycle described above). A conversion circuit 1020 is used to perform a serial first conversion on the N1 signals output from the N1 calculations within the pipeline cycle. An output circuit 1030 is used to perform a serial second conversion on the N1 conversion results of the conversion circuit 1020. These N1 storage cell groups may belong to the same storage array, such as a first storage array. The first storage array may also include other storage cell groups besides these N1 storage cell groups. In some embodiments, N1 may be equal to the number of serial stages in which the conversion circuit 1020 performs the first conversion on the signals output by the storage circuit.

[0147] In this embodiment, at least two memory cell groups in the same memory array can reuse the conversion circuit and / or output circuit, reducing the number of conversion circuits and / or output circuits and further saving hardware resources. The conversion circuit 1020 and / or output circuit 1030 can operate in parallel with the memory circuit. For example, the running time of the conversion circuit 1020 and / or output circuit 1030 can overlap with the output hold time of the memory circuit. As an example, after N1 memory cell groups in the memory circuit complete the calculation and output a stable signal, the N1 memory cell groups can enter the output hold time, that is, continuously output a stable signal. Utilizing this output hold time, the conversion circuit can perform a serial first conversion on the N1 signals of the N1 memory cell groups, and / or the output circuit can perform a serial second conversion on the N1 conversion results. This is beneficial for improving the parallelism of the circuits in the in-memory computing device, making full use of the circuits in the time domain, thereby improving the computing power and computing performance of the in-memory computing device.

[0148] For ease of understanding, Figure 11 shows a pipeline diagram of the in-memory computing device 1000 shown in Figure 10.

[0149] As shown in Figure 11, the computation runtime of the N1 memory cell group is denoted as C1. This C1 may include the computation settling time Tr and the output hold time Ts, as shown in the shaded area in Figure 11.

[0150] As shown in Figure 11, within one pipeline cycle T_Pipe, N1 memory cell groups can perform calculations synchronously or asynchronously. This calculation runtime includes a calculation settling time Tr and an output hold time Ts. During the output hold time Ts of the N1 memory cell groups, the conversion circuit and the output circuit can operate in parallel. For example, the conversion circuit can serially perform N1 first conversions on the signals of the N1 memory cell groups. As an example, Figure 11 shows the case where N1 = 4. The 4 memory cell groups complete 4 calculations within the calculation settling time, outputting 4 signals. The conversion circuit can serially perform 4 conversions on the signals output by these 4 memory cell groups. The unit conversion time for one conversion by the conversion circuit is illustrated as T1 in the figure. Similarly, the output circuit can serially perform N1 second conversions on the N1 conversion results. The unit output time for one conversion by the output circuit is illustrated as T2 in the figure.

[0151] Optionally, in the example of Figure 11, the output circuit and the conversion circuit can operate in parallel. For example, the time it takes for the output circuit to perform a second conversion on the first conversion result corresponding to the first signal can at least partially overlap with the time it takes for the conversion circuit to perform a first conversion on the second signal; for example, the two times can completely overlap. Here, the first signal and the second signal are two adjacent signals received serially by the conversion circuit.

[0152] Alternatively, in some implementations, the output circuit and the conversion circuit can also operate in series. Figure 12 shows another pipeline schematic diagram of the in-memory computing device provided in an embodiment of this application.

[0153] In the example shown in Figure 12, after the conversion circuit performs a first conversion on the first signal to obtain a first conversion result, the output circuit performs a second conversion on the first conversion result. After the output circuit completes the second conversion on the first conversion result to output the first calculation result, the conversion circuit can continue to perform a first conversion on the second signal.

[0154] In this embodiment, the pipeline cycle can be determined based on the operating mode of the output circuit and the conversion circuit, the unit computation time, and the unit conversion time; or, the pipeline cycle can be determined based on the operating mode of the output circuit and the conversion circuit, the unit computation time, the unit conversion time, and the unit output time. The operating mode of the output circuit and the conversion circuit includes the serial mode or the parallel mode described above, and the unit computation time, unit conversion time, and unit output time can be referred to the description in the above embodiments. When multiple memory cell groups operate synchronously, the computation settling time Tr can include one unit computation time; when multiple memory cell groups operate asynchronously, the computation settling time Tr can be greater than one unit computation time.

[0155] In the example shown in Figure 11 above, when the output circuit and the conversion circuit operate in parallel, the pipeline cycle T_Pipe of the in-memory computing device can include the sum of the computation settling time Tr (i.e., at least one unit of computation time) and N1 times the unit conversion time. That is, corresponding to Figure 11, T_Pipe = Tr + N1 × T1.

[0156] In the example shown in Figure 12 above, when the output circuit and the conversion circuit operate in series, the pipeline cycle T_Pipe of the in-memory computing device can include the sum of the computation settling time Tr (i.e., at least one unit of computation time), N1 times the unit conversion time, and (N1-1) times the unit output time. That is, corresponding to Figure 12, T_Pipe = Tr + N1 × T1 + (N1-1) × T2.

[0157] In this embodiment, the output circuit and the conversion circuit can be selected to operate serially or in parallel according to actual needs. In the case of serial operation, it is beneficial to simplify the hardware implementation and control of the in-memory computing device and enhance the stability of the in-memory computing device. In the case of parallel operation, the pipeline cycle of the in-memory computing device can be further shortened, the operating efficiency and speed of the in-memory computing device can be improved, thereby further improving the computing power of the in-memory computing device.

[0158] For example, N1 memory cell groups in the same memory array can perform calculations in parallel. These N1 memory cell groups can share a single conversion circuit and output circuit, thereby reducing the number of conversion and output circuits and further saving hardware resources. After a calculation settling time Tr, the N1 memory cell groups complete N1 calculations and output N1 signals, which are sequentially sent to the conversion circuit. Upon receiving the signal, the conversion circuit begins the first conversion. After a unit conversion time T1, the conversion result is sent to the output circuit. The conversion circuit can receive the next signal immediately after completing each conversion, improving its utilization rate. The output circuit receives the conversion result from the conversion circuit, performs a second conversion, and outputs the calculation result to the subsequent processing system. When the running time of the conversion circuit and the output circuit is the same, the output circuit can receive the next input from the conversion circuit immediately after completing each output, improving its utilization rate. After the conversion circuit performs the second conversion on the N1st conversion result, the N1 memory cell groups can enter a new round of calculations, further enhancing the computing power of the in-memory computing device.

[0159] In the above embodiments, the N1 memory cell groups can be a set of memory cells that reuse the same conversion circuit and output circuit in the same memory array. Optionally, in some examples, the memory array may include multiple such memory cell sets. For example, FIG13 shows a schematic block diagram of another in-memory computing device 1300 provided in an embodiment of this application.

[0160] As shown in Figure 13, in the in-memory computing device 1300, the storage circuit includes: a first storage array, which includes M1 sets of storage cells 1310, each set of storage cells 1310 including N1 groups of storage cells, each group of storage cells including multiple storage cells connected to the same output terminal, where N1 and M1 are positive integers greater than 1. The conversion circuit 1320 includes M1 conversion sub-circuits connected to the M1 sets of storage cells, each conversion sub-circuit performing a first conversion on the signal output by a group of storage cells in its corresponding set of storage cells. The output circuit 1330 includes M1 output sub-circuits connected to the M1 conversion sub-circuits, each output sub-circuit performing a second conversion on the conversion result of its corresponding conversion sub-circuit.

[0161] In this embodiment, N1 groups of memory cells in a memory cell set 1310 can share a single conversion sub-circuit. During one conversion process, one conversion sub-circuit can convert the signal of one group of memory cells in the memory cell set 1310. Optionally, M1 conversion sub-circuits can convert the signals output from the M1 groups of memory cells in the M1 memory cell sets 1310 in parallel. Through N1 serial conversions, the M1 conversion sub-circuits can complete the signal conversion of (N1×M1) groups of memory cells in the M1 memory cell sets 1310.

[0162] Similar to the conversion circuit 1320 described above, the output circuit 1330 may include M1 output sub-circuits connected to the M1 conversion sub-circuits. Optionally, the M1 output sub-circuits may perform a second conversion on the M1 conversion results of the M1 conversion sub-circuits in parallel. In addition, through N1 serial conversions, the M1 output sub-circuits may complete the second conversion of (N1×M1) conversion results.

[0163] According to the technical solution of this application embodiment, corresponding to the M1 sets of storage cells in the first storage array, the conversion circuit is provided with M1 corresponding conversion sub-circuits and M1 output sub-circuits. One conversion sub-circuit and one output sub-circuit are responsible for N1 groups of storage cells in one set of storage cells. In other words, N1 groups of storage cells can share one conversion sub-circuit and one output sub-circuit. The number of conversion sub-circuits and output sub-circuits in the in-memory computing device can be reduced to 1 / N1 of the number of groups of storage cells in the storage array. For example, when a group of storage cells is a column of storage cells in the storage array, the number of conversion sub-circuits and output sub-circuits can be 1 / N1 of the number of columns in the storage array. Compared with the technical solution of configuring one conversion sub-circuit and one output sub-circuit for each column of storage cells, the solution provided by this application embodiment can reduce the hardware resources required by the in-memory computing device. On this basis, the M1 conversion sub-circuits can perform the first conversion on the M1 signals generated by the M1 sets of storage cells in parallel, and the M1 output sub-circuits can perform the second conversion on the M1 conversion results in parallel, which is beneficial to improving the parallelism of the internal circuits of the in-memory computing device and thus improving computing power.

[0164] Figure 14 shows a schematic block diagram of another in-memory computing device 1400 provided in an embodiment of this application.

[0165] As shown in Figure 14, the in-memory computing device 1400 includes a storage circuit 1410, a selection circuit 1420, a conversion circuit 1430, and an output circuit 1440. The storage circuit 1410 may include M1 sets of storage cells, and each set of storage cells includes N1 groups of storage cells. The selection circuit 1420 is connected between the M1 sets of storage cells in the storage circuit 1410 and the conversion circuit 1430. The selection circuit 1420 can select signals from the M1 sets of storage cells in parallel and input them to the conversion circuit 1430, and can also select signals from the N1 sets of storage cells in a series and input them to the conversion circuit 1430 sequentially.

[0166] For a set of N1 memory cells, which may include a first memory cell group and a second memory cell group, a selection circuit 1420 may be connected between the conversion circuit and the first and second memory cell groups to time-divisionally select the signals output by the first and second memory cell groups to be input to the conversion circuit. It is understood that the N1 memory cell groups may also include three or more memory cell groups, and the selection circuit can be used to time-divisionally select the signals output by these additional memory cell groups to be input to the conversion circuit.

[0167] Optionally, the first and second storage unit groups can be computed in parallel or in a non-parallel manner. In the case of parallel computing, it is beneficial to shorten the overall computing time of the storage circuit, thereby improving the computing speed and effect.

[0168] Referring again to Figure 14, corresponding to the M1 sets of memory cells in the storage circuit, the selection circuit 1420 may include M1 selection sub-circuits, each connected to one of the M1 sets of memory cells. Each selection sub-circuit can be used to perform time-division selection of the signals output by N1 groups of memory cells within a single set. Optionally, the M1 selection sub-circuits can operate in parallel, performing parallel selection of the signals output by the M1 groups of memory cells within the M1 sets of memory cells.

[0169] Optionally, the conversion circuit 1430 may include M1 conversion sub-circuits connected to the M1 selection sub-circuits. The output circuit 1440 includes M1 output sub-circuits connected to the M1 conversion sub-circuits, and the relevant schemes of the conversion sub-circuits and output sub-circuits can be found in the relevant description of the embodiment shown in FIG13 above.

[0170] Figure 15 shows a schematic structural block diagram of another in-memory computing device 1500 provided in an embodiment of this application.

[0171] As shown in Figure 15, the in-memory computing device 1500 includes: a first memory array 1510, a second memory array 1520, a conversion circuit 1530, and an output circuit 1540. The first memory array 1510 includes N1 memory cell groups, and the second memory array 1520 includes N2 memory cell groups. The conversion circuit 1530 is connected between the first memory array 1510, the second memory array 1520, and the output circuit 1540. In some embodiments, the first memory array 1510 may further include other memory cell groups besides the N1 memory cell groups, and the second memory array 1520 may further include other memory cell groups besides the N2 memory cell groups. In some embodiments, N1 may be equal to the number of serial stages in which the conversion circuit performs the first conversion on the signal output from the first memory array 1510. N2 may be equal to the number of serial stages in which the conversion circuit performs the first conversion on the signal output from the second memory array 1520.

[0172] In the first storage array 1510, N1 memory cell groups can perform N1 calculations in the first pipeline cycle, and in the second storage array 1520, N2 memory cell groups can perform N2 calculations in the second pipeline cycle. A conversion circuit 1530 performs a serial first conversion on the N1 signals output from the N1 calculations and a serial first conversion on the N2 signals output from the N2 calculations. An output circuit 1540 performs a serial second conversion on the N1 conversion results from the conversion circuit 1530 and a serial second conversion on the N2 conversion results. In some embodiments, the first conversions of the N1 and N2 signals can be performed continuously. In some embodiments, the second conversions of the N1 and N2 conversion results can be performed continuously.

[0173] Optionally, the relevant descriptions of the first storage array 1510, the conversion circuit 1530, and the output circuit 1540 in the embodiments of this application can be found in the relevant descriptions of the embodiments shown in Figures 10 to 14 above.

[0174] Optionally, the technical solution in which the second storage array 1520 cooperates with the conversion circuit 1530 and the output circuit 1540 is similar to the technical solution in which the first storage array 1510 cooperates with the conversion circuit 1530 and the output circuit 1540. Please also refer to the relevant description of the embodiments shown in Figures 10 to 14 above.

[0175] As an example, Figure 15 only illustrates that the in-memory computing device includes two memory arrays. The in-memory computing device may also include three or more memory arrays. Any memory array can be converted by a conversion circuit and an output circuit. The relevant schemes for any memory array can be found in the context of the schemes related to the first memory array 1510 and / or the second memory array 1520. This article will not elaborate further.

[0176] In the embodiments of this application, the N1 memory cell groups in the first memory array and the N2 memory cell groups in the second memory array can reuse the conversion circuit and the output circuit. By reusing the conversion circuit and the output circuit, the number of hardware circuits can be saved, which is beneficial to saving hardware resources and reducing hardware costs. It can also reduce the size of the memory computing device, thereby reserving more space for other circuits in the chip or reducing the chip size.

[0177] Optionally, in some implementations, the first flow cycle and the second flow cycle may include overlapping time.

[0178] As examples, Figures 16 and 17 show pipeline diagrams for two other in-memory computing devices.

[0179] As shown in Figures 16 and 17, the runtime of the first and second memory arrays is represented by C1 and C2, respectively. The shaded areas in these runtimes represent the output hold times of the two memory arrays, while the unshaded areas represent the computation settling times. The unit conversion time of one conversion by the conversion circuit is represented by T1, and the unit output time of one conversion by the output circuit is represented by T2.

[0180] Referring to the relevant descriptions in the embodiments shown in Figures 11 and 12 above, for the case where the storage array includes multiple groups of storage cells, the conversion circuit and the output circuit sequentially convert the multiple groups of storage cells. As an example, Figures 16 and 17 show the case where N1 = N2 = 4, that is, for the first storage array and the second storage array, both the conversion circuit and the output circuit perform 4 conversions.

[0181] In the embodiments shown in Figures 16 and 17, the conversion circuit can operate in parallel with the memory array. Optionally, the time during which the conversion circuit converts the signal output from the first memory array may at least partially overlap with the operating time of the first memory array, and / or at least partially overlap with the operating time of the second memory array. In some embodiments, the time during which the conversion circuit converts the signal output from the first memory array may at least partially overlap with the output hold time of the first memory array, and / or at least partially overlap with the calculated settling time of the second memory array. For example, the time during which the conversion circuit converts the signal output from the first memory array may fall within the calculated settling time of the second memory array. As another example, the time during which the conversion circuit converts the signal output from the first memory array may fall within the output hold time of the first memory array.

[0182] Through the technical solution of this embodiment, the conversion circuit can operate in parallel with the first storage array and the second storage array, thereby greatly improving the parallelism of the circuits in the in-memory computing device, improving computing efficiency and computing speed, and thus improving the computing power of the in-memory computing device.

[0183] Optionally, as shown in Figure 16, the output circuit can run in parallel with the conversion circuit. When the conversion circuit and the output circuit run in parallel, the first pipeline cycle T_Pipe1 corresponding to the first memory array can be determined based on the unit computation time and unit conversion time of the first memory array, and the second pipeline cycle T_Pipe2 corresponding to the second memory array can be determined based on the unit computation time and unit conversion time of the second memory array. The calculation methods for the first pipeline cycle of the first memory array and the second pipeline cycle of the second memory array can be found in the relevant description of the embodiment in Figure 11 above.

[0184] Optionally, as shown in Figure 17, the output circuit can also be connected in series with the conversion circuit. When the conversion circuit and output circuit are connected in series, the first pipeline cycle T_Pipe1 corresponding to the first memory array can be determined by the unit computation time, unit conversion time, and unit output time of the first memory array, and the second pipeline cycle T_Pipe2 corresponding to the second memory array can be determined by the unit computation time, unit conversion time, and unit output time of the second memory array. The calculation methods for the first pipeline cycle T_Pipe1 of the first memory array and the second pipeline cycle T_Pipe2 of the second memory array can be found in the relevant description of the embodiment in Figure 12 above.

[0185] Optionally, in some embodiments, the first pipeline cycle T_Pipe1 and the second pipeline cycle T_Pipe2 may include overlapping time. For example, the overlapping time includes the time for the conversion circuit to serially convert the N1 signals of the N1 computed outputs of the first memory array; that is, the time for the conversion circuit to serially convert the N1 signals of the first memory array in the first pipeline cycle T_Pipe1 may be located in the second pipeline cycle T_Pipe2. Optionally, the time for the conversion circuit to serially convert the N1 signals of the first memory array in the first pipeline cycle T_Pipe1 may be located within the computation stabilization time of the second memory array in the second pipeline cycle T_Pipe2.

[0186] Optionally, the aforementioned overlapping time may include, in addition to the time for the conversion circuit to serially convert the N1 signals of the first memory array, at least a portion of the computation time of the first memory array; that is, at least a portion of the computation time of the first memory array in the first pipeline cycle T_Pipe1 may be located in the second pipeline cycle T_Pipe2. Optionally, a portion of the computation time of the first memory array in the first pipeline cycle T_Pipe1 may be located within the computation time of the second memory array in the second pipeline cycle T_Pipe2.

[0187] The technical solution of this application embodiment includes overlapping time between the first pipeline cycle of the first storage array and the second pipeline cycle of the second storage array, which enables the first storage array and the second storage array to operate in parallel, thereby improving the utilization rate of each storage array in the time domain and enhancing the computing power of the in-memory computing device.

[0188] Optionally, the time interval between the start time of the first memory array and the start time of the second memory array (shown as the first time t1 in Figures 16 and 17) can be controlled to achieve the overlap between the first pipeline cycle and the second pipeline cycle.

[0189] Optionally, the first time t1 can be determined based on one or more of the following: unit conversion time, unit output time, unit computation time of the first storage array, and unit computation time of the second storage array.

[0190] For example, in the embodiment shown in Figure 16, the first time t1 can be equal to N1 times the unit conversion time, i.e., t1 = N1 × T1. In the embodiment shown in Figure 17, the first time t1 can be equal to the sum of N1 times the unit conversion time and (N1-1) times the unit output time, i.e., t1 = N1 × T1 + (N1-1) × T2.

[0191] In this approach, the conversion circuit can continuously convert the signals output by the first and second memory arrays, and the start time of the conversion circuit for the signals output by the memory array is close to or equal to the end time of the computation of that memory array. Therefore, in this embodiment, the conversion circuit and the multiple memory arrays cooperate closely, and the parallelism of each circuit is high. This not only improves the computing power of the in-memory computing device but also helps to improve the reliability of the in-memory computing device.

[0192] In other embodiments, the computation settling time and output hold time of the first storage array are substantially the same, and the computation settling time and output hold time of the second storage array are substantially the same. The output hold time of the first storage array and the computation settling time of the second storage array substantially overlap, and the output hold time of the second storage array substantially overlaps with the computation settling time of the first storage array in the next round. In some embodiments, the first pipeline cycle T_Pipe1 = the second pipeline cycle T_Pipe2.

[0193] In other embodiments, the first time t1 may also be equal to the computation settling time of the first memory array and / or the computation settling time of the second memory array. For example, in the examples shown in Figures 16 and 17, t1 may be equal to the computation settling time of the first memory array (the unshaded area of ​​C1 in the figures). The computation settling time of the first memory array may be equal to at least one unit of computation time. In this embodiment, the first pipeline cycle and the second pipeline cycle overlap to improve the parallelism of the circuitry in the in-memory computing device.

[0194] In practical applications, the initial computation interval (first time t1) of the two storage arrays can be adaptively designed according to the actual situation to comprehensively optimize the hardware architecture and improve the parallel time of the circuits in the in-memory computing device, thereby improving the computing power of the in-memory computing device.

[0195] For example, two memory arrays perform calculations alternately. The starting calculation time of the second memory array lags behind the stabilization time of the first memory array compared to the starting calculation time of the first memory array, or lags behind the conversion time of the conversion circuit for the first memory array (this time can be equal to N1 times the unit conversion time or the sum of N1 times the unit conversion time and (N1-1) times the unit output time). After the memory array completes the calculation, it outputs multiple signals, for example, N1 signals from the first memory array and N2 signals from the second memory array, which are sequentially sent to the conversion circuit. Upon receiving the signals, the conversion circuit begins the first conversion and sends the conversion result to the output circuit. The conversion circuit can receive the next signal immediately after completing each conversion, improving the utilization rate of the conversion circuit. The output circuit receives the conversion result from the conversion circuit, performs the second conversion, and outputs the calculation result to the subsequent processing system. When the running time of the conversion circuit and the output circuit is the same, the output circuit can receive the next input from the conversion circuit immediately after completing each output, improving the utilization rate of the output circuit. After the conversion circuit completes the conversion of the last signal from the memory array, multiple memory cell groups in the array can enter a new round of computation, further enhancing the computing power of the in-memory computing device. Optionally, the first conversion of the signals output by the first and second memory arrays can be performed alternately, or the first conversion of the signal output by one memory array can be performed first, followed by the first conversion of the signal output by the other memory array. Similarly, the second conversion of the conversion results of the signals output by the first and second memory arrays can be performed alternately, or the second conversion of the conversion result of the signal output by one memory array can be performed first, followed by the second conversion of the conversion result of the signal output by the other memory array. This scheme allows the two memory arrays to reuse the same conversion circuit and output circuit, thereby saving hardware resources of the in-memory computing device.

[0196] Figure 18 shows a schematic structural block diagram of another in-memory computing device 1800 provided in an embodiment of this application.

[0197] As shown in Figure 18, the in-memory computing device 1800 includes: a first memory array 1810, a second memory array 1820, a selection circuit 1830, a conversion circuit, and an output circuit. Both the first memory array 1810 and the second memory array 1820 can be connected to the selection circuit 1830, and the conversion circuit is connected between the selection circuit 1830 and the output circuit. The selection circuit 1830 can be used to time-division select the signal inputs of the first memory array 1810 and the second memory array 1820 to the conversion circuit.

[0198] As an example, the first storage array 1810 may include a first storage cell group and a second storage cell group, and the second storage array 1820 may include a third storage cell group and a fourth storage cell group. All four storage cell groups can be connected to a selection circuit, and the selection circuit 1830 can be used to time-division select the signal output from the four storage cell groups to be input to the conversion circuit.

[0199] This application embodiment only takes the memory computing device 1800 including a first memory array 1810 and a second memory array 1820, and both the first memory array 1810 and the second memory array 1820 include two memory cell groups as an example. The memory computing device 1800 may also include three or more memory arrays, and a memory array may also include three or more memory cell groups. The selection circuit 1830 can be used to select the signal output of the more memory cell groups in a time-division manner to input to the conversion circuit.

[0200] Referring again to Figure 18, in some embodiments, the first storage array 1810, as shown in Figures 13 and 14 above, includes M sets of storage cells, and each set of storage cells includes N1 groups of storage cells. Similar to the first storage array 1810, the second storage array 1820 may also include M sets of storage cells, and each set of storage cells includes N2 groups of storage cells.

[0201] The selection circuit 1830 may include multiple selection sub-circuits for connecting to sets of memory cells in two memory arrays, respectively. For example, the selection circuit 1830 may include M selection sub-circuits. For instance, one selection sub-circuit in the selection circuit 1830 may be connected to a set of memory cells in the first memory array 1810 and a set of memory cells in the second memory array 1820, respectively. This selection sub-circuit can be used to perform time-division multiplexing of the memory cell groups in the two sets of memory cells in the two memory arrays for input to the conversion circuit. Furthermore, the multiple selection sub-circuits can execute in parallel to achieve parallel input of signals from multiple sets of memory cells to the conversion circuit, thereby improving parallelism.

[0202] In the embodiment shown in FIG18, the conversion circuit may include a plurality of conversion sub-circuits connected to a plurality of selection sub-circuits (conversion sub-circuit-1 and conversion sub-circuit-M are illustrated in the figure), and the output circuit may include a plurality of output sub-circuits connected to a plurality of selection sub-circuits (output sub-circuit-1 and output sub-circuit-M are illustrated in the figure).

[0203] In this embodiment, not only can multiple memory arrays (such as the first and second memory arrays mentioned above) reuse the same conversion circuit and output circuit, but multiple sets of memory cells in multiple memory arrays can reuse the same conversion sub-circuit in the conversion circuit and the same output sub-circuit in the output circuit. By reusing the conversion circuit and output circuit, and by reusing the conversion sub-circuit in the conversion circuit and the output sub-circuit in the output circuit, the number of hardware circuits can be reduced to a large extent, which is beneficial for saving hardware resources and reducing hardware costs. It can also reduce the size of the in-memory computing device, thereby reserving more space for other circuits in the chip or reducing the chip size.

[0204] The above description, with reference to Figures 4 to 18, illustrates the device embodiments provided in this application. The following description, with reference to Figure 19, illustrates the method embodiments provided in this application. For ease of description and brevity, the steps of the method embodiments described below can be referenced to the corresponding descriptions in the foregoing device embodiments; repeated details will not be elaborated upon.

[0205] Figure 19 shows a schematic flowchart of a control method provided in an embodiment of this application. This control method is used to control a storage circuit, a conversion circuit, and an output circuit.

[0206] As shown in Figure 19, the control method 1900 may include the following steps.

[0207] 1910: The control storage circuit performs multiple calculations during the first pipeline cycle.

[0208] 1920: The control conversion circuit performs a first conversion on multiple signals from multiple calculation outputs to output multiple conversion results.

[0209] 1930: The control output circuit performs a second conversion on multiple conversion results to output multiple calculation results.

[0210] The calculations include a first calculation and a second calculation. The above-mentioned 1920 may include: the process of the control conversion circuit performing a first conversion on the first signal output by the first calculation in parallel with the running process of the second calculation.

[0211] Optionally, the in-memory computing device in this application embodiment can be any of the in-memory computing devices provided in Figures 4 to 8 above. The control method 1900 can be executed by a control device, which can be used to control the operating sequence of the circuits in the in-memory computing device to complete the calculation, conversion and output of data.

[0212] Optionally, the control device and the in-memory computing device can be separate physical devices, for example, they can be separate semiconductor chips. The control device may include at least one control chip, and the in-memory computing device may include at least one memory chip. Optionally, the storage circuit, conversion circuit, and output circuit in the in-memory computing device can also be separate physical devices, for example, they can be separate semiconductor chips. Alternatively, the storage circuit, conversion circuit, and output circuit can be integrated into the same semiconductor chip.

[0213] In some possible implementations, 1920 above may include: controlling the conversion circuit to perform a first conversion on the first signal and outputting a first conversion result. 1930 above may include: the process of controlling the output circuit to perform a second conversion on the first conversion result is parallel to the process of the conversion circuit to perform a first conversion on the second signal calculated and output by the second conversion circuit.

[0214] In some possible implementations, 1920 above may include: controlling the conversion circuit to perform a first conversion on the first signal and outputting a first conversion result. 1930 above may include: controlling the output circuit to perform a second conversion on the first conversion result in parallel with the execution process of the second calculation.

[0215] Optionally, the number of calculations performed within the first flow cycle is related to one or more of the unit calculation time, unit conversion time, and unit output time.

[0216] As one possible circuit structure, the above-mentioned storage circuit may include: N storage arrays, with a conversion circuit connected to the N storage arrays, where N is a positive integer greater than 1; wherein, 1910 may include: controlling the N storage arrays to perform N calculations within a first pipeline cycle, wherein the start time of any two adjacent calculations differs by a first time interval. 1920 may include: controlling the conversion circuit to perform a serial first conversion on the N signals output from the N calculations. 1930 may include: controlling the output circuit to perform a serial second conversion on the N conversion results of the conversion circuit.

[0217] Optionally, the first time can be determined based on unit conversion time or unit output time. In some implementations, the absolute value of the difference between the unit conversion time and the unit output time is less than or equal to a time threshold.

[0218] Optionally, the first pipeline cycle may be determined based on unit computation time, or unit computation time and unit conversion time. In some embodiments, the first pipeline cycle includes unit computation time and an interval time, the interval time being an integer multiple of the unit conversion time.

[0219] The in-memory computing device includes N memory arrays, a conversion circuit, and an output circuit. The device further includes a selection circuit connected between the conversion circuit and the N memory arrays. The control method provided in this application further includes controlling the selection circuit to sequentially input multiple signals output from the N memory arrays to the conversion circuit.

[0220] In some possible implementations, one of the N memory arrays comprises M memory cell groups, where M is a positive integer greater than 1; each memory cell group comprises multiple memory cells connected to the same output terminal. The selection circuit may include M selection sub-circuits, one of which is connected to the output terminal of each of the N memory cell groups in the N memory arrays. The control method may include controlling the selection circuit to select the signal output from one of the N memory cell groups and input it to the conversion circuit.

[0221] As another possible circuit structure, the above-mentioned storage circuit may include: a first storage array comprising N1 groups of storage cells, each group comprising multiple storage cells connected to the same output terminal, where N1 is a positive integer greater than 1. 1910 may include: controlling the N1 groups of storage cells to perform N1 calculations within a first pipeline cycle. 1920 may include: controlling a conversion circuit to perform a serial first conversion on the N1 signals output from the N1 calculations within the first pipeline cycle, obtaining N1 conversion results. 1930 may include: controlling an output circuit to perform a serial second conversion on the N1 conversion results.

[0222] In some possible implementations, the output circuit and the conversion circuit operate in parallel, or the output circuit and the conversion circuit operate in series.

[0223] Optionally, the first pipeline cycle can be determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, and the unit conversion time; or, the first pipeline cycle can be determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, the unit conversion time, and the unit output time.

[0224] For example, the output circuit and the conversion circuit operate in parallel, and the first pipeline cycle includes at least one unit of computation time and N1 times the unit conversion time.

[0225] For example, the output circuit and the conversion circuit operate in series, and the first pipeline cycle includes at least one unit of computation time, N1 times the unit of conversion time, and (N1-1) times the unit of output time.

[0226] Optionally, the aforementioned N1 memory cell groups include a first memory cell group and a second memory cell group. The memory computing device may further include a selection circuit connected between the conversion circuit and the first and second memory cell groups. The control method further includes controlling the selection circuit to time-division select the signals output by the first and second memory cell groups and input them to the conversion circuit.

[0227] In some implementations, the first and second memory cell groups are computed in parallel.

[0228] Optionally, in addition to the first storage array, the storage circuit further includes a second storage array, which comprises N2 groups of storage cells, where N2 is a positive integer greater than 1. The control method further includes: controlling the N2 groups of storage cells to perform N2 calculations within a second pipeline cycle; controlling the conversion circuit to perform a serial first conversion on the N2 signals output from the N2 calculations within the second pipeline cycle to obtain N2 conversion results; and controlling the output circuit to perform a serial second conversion on the N2 conversion results.

[0229] Optionally, the first pipeline cycle and the second pipeline cycle include an overlap time. In some embodiments, this overlap time includes the time it takes for the conversion circuit to serially convert the N1 signals of the N1 computed outputs.

[0230] Optionally, in the first storage array, the N1 storage cell groups include a first storage cell group and a second storage cell group; in the second storage array, the N2 storage cell groups include a third storage cell group and a fourth storage cell group. The storage and computing device further includes a selection circuit connected between the conversion circuit and the first and second storage arrays. In this case, the control method further includes controlling the selection circuit to time-division select the signals output from the first, second, third, and fourth storage cell groups and input them to the conversion circuit.

[0231] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0232] This application also provides a control device for controlling a memory computing device, the memory computing device including a storage circuit, a conversion circuit, and an output circuit. Figure 20 shows a schematic structural block diagram of a control device 2000 provided in an embodiment of this application.

[0233] The control device 2000 includes a first control module 2010, a second control module 2020, and a third control module 2030. The first control module 2010 controls the storage circuit to perform multiple calculations within a first pipeline cycle to output multiple signals. The second control module 2020 controls the conversion circuit to perform a first conversion on the multiple signals to output multiple conversion results. The third control module 2030 controls the output circuit to perform a second conversion on the multiple conversion results to output multiple calculation results. The multiple calculations include a first calculation and a second calculation. The second control module 2020 controls the conversion circuit to perform the first conversion on the first signal output from the first calculation in parallel with the execution of the second calculation.

[0234] Optionally, the control device 2000 in this embodiment can be used to execute the control method provided in the above embodiments. As an example, the first control module 2010 can be used to execute 1910 in the above method embodiment, the second control module 2020 can be used to execute 1920 in the above method embodiment, and the third control module 2030 can be used to execute 1930 in the above method embodiment.

[0235] The first control module 2010, the second control module 2020, and the third control module 2030 can be implemented using computer software, electronic hardware, or a combination of both. Whether the functions of these three control modules are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0236] This application also provides a control device. Figure 21 shows a schematic structural block diagram of a control device 2100 provided in an embodiment of this application.

[0237] As shown in FIG21, the control device 2100 includes: at least one processor 2110 and an interface circuit 2120. The interface circuit 2120 is used to connect to the memory computing device via signals. The at least one processor 2110 is used to execute the control method provided in the above embodiments.

[0238] This application also provides an in-memory computing system. Figure 22 shows a schematic structural block diagram of an in-memory computing system 2200 provided in an embodiment of this application.

[0239] As shown in Figure 22, the in-memory computing system 2200 includes an in-memory computing device 2210 and a control circuit 2220, wherein the control circuit 2220 is configured to control the operating state of the in-memory computing device 2210, such as programming state and calculation state.

[0240] Optionally, the memory computing device 2210 in this application embodiment can be any of the memory computing devices provided in the above embodiments.

[0241] In some practical applications, the in-memory computing device 2210 and the control circuit 2220 can be two separate physical devices. For example, the in-memory computing device 2210 may include at least one memory chip or in-memory computing chip, and the control circuit 2220 may include a control chip. Alternatively, in other applications, the in-memory computing device 2210 and the control circuit 2220 can be integrated into a single component. For example, they can be integrated and packaged in the same chip.

[0242] Some embodiments of this disclosure may also provide an electronic device. For example, FIG23 shows a schematic diagram of an electronic device according to an exemplary embodiment of this disclosure. The electronic device 2300 may include a memory computing device 2310 for processing data of the electronic device 2300. The electronic device 2300 may also include an input / output device 2320 for receiving user input or outputting processing results. This disclosure does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device 2300 may also include a processor 2330, which may process data provided to the memory computing device 2310 or process output data from the memory computing device 2310. The output of the input / output device 2320 may be based on the output of the processor 2330 or the output of the memory computing device 2310.

[0243] This disclosure does not limit the type of electronic device. For example, according to some embodiments, electronic device 2300 may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, electronic device 2300 may include portable terminals. For example, electronic device 2300 may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, electronic device 2300 may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, electronic device 2300 may also include devices such as servers.

[0244] In the above embodiments, the descriptions of different embodiments have different emphases. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments above can be freely combined as needed. And as technology evolves, the elements described in this disclosure can be replaced by equivalent elements appearing after this disclosure.

Claims

1. A storage computing device, characterized in that, include: Storage circuitry is used to perform multiple calculations within the first pipeline cycle; A conversion circuit, connected to the storage circuit, is used to perform a first conversion on the multiple signals output by the multiple calculations and output multiple conversion results; An output circuit, connected to the conversion circuit, is used to perform a second conversion on the multiple conversion results and output multiple calculation results; The plurality of calculations include a first calculation and a second calculation, and the process of the conversion circuit performing a first conversion on the first signal output by the first calculation runs in parallel with the process of the second calculation.

2. The storage and computing device according to claim 1, characterized in that, The conversion circuit performs a first conversion on the first signal and outputs a first conversion result. The process of the output circuit performing a second conversion on the first conversion result is parallel to the process of the conversion circuit performing a first conversion on the second signal calculated and output by the second conversion circuit.

3. The storage device according to claim 1 or 2, characterized in that, The conversion circuit performs a first conversion on the first signal and outputs a first conversion result. The output circuit performs a second conversion on the first conversion result in parallel with the second calculation process.

4. The storage device according to any one of claims 1 to 3, characterized in that, The number of calculations performed within the first pipeline cycle is related to one or more of the following: unit calculation time, unit conversion time, and unit output time.

5. The storage device according to any one of claims 1 to 4, characterized in that, The storage circuit includes N storage arrays, and the conversion circuit is connected to the N storage arrays, where N is a positive integer greater than 1; The N storage arrays are used to perform N calculations within the first pipeline cycle, wherein the start time of two adjacent calculations differs by a first time. The conversion circuit is used to perform a first serial conversion on the N signals of the N calculated outputs; The output circuit is used to perform a second, serial conversion on the N conversion results of the conversion circuit.

6. The storage and computing device according to claim 5, characterized in that, The first time is determined based on unit conversion time or unit output time.

7. The storage and computing device according to claim 6, characterized in that, The absolute value of the difference between the unit conversion time and the unit output time is less than or equal to the time threshold.

8. The storage device according to any one of claims 5 to 7, characterized in that, The first flow cycle is determined based on unit calculation time, or the first flow cycle is determined based on unit calculation time and unit conversion time.

9. The storage device according to claim 8, characterized in that, The first flow cycle includes the unit calculation time and the interval time, wherein the interval time includes an integer multiple of the unit conversion time.

10. The storage device according to any one of claims 5 to 9, characterized in that, Also includes: A selection circuit is connected between the conversion circuit and the N storage arrays. The selection circuit is used to select the plurality of signals output by the N storage arrays and input them sequentially to the conversion circuit.

11. The storage device according to claim 10, characterized in that, One of the N storage arrays includes M storage cell groups, where M is a positive integer greater than 1; a storage cell group includes multiple storage cells, and the multiple storage cells are connected to the same output terminal. The selection circuit includes M selection sub-circuits. Each selection sub-circuit is connected to the output of N memory cell groups of N memory arrays and is used to select the signal output of one of the N memory cell groups to be input to the conversion circuit.

12. The storage device according to any one of claims 1 to 4, characterized in that, The storage circuit includes a first storage array, which includes N1 storage cell groups. Each storage cell group includes multiple storage cells, and the multiple storage cells are connected to the same output terminal. N1 is a positive integer greater than 1. The N1 storage unit groups are used to perform N1 calculations within the first pipeline cycle; The conversion circuit is used to perform a serial first conversion on the N1 calculated output signals within the first flow cycle to obtain N1 conversion results; The output circuit is used to perform a second serial conversion on the N1 conversion results.

13. The storage device according to claim 12, characterized in that, The output circuit and the conversion circuit operate in parallel, or the output circuit and the conversion circuit operate in series.

14. The memory computing device according to claim 12 or 13, characterized in that, The first flow cycle is determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, and the unit conversion time; or, The first flow cycle is determined based on the operating mode of the output circuit and the conversion circuit, the unit calculation time, the unit conversion time, and the unit output time.

15. The memory computing device according to claim 14, characterized in that, The output circuit and the conversion circuit operate in parallel, and the first pipeline cycle includes at least one unit calculation time and N1 times the unit conversion time.

16. The storage device according to claim 14, characterized in that, The output circuit and the conversion circuit operate in series, and the first pipeline cycle includes at least one unit calculation time, N1 times the unit conversion time, and (N1-1) times the unit output time.

17. The memory computing device according to any one of claims 12 to 16, characterized in that, The N1 storage unit groups include a first storage unit group and a second storage unit group, and the storage computing device further includes: A selection circuit is connected between the conversion circuit and the first storage unit group and the second storage unit group. The selection circuit is used to select the signals output by the first storage unit group and the second storage unit group to be input to the conversion circuit in a time-division manner.

18. The storage device according to claim 17, characterized in that, The first storage cell group and the second storage cell group perform calculations in parallel.

19. The storage device according to any one of claims 12 to 18, characterized in that, The storage circuit further includes a second storage array, which includes N2 groups of storage cells, where N2 is a positive integer greater than 1. The N2 storage unit groups are used to perform N2 calculations in the second pipeline cycle; The conversion circuit is used to perform a first serial conversion on the N2 calculated output signals during the second flow cycle to obtain N2 conversion results; The output circuit is used to perform a second serial conversion on the N2 conversion results.

20. The memory computing device according to claim 19, characterized in that, The first flow cycle and the second flow cycle include overlapping time.

21. The storage device according to claim 20, characterized in that, The overlap time includes the time it takes for the conversion circuit to serially convert the N1 calculated output signals.

22. The storage device according to any one of claims 19 to 21, characterized in that, The N1 storage unit groups include a first storage unit group and a second storage unit group, the N2 storage unit groups include a third storage unit group and a fourth storage unit group, and the storage computing device further includes: A selection circuit is connected between the conversion circuit and the first and second storage arrays. The selection circuit is used to select, in a time-division manner, the signals output from the first, second, third, and fourth storage unit groups and input them to the conversion circuit.

23. A control method, characterized in that, The method for controlling a memory computing device includes: a storage circuit, a conversion circuit, and an output circuit; the control method includes: The storage circuit is controlled to perform multiple calculations during the first pipeline cycle; The conversion circuit is controlled to perform a first conversion on the multiple signals output by the multiple calculations, so as to output multiple conversion results; The output circuit is controlled to perform a second conversion on the multiple conversion results to output multiple calculation results; The plurality of calculations includes a first calculation and a second calculation. The control of the conversion circuit to perform a first conversion on the plurality of signals to output a plurality of conversion results includes: the process of controlling the conversion circuit to perform a first conversion on the first signal output by the first calculation is parallel to the running process of the second calculation.

24. The control method according to claim 23, characterized in that, The control circuit performs a first conversion on the multiple signals to output multiple conversion results, including: The conversion circuit is controlled to perform a first conversion on the first signal and output a first conversion result; The control circuit performs a second transformation on the multiple conversion results to output multiple calculation results, including: The process of controlling the output circuit to perform a second conversion on the first conversion result is parallel to the process of the conversion circuit to perform a first conversion on the second signal of the second calculated output.

25. The control method according to claim 23 or 24, characterized in that, The control circuit performs a first conversion on the multiple signals to output multiple conversion results, including: The conversion circuit is controlled to perform a first conversion on the first signal and output a first conversion result; The control circuit performs a second transformation on the multiple conversion results to output multiple calculation results, including: The process of controlling the output circuit to perform a second conversion on the first conversion result is parallel to the process of the second calculation.

26. The control method according to any one of claims 23 to 25, characterized in that, The number of calculations performed within the first pipeline cycle is related to one or more of the following: unit calculation time, unit conversion time, and unit output time.

27. A control device, characterized in that, For controlling a memory computing device, the memory computing device includes: a storage circuit, a conversion circuit, and an output circuit; the control device includes: The first control module is used to control the storage circuit to perform multiple calculations during the first pipeline cycle in order to output multiple signals; The second control module is used to control the conversion circuit to perform a first conversion on the multiple signals in order to output multiple conversion results; The third control module is used to control the output circuit to perform a second conversion on the multiple conversion results in order to output multiple calculation results; The plurality of calculations include a first calculation and a second calculation. The second control module is used to control the process of the conversion circuit performing a first conversion on the first signal output by the first calculation to run in parallel with the process of the second calculation.

28. A control device, characterized in that, It includes at least one processor and an interface circuit, the interface circuit being used for signal connection with a storage circuit, a conversion circuit and an output circuit, the at least one processor being used to execute the control method as described in any one of claims 23 to 26.

29. An in-memory computing system, characterized in that, include: The storage device as described in any one of claims 1 to 22; A control circuit is configured to control the operating state of the memory computing device.

30. An electronic device, characterized in that, It includes the storage device as described in any one of claims 1 to 22, or the control device as described in claim 27 or 28, or the storage system as described in claim 29.

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