Method for preparing a silicon-on-insulator substrate comprising an electrical charge trapping layer and having predetermined characteristics

Abstract

The invention relates to a method for preparing a silicon-on-insulator substrate (S) comprising an electrical charge trapping layer (4) and having radio frequency and defectivity characteristics below predetermined thresholds. A thickness of the electrical charge trapping layer (4) is chosen to be strictly greater than 1 micrometre and less than 1.6 micrometres. The preparation method comprises a finishing sequence comprising an annealing step exposing the exposed face of the substrate to a neutral or reducing atmosphere for at least 30 minutes at a temperature strictly between 1050°C and 1100°C. According to the invention, the thickness of the electrical charge trapping layer (4) and the temperature of the annealing step are chosen so that the radio frequency and defectivity characteristics are below the respective predetermined thresholds.

Description

A method for preparing a silicon-on-insulator substrate comprising an electrical charge trapping layer and exhibiting predetermined characteristics. FIELD OF INVENTION

[0001] The present invention relates to a silicon-on-insulator substrate comprising an electrical charge trapping layer. These substrates find significant application in the field of radio frequency integrated devices, i.e., electronic devices processing signals with frequencies between approximately 3 kHz and 300 GHz, for example, in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.). These substrates also find application in the field of photonics. The invention relates particularly to a manufacturing process ensuring that this substrate exhibits predetermined, i.e., sufficiently satisfactory, defect and radio frequency characteristics. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The applicant, SOITEC, markets silicon-on-insulator substrates under the name RFeSi®. These substrates consist of a thin surface layer of crystalline silicon, which may, for example, be 145 nm thick. This thin surface layer is deposited on, and in contact with, a buried dielectric layer of silicon dioxide, for example, 200 nm thick. The buried dielectric layer itself rests on a polycrystalline silicon charge-trapping layer (referred to as the "trapping layer" for simplicity in the remainder of this description) with a thickness of 1.7 micrometers. The trapping layer is deposited on a monocrystalline silicon base substrate with high resistivity and a thickness of several hundred micrometers; this base substrate provides the mechanical support for the stack.Such a silicon-on-insulator substrate, particularly through the choice of trapping layer thickness, is capable of ensuring sufficiently satisfactory radio frequency (RF) performance when used to receive RF components.

[0003] The RF characteristics of the substrate can be established by measuring the second harmonic distortion HD2 (in dB), as documented in the publication "White paper – RF SOI Characterisation" of January 2015 and published by SOITEC.

[0004] The newly presented RFeSi™ silicon-on-insulator substrate is notably capable of achieving an HD2 measurement of less than -90dBm, for a signal with a frequency of 900 MHz and a power chosen at 15dBm, as detailed in the aforementioned document.

[0005] The fabrication of the trapping layer for this substrate follows the guidelines of document US9129800B2. A very thin layer of silicon oxide, less than a few nanometers thick, is formed on a base substrate with high resistivity, typically greater than 500 Ohms·cm. The polycrystalline silicon trapping layer is then deposited onto the very thin silicon oxide layer using a vapor deposition technique.

[0006] This deposition typically includes the formation of a germ portion of the trapping layer at a relatively low temperature of around 900°C, followed by the deposition of the rest of the layer at a relatively high temperature of around 1100°C.

[0007] The very thin layer of silicon oxide serves to prevent or limit the recrystallization of the trapping layer during its formation or during the heat treatment steps that the silicon-on-insulator substrate may receive during its manufacture or use.

[0008] Planarization can be planned, for example by mechano-chemical polishing ("chemical mechanical polishing" according to the Anglo-Saxon terminology often used in the field), of the trapping layer after its deposition in order to facilitate the next step of layer transfer.

[0009] The surface thin film and the buried dielectric layer are transferred onto the trapping layer according to Smart Cut® technology. In one implementation of this technology, the dielectric layer is first formed by oxidation of a so-called "donor" substrate, in this case monocrystalline silicon. Then, a brittle plane is formed at a chosen depth within the donor substrate by introducing so-called "light" species, typically hydrogen and / or helium species introduced by ion implantation into the donor substrate.

[0010] The donor substrate is then assembled to the trapping layer resting on the base substrate, for example by molecular adhesion. The donor substrate is then fractured at its weak plane, thus transferring the dielectric layer and a thin surface silicon layer onto the base substrate and the trapping layer.

[0011] A finishing sequence is applied to this structure, aimed in particular at restoring the crystallographic and thickness characteristics of the surface thin film. This finishing sequence may thus include, in the case of the RFeSi® range silicon-on-insulator substrate, a stabilization step aimed in particular at removing a work-hardened portion of the surface thin film, thermal annealing at 1100°C for one hour in a neutral or reducing atmosphere in order to reduce the roughness of the free surface of the surface thin film, and a final thinning by sacrificial oxidation to provide a surface thin film whose thickness corresponds precisely to the required thickness.

[0012] The US2021 / 249301 document aims to form a relatively thin trapping layer in a silicon-on-insulator substrate, this layer being made partly amorphous to limit the occurrence of bonding defects.

[0013] Document EP2503592 proposes an alternative approach to document US9129800 for forming the trapping layer. According to this alternative approach, the very thin silicon oxide layer and the deposition of the polycrystalline silicon trapping layer are carried out "in situ" within the vapor deposition chamber of the trapping layer, for example, by introducing an oxidizing gas into the deposition chamber before initiating the growth of the polycrystalline silicon layer. This alternative approach offers several advantages in terms of production rate and control of the risk of contamination by doping substances, such as boron. SUBJECT OF THE INVENTION

[0014] One aim of the invention is to propose a method for manufacturing a silicon-on-insulator substrate comprising a charge-trapping layer, the method implementing the "in situ" approach proposed by document EP2503592.

[0015] More specifically, one aim of the invention is to deploy the "in situ" approach aimed at forming a silicon-on-insulator substrate comprising a charge-trapping layer, this substrate having characteristics similar to those of the substrate conforming to the prior art, particularly in terms of defectivity and RF performance. BRIEF DESCRIPTION OF THE INVENTION

[0016] To achieve this goal, the object of the invention proposes a method for preparing a silicon-on-insulator substrate comprising a polycrystalline silicon electrical charge trapping layer, the method comprising: a step of preparing a support substrate including the formation, "in situ" in a chamber of a vapor deposition equipment, of the electrical charge trapping layer, the formation of the electrical charge trapping layer including the oxidation of a silicon base substrate and the deposition of a polycrystalline silicon layer on the oxidized base substrate; a step of polishing the polycrystalline silicon layer giving a determined thickness to the trapping layer; a step of oxidizing a silicon donor substrate so as to form a silicon oxide layer;a sequence of sampling and transferring a top layer of the donor substrate onto the support substrate to constitute an intermediate substrate comprising the support substrate, a silicon surface layer on the support substrate and a silicon oxide layer buried between and in contact with the support substrate and the surface layer; a finishing sequence of an exposed silicon face of the surface layer of the intermediate substrate comprising a smoothing annealing step exposing the exposed silicon face to a neutral or reducing atmosphere for at least 30 minutes at a determined temperature.

[0017] According to the invention, the determined thickness of the trapping layer is between 0.5 micrometers and 2 micrometers and the determined temperature is between 1000°C and 1200°C.

[0018] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: the determined thickness is strictly greater than 1 micrometer and strictly less than 1.6 micrometers and the determined temperature is between 1050°C and 1100°C; the determined thickness is between 1.2 micrometers and 1.5 micrometers and the determined temperature is strictly between 1050°C and 1100°C; the determined thickness is between 1.5 micrometers and 1.6 micrometers and the determined temperature is strictly between 1050°C and 1075°C; the base substrate has a resistivity strictly greater than 500, preferably greater than 1000 ohms.cm, and more preferably greater than 3000 ohms.cm; the oxidized base substrate comprises a silicon oxide layer having a thickness between 0.4 nm and 0.8 nm;the oxidation of the silicon base substrate is carried out at a temperature between 900°C and 1150°C; the deposition of a polycrystalline silicon layer on the oxidized base substrate is carried out at a temperature strictly between 1000°C and 1200°C; the oxidation step of the donor substrate leads to the formation of a buried silicon oxide layer with a thickness between 100 nm and 400 nm, preferably between 150 nm and 250 nm; the sampling and transfer sequence includes the formation of a brittle plane at a determined depth of the donor substrate by ion implantation of hydrogen and / or helium, the assembly of the donor substrate to the support substrate and the fracturing of the donor substrate at the level of the brittle plane;The finishing sequence also includes, before the annealing step, a stabilization step comprising oxidation of part of the surface layer, annealing of the intermediate substrate, and removal of the oxidized part of the surface layer; the finishing sequence also includes, after the annealing step, a sacrificial oxidation step.

[0019] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0020]

[0021] Lare represents a defect map of the exposed face of a surface layer of a prior art SOI substrate, including a trapping layer formed by an "ex situ" technique;

[0022]

[0023] Larepresents a defect map of the exposed face of a surface layer of an SOI substrate comprising a trapping layer formed by an "in situ" technique, the SOI substrate having been manufactured by the same layer transfer process as that used to form the prior art substrate of which a defect map is shown on the;

[0024]

[0025] Lare represents a preparation process according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0026] A silicon-on-insulator substrate (referred to as "SOI substrate" hereafter) must, of course, meet very precise specifications. These specifications relate in particular to the thickness and uniformity of the surface layer and the buried silicon oxide layer. When the SOI substrate has a trapping layer, it must also exhibit satisfactory RF characteristics, for example, an HD2 measurement of -90 dBm or less for a substrate from the RFeSi® range presented in the introduction to this application.

[0027] Furthermore, the exposed surface of the SOI substrate's surface layer must have a flawless finish. To achieve this, it is common practice to inspect the substrate using dark-field microscopy with an incident light beam (of a specific wavelength, for example, 90 nm) directed at an inspection point that scans the exposed surface of the substrate. A light-collecting device and a detector allow for the selective measurement of scattered light at the inspection point, excluding light that is simply reflected. Such an inspection can be performed, for example, using the Surfscan™ SP1 inspection equipment from KLA.

[0028] When the inspected surface is perfectly flat and free of any particles, the light beam is reflected off it without any deviation, and no light radiation is collected and detected by the equipment. Conversely, any surface irregularity or particle present at the inspection point causes the beam to scatter spatially at specific azimuthal and / or elevation angles, which are then collected and directed towards the detector. The measurement of this radiation constitutes a signature carrying information about the presence, position, and / or nature of a surface defect or particle at the inspection point.

[0029] The term "Light Point Defect" or LPD (which could be translated into French as "défaut pointu lumineux") commonly refers to any surface defect that produces diffuse radiation at the inspection point, as measured by the detector. Other defects are not point-like but are relatively widespread across the exposed surface of the surface layer. Such defects are usually referred to as "area defects" (which could be translated into French as "défaut de surface"). This inspection technique allows for the creation of a map of the defects present on the exposed surface of the surface layer, the grouping of these defects into classes ("LPDs," "Area") based on the signature of the collected radiation, or the counting of these defects to obtain an indicator of the quality or defect level of the surface layer.An inspected substrate is retained or rejected according to its level of defectivity with respect to predetermined defect requirements.

[0030] We have thus represented on a defect map of the exposed face of a surface layer of the SOI substrate of the RFeSi® range of the prior art and presented in the introduction to this application.

[0031] As a reminder, this SOI substrate comprises, on a base substrate, a 1.7 micrometer polycrystalline silicon trapping layer, a 200 nm silicon oxide layer, and a 145 nm crystalline silicon surface layer. The trapping layer was formed according to the prior art "ex-situ" approach, and the finishing sequence includes annealing by exposing the exposed surface of the surface layer to a neutral or reducing atmosphere for 1 hour at a temperature of 1100°C.

[0032] With the aim of integrating into a silicon-on-insulator substrate a trapping layer formed according to the "in situ" approach presented in the introduction to this application, the same manufacturing process as that used for the SOI substrate of the RFeSi® range of the prior art was applied to a base substrate having such a layer.

[0033] More specifically, the same base substrate used to form a prior art SOI substrate was introduced into a chamber of a vapor deposition system, such as an epitaxial frame. The base substrate was then treated to form the trapping layer, without removing it from the chamber and therefore without exposing it to any gases or atmosphere other than those introduced or present in the chamber throughout the process. This treatment involved the formation of a thin silicon oxide layer approximately 0.5 nm thick by oxidation of the base substrate at a temperature close to 1000°C by introducing an oxygen-containing gas into the chamber.Then, without removing the base substrate from the chamber, a polycrystalline silicon trapping layer was formed directly onto the thin silicon oxide layer at a temperature between 1000°C and 1200°C by introducing a silicon-containing precursor gas into the chamber at a chosen flow rate. This trapping layer growth step was continued until a thickness slightly greater than 1.7 micrometers was achieved. After polishing the trapping layer to smooth its surface, a 1.7-micrometer-thick layer was obtained, just as in the prior art SOI substrate.

[0034] Following these "in situ" formation steps, the trapping layer of a support substrate is thus obtained, and the manufacturing process described in the introduction to this application can be continued identically. Specifically, the finishing sequence, including an annealing step, is applied to the crystalline silicon surface layer transferred to the support substrate. This step exposes the surface of this layer to a neutral or reducing atmosphere for one hour at a temperature of 1100°C.

[0035] The substrate thus manufactured is then characterized, in particular by its HD2 measurement which turns out to be well below the targeted -90dBm, and by a defect measurement.

[0036] This represents the defect map established on this SOI substrate. Quite unexpectedly, this map clearly reveals a very excessive defect density.

[0037] Unlike the trapping layer formed "ex situ", it appears that a trapping layer formed "in situ", when subjected to the treatments of a manufacturing process of an SOI substrate, causes the appearance of defects in large quantities over the entire extent of the SOI substrate.

[0038] According to the inventors' intuition, these defects could arise from a rearrangement of the grains in the polycrystalline silicon layer, particularly during the heat treatments of the finishing sequence, and especially during annealing of the surface layer under a neutral or reducing atmosphere. This rearrangement tends to cause defects on and within the surface layer, which are visible using dark-field microscopy equipment.

[0039] To better understand this phenomenon and confirm this intuition, experiments were conducted to produce SOI substrates from a wide variety of trapping layer thicknesses (column "Ep") and at various annealing temperatures (column "Temp"). HD2 and defect characterization were then performed, and these characteristics were categorized as OK (acceptable characteristic) / NOK (unacceptable characteristic). For the radio frequency characteristic, it was considered acceptable if the HD2 measurement was below -90 dBm reproducibly. For the defect, it was considered acceptable if the defect map did not show a cross pattern like the one shown in the image. The collected data are summarized in the following table.

[0040] Ep (mm) Temp (°C) HD2 Defect (<-90dBm)

[0041] 1.7 1100 NOK OK

[0042] 1.7 1075 NOK OK

[0043] 1.7 1050 NOK OK

[0044] 1.6 1100 NOK OK

[0045] 1.6 1050 OK* OK

[0046] 1.4 1100 OK* OK

[0047] 1.4 1050 OK OK

[0048] 1 1100 OK NOK (non-repeatable)

[0049] 1 1075 OK NOK (non-repeatable)

[0050] 1 1050 OK NOK (non-repeatable)

[0051] * The defect was classified as acceptable, but the cross pattern can be detected with very low intensity.

[0052] This table shows that a trapping layer with a thickness of 1 micrometer does not cause the defect observed on the first test vehicle shown in the table for a thickness of 1.7 micrometers. However, this reduced trapping layer thickness does not allow for SOI substrates to exhibit a stable HD2 measurement below the fixed threshold of -90 dBm. It therefore appears that this 1-micrometer thickness represents the lower limit for meeting this performance criterion. Indeed, this criterion is met for all other thicknesses in the table.

[0053] For a maximum thickness of 1.7 micrometers, all evaluated annealing temperatures (1050°C, 1075°C, and 1100°C) result in unsatisfactory defects; this thickness is therefore excessive and constitutes the upper limit. Conversely, a trapping layer thickness of 1.6 micrometers combined with annealing at a moderate temperature of 1050°C yields a SOI substrate that satisfies both RF performance and defect criteria. A trapping layer thickness of 1.4 micrometers can be processed across the entire temperature range between 1000°C and 1100°C while still meeting both RF performance and defect criteria.

[0054] It is therefore observed that the surface layer defect, all other things being equal, tends to worsen with increasing annealing temperature. Further experiments confirmed that the RF performance, measured by HD2, improved with increasing trapping layer thickness.

[0055] It therefore appears that manufacturing a SOI substrate with radio frequency and defect characteristics below predetermined thresholds requires jointly selecting the trapping layer thickness and the annealing temperature. The greater the trapping layer thickness (which favors the RF characteristic), the lower the temperature must be. Annealing at relatively high temperatures is generally preferred, for example, to improve the layer's smoothness, but such a high temperature then necessitates reducing the trapping layer thickness to avoid excessively degrading the surface layer's defectivity.

[0056] The choice of trapping layer thickness and annealing temperature is, of course, linked to the required performance level and therefore to the thresholds chosen for the radio frequency and defect characteristics of the substrate. By modifying these thresholds to make the radio frequency and / or defect performance level less demanding, we open up the range of possible thickness / temperature ranges.

[0057] These observations are used to propose a method for preparing a SOI substrate with a trapping layer. This method is designed so that the radio frequency and defect characteristics of the fabricated SOI substrate meet predetermined requirements; for example, for the radio frequency characteristic, an HD2 measurement below the threshold of -90 dBm. For the defect characteristic, this could be, for example, the absence of an extended pattern (such as the cross pattern shown above) in the dark-field defect mapping of the surface layer.

[0058] Alternatively, a detectivity threshold can be defined as a maximum value that the sum of the point light defects revealed by the inspection equipment must not exceed. For example, this sum could be less than 100 for inspection equipment with an incident light beam having a wavelength of 90 nm.

[0059] With reference to the, this process first includes a preparation step S1 of a support substrate 1 comprising a base substrate 5 in crystalline silicon and the trapping layer 4 in polycrystalline silicon.

[0060] The basic substrate 5 can take the form of a circular plate of standardized dimensions, for example 200 mm or 300 mm, or even 450 mm in diameter. But the invention is in no way limited to these dimensions or this shape.

[0061] The base substrate 5 is advantageously made of monocrystalline silicon and has a thickness of several hundred microns. Preferably, the base substrate has a high resistivity, strictly greater than 500 or 1000 ohms·cm, and even more preferably greater than 3000 ohms·cm. This limits the density of charges, holes or electrons, that can move within the base substrate and thus degrade the RF performance of the final substrate S. For example, it could be a CZ substrate with low interstitial oxygen content, which, as is well known, has a resistivity that can exceed 1000 ohms·cm.

[0062] The trapping layer 4 is formed "in situ" on the base substrate 5 in a chamber of a vapor phase deposition equipment, without removing the base substrate 5 from this chamber and therefore without exposing it to any gases or atmosphere other than those introduced or present in the chamber.

[0063] This treatment may include deoxidation annealing of the base substrate 5 in a reducing or weakly reducing atmosphere, for example at a temperature between 900°C and 1200°C, to remove any native oxide that may be present on the surface. Then, a thin dielectric layer Ox, typically between 0.3 nm and 0.8 nm thick, preferably around 0.5 nm, is formed by oxidizing the base substrate 5 by introducing a gas containing or composed of oxygen into the chamber at a chosen flow rate for a predetermined duration. This thin silicon oxide layer Ox can be formed at a temperature between 900°C and 1150°C, and preferably between 950°C and 1100°C. Then, without extracting the base substrate 5 from the chamber, the trapping layer 4 in polycrystalline silicon is formed directly on the thin layer of silicon oxide Ox by introducing into the chamber, with a chosen flow rate, a precursor gas containing silicon.The amorphous nature of the thin layer of silicon dioxide Ox prevents the crystallization of the trapping layer 4 that forms during this step, which could occur if the thin layer of silicon dioxide Ox were not present. The trapping layer 4 can be formed at a temperature between 1000°C and 1200°C.

[0064] This growth step of the trapping layer 4 is continued until it reaches a thickness slightly greater than the target thickness. After a polishing step to smooth the surface of this layer, a trapping layer 4 of a specific thickness is obtained. The choice of this specific thickness value will be discussed later in this description.

[0065] The preparation of the SOI substrate is then carried out via a sampling and transfer sequence implementing Smart Cut® technology, as explained in the introduction to this application.

[0066] Thus, during a embrittlement step S2, a brittle layer P is formed in a donor substrate 8 of monocrystalline silicon by introducing, through a main surface of the substrate, generally by implantation, so-called "light" species such as hydrogen and / or helium. The implantation energy defines the average depth of introduction of these species and the position of the brittle layer P within the thickness of the donor substrate 8.

[0067] This embrittlement step is preceded by an oxidation step of the donor substrate 8, in order to form a surface layer of silicon oxide 3 intended to form, at least in part, the buried silicon oxide layer of the final SOI substrate S.

[0068] The fragile layer P defines, with the main surface of the donor substrate, a top layer 2 which we seek to take from the donor substrate 8 and transfer onto the support 1 to form an intermediate substrate.

[0069] To transfer this upper layer 2 containing the silicon oxide layer 3 with which the donor substrate 8 has been provided, the latter is assembled to the support 1, during an assembly step S3, generally by molecular adhesion of its main face to a main face of the support.

[0070] In a subsequent fracture step S4, the assembly is fractured at and along the fragile layer P of the donor substrate 8, so as to transfer the upper layer 2 onto the support 1. At the end of this fracture, we have on the one hand a residue 8' of the donor substrate, which can be reused in a new sampling cycle, and on the other hand the intermediate substrate 1' composed of a surface layer 2 of crystalline silicon, the silicon oxide layer 3 buried on and in contact with the support 1.

[0071] Fracture can be induced in multiple ways, thermally and / or mechanically. Typically, a plurality of assemblies are placed in a so-called "fracture furnace," and the temperature of this furnace is raised to a moderate level, typically between 300°C and 600°C. This heat treatment, possibly assisted mechanically or with the aid of fracture initiators integrated into the assemblies, causes the detachment of the thin layers 2 from the donor substrates 8.

[0072] As mentioned in the introduction, the SOI substrates resulting from this layer transfer sequence are generally not suitable for directly receiving components. Due to the fracture step, a transferred thin layer 2 exhibits degraded crystalline quality and a very rough free surface.

[0073] It is therefore common to apply a sequence of processing steps, called the finishing sequence S5, to the intermediate substrate 1' obtained at the end of the fracture step S4 to restore the crystalline quality of the surface layer 2, reduce the roughness of its free surface below a threshold roughness, and give it by thinning a determined and very uniform thickness.

[0074] An S5 finishing sequence may initially include a so-called "stabilization" step. This step, well known to those skilled in the art, involves placing an intermediate substrate 1' in an oxidation furnace. A portion of the upper silicon surface layer is thus oxidized in a dry or humid oxygen-rich atmosphere, and then the intermediate substrate is heated to a temperature exceeding 850°C or 950°C. Following this heat treatment, the oxidized upper portion of the surface layer is removed, typically by selective etching with a hydrofluoric acid solution. This stabilization treatment helps improve the crystalline quality of the surface layer and reduce its thickness to approach its target thickness.

[0075] The S5 finishing sequence may then include a smoothing step. This step involves annealing the exposed silicon surface of the surface layer 2 to a neutral or reducing atmosphere for at least 30 minutes at a predetermined temperature. The choice of this predetermined annealing temperature will be discussed later in this description. Annealing can be carried out in a conventional smoothing furnace, which may have a horizontal or vertical configuration, as is well known to those skilled in the art.

[0076] After this smoothing step, the surface layer 2 can be thinned to a target thickness. This thinning step may involve sacrificial oxidation of the thin layer or the application of a silicon etching solution, such as a tetramethylammonium hydroxide (TMAH) solution.

[0077] In any event, the finishing sequence S5 aims to treat the exposed face of the surface layer 2 of the intermediate substrate 1' and includes at least one annealing step exposing the exposed silicon surface of the surface layer to a neutral or reducing atmosphere for at least 30 minutes at a determined temperature.

[0078] According to the present invention, the determined thickness of the charge trapping layer 4 and, simultaneously, the determined temperature of the annealing stage are chosen so that the radio frequency and defect characteristics are well below the respective predetermined thresholds.

[0079] In general, the determined thickness of the trapping layer 4 is within the range of 0.5 micrometers to 2 micrometers. Simultaneously, the determined temperature of the annealing step is between 1000°C and 1200°C.

[0080] Thus, the predetermined thickness can be chosen between 1.2 micrometers and 1.5 micrometers, and the determined temperature can be chosen between 1050°C and 1100°C. With these choices, the RF and defect characteristics presented above can be satisfied (HD2 measurement less than or equal to -90dBm and absence of a cross pattern on the defect map).

[0081] Alternatively, and for RF characteristics and defectivity under the same predetermined thresholds, the predetermined thickness is chosen between 1.5 micrometers and 1.6 micrometers and the determined temperature is chosen between 1050°C and 1075°C.

[0082] More generally, and while ensuring that the RF and defect characteristics are well below these same predetermined thresholds, the determined thickness of the charge trapping layer 4 can be chosen to be strictly greater than 1 micrometer and strictly less than 1.6 micrometers. Simultaneously, the determined temperature of the annealing step can be chosen to be between 1050°C and 1100°C.

[0083] Of course the invention is not limited to the modes of implementation described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

A process for preparing a silicon-on-insulator substrate (S) comprising an electrical charge-trapping layer (4) of polycrystalline silicon, the process comprising: a preparation step (S1) of a support substrate (1) comprising the formation, "in situ" in a chamber of a vapor deposition equipment, of the electrical charge-trapping layer (4), the formation of the electrical charge-trapping layer (4) comprising the oxidation of a silicon base substrate (5) and the deposition of a polycrystalline silicon layer on the oxidized base substrate (5); a polishing step of the polycrystalline silicon layer giving a determined thickness to the trapping layer (4); an oxidation step of a silicon donor substrate (8) so as to form a silicon oxide layer (3);a sampling and transfer sequence (S2, S3, S4) of a top layer (2) of the donor substrate (8) onto the support substrate (1) to constitute an intermediate substrate (1') comprising the support substrate (1), a surface layer (2) of silicon on the support substrate (1) and a layer of silicon oxide (3) buried between and in contact with the support substrate (1) and the surface layer (2); a finishing sequence (S5) of an exposed silicon face of the surface layer (2) of the intermediate substrate (1') comprising a smoothing annealing step exposing the exposed silicon face to a neutral or reducing atmosphere for at least 30 minutes at a determined temperature; the preparation process being characterized in that the determined thickness of the trapping layer (4) is between 0.5 micrometers and 2 micrometers and the determined temperature is between 1000°C and 1200°C. Preparation method according to the preceding claim wherein the determined thickness of the electrical charge trapping layer (4) is strictly greater than 1 micrometer and strictly less than 1.6 micrometer and wherein the determined temperature of the annealing step is between 1050°C and 1100°C. Preparation method according to the preceding claim wherein the determined thickness is between 1.2 micrometers and 1.5 micrometers and the determined temperature is between 1050°C and 1100°C. Preparation method according to claim 1 wherein the determined thickness is between 1.5 micrometers and 1.6 micrometers and the determined temperature is strictly between 1050°C and 1075°C. A preparation method according to any one of the preceding claims, wherein the base substrate (5) has a resistivity strictly greater than 500, preferably greater than 1000 ohms.cm, and more preferably greater than 3000 ohms.cm. A preparation method according to any one of the preceding claims, wherein the oxidized base substrate (5) comprises a silicon oxide layer having a thickness of between 0.4 nm and 0.8 nm. Preparation process according to any one of the preceding claims wherein the oxidation of the basic substrate (5) in silicon is carried out at a temperature between 900°C and 1150°C. A preparation method according to any one of the preceding claims, wherein the deposition of a layer of polycrystalline silicon on the oxidized base substrate (5) is carried out at a temperature strictly between 1000°C and 1200°C. A preparation method according to any one of the preceding claims, wherein the oxidation step of the donor substrate (8) leads to the formation of an embedded silicon oxide layer (3) having a thickness between 100 nm and 400 nm, preferably between 150 nm and 250 nm. A preparation method according to any one of the preceding claims, wherein the sampling and transfer sequence (S2,S3,S4) comprises the formation of a fragile plane (P) at a determined depth of the donor substrate (8) by ion implantation of hydrogen and / or helium, the assembly of the donor substrate (8) to the support substrate (1) and the fracturing of the donor substrate (8) at the level of the fragile plane (P). Preparation process according to any one of the preceding claims wherein the finishing sequence (S5) also includes, prior to the annealing step, a stabilization step comprising oxidation of a portion of the surface layer (2), annealing of the intermediate substrate (1'), and removal of the oxidized portion of the surface layer (2). Preparation process according to any one of the preceding claims wherein the finishing sequence (S5) also includes, after the annealing step, a sacrificial oxidation step.

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