Electronic device using si-GE heterostructure

Abstract

An electronic device is presented comprising a semi conductor structure comprising a silicon device layer located on top of an insulator, said silicon device layer comprising: a first highly doped P+ silicon region and a second highly doped N+ region, which is spaced from the first highly doped P+ silicon region by a first intrinsic region of the silicon device layer, and which comprises an integrated Ge-region at least partially embedded in the silicon device layer. The semiconductor structure may have a lateral or semi-lateral configuration. In various embodiments and device applications, the integrated Ge-region may be substantially undoped region, or a relatively lightly N-doped region, or may be a highly doped N+ region and / or having a tensile and / or compressive stress.

Description

[0001] ELECTRONIC DEVICE USING SI-GE HETEROSTRUCTURE

[0002] TECHNOLOGICAL FIELD AND BACKGROUND

[0003] The present disclosure is in the general field of silicon photonics and is particularly related to optical components utilizing Germanium (Ge) integration into Silicon (Si) material.

[0004] Silicon photonics is seen as a major enabler for optical data communication, signal processing and sensing applications. The fabrication of photonic circuits relies on processes and protocols similar to the commonly implemented complementary metal- oxi de- semi conductor (CMOS) technology, and thus it is restricted to a well-defined set of materials, preferentially from the group IV atomic column, like Silicon. Many of the required photonic components have been successfully developed in such CMOS-like technology, but the key element, an electrically driven laser source fully integrated on Si, is still missing. Despite the constant progress of heterogeneous integration of III -V based lasers on Si, the development of optical sources realized in group IV still represents a long-term interest in the Si-photonics field.

[0005] Germanium, thanks to its CMOS compatibility and near direct bandgap configuration, i.e., 0.136 eV offset between the conduction band minima at T and L, is the best candidate, providing that directness can be improved. Among the known approaches to reduce the energy gap between the conduction band minima at T and L are strong doping with donors (N+) and the application of tensile strain.

[0006] An electrically pumped P+N+N+Ge-on-Silicon heterojunction diode laser, having a vertical architecture, was demonstrated by Camacho-Aguilera et al. (“An electrically pumped germanium laser,” Optics Express, vol. 20, No. 10, pp. 11316-11320, May 2012). In this work, room temperature multimode laser with ImW output power was measured. Phosphorous doping in Germanium at a concentration over 4xl019cm-3was achieved, and a Germanium gain spectrum of nearly 200nm was observed. GENERAL DESCRIPTION

[0007] There is yet a need in the art for novel architectures of Si-Ge heterostructures to improve the luminous efficiency of Germanium integrated on silicon chips.

[0008] Among the reasons why fully integrated germanium (Ge)-based light sources on silicon (Si) remain difficult to realize are: fabrication difficulties, insufficient gain of Gebased coherent sources, too high optical losses making the emitted power very inefficient, coupling losses between the Ge waveguide and the Si bus, and inefficient thermal management.

[0009] The present disclosure, in one of its aspects, provides a novel electronic device including a semiconductor structure specially designed to improve the luminous efficiency of Ge integrated on Si chips and resolve the problems mentioned above. The semiconductor structure includes a silicon device layer located on top of an insulator, where the silicon device layer includes a first highly doped P+silicon region and a second region including a highly doped N+region, where second region includes an integrated Ge region at least partially embedded in the silicon device layer.

[0010] This novel configuration of the semiconductor structure is generally a lateral-type configuration in the meaning that Ge region is integral in a silicon device layer, and can be implemented as a “lateral” configuration or a “semi-lateral” configuration. This configuration provides monolithically integrated (built-in) on chip solutions of light emission, amplification and detection in Silicon on Insulator (SOI) or Silicon-based platforms within Silicon Photonics, while integrating germanium (Ge) material into silicon (Si) material. The implementation of the technology of the present disclosure utilizes fabrication processes and materials which are compatible with standard Complementary Metal-Oxide Semiconductor (CMOS) technology.

[0011] The lateral and semi-lateral configurations of the Si-Ge semiconductor structure of the present disclosure provide a large active Si-Ge interface length, allowing to better control the stress of the Ge medium, thereby providing larger gain for emission at shorter wavelengths, which may be advantageously used in various applications.

[0012] In some embodiments, the present disclosure provides a novel PIN-based semiconductor structure including the intrinsic region I (IN+I) of the silicon device layer including the integrated Ge-region. Considering the lateral configuration of the semiconductor structure of the present disclosure, provision of P+and N+highly doped silicon (Si) regions at both sides of the specially designed intrinsic region I (IN+I) with the integrated Ge-region in the silicon device layer, provides a P+IN+IN+structure including Si and Ge. Such structure is capable of emitting and detecting light and may surpass, in terms of performance and efficiency, other solutions such as Indium Phosphide (InP) emitters, as well as hybrid solutions, such as InP emitters on SOI.

[0013] The too high optical losses reported for existing Si-Ge emitters of vertical configurations are mainly due to the metal contacts and the highly doped regions being in close proximity with the Ge waveguide. The lateral (and semi-lateral) device configurations of the present disclosure resolve this problem and reduce the optical losses dramatically by providing sufficient distances between metal contacts (and plugs) and the highly doped regions, and the Ge waveguide (formed by the integrated Ge-region).

[0014] The lateral (or semi-lateral) configuration of the semiconductor structure of the present disclosure provides an equal height between the Ge waveguide where light is created and propagating and the silicon waveguide or a bus to which the light needs to be coupled. Such lateral (or semi-lateral) configuration allows to integrate, e.g., ring resonators, and a smooth coupling of the emitted power via a directional coupler, taper waveguides or other types of known couplers. This is in contrast with existing Si-Ge emitters, mostly based on vertical architecture in which the Ge waveguide is not on the same plane as the Si bus waveguide, making the coupling between the two inefficient and complicated.

[0015] The lateral design of the semiconductor structure of the present disclosure allows to add an additional embedded electrode or system in close (direct) proximity to the active Ge region, providing capabilities which the existing vertical designs are lacking. In particular, such additional electrode may provide direct modulation, wavelength tunability, optical band tunability, increased emitted power, direct TEC and cooling, and a calibration electrode.

[0016] Thus, according to one broad aspect of the present disclosure, it provides an electronic device comprising a semiconductor structure comprising a silicon device layer located on top of an insulator, said silicon device layer comprising: a first highly doped P+silicon region and a second highly doped N+region, which is spaced from the first highly doped P+silicon region by a first intrinsic region of the silicon device layer, and which comprises an integrated Ge-region at least partially embedded in the silicon device layer. In some embodiments, the semiconductor structure further comprises a clad on top of the silicon device layer.

[0017] The electronic device further comprises electric contacts of an electrode arrangement, said electric contacts comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region.

[0018] In various embodiments, the integrated Ge region may be a substantially undoped region, or a relatively lightly N-doped region, or the integrated Ge region may be a highly doped N+region and / or having tensile or compressive stress.

[0019] In some embodiments, the semiconductor structure has a lateral configuration. To this end, the silicon device layer further comprises a second intrinsic region, and the second region comprises a silicon region, being said highly doped N+region, and comprises said integrated Ge region which is separated from said highly doped N+region by said second intrinsic region, such that said first intrinsic region and said second intrinsic region are located at opposite sides of said integrated Ge region.

[0020] For example, electric contacts of an electrode arrangement are used comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, said first intrinsic region and said second intrinsic region having a predetermined first length Si and a predetermined second length S2, respectively. These lengths Si and S2 may be substantially the same, or may be different, and at least one of these lengths may be zero or approximately zero.

[0021] In some embodiments of the lateral configuration of the semiconductor structure, the integrated Ge region is configured as substantially undoped or relatively lightly doped N+, the device being therefore configured as a P+ININ+Si-Ge heterostructure.

[0022] In some embodiments of the lateral configuration of the semiconductor structure, the electric contacts of the electrode arrangement comprise first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, and a third contact of a second electrode, said third contact being associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer.

[0023] The configuration can be such that the third contact directly interfaces a top surface of the integrated Ge region, or the third contact is spaced from the integrated Ge region by a portion of the clad. In any of these embodiments, the third contact may be configured as a split contact formed by first and second spaced-apart electrode elements of the second electrode aligned with opposite edges, respectively, of the integrated Ge region.

[0024] In some embodiments, the third contact is configured as a split contact formed by first and second spaced-apart electrode elements of the second electrode aligned with opposite edges, respectively, of the integrated Ge region, said portion of the clad comprising P+doped region and N+doped region aligned with, respectively, said opposite edges of the integrated Ge region, thereby forming with said integrated Ge region first P+N+junction and second N+N+junction, respectively.

[0025] In some embodiments, said portion of the clad comprises a P+doped region or a N+doped region, forming with said integrated Ge region a P+N+diode or N+N+junction, respectively.

[0026] In some embodiments, the lateral-type semiconductor structure has a semi-lateral configuration. The second region comprises said integrated Ge region being the highly doped N+Ge region, and the device comprises electric contacts of an electrode arrangement comprising first and second contacts of a first electrode being associated with, respectively, said first highly doped P+region and said integrated Ge region, thereby forming a P+IN+Si-Ge heterostructure operable as a diode.

[0027] In some embodiments of the semi-lateral configuration, said second contact is located at least partially in a clad, extending on top of the silicon device layer, and being aligned with the integrated Ge region in a substantially symmetrical configuration with respect to said integrated Ge region, such that said second contact is substantially identically spaced from opposite edges of the integrated Ge region. In some other embodiments, said second contact is located at least partially in a clad, extending on top of the silicon device layer, and being aligned with the integrated Ge region in a substantially asymmetrical configuration with respect to edges of said integrated Ge region, such that second contact is aligned with an edge of the integrated Ge region further from said first intrinsic region.

[0028] In any of these embodiments, the configuration may be such that the second contact directly interfaces with said integrated Ge region, or the second contact is spaced from said integrated Ge region by a portion of the clad. In the latter case, said portion of the clad comprises a P+doped region or a N+doped region, forming with said N+doped integrated Ge region a P+N+or N+N+junction, respectively. As noted above, in various embodiments of the lateral-type configuration of the semiconductor structure, the integrated Ge region may be configured with one or more of the following characteristics: highly N+doping, tensile stress, and compressive stress. This provides desired / predefined energy band profile of the integrated Ge region.

[0029] In some embodiments, the energy band profile of the integrated Ge region is predefined to provide direct gap light emission within the integrated Ge region upon application of an electric field via electric contacts comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region.

[0030] In some embodiments of such electronic device with the direct gap light emission within the integrated Ge region, the electrodes arrangement may further comprise a third contact of a second electrode being associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer, said second electrode being configured and operable as a thermo-optical electrode heater, inducing a change in refractive index of the integrated Ge region by induced heating, thereby affecting a power of said direct gap light emission at a specific wavelength.

[0031] In some embodiments, the electronic device is configured and operable as a broadband optical source device (e.g., LED) emitting light in a range of 1,400 - 13,000 nm.

[0032] In some embodiments, the electronic device further comprises a resonator located in a light propagating direction, confined within the integrated Ge region the device being operable as a coherent optical source device. Such device can operate as a laser.

[0033] In some embodiments, the electronic device is configured and operable as an optical amplifier by setting a voltage around a lasing threshold voltage applied to the semiconductor structure via electrical contacts thereby amplifying external light being coupled to the integrated Ge region.

[0034] In some embodiments, the electronic device is configured and operable as an electro-absorption modulator.

[0035] In some embodiments of the device with the lateral configuration of the semiconductor structure, where the integrated Ge region is a highly N+doped region and / or has a tensile or compressive stress, and the electrode arrangement includes first and second contacts of a first electrode associated with said first highly doped P+region and said N+region of the second region, and a third contact of a second electrode associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer, the electronic device may be configured and operable as a photonic junction field-effect transistor (JFET) with the integrated Ge region operating as a gate.

[0036] In some other embodiments of the device with the lateral configuration of the semiconductor structure, where the integrated Ge region is a highly N+doped region and / or has a tensile or compressive stress, and the electrode arrangement includes first and second contacts of a first electrode associated with said first highly doped P+region and said N+region of the second region, and a third contact of a second electrode associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer, where the third contact is split into first and second elements, the electronic device may be configured and operable as a photonic junction field-effect transistor (JFET) with a gate on the integrated Ge region and independent carrier injection into the integrated Ge medium through said first and second electrode elements of the second electrode.

[0037] In any of the above embodiments, using the integrated Ge region being the highly N+doped region and / or has a tensile or compressive stress, and the electrode arrangement including the first and second electrodes, the electronic device can be configured and operable as an optical amplifier; or as a high-power light emitter by providing extra carriers via the second electrode.

[0038] Also, in the above embodiments using the integrated Ge region being the highly N+doped region and / or has a tensile or compressive stress, and the electrode arrangement including the first and second electrodes, the electronic device can be configured and operable to provide direct gap light emission within the integrated Ge region upon application of an electric field via the first and second electric contacts of the first electrode, the second electrode being configured and operable as a stress-inducing electrode on the integrated Ge region, thereby affecting an energy band gap of the integrated Ge region, and thereby affecting one or more properties of light emission in the integrated Ge region.

[0039] The second electrode may comprise one or more of the following: a piezoelectric compound configured and operable to create stress under applied electrical power, Micro- Electro-Mechanical Systems (MEMS), polymers known to create stress under applied electrical / optical power. In any of the above embodiments using the integrated Ge region being the highly N+doped region and / or has a tensile or compressive stress, and the electrode arrangement including the first and second electrodes, the electronic device can be configured and operable to provide direct gap light emission within the integrated Ge region upon application of an electric field via the first and second electric contacts of the first electrode, said second electrode being configured and operable as a thermo-electric- cooler (TEC), configured and operable to regulate a temperature within and in the vicinity of the integrated GE region.

[0040] In some embodiments of the lateral configuration of the semiconductor structure, where the integrated Ge region has at least one of the following configurations: a highly doped N+Ge region, has a tensile stress, has compressive stress affecting an energy band gap of the integrated Ge region, and where the electric contacts of an electrode arrangement are provided comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, the device can be operable as a channel waveguide for propagating light being confined within said integrated Ge region, which may be fully embedded in the silicon device layer.

[0041] In some embodiments of the lateral configuration of the semiconductor structure with the integrated Ge region being undoped or a relatively lightly doped N region, and the electrode arrangement is provided including the first electrode, the device can be operable as a photodetector.

[0042] According to another broad aspect of the present disclosure, it provides an electronic device comprising a silicon device layer on an insulator, and an integrated Ge region at least partially embedded within a portion of said silicon device layer being enclosed between first and second intrinsic regions of said silicon device layer thereby forming a heterostructure Si-Ge waveguide.

[0043] According to yet another broad aspect of the present disclosure, it provides an electronic device comprising a semiconductor structure comprising a silicon device layer located on top of an insulator, said silicon device layer comprising: a first highly doped P+silicon region and a second region which comprises a highly doped N+region, wherein said second region comprises an integrated Ge-region at least partially embedded in the silicon device layer such that at least a bottom surface of said integrated Ge-region forms an interface with an intrinsic region of the silicon device layer. In its yet further broad aspect, the present disclosure provides an electronic device comprising: a semiconductor structure comprising: a silicon P+layer, and a clad on top of the silicon P+layer, said clad comprising an integrated N+doped Ge region directly interfacing with a surface region of the silicon P+layer; and an electrode comprising an electrical contacts arrangement, at least one first contact of said electric contacts arrangement being associated with the silicon P+layer and at least one second contact of said electric contacts arrangement being associated with the integrated N+doped Ge region.

[0044] The electrical contacts arrangement may comprise a pair of spaced-apart first contacts of the electrode contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact interfaces / contacts a top surface of the integrated N+doped Ge region.

[0045] In some embodiments of the semi-vertical configuration, the device can be configured as follows: the semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+P+diode or P+N+N+junction; and the electrical contacts arrangement comprises a pair of spaced-apart first contacts of the electrode contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom, and said at least second contact of contacting a top surface of the P+doped region or the N+doped region.

[0046] In some embodiments of the semi-vertical configuration, the electrical contacts arrangement comprises a first pair of spaced-apart first contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprises a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

[0047] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+P+diode or P+N+N+junction; and said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact of comprises a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the P+doped region or the N+doped region.

[0048] In some embodiments of the semi-vertical configuration, the electrical contacts arrangement comprises: said at least one first contact extending along a bottom surface of the silicon P+layer; and said second contact of said electric contacts arrangement comprising a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

[0049] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: said at least one first contact extending along a bottom surface of the silicon P+layer; and said second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the P+doped region or the N+doped region.

[0050] The present disclosure in its yet another broad aspect provides an electronic device comprising: a semiconductor structure comprising: a silicon P+layer, and a clad on top of the silicon P+layer, said silicon P+layer comprising an integrated N+doped Ge region embedded in said silicon P+layer; and an electrode comprising an electrical contacts arrangement, at least one first contact of said electrical contact arrangement associated with the silicon P+layer and at least one second contact of said electrical contacts arrangement associated with the integrated N+doped Ge region.

[0051] In some embodiments of the semi-vertical configuration, said electrical contacts arrangement comprises: a pair of spaced-apart contacts of the at least one first contact at least partially embedded in the clad and contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact at least partially embedded in the clad and contacting a top surface of the integrated N+ doped Ge region.

[0052] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises either one of a P+region or an N+region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises a pair of spaced-apart contacts of the at least one first contact at least partially embedded in the clad and contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said second contact contacting a top surface of either one of the P+region or the N+region.

[0053] In some embodiments of the semi-vertical configuration, said electrical contacts arrangement comprises: the at least one first contact contacting a bottom surface of said silicon P+layer; and the at least one second contact contacting a top surface of the integrated N+doped Ge region.

[0054] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises either one of a P+region or an N+region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: the at least one first contact of the contacting a bottom surface of said silicon P+layer; and the at least one second contact of the second electrode contacting a top surface of said either one of the silicon / polysilicon P+region or the silicon / polysilicon N+region.

[0055] In some embodiments of the semi-vertical configuration, said electrical contacts arrangement comprises: said at least one first contact comprising the first contact extending along a bottom surface of the silicon P+layer; and said at least one second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the integrated N+doped Ge region.

[0056] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises a pair of spaced apart doped regions embedded in the clad and interfacing with a pair of spaced-apart top regions of said integrated N+doped Ge region, each of said pair of the doped regions being configured as a P+region or as an N+region, thereby forming with said integrated N+doped Ge region a pair of P+N+diodes or a pair of P+N+N+junctions; and said electrical contacts arrangement comprises: said at least one first contact of comprising the first contact extending along a bottom surface of the silicon P+layer; and said at least one second contact comprising a pair of spaced-apart contacts contacting said pair of the spaced-apart doped regions.

[0057] In some embodiments of the semi-vertical configuration, said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprises a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

[0058] In some embodiments of the semi-vertical configuration, the device can be configured as follows: said semiconductor structure further comprises either one of a silicon / polysilicon P+region or a silicon / polysilicon N+region on top of said integrated N+ doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced- apart top surface regions of the silicon / poly silicon P+region or the silicon / poly silicon N+region.

[0059] BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to better understand the subject matter that is disclosed herein and to exemplify how it may be carried out in practice, embodiments will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0061] Fig. 1A schematically shows a semiconductor structure for use in an electronic device of the present disclosure based on a Si-Ge platform;

[0062] Fig. IB is a schematic illustration of a lateral configuration of the electronic device of the present disclosure; Figs. 2A to 2C exemplify electronic devices of the present disclosure with the lateral configuration of the semiconductor structure where the integrated Ge region is enclosed by two intrinsic regions and electrode arrangement includes a first electrode;

[0063] Figs. 3A and 3B exemplify electronic devices of the present disclosure with the lateral configurations of the semiconductor structure and an electrode arrangement including first and second electrodes, wherein the second electrode is placed above the integrated Ge region with a gap between them (Fig. 3A) the second electrode is placed above the integrated Ge region and directly interfaces with the integrated Ge region (Fig. 3B);

[0064] Figs. 4A and 4B exemplify electronic devices of the present disclosure with the lateral configuration of the semiconductor structure and electrode arrangement including first and second electrodes, where the second electrode includes PN di ode / NN junction is configured as a single contact with the semiconductor structure (Fig. 4A) or is configured as a split electrode (Fig. 4B) forming a “double junction” configuration;

[0065] Figs. 5A to 5D exemplify electronic devices of the present disclosure with the lateral configuration of the semiconductor structure and electrode arrangement including first and second electrodes where the second electrode is configured as a thermo-optical heater (Fig. 5A), a TEC setup (Fig. 5B), a stress-inducing electrode with a clad layer interface (Fig. 5C), and a stress-inducing electrode with direct contact to the integrated Ge region (Fig. 5D);

[0066] Figs. 6A to 6D exemplify electronic devices of the present disclosure with semilateral configuration of the semiconductor structure and electrode arrangement including a first electrode , wherein in Fig. 6A a second contact of the electrode interfaces with the integrated Ge region and is substantially identically spaced from opposite edges of the integrated Ge region, in Fig. 6B a conducting (doped) layer is introduced between the second contact and the integrated Ge region, in Fig. 6C the second contact interfaces with the integrated Ge region and is aligned with an edge of the integrated Ge region further from the intrinsic region, and in Fig. 6D the second contact is aligned with an edge of the integrated Ge region further from the intrinsic region and a conducting (doped) layer is introduced between the second contact and the integrated Ge region;

[0067] Figs. 7A-7H exemplify various devices of the present disclosure configured as a planar optical source / detector within a resonator formation; Figs. 8A and 8B exemplify the lateral device configuration of the present disclosure (Fig. 8B) as compared with a general art example of a vertical design (Fig. 8A);

[0068] Figs. 9A and 9B exemplify the Si-Ge electronic device of the present disclosure with a heater setup on the top and an in-chip TEC that regulate temperature deviations and tune wavelengths, wherein each unit, i.e. a light source with direct modulation, can participate in a WDM array, all built-in on the same chip;

[0069] Fig. 10 exemplifies the Si-Ge electronic device of the present disclosure functioning as an optical amplifier;

[0070] Fig. 11 exemplifies the Si-Ge electronic device of the present disclosure functioning as an active amplitude modulator;

[0071] Fig. 12 exemplifies the Si-Ge electronic device of the present disclosure configured as a channel waveguide;

[0072] Fig. 13 exemplifies the Si-Ge electronic device of the present disclosure functioning as an optical photodetector;

[0073] Figs. 14A to 14D illustrate parameter variations of the semiconductor structure of the present disclosure, wherein Fig. 14A shows variation in space between the doped regions and the integrated Ge region, Fig. 14B shows variation in the distance between the metal plug and the end of the doped region, Fig. 14C shows variation in the width of the integrated Ge region, and Fig. 14D shows variation in the height of the integrated Ge region;

[0074] Fig. 15 exemplifies fabrication results of the P+IN+IN+Si-Ge structure of the present disclosure;

[0075] Fig. 16 exemplifies the semiconductor structure of the lateral-type configuration according to another aspect of the present disclosure;

[0076] Fig. 17 exemplifies the semiconductor structure of the lateral-type configuration according to yet further aspect of the present disclosure;

[0077] Figs. 18A to 18F exemplify electronic devices according to yet another aspect of the present disclosure utilizing vertical configurations of Si-Ge structures in Si platform; and

[0078] Figs. 19A to 19H exemplify electronic devices of the present disclosure utilizing semi-vertical Si-Ge configurations in which the integrated Ge region is embedded in the highly P+doped Si bulk. DETAILED DESCRIPTION OF EMBODIMENTS

[0079] Reference is made to Fig. 1A showing schematically a semiconductor structure 120 configured and operable according to the present disclosure. The semiconductor structure is suitable for use in an electronic device for various applications, as described below. The semiconductor structure 120 has the lateral-type configuration, i.e., the main functional parts of the semiconductor structure are located within a silicon device layer 10 (generally, intrinsic layer) of the structure 120. As will be described more specifically further below, this may be a so-called "lateral" or a "semi-lateral" configuration of the semiconductor structure 120.

[0080] The silicon device layer 10 is located on top of an insulator (SOI) 20. The insulator 20 is a buried oxide layer which may typically include Silicon Dioxide (SO2) but may also include Silicon Nitride (SisN^. Other types of insulators or dielectric mediums, such as Indium Tin Oxide (ITO), Silicon Oxynitride (SiON), Silicon Carbide (SiC), Tantalum Pentoxide (Ta20s), Titanium Dioxide (TiO2), Zinc Oxide (ZnO), and Niobium Pentoxide (Nb2Os) may be included as well.

[0081] The silicon device layer 10 includes a first highly doped P+silicon region 30 and a second highly doped N+region 40, which is spaced from the first highly doped P+silicon region by a first intrinsic region II of the silicon device layer 10. According to the present disclosure, the second highly doped N+region 40 includes an integrated Ge-region 42 which is at least partially embedded in the silicon device layer 10.

[0082] In some embodiments, the semiconductor structure 120 further includes a clad 60 on top of the silicon device layer 10.

[0083] It is noted that in some embodiments, e.g., where the electronic device is configured to be operable as a laser, configuring the semiconductor structure 120 without the clad 60 may be even advantageous because it may allow heat to dissipate better out of the integrated Ge region 42, which generates heat due to (laser) light generation. In some embodiments, the lack of cladding may allow implementing a fan ventilating directly towards the integrated Ge region 42, thereby aiding to displace the heat out of the integrated Ge region 42.

[0084] It should be noted, although not specifically shown here, that the electronic device utilizing the above-described semiconductor structure of the present disclosure also includes electric contacts of an electrode arrangement. As exemplified in Fig. 1A, in some embodiments, the integrated Ge region 42 may by itself form the second highly doped N+region 40. Accordingly, the electric contacts are associated with the first highly P+doped region 30 and the integrated Ge region 42 presenting the second highly N+doped region 40. This is a so-called "semilateral configuration, which will be specifically exemplified and described further below.

[0085] As also exemplified in Fig. 1A, in some other embodiments the second highly doped N+region 40 is formed by the integrated Ge region 42 and a highly N+doped region 44 spaced from the integrated Ge region 42 by a second intrinsic region 12 of the silicon device layer 10. This is a so-called "lateral configuration" of the semiconductor structure 120, in which the first intrinsic region II and the second intrinsic region I2 are located at opposite sides of the integrated Ge region 42. In the lateral configuration, the integrated Ge region may be substantially undoped, or a relatively lightly N-doped region (as compared to that of region 44), or highly N+doped. In the lateral configuration, the electric contacts are associated with the regions 30 and 44 and in some examples also with the Ge region 42. This will be specifically exemplified and described further below.

[0086] It should be noted that the lateral -type (planar) configuration of the semiconductor structure of any of the examples described herein can be implemented in any suitable geometry, e.g., open / closed loop structure such as ring-like structure. This depends inter alia on the specific application of the electronic device, e.g., including its interaction with other devices of a common system of the specific application. This is exemplified in Figs. 7A-7H, 9A-9B described specifically further below.

[0087] Reference is now made to Fig. IB exemplifying an electronic device 100 with the lateral configuration of the semiconductor structure 120. To facilitate understanding, the same reference numbers are used to identify functionally common components / elements in all the examples described herein with reference to Figs. 1A to 17.

[0088] The semiconductor structure 120 of the electronic device 100 exemplified in Fig- IB, is configured generally similar as that of Fig. 1A, namely includes the silicon device layer 10 which is located on top of the insulator 20 and includes the first highly doped P+silicon region 30 and the second highly doped N+region 40, which is spaced from region 30 by the first intrinsic region II. In this example of the lateral configuration, region 40 includes the integrated Ge region 42 and the highly N+doped region 44 spaced from the integrated Ge region 42 by the second intrinsic region I2. As noted above and schematically shown in Fig. IB, in various embodiments of the lateral configuration, the integrated Ge region 42 may be highly N+doped (Ge-N+) or relatively lightly N-doped region (Ge-N) or undoped (Ge).

[0089] The electronic device 100 includes electric contacts of an electrode arrangement. The electric contacts are at times referred to herein as electrode elements. The electrode arrangement may include a single (first) electrode whose contacts are associated with the highly doped P+region 30 and highly doped N+region 44, or may also include a second electrode whose contact(s) is / are associated with the integrated Ge region 42. These will also be described and exemplified more specifically further below.

[0090] In the example of Fig. IB, a single-electrode configuration is shown. This single (first) electrode includes first and second contacts ECI and EC2 associated, respectively, with the first highly doped P+region 30 and the highly doped N+region 44.

[0091] Reference is made to Figs. 2A-2C showing specific non-limiting examples of the electronic devices of the present disclosure with the lateral configuration of the semiconductor structure. These devices 100 are configured generally similar to the device of Fig. IB. In these devices, the semiconductor structure 120 includes silicon device layer 10 located on top of insulator 20 and covered by clad layer 60, whose provision is optional as described above, and which if used can be configured using any known suitable technique, e.g., being Silicon Dioxide (SiCh) or Silicon Nitride (SisN^, Indium Tin Oxide (ITO), Silicon Oxynitride (SiON), Silicon Carbide (SiC), Tantalum Pentoxide (Ta2Os), Titanium Dioxide (TiO2), Zinc Oxide (ZnO), and Niobium Pentoxide (bt^Os).

[0092] The silicon device layer 10 has highly doped P+region 30 and highly doped N+region 44 (e.g., having about 1019-102°cm'3respective doping concentrations), and integrated Ge region 42 enclosed by first and second intrinsic regions II and 12. The electrode arrangement includes the first electrode whose electric contacts ECI and EC2 are associated with the first highly doped P+region 30 and the N+region 44 of the second region 40 and applied to both doped regions 30 and 44 to form metal (e.g., ohmic or Schottky) contacts.

[0093] Creation of desirably doped regions can be implemented using any known suitable technique(s). For example, the highly doped region 30 with acceptors, P+(holes), in silicon device layer 10 may be obtained by doping the Si device layer 10 in the respective region with Boron; a highly doped region 44 with donors, N+(electrons), can be obtained by doping the Si device layer 10 in the respective region with Phosphorus or Arsenic. It should be noted that before introducing the integrated Ge region 42, the semiconductor structure formed by highly doped P+and N+regions within the silicon device layer being spaced from one another by an intrinsic portion of the silicon device layer actually presents a classical PIN diode on SOI or silicon substrate. In order to form the semiconductor structure 120 of the present disclosure, a trench is made in a region I of the intrinsic portion of the Si device layer 10 between the P+and N+regions 30 and 44, and an integrated Ge region 42 is formed in this trench.

[0094] The integration of Ge region 42 can be performed by various known techniques, such as evaporation, deposition, epitaxy and epitaxial growth. Each technique uses different kinds of machines, however, all of the machines and techniques are CMOS compatible and can be found in traditional (& VLSI) fabrication facilities that support photonics integration in chips within SOI and Si-based platforms.

[0095] As exemplified in Fig. 2A, first and second intrinsic regions II and 12 at opposite sides of the integrated Ge region 42 (i.e., first intrinsic region II between the highly doped P+region 30 and the integrated Ge region 42, and second intrinsic region 12 between the integrated Ge region 42 and the highly doped N+region 44) have a predetermined first length Si and a predetermined second length S2, respectively. The first and second contacts ECI and EC2 of the first electrode are associated with regions 30 and 44, respectively. In some embodiments, the predetermined lengths Si and S2 are substantially the same, whereas in some other embodiments, the predetermined lengths Si and S2 are different.

[0096] As further exemplified in Fig. 2A, some design parameters of the semiconductor structure 120 can be varied during fabrication. These parameters include one or more of the following: the distance D [nm] between the edges of metal plugs / contacts and the respective edges of the highly doped regions (e.g., first distance, Di [nm], between edge El of contact ECI and edge 30' of highly doped P+region 30, and second distance, D2 [nm], (which may or may not be the same as the first distance) between edge E2 of contact EC2 and edge 44' of highly doped N+region 44; the width W [nm] of the integrated Ge region 42; and the height H [nm] of the integrated Ge region 42.

[0097] As further exemplified in Fig. 2A, the integrated Ge region 42 can be configured as a highly doped N+region, e.g., with about 5- 1019cm'3doping concentration. In this case (i.e., with highly doped Ge region), the electronic device 100 is configured as a P+IN+IN+Si-Ge heterostructure. However, as noted above, in other embodiments, the integrated Ge region 42 may be configured as substantially undoped or relatively lightly doped N . In such configurations of the semiconductor structure, the device is configured as a P+ININ+Si- Ge heterostructure.

[0098] It is noted that it is possible to obtain a finer quality of the integrated Ge region 42 and its integration into the trench in the Si device layer 10 by annealing the Si and Ge containing regions at various stages within the fabrication cycle.

[0099] Additionally, or alternatively, it is possible to integrate the Ge region 42 within the trench in the Si device layer 10 such that the Ge region is stressed. Generally, in some embodiments, the integrated Ge region 42 can be configured as highly N+doped, and / or having tensile stress, and / or having compressive stress, thereby defining an energy band profile of the integrated Ge region. The energy band profile of the integrated Ge region 42 can be configured to provide direct gap light emission within the integrated Ge region upon application of an electric field via the electric contacts including at least contacts ECI and EC2 associated with P+doped and N+doped regions 30 and 44.

[0100] The above considerations can provide that the energy needed to optically emit light from the direct bandgap of the Ge medium is reduced. This occurs due to the reduction in the energy gap between the indirect L and the direct T band valleys from 0.136 eV to 0.112 eV (under 0.25 % tensile strain).

[0101] Due to thermal expansion mismatch between the Ge and Si lattice, an average thermal stress of 0.25 % tensile strain in an epitaxial Ge layer on Si can be obtained along the Ge medium layer. The deposition of clad 60 (e.g., such as SiCh or Si3N4) on top of the silicon device layer (e.g., at least above the integrated Ge region 42) can apply additional stress on the Ge medium, which may increase the average stress in the integrated Ge region 42 and uniform it throughout its depth. Provision of the clad can also passivate the top surface of the Ge region 42 and reduce surface defects that increase the optical losses.

[0102] As noted above, in the example of Fig. 2A, the integrated Ge region 42 itself is a highly doped Ge-N+region, i.e., highly doped with donors (electrons). This can be implemented by doping the region 42 with Phosphorus, Antimonide or Arsenic. Doping the integrated Ge region 42 with N+donors fills the indirect band level, L, with electrons which in turn raises the Fermi level towards the direct band T level. Thus, under applied voltage, injected electrons are forced into the direct T valley and recombine with holes, resulting in efficient direct gap light emission. To make the optical band gap of the Ge completely direct gap, i.e. to reduce the gap between the L and T bands to 0, the N+donors’ concentration may reach 7.6* 1019cm'3. If the integrated Ge region is not stressed at all (like a bulk Ge), then the concentration providing direct band gap may be l ><1020cm'3. The larger the stress, the smaller the doping concentration may be. The stress red shifts the emission wavelengths towards longer wavelengths (at least under tensile strain) and doping the Ge medium blue shifts the emission wavelength towards shorter wavelengths. A tradeoff exists between the two effects. Generally, the N doping concentration of the Ge region in some embodiments of the present disclosure is above IxlO14cm'3. A compressive stress applied to the integrated Ge region may increase the energy gap of the direct-gap (of the T band), thus might potentially allow emission / detection of light at 1,400 nm and shorter wavelengths reaching 1,000 nm.

[0103] The semiconductor structure 120 of the lateral configuration with the integrated Ge region 42 being configured as a highly doped N+region (e.g., as shown in Fig. 2A), provides a new type of electronic device 100 configured as a P+IN+IN+Si-Ge heterostructure on SOI or silicon. This configuration of the semiconductor structure 120 allows to increase the electric field strength in the electronic device 100 as compared to a similar Si PIN diode without the integrated Ge region 42. In addition, the configuration of the semiconductor structure 120 of Fig. 2A reduces the optical losses of the generated light in the integrated Ge region / medium 42 due to distancing the first highly P+doped Si region 30 from the highly N+doped Si region 44, as well as distancing the electric contacts (metal) regions, from the evanescent field of the propagating modes. This advantage is detailed and analyzed further below.

[0104] In the description below, the electronic device 100 of Fig. 2A and its variations are referred to as a “lateral P+IN+IN+Si-Ge device” to emphasize the fully lateral mutual placement of the integrated Ge region 42 with respect to the highly P+doped Si region 30 and the highly N+doped Si region 44.

[0105] Fig. 2B exemplifies operation of the electronic device 100 and the semiconductor structure 120 of Fig. 2A. By applying voltage to the electric contacts ECI and EC2, holes start flowing from the highly doped P+region 30 towards the highly doped N+region 44. Similarly, electrons from the highly doped N+region 44 start flowing towards the highly doped P+region 30. The holes and electrons carriers create a current in the circuit, behaving as a typical PIN diode driven under forward bias. Since the carriers, while flowing through the intrinsic region / portion I of the silicon device layer 10 between P+doped and N+doped regions 30 and 44, encounter the highly doped Ge-N+region 42 (i.e., a highly electrically conducting region), the majority of these carriers can flow through the highly doped Ge region 42.

[0106] Therefore, since the highly conducting region 42 (Ge-N+region) now exists in the overall intrinsic region / portion I (IN+I), there exists a stronger electric field in this region, i.e., between the highly P+doped Si region 30 and highly N+Si region regions 44, and therefore lesser power consumption is needed to drive the same carrier concentrations in the overall intrinsic I region / portion had it not existed. In essence, the effective length of the Si intrinsic region I is decreased, which in turns, reduces the series resistance.

[0107] Holes which interact with electrons in the integrated Ge region can recombine and emit light (photons) at wavelengths relating to the Ge band gaps. Emissions of slightly different wavelengths may occur with recombination of carries in the Si-Ge interface as well. Emission of light can occur in a wavelength range of 1,400 nm to 1,800 nm. Typically, the emission from the Si-Ge interface is at shorter wavelengths than that from the Ge medium. As will be described more in detail below, the integrated Ge region 42 of the electronic device 100 may be configured with an energy band profile enabling operation of the device as a broadband optical source device (e.g., LED) emitting light in a range of 1,400 - 13,000 nm.

[0108] The Si-Ge interface (42D in Fig. 2B) mainly comprises a p-n junction, which is formed due to the highly N+doped Ge region / medium 42 in contact with the intrinsic (or typically lightly P doped 1015cm'3) silicon material of the silicon device layer 10 surrounding it (e.g., intrinsic regions II and 12 regions in Fig. 2B), and of a Si-Ge alloy which is formed during the integration of the Ge medium in the trench made in the Si layer. Due to highly N+doping of the integrated Ge region 42, a high concentration of dopant electrons exists in the interface region (e.g., 42D). This concentration is larger than the average concentration in the Ge medium in the internal volumes of the integrated Ge region 42 not interfacing with the silicon device layer 10.

[0109] In the lateral configuration of the semiconductor structure 120 of Figs. 2A and 2B, the Si-Ge interface exists both at the bottom of the Ge medium (e.g., indicated as 42D at the interface with the bottom intrinsic region in Fig. 2B) and at its sides (e.g., indicated as 42E at the interface with the first intrinsic region II in Fig. 2B) Thus, this configuration of the semiconductor structure 120 provides a larger interaction area compared to other known devices using Ge layers, such as placing the Ge layer on top of the silicon layer 10 (e.g. vertical stack) or other known in the art vertical and / or semivertical configurations where the Ge layer is placed substantially on top of the silicon layer.

[0110] The light emitted within the highly N+doped Ge region 42 excites a propagating mode or several modes (multi-modes) inside the Ge region 42 that propagate(s) in the Si- Ge waveguide-like structure in the length direction (along the z-axis defined in Fig. 2B), as indicated by L [pm] and its accompanying arrow. The semiconductor structure 120 can thus function as a fully lateral, built inside the chip, electro-optically integrated, broadband optical source device (LED).

[0111] In some embodiments, for example, where the integrated Ge region 42 is configured as a highly doped N+region (example of Figs. 2A and 2B), the electronic device 100 may further include a resonator located in a light propagating direction (e.g., along the z-axis defined in Fig. 2B), the resonator being confined within the integrated Ge region 42. Such configuration enables lasing to occur under a threshold voltage or current, the electronic device 100 being thereby operable as a coherent optical source device. The resonator may be based on any known configuration, such as classical resonators based on Fabry-Perot, ring-resonator, etc. (see, for example, Fig. 7A). The electronic device 100 including the semiconductor structure 120 may thus function as a fully lateral, built inside the chip, coherent optical source device (laser).

[0112] It should be noted, and will be described below, that lasing may be achieved with the electronic device 100 also with un-doped or lightly N-doped Ge region 42, provided that sufficient tensile or compressive stress is applied to the integrated Ge region and / or the surrounding interface (Si-Ge) 42.

[0113] In the following, the optical losses within the overall intrinsic region I (IN+I) are analyzed and evaluated in detail.

[0114] Light generated / emitted by the Ge medium in the integrated Ge region 42 excites a propagating mode (or several modes) in the Ge waveguide-like medium. The light is guided in the integrated Ge region 42 as in a waveguide layer because of the high refractive index of Ge, 4.2 at k= l ,55pm, compared to the other materials surrounding the integrated Ge region (the highest refractive index is that of Si, 3.47 at k=1.55pm). Depending on the width of the integrated Ge region 42 (denoted W in Figs. 2A and 2B), the 1stpropagating mode (fundamental mode) energy is distributed in the center with tails of the field, aka evanescent field, outside the Ge medium. The larger the width W is, the shorter the tails are. As the width W increases, more propagating modes are excited that take some of the energy that could excite the fundamental mode. In addition, these modes may interfere in the resonator in the case of a laser structure and significantly degrade the laser performances.

[0115] The tail of the optical field may interact with the highly doped Si regions (see example of a Field Tail of 1stMode in Fig. 2C) and consequently experience very large optical loss. In particular, interaction with the P+(holes) region 30 may generate 3.5 times larger loss than interaction with the N+(electrons) region 44. In addition, the optical field may also interact with the metal contacts (e.g., ECI and EC2), which further significantly increases the losses.

[0116] The existence of the Si intrinsic region I enables to distance the doped regions (e.g., regions 30 and 44) and the metal contacts to a distance such that the propagating modes, and in particular the fundamental mode, have no interaction with them.

[0117] On the vertical axis (y axis) the evanescent field interacts with the clad and the insulator layer beneath the silicon, where both layers are mediums chosen to provide minimal (if any) optical loss. Therefore, there is no optical loss from the vertical axis.

[0118] This means that the generated light suffers optical losses only from the highly doped N+(with electrons) integrated Ge region 42 and the presence of charged carrier concentrations under applied voltage, i.e., current driving charge carriers (holes + electrons).

[0119] It should be noted that in known structures of emitter and detector devices based on Si and Ge compounds, the generated light always interacts with the highly doped Si regions. One method aimed to reduce this loss includes widening of the Ge region / layer in order to confine more energy of the fundamental mode in the Ge region. This results in the tail field being shorter and with lesser energy than the field in the center. However, by doing that, other modes are excited (from both polarizations, TE and TM-like). Some of the known structures, such as vertical structures, cannot avoid the light and metal interaction, and therefore, suffer additional losses. It is noted that known Si-Ge structures also suffer from losses due to the doped Ge region and the driving current mentioned above in relation to the structure of the present disclosure.

[0120] The optical confinement factor for propagating modes in a Si-Ge waveguide is -60% at wavelength around 1,550 nm. The loss due to the direct proximity of the Ge waveguide and the highly doped Si regions is larger than 300 cm'1, or 1,303 dB / cm (not considering losses from the metals). This loss is completely avoided in the P+IN+IN+structure of the present disclosure.

[0121] The absorption loss due to presence of free carriers is typically described by: «FCA (A„ml) = 3.4 ■ 10-25. A)Vlcm-s]• A2,25+ 3.2 • 10-25■ AP[cm-3]• A2,43[^] (1) where AN and AP are the concentrations of the electrons and holes respectively.

[0122] Considering 0.25% tensile-strained Ge that is doped with electrons at 7.6* 1019cm'3, the loss described by Eq. (1), due to this highly doped Ge region, is therefore 390 cm'1, or 1,693 dB / cm.

[0123] To emit light, the net gain should be larger than 0. The gain from direct transition occurs once enough carriers are injected into the Ge medium under applied voltage. The presence of the injected carriers (holes and electrons) increases the optical loss.

[0124] In the Si-Ge electronic device of the present disclosure, the total loss prior to applying voltage, is 390 cm'1. Emission starts (net gain = 0) at carrier injection of 3.5* 1018cm'3, with total loss of 500 cm'1. To reach a net gain of 100 cm'1, an injection carrier of 4.8* 1018cm'3, with a total loss of 520 cm'1, is needed.

[0125] It should be noted that at threshold current, the indirect band gap, L, is also in the population inversion state and contributes an optical gain of about 50 cm'1. Therefore, the concentration of the carrier injection required will be lower. For a net gain of 100 cm'1, the injection carrier needed is around 3* 1018cm'3(instead of 4.8* 1018cm'3).

[0126] For comparison, in the known Si-Ge structures, the total loss prior to applying voltage, is about 690 cm'1. Emission starts (net gain equal 0) at carrier injection of 7.5* 1018cm'3, with total loss of 850 cm'1. To reach a net gain of 100 cm'1, an injection carrier of 9* 1018cm'3, with a total loss of 900 cm'1, is needed (including the gain of the indirect band gap).

[0127] For InP lasers (on InP platform), the typical net gain at 1,550 nm is between 50 to 100 cm'1. For hybrid integration of InP on SOI platform, this number is expected to be much lower (mainly because of (hybrid) integration losses).

[0128] The above analysis clearly shows that the electronic device with the semiconductor structure of the present disclosure including the Si intrinsic region / portion I including the integrated Ge-region 42 (e.g., in the P+IN+IN+structure of Fig. 2 A) provides the same gain with a third of the carrier concentration needed in other known devices, i.e., carrier concentration of 3* 1018cm'3vs. 9* 1018cm'3. In addition, the semiconductor structure 120 of the present disclosure can provide a net gain of 100 cm'1, which is the same gain level provided by other solutions (e.g., InP), quite close to the threshold current (required for the start of light emission).

[0129] At larger carrier injection of l * 1019cm'3, the net gain of the semiconductor structure 120 of the present disclosure, can reach up to 500 cm'1, which can be suitable for high power emission.

[0130] The reduction of the optical losses, due to the presence of the specially designed Si intrinsic portion I with the integrated Ge region in the semiconductor structure of the present disclosure, results in the following advantageous implications: (i) larger achievable gain and optical power emission; (ii) lower threshold voltage / current leading to lower power consumption; (iii) lesser heat generated leading to lesser TEC power consumption; (iv) more stable and reliable performance and operation; (v) lesser short- term / 1 ong-term damage and degradation (due to lesser heat); (vi) larger responsivity for optical detection (photon-to-current conversion); and (vii) larger SNR for photodetection.

[0131] As will be described below, additional advantage allows application of the second electrode to the semiconductor structure 120. The influence of the second electrode may be significantly increased and under lesser power consumption.

[0132] As mentioned above, the provision of the Si intrinsic portion I with the integrated Ge-region 42 advantageously provides distancing of the Si-Ge interface from the highly doped P+and N+regions 30 and 44 in the silicon device layer 10. The photons that are generated in the Si-Ge interface, i.e., in the p-n junction and Si-Ge alloy, require some propagating distance before they are fully “added” to the excited mode, therefore, any proximity or contact with a highly doped Si region may exert larger losses on them.

[0133] In addition, due to a difference in the refractive index at the interface layer (e.g., 42D in Fig. 2B) compared to that at the center of the integrated Ge region 42, the generated photons may excite propagating modes that will confine the light in the center of the interface layer rather than at the center of the integrated Ge region itself. The refractive index at the interface, which might be non-uniform and larger than that at the center of the Ge region, is different due to the presence of the Si-Ge alloy, stress, and the presence of a higher dopant concentration of electrons.

[0134] The tail of the optical field of the propagating modes may not be symmetric, and even longer, as well as leaning towards the highly doped Si-P+region 30 (see Fig. 2C). Consequently, the propagating modes may suffer larger losses as compared to the situation where they are confined in the center of the Ge medium. Fig. 2C exemplifies a semiconductor structure 120 where the predetermined lengths Si and S2 of the respective intrinsic regions II and 12, are different (i.e., Si^Sz). Specifically, such configuration can prevent losses in case the light is more confined in the interface region. For example, to avoid such losses, the length of either one of the Si intrinsic regions II and 12 can be increased, or it can be spaced asymmetrically

[0135] Optical losses in the electronic device of the present disclosure are considerably reduced as compared to other known Si-Ge semiconductor structures thanks to the unique lateral integration of the Ge region 42 within the silicon device layer 10. The sidewalls surface roughness of the Si etched sidewalls that interface with the Ge medium in region 42 yield lower optical losses compared to silicon dioxide (SiCh) walls that typically interface with the Ge medium in vertical devices. According to a model commonly used to evaluate sidewalls roughness losses, the roughness losses decrease with lower refractive index contrast in the lateral plane. Since the refractive index contrast between Ge and Si is much smaller (~0.7) than that between Ge and Air (-4.2), the roughness losses in the electronic device of the present disclosure can be significantly smaller, i.e., by about one order of magnitude compared to known vertical devices.

[0136] In the following, the optical bandwidth of the electronic device 100 of the present disclosure is described.

[0137] The presence of the Si intrinsic region / portion I including the integrated Ge region 42 allows avoiding the losses in the highly doped Si regions of the silicon device layer 10 and metal contacts when the generated, amplified or detected light is related to higher order modes (vs. the fundamental mode) and to different polarizations of the propagating modes.

[0138] In addition, the same structure can also avoid these losses for a larger bandwidth of the wavelength range. In particular, the Si intrinsic region / portion I with the integrated Ge region 42 provides for sustaining a large optical bandwidth in cases where the second electrode is used to configure the structure to act as a tunable wavelength light source / detector, or as a tunable wavelength band light source / detector, as described further below.

[0139] Changing the wavelength causes changes in the mode field shape and its tail length. Consequently, without the Si intrinsic region / portion I with the integrated Ge region 42, the losses will change according to the light’s wavelength, mode order and polarization. Thus, the performance will not be uniform with bandwidth. When a single mode operation is required, the Si intrinsic region I with integrated Ge region allows to shrink the waveguide dimensions, in particular the width of the integrated Ge region / layer 42, to support a single mode operation and avoid the interaction of the tail with the highly doped Si regions.

[0140] As mentioned above, the electronic device 100 of the present disclosure may function as a fully lateral, built inside the chip, coherent optical source device, which may be coupled to a Si bus configured to carry the light from the semiconductor structure 120 into the next circuit. The smaller Ge waveguide dimensions (i.e., the width W) in the semiconductor structure 120 can ease the sensitivity of the coupler unit that participates in coupling the related light into and out of a Si bus.

[0141] In the following, a variation of the electronic device 100 of the present disclosure is described, wherein the additional (second) electrode is applied to the lateral configuration P+IN+IN+semiconductor structure 120. The entire device is on-chip (built- in) in SOI and Si-based platforms and can perform the following: (a) direct modulation of the light emitted or detected (LED / Laser / Amplifier / Single Photon and Detector); (b) tuning the emitted wavelength (tunable Laser); (c) tuning the emitted wavelength band, SWIR to MWIR (tunable band Laser); (d) tuning the Quantum Efficiency (QE) of detected light (tunable QE detector); (e) tuning the detected wavelength band, SWIR to MWIR (tunable band detector); (f) high power emitter or enhanced amplifier, it can be applied for both emission of light and for amplifying incoming light; (g) providing embedded architecture for temperature control (TEC) and cooling; and (h) providing embedded architecture for calibration electrode.

[0142] Reference is made to Figs. 3A and 3B exemplifying electronic devices 100 configured according to some embodiments of the present disclosure. Each of these electronic devices 100 includes the semiconductor structure 120 of the lateral configuration described above, namely including the silicon device layer 10 having highly doped P+region 30, highly doped N+region 44, and integrated Ge region 42 spaced from regions 30 and 44 by intrinsic regions II and 12 of the silicon device layer 10. In the examples of Figs. 3A and 3B, similar to the lateral P+IN+IN+Si-Ge device of Fig. 2A, the integrated Ge region 42 is configured as a highly doped N+Ge region. Also, in the examples of Figs. 3A and 3B, the electrode arrangement includes the first electrode having electric contacts ECI and EC2 associated with the regions 30 and 44 and additionally includes a second electrode having third electric contact EC3 associated with the integrated Ge region 42 and located above region 42, such that contact EC3 is at least partially in a clad layer 60 on top of the silicon device layer 10.

[0143] In some embodiments, as exemplified in Fig. 3A, the third contact EC3 is spaced from the integrated Ge region 42 by a portion of the clad 60. In some other embodiments, as exemplified in Fig. 3B, the third contact EC3 directly interfaces a top surface of the integrated Ge region 42.

[0144] Depending on the thickness of the oxide between the metal of the third contact EC3 and the integrated Ge region 42 (in the configuration shown in Fig. 3A), a Metal- Oxi de- Semi conductor (MOS) capacitor is formed and can influence the concentration of the carriers in the integrated Ge region. This control of carriers’ concentration allows to change the power of the optical light emitted at the specific wavelength and serves as a high-speed modulator. Consequently, it results in a direct modulation of the light being emitted, amplified or detected by the electronic device 100. Since the 2ndelectrode introduces an electric field on the integrated Ge region 42, it may also affect its energy bands’ structure. This may strengthen the overall effect in some applications, e.g., direct modulation, and may decrease the power needed to obtain the same performance of the device.

[0145] Considering the electronic device 100 of Figs. 3A or 3B configured as an optical amplifier, the second electrode (third contact EC3) can be used as a “volume knob” for setting the amplification strength.

[0146] Considering the electronic device 100 of Figs. 3A or 3B configured as a photodetector, the second electrode (third contact EC3) can tune the quantum efficiency (QE) of the detected wavelength by applying an electric field and modifying the bands’ structure.

[0147] Since the effect of the second electrode occurs due to the introduction of the electric field, the entire structure may act as a Photonic Field-Effect Transistor (P-FET) device.

[0148] Fig. 4A exemplifies an electronic device 100 configured generally similar to that of Fig. 3A, and being different therefrom in that the portion of the clad 60, by which the third contact EC3 (second electrode) is spaced from the integrated Ge region 42, includes a P+doped region 70A or an N+doped region 70B, forming with the integrated Ge region 42 a P+N+diode or N+N+junction, respectively.

[0149] The region 70A or 70B may be implemented with mediums that can be intentionally doped (n type or p type) and can be integrated on silicon or SOI platform, e.g. Silicon, Polysilicon, Amorphous Si (a-Si:H), Si-Ge alloys, poly-Si-Ge, Silicon Carbide (SiC) and Gallium Nitride (GaN).

[0150] Together with the P+IN+IN+electrical structure, the entire structure may function as a Photonic Junction Field-Effect Transistor (P-JFET) with a source, a drain, and a gate on the gain Ge medium. The general structure of Fig. 4A may be used in applications such as a high-power emitter or an enhanced optical amplifier. In some embodiments, the second electrode (constituted by electric contact EC3) may be used to change the carrier concentration inside the integrated Ge region 42 for the purposes of modulating the emitted light. In other embodiments, such second electrode may contribute excess holes or electrons in order to increase the emitted or amplified optical power.

[0151] If the lateral P+IN+IN+structure cannot saturate the Ge gain medium, then providing more holes or electrons via the second electrode source, can result in a net optical power increase. Therefore, the electronic device 100 of Fig. 4A can serve as a high-power light emitter or provide enhanced amplification for coupled light signals.

[0152] It should be noted that the portion of the clad between the second electrode EC3 and the integrated Ge region may not be configured as a donor or acceptor, but can serve as a full junction, i.e., can be in the form of a split contact formed by first and second spaced-apart electrode elements (electric contacts) of the second electrode aligned with opposite edges, respectively, of the integrated Ge region. Such a split configuration is exemplified in Fig. 4B.

[0153] Fig. 4B shows an electronic device 100 including the semiconductor structure of the lateral configuration as described and exemplified above, and the electrode arrangement configured generally similar to that of Fig. 4A, i.e., including electric contacts ECI and EC2 of the first electrodes applied to highly P+doped and highly N+doped regions 30 and 44, and the second electrode associated with the integrated Ge region 42 and having a doped portion.

[0154] However, in the example of Fig. 4B, the third metal contact EC3 is configured as a split contact formed by first and second spaced-apart electrode elements, EC3A and EC3B, of the second electrode which are aligned with opposite edges, respectively, of the integrated Ge region 42, and these electrode elements EC3A and EC3B of third contact EC3 are spaced from the edges of the integrated Ge region 42 by spaced-apart oppositely doped regions 70A and 70B of the clad 60 portion. These regions 70A and 70B of the clad portion are P+doped and N+doped regions and they are aligned with, respectively, the opposite edges of the integrated Ge region 42, thereby forming with the integrated Ge region 42 first P+N+junction and second N+N+junction, respectively. The regions 70A and 70B may be implemented with mediums that can be intentionally doped (n type or p type) and can be integrated on silicon or SOI platform (e.g. Silicon, Polysilicon, etc.). This split-electrode configuration is referred to herein as “Double Injection”, since two independent electrodes (through EC3A and EC3B) inject carriers into the Ge medium.

[0155] In the example of Fig. 4A or 4B, the second electrode above the integrated Ge region 42 can be deposited or grown by various known techniques, similar to those detailed for the Ge deposition as is described in detail further below. Typically, the doped regions 70A / 70B are made by silicon or polysilicon mediums.

[0156] Reference is made to Figs. 5A to 5C exemplifying device 100 configuration according to some other embodiments. The devices of these examples include the semiconductor structure 120 of the lateral configuration as described above including the N+doped integrated Ge region 42 enclosed by the intrinsic regions II and 12.

[0157] Fig. 5A exemplifies the device configured and operable to provide direct gap light emission within the integrated Ge region 42 upon application of an electric field via the first and second electric contacts ECI and EC2 of the first electrode. In this example, the second electrode is configured and operable as a thermo-optical electrode heater 80, inducing a change in refractive index of the integrated Ge region 42 by induced heating, thereby affecting the power of the direct gap light emission at a specific wavelength. In this configuration, the second electrode is spaced from the integrated Ge region and is placed above or projecting from the clad 60.

[0158] Depending on the thickness of the oxide (clad) between the heater 80 and the integrated Ge region 42, a Thermo-Optical electrode heater is formed that can influence the refractive index of the Ge medium by induced heating. This allows increase or decrease of the power of light being emitted at the specific wavelength due to the change in refractive index. In particular, such control of the power at a specific wavelength may be useful in case the semiconductor structure 120 forms a cavity for lasing, as will be described below.

[0159] In some embodiments, the thermo-optical electrode heater 80 may shift the emitted wavelength significantly while retaining roughly the same power at each emitted wavelength, thus serving as a tunable light source, e.g., a tunable LED / Laser.

[0160] The thermo-optical effect on Ge medium is stronger than on alternative mediums such as Si, InP or GaAs. Therefore, less power consumption is needed in order to shift the operating wavelength (see Table 1 below) which allows the electronic device 100 having the configuration of Fig. 5A, to function as a much more efficient tunable light source, in particular, a tunable laser.

[0161] Table 1

[0162] In addition, if the heating is intense, the emitted power may increase due to thermal energy that excites additional electrons to flow into the direct band gap T.

[0163] The heater electrode 80 can be deposited by various known techniques and may include any of the following materials: Tungsten metal, Titanium metal, Copper metal, other metals, polymers, and materials that can generate efficient heating under applied electrical / optical power.

[0164] Fig 5B exemplifies a general structure of the electronic device 100 with a thermo- electric-cooler (TEC) setup 82 to regulate the temperature and cool the device. The electronic device 100 of Fig. 5B is configured and operable to provide direct gap light emission within the integrated Ge region 42 upon application of an electric field via the first and second electric contacts ECI and EC2 of the first electrode. The second electrode is configured and operable as a thermo-electric-cooler (TEC) 82, configured and operable to regulate a temperature within and in the vicinity of the integrated Ge region. Depending on the thickness of the oxide between the TEC structure 82 and the integrated Ge region / layer 42, a temperature control system can absorb the heat, and in addition, can apply cooling to stabilize and enhance the performance of the device.

[0165] The interaction between the TEC setup 82 and the N+doped integrated Ge region / waveguide 42 can be direct and depends on the thickness of the remaining clad 60. For example, the TEC setup 82 may be directly interfaced with the integrated Ge region 42 (not shown in a figure). Within the integrated Ge region 42 and its vicinity, heat may be generated due to the interaction between the holes and electrons. By having a direct proximity to the integrated Ge region 42, the TEC 82 and its cooling system have the most efficient opportunity to regulate the temperature of the electronic device 100.

[0166] As described above (see Table 1), the temperature needed to shift the wavelength by 1 nm, or balance unwanted temperature deviations, is lesser in the electronic device of the present disclosure as compared to the temperature needed to do the same for devices in other platforms (e.g., InP, GaAs, etc.). Since practical in-chip light sources from any platform require temperature control system, the overall power consumption of the entire system (light source + TEC) is expected to be lower in the device of the present disclosure, even in cases where the light source structure itself is less efficient than those of other platforms.

[0167] It should be noted that, generally, it is possible to place on top of the integrated Ge region an electrode that can create physical or mechanical (tensile or compressive) stress on the Ge region. This electrode can be controlled by applied voltage or by other typical methods known in the art. Changes in stress (tensile or compressive) can cause significant changes in the energy gap between the indirect and direct band gaps of the Ge medium. This, in turn, can provide the following capabilities: (i) shift the center of the emitted wavelength (e.g., LED emission, lasing emission and amplification wavelength range); (ii) shift the center of the detected wavelength range (photodetection); (iii) change the power emitted or amplified; (iv) change the refractive index of the Ge medium; (v) change the loss coefficient of the Ge medium; and (vi) change other properties related to the Ge medium and the Si-Ge interface.

[0168] Unlike the other types of electrodes described above, a stress-inducing electrode may affect more than one parameter at the same time. An example of such a configuration is shown in Fig. 5C. Fig. 5C shows an electronic device 100 including a semiconductor structure 120 of the lateral configuration described above, and the electrode arrangement including the first electrode whose first and second electric contacts ECI and EC2 are associated with / applied to the highly doped P+and highly doped N+regions 30 and 44 of the silicon device layer 10, and the second electrode including a third contact EC3 associated with the integrated N+doped Ge region 42. The semiconductor structure 120 of Fig. 5C is configured and operable to provide direct gap light emission within the integrated N+doped Ge region 42 upon application of an electric field via the first and second electric contacts ECI and EC2 of the first electrode. The third contact EC3 associated with the integrated Ge region 42 is located above region 42 being at least partially in the clad 60 such that the third contact EC3 is spaced from the integrated Ge region 42 by a portion of the clad 60. The second electrode is configured and operable as a stress-inducing electrode 84 inducing stress on the integrated Ge region 42, thereby affecting an energy band gap of the integrated Ge region 42, and thereby affecting one or more properties of light emission in the integrated Ge region 42.

[0169] Due to the capability of significantly changing the energy band gaps of the Ge medium that can be caused by induced stress (tensile or compressive), the energy gap for radiation achieved by the induced stress may correspond to emission in the range of 1,400 - 1,800 nm and may even exceed emissions at wavelengths of 3 pm and higher.

[0170] Therefore, the electronic device 100 of the present disclosure can serve as tunable emitter, amplifier or detector that can tune the operating optical bands, e.g. between O- Band to L-Band and even wider bands, from Short Wave IR (SWIR), ~1.3 pm, to Mid Wave IR (MWIR), -5 pm.

[0171] The stress-inducing electrode 84 can be implemented by various known compounds, methods and techniques including any of the following: (a) a piezoelectric compound that can create stress under applied electrical power; (b) Micro-Electro- Mechanical Systems (MEMS); (c) polymers that that can create stress under applied electrical power, such as polyvinylidene difluoride (PVDF); (d) other known compounds or materials that can generate stress under applied electrical / optical power; and (e) other known compounds, or materials with effects, that can apply pressure, stress or deformation to typical CMOS clad layers such as silicon dioxide, SiO2, silicon nitride, SislS , etc. The effect on the clad layer will pass to the Ge layer beneath. The interaction between the stress-inducing electrode 84 and the integrated Ge region / waveguide 42 can be direct. Such direct interfacing of the stress-inducing electrode 84 with the integrated Ge region 42 is shown in Fig. 5D in a self-explanatory manner. The direct interfacing can increase the net stress that is applied to the Ge medium. Furthermore, the clad medium may be limited to transfer stress of only one kind, i.e., tensile or compressive stress. Also, a large amount of stress which is exerted on a clad medium may introduce optical losses, while the material of the stress electrode may be chosen or designed such that it can handle the required stress without deformations.

[0172] It is noted that all the configurations described above and including the second electrode (Figs. 3A - 3B, 4A - 4B, and 5A - 5D) could be considered as the electronic devices described in Figs. 2A - 2C, but with an additional embedded electrode used only for calibration. Because the second electrode is located such that it has a direct access to the integrated Ge region (waveguide), the electrode can be used to calibrate the various parameters relating to the emission, amplification or detection of light.

[0173] Reference is made to Figs. 6A to 6D exemplifying configurations of the electronic device 100 including the semiconductor structure 130 of the “semi-lateral” configuration of generally lateral-type design as described above, i.e., the main functional parts of the semiconductor structure are located within a silicon device layer 10 (generally, intrinsic layer) of the semiconductor structure 120.

[0174] Thus, the semiconductor structure 120 of the semi-lateral configuration includes silicon device layer 10 located on top of insulator (SOI) 20, being a buried oxide layer which may typically include silicon dioxide (SO2) but may also include silicon nitride (SisN^. The silicon device layer 10 includes first highly doped P+silicon region 30 and second highly doped N+region 40, which is spaced from the first highly doped P+silicon region 30 by first intrinsic region II of the silicon device layer 10 and includes integrated Ge-region 42 at least partially embedded in the silicon device layer 10. In some embodiments, the semiconductor structure 120 further includes clad 60 on top of the silicon device layer 10. Also provided in the electronic device of these examples is an electrode arrangement,

[0175] The semiconductor structure 120 in the examples of Figs. 6A to 6D differs from the semiconductor structure of lateral configuration (e.g., of Fig. 2A) in that the second highly doped N+region 40 is formed by the integrated highly doped N+Ge region 42, and accordingly, the silicon device layer 10 includes a single (first) intrinsic region II enclosed between the first highly doped P+silicon region 30 and the integrated Ge region 42

[0176] Fig. 6A shows the device 100 with the semi-lateral semiconductor structure 120 and first and second contacts ECI and EC2 of the electrode arrangement associated with, respectively, the first highly doped P+region 30 and the integrated Ge region 42, thereby forming a P+IN+Si-Ge heterostructure operable as a PIN diode in SOI or silicon.

[0177] Similar to the lateral configuration semiconductor structure described above, the highly doped P+region 30 in the silicon device layer 10 of the SOI is usually implemented by doping the Si device layer with Boron.

[0178] It is noted that both the semi-lateral and lateral configurations present a lateraltype design of the semiconductor structure 120, while the semi-lateral configuration can be classified as a “sub structure” of the “lateral” configuration. The difference between the ”semi-lateral” and “lateral” configurations is in the removal of the highly doped N+region 44 in the Si device layer 10 spaced from the integrated Ge region by second intrinsic region I2. In the semi-lateral semiconductor structure 120, the function of the highly doped N+region 44 needed to deliver current is “replaced” by the highly doped N+electron carrier in the integrated N+doped Ge region 42.

[0179] In the examples of Figs. 6A and 6B, the second contact EC2 is located at least partially in the clad 60, on top of the silicon device layer 10, and is aligned with the integrated Ge region 42 in a substantially symmetrical configuration with respect to the integrated Ge region 42. In these examples, the second metal contact EC2 is substantially identically spaced from opposite edges of the integrated Ge region 42.

[0180] In the example of Fig. 6A, the second contact EC2 directly interfaces with the integrated Ge region 42, whereas in the example of Fig. 6B, the second contact EC2 is spaced from the integrated Ge region 42 by a portion of the clad 60. Also, in the example of Fig. 6B, this portion of the clad 60 includes a P+doped region 70A or a N+doped region 70B, forming with the N+doped integrated Ge region 42 a P+N+or N+N+junction, respectively.

[0181] The region 70A / 70B may be implemented using mediums that can be intentionally doped (n type or p type) and can be integrated on silicon or SOI platform (e.g. Silicon, Polysilicon, etc.).

[0182] In the examples of Figs. 6C and 6D, the second contact EC2 is located at least partially in the clad 60, on top of the silicon device layer 10, and is aligned with the integrated Ge region 42 in a substantially asymmetrical configuration with respect to opposite edges of the integrated Ge region 42. The second metal contact EC2 in these configurations is aligned with an edge of the integrated Ge region 42 further from the first intrinsic region II.

[0183] In the example of Fig. 6C, the second contact EC2 directly interfaces with the integrated Ge region 42, whereas in the example of Fig. 6D, the second contact EC2 is spaced from the integrated Ge region 42 by a portion of the clad 60. The additional distancing of the second contact EC2 from the integrated Ge region 42 may reduce the optical losses that the generated light will suffer due to the proximity of the metal.

[0184] In the example of Fig. 6D, the portion of the clad 60 includes a P+doped region 70A or a N+doped region 70B, forming with the N+doped integrated Ge region 42 a P+N+or N+N+junction, respectively. The region 70A / 70B may be implemented using mediums that can be intentionally doped (n type or p type) and can be integrated on silicon or SOI platform (e.g. Silicon, Polysilicon, etc.).

[0185] In the following, possible applications of the various configurations of the electronic device 100 of the present disclosure are described.

[0186] As was mentioned above, the electronic device 100 including the semiconductor structure the lateral-type, i.e., lateral or semi-lateral configuration, can function as a fully lateral, built inside the chip, laser. By placing the semiconductor structures of the present disclosure in a resonator design, a planar cavity can be formed to support lasing at specific wavelengths. Typical resonators known in the arts are micro ring-based resonators and Fabry-Perot resonators. Other known resonators, such as Bragg and Photonic Crystals resonators, may be employed as well and have similar characteristics as the typical resonators.

[0187] Figs. 7A-7H show exemplary in-chip planar resonators utilizing the semiconductor structures of the present disclosure configured as described above. As noted above, the semiconductor structure, configured according to the present disclosure, can be implemented in any suitable geometry / shape. In the examples of Figs. 7A, 7C- 7E, the semiconductor structure 120 has a ring-like shape, and the devices shown in these figures have substantially planar configurations. The electronic devices of all these examples include the semiconductor structure 120 of the lateral configuration as described above (i.e., silicon device layer includes P+and N+doped regions 30 and 44 at opposite sides of the integrated Ge region 42), where the integrated Ge region is highly N+doped and / or has a tensile or compressive stress to provide predefined energy band profile.

[0188] In the electronic devices 700, 710, 720, 730 of Figs. 7A, 7C, 7D and 7E, the semiconductor structure 120 is configured as a ring resonator associated with linear waveguides. In all these structures the semiconductor structure 120 shows at least one discontinuity region DR along the ring-like structure, specifically a discontinuity in the electrode arrangement. As shown in Fig. 7A, the discontinuity is in the highly P+doped Si region 30 which is missing in at least a portion of the ring resonator 700 and in the first metal contact ECI. The discontinuous region DR of the ring-like structure of Fig. 7A is indicated by a dashed line. Thus, the device 700 includes the electrode arrangement formed by first and second metal contacts ECI and EC2 of the first electrode associated with the P+and N+doped regions 30 and 44 at opposite sides of the integrated Ge region 42 only along a portion of the ring circumference However, the integrated Ge region 42 forms a continuous ring resonator having a notch (all-pass) configuration which is commonly used as a cavity for lasing. The integrated Ge structure 42 generates light in the ring portions having the structure of the semiconductor structure 120, the emitted light propagating inside the continuous integrated Ge region 42 interferes within the ring, and lasing can occur above a threshold voltage / current. It is noted that the doping of the Ge medium in the directional coupler region may be the same or different than the doping in the resonator region.

[0189] The linear waveguide 702, aka bus, is made of Si and is located in the same plane as the resonator waveguide 120. The portion of the integrated Ge region in the discontinuity region DR is designated 704 and, as will be described below, serves as a directional coupler 703 together with the linear waveguide 702.

[0190] More specifically, interfacing portions of the Si bus 702 and the Ge region 704 of the discontinuity region DR of the resonator waveguide form an asymmetric directional coupler (DC) 703, where light can be coupled bi-directionally between the Ge portion 704 of the resonator waveguide and bus waveguide 702. By controlling the coupling strength, the properties and performances of the cavity and laser can be controlled. Such DC unit can be used to minimize back reflections and can allow transferring the light into the bus waveguide without suffering alignments and other optical losses due to the differences in materials, i.e., Si and Ge. The directional coupler 703 with a curved Ge portion 704 as shown in Fig. 7A, is typically used in combination with a ring or a racetrack shape resonator to form a cavity. If the curved Ge waveguide 704 and (Si) bus waveguide 702 are of the same sizes and refractive index, then the unit is considered a symmetric DC, otherwise, an antisymmetric DC.

[0191] Fig. 7B shows possible configurations of waveguide structures, configured as directional couplers of the ring cavity, where each directional coupler can be implemented with rib-type Si-Ge waveguide (R) e.g., 703A(R), 703B(R) (in Fig. 7A), and 703C(R), or semi-rib like (SR) Si-Ge waveguide, e.g., 703A(SR) and 703B(SR).

[0192] If the Ge and Si waveguides, 704 and 702, are close enough, optical power can be coupled from the Ge waveguide 704 (where light was generated and propagating) into the Si waveguide 702.

[0193] The directional coupler 703B(SR) (which may be also in a rib-type (R) configuration, not shown in the figure) is configured with a Si-N+region 44 and a metal contact EC2, located to the right side of the Ge waveguide 704. There is no emission from the Ge medium, or any electrical activity in the structure, as there is no close circuit (no Si-P+region exists). The N+doped region in the directional coupler is the continuation of the N+region inside in the inner ring of the resonator (which is typically in the shape of either a full circle or a thick curved section (like a ring)). If it is “cut” near the DC region like the P+curve section, it might be misaligned at the edges with the N+counterpart. Therefore, typically, the N+doped region is made as a full circle and the P+is cut near the DC unit. The same scheme is employed for a ring modulator (not laser, but a modulator) where it needs P+and N+regions as well, to make the modulation and avoid current in the DC section to reduce optical losses on the signals propagating in the bus.

[0194] The directional coupler 703C(R) (which may be also in a semi-rib configuration, not shown in the figure) is configured with a Si-P+region 30 and metal contact ECI located to the left side of the Si waveguide 702, in addition to the Si-N+region 44 and a metal contact EC2, located to the right side of the Ge waveguide 704. Emission of light may occur from the Ge medium as current can still pass in the thin bottom Si slab region. Depending on the size of the intrinsic region I needed to efficiently generate light by the Ge medium, the Si-P+region 30 may not exist to the left of the Si rib bus, but rather, may need to exist somewhere else. Since a very low coupling strength between the waveguides 704 and 702 is typically needed in most applications, the effective length of coupling required is very small, usually a few microns. Therefore, the optical loss that might be exerted on the Si rib bus due to current flowing, or presence of doped region, may be insignificant.

[0195] In the device 710 of Fig. 7C the semiconductor structure 120, configured as a ring-like resonator, is associated with two linear waveguides 702 in an Add-Drop configuration. Here, adding the additional bus allows further control on the properties of the laser and, in some cases, may relax the fabrication tolerances in order to achieve specific performances.

[0196] The device 720 of Fig. 7D includes the cascaded arrangement (serial configuration) of two ring-like resonator structures based on semiconductor structures 120, associated with a linear waveguide 702. This configuration allows to achieve mode selection in the laser performance.

[0197] The device 730 of Fig. 7E includes the semiconductor structure 120, configured as a ring-like resonator, which is associated with linear waveguides 702. In this example, the waveguide 702 includes a portion 702A made of Ge which is coupled, via a taper 702C, with a Si portion 702B. The Ge portion 702A of the waveguide 702 forms the directional coupler 703.

[0198] Thus, in this example, the ring resonator based on semiconductor structure 120 in a notch configuration interfaces a Si-Ge bus waveguide 702. The bus makes it easier to extract light being emitted within the cavity of the device 730. The DC unit can then be designed to be symmetric which makes it also easier to fabricate. The light can be then transferred to the Si bus portion 702B by a standard in-chip planar taper waveguide or structure 702C.

[0199] An efficient taper is configured to match the momentums of the modes supported in the Si-Ge portion 702A and Si portion 702B of the bus, as well as to match their mode profiles, i.e., their distributions in space. Mathematically, these matchings can be expressed as

[0200] Momentum : ntLt~Ge= ntLt

[0201] Profile: (i / ;s£-GeI isi} Esi~Ge• Esi= 1 where weis the effective index of the supported mode and E is its electric field; and T corresponds to the mode wavefunction.

[0202] If mismatch between the momentums exists, then reflection occurs (needed for a cavity). If mismatch between the profiles exist, then optical losses occur, which are to be avoided.

[0203] In the electronic devices 740, 750, and 760 of Figs. 7F, 7G, and 7H , the semiconductor structure 120 is configured as a Fabry Perot resonator.

[0204] More specifically, in the device 740 of Fig. 7F, the Fabry-Perot structure includes typical reflectors 706A (aka mirrors) implemented by two Field Matching Reflector (FMR) units. The FMR unit can be a planar taper, coupler or other types of in-chip planar structure. An efficient FMR unit is configured to match the profiles of the modes but not their momenta, thus acting as a reflector without optical losses. The difference, R, in momentums defines the reflection strength. By designing this difference, the reflection can be controlled, as well as the properties and performances of the cavity and laser. Mathematically, these conditions can be expressed as:

[0205] Momentum:

[0206] Profile: (i / ;s£-GeI isi} fmEsi~Ge• Esi= 1

[0207] In the device 750 of Fig. 7G, the Fabry-Perot structure includes two reflectors 706B implemented by planar in-chip corrugation waveguide units. A corrugation waveguide can act as a planar Bragg grating which allows to control the reflection of the light according to the number and shape of the corrugation. The optical losses of such units can be designed to be very small.

[0208] In the device 760 of Fig. 7H, the Fabry-Perot structure includes two reflectors 706C implemented by a material stack (in the figure, only one layer is shown, made of oxide), e.g. Bragg mirror or Fabry -Perot. The stack results in a predefined light reflection strength, thus shaping the properties and performances of the cavity and laser.

[0209] As described above, the light generated by the Ge medium in the integrated Ge region 42, excites a propagating mode (or several modes) in the Ge waveguide-like medium. The light is then guided in the integrated Ge region 42 as in a waveguide layer. As described further below, the electric device 100 may be configured to operate as a photodetector as well. The advantage of the Ge waveguide emitter, or detector, being at the same planar level as the Si bus on the SOI, is the ability to fully couple the emitted light to the Si bus (or the input signal light to be detected into the Ge waveguide) without optical losses. This is demonstrated in Figs. 8A and 8B.

[0210] Fig. 8A shows a known in the art vertical design in which the light source is located above the Si bus and needs to be coupled to Si bus located at a different height in the SOI platform.

[0211] Fig. 8B shows the electronic device 100 of the present disclosure, which includes the semiconductor structure 120 of the present disclosure (of the lateral configuration in this example) allowing to couple all optical power available by the lasing cavity into the Si bus without losses. Since the emitted light is coupled directly to the Si bus and the planar couplers used in the device can be fully controlled, back reflections from these couplers to the laser cavity can be avoided or diminished to insignificant levels. This yields a monolithic integration of Si-Ge light sources and detectors into the SOI platform within Silicon Photonics architecture.

[0212] Figs. 9A and 9B show schematically an exemplary Wavelength Division Multiplexing (WDM) transmitter, that includes the in-chip Si-Ge light sources and TEC of the present disclosure (see for example the example of Fig. 5B described above), with the expected power consumptions of the various components indicated on the figures.

[0213] Fig. 9 A shows a WDM array with N units wherein each unit is a light source with direct modulation according to the teachings of the present disclosure (e.g., electronic device 100), with all structures and units built-in on the same chip. The WDM array is an example of a practical implementation of the Si-Ge heterostructure of the present disclosure serving as a laser / LED in the silicon photonics platform.

[0214] In the example of Fig. 9B, the electronic device 100 of the present disclosure is being TEC -like controlled by sensing the heat the electronic device 100 generates (on- chip temperature sensors) and compensating (or regulating) that heat via the second electrode, together with, integrated electrical circuits (TEC electrical circuits on the righthand side).

[0215] Except for the electronic device 100, all other components and circuits are available today in fab’s PDK (Process Design Kit). However, the known vertical Si-Ge devices, or other hybrid integration of other solutions (e.g. InP over silicon), cannot enjoy this monolithic integration of the Si in-chip TEC platform circuits. In the lateral-type implementation of Si-Ge technology of the present disclosure, a Peltier may not be required since the heater / cooler can be placed directly over the waveguide region, i.e. at the second electrode location (see Fig. 5B). However, for hybrid light sources solutions, such as an InP laser on top of a Si layer, a Peltier is needed and is either included in the InP unit or aside the Si layer (usually beneath the chip). The modulation can be direct (e.g., via a ring laser / LED) or by an external circuit adjacent to it (e.g. a silicon photonics ring-based or MZI modulator). The specific configuration shown in Fig. 9A is also suitable for receiver applications such as frequency lock-in amplifier and photodetectors array.

[0216] Since the electronic device 100 of the present disclosure can serve as both an optical emitter and an optical detector (detector implementation is described further below), it is possible to set the voltage applied to the device around the lasing threshold voltage to amplify external light coupled to the Ge waveguide (forming the integrated Ge region 42). The amplification can be realized in the wavelength ranges of the Ge and Si- Ge interface bandgaps.

[0217] Fig. 10 exemplifies an electronic device 100 with the semiconductor structure 120 of the present disclosure (having lateral configuration in this example) configured and operable as an optical amplifier. This is achieved by setting a voltage +V around a lasing threshold voltage, applied to the semiconductor structure 120 via the electrical contacts ECI and EC2, thereby amplifying external light being coupled to the integrated N+doped Ge region 42.

[0218] It should be noted that integrating hybrid solutions, such as InP optical amplifier, on a SOI and Si-based platforms is very difficult since the hybrid unit needs to be aligned perfectly to both the input and output Si bus waveguides. However, with the Si-Ge lateraltype (planar) structure of the present disclosure, the integration is seamless due to planar couplers (not shown in Fig. 10) that can have insignificant losses, if any.

[0219] As described above with respect to the general device structure of Fig. 3A including the second electrode, such device can be configured and operable as an optical amplifier as well. The second electrode implemented through the third electric contact EC3 may serve to change the carrier concentration inside the integrated N+Ge region 42 for the purpose of increasing the concentration of holes or electrons, thereby amplifying optical power passing through the semiconductor structure 120. Additionally, any one of the electronic devices 100 exemplified in Figs. 6A to 6D may be configured and operable as an optical amplifier.

[0220] Fig. 11 exemplifies an electronic device, denoted 100A, configured and operable as an electro-absorption modulator, coupled to another electronic device 100B configured and operable as light emitter. The electronic devices 100A and 100B include the semiconductor structures 120 of the lateral configuration configured generally similar to that of Fig. 2A described above. However, it should be noted that any one of the semiconductor structure configurations described in Figs. 3, 4A-4B, and 6A-6D, with an appropriate configuration of the energy band profile (by highly doping the integrated Ge region and / or applying induced stress (tensile and / or compression stress) on the integrated Ge region) may also be configured and operable as an electro-absorption modulator.

[0221] For the application of modulators, the absorption coefficient for Ge around wavelengths of 1,550 nm is very large, consequently, the interaction length required for the same extinction ratio (ER) of the light amplitude is smaller for a Ge amplitude modulator than for the same Si phase modulator in, e.g., a MZI configuration.

[0222] Phase modulators and other type of modulation devices can also be realized using the semiconductor structures of the present disclosure of lateral or semi-lateral configurations as described above. Therefore, it is possible to realize different active components such as an electro / thermo-optical switch, tunable filter, phase shifter, etc.

[0223] Fig. 12 exemplifies an electronic device 100 of the present disclosure including the semiconductor structure 120 of the lateral configuration wherein the integrated Ge region 42 is configured as a highly doped N+Ge region, and wherein electric contacts of an electrode arrangement are provided comprising the first and second contacts ECI and EC2 of the first electrode being associated with the first highly doped P+region 30 and the N+region 44 of the second region 40. The integrated Ge region 42 may also be stressed (tensile or compressive stress) thereby affecting its energy band gap. The semiconductor structure 120 is configured such that the integrated Ge region 42 is fully embedded in the silicon device layer 10 and is operable as a channel waveguide for propagating light being confined within the integrated Ge region.

[0224] The channel waveguide configuration of Fig. 12 may be obtained if during the integration of the Ge region 42 within the Si trench (within the silicon device layer 10), the Ge region does not cover, in terms of thickness, the whole Si trench. Rather, the Ge region 42 fills the trench up to a certain thickness. Then, a Si layer 10A, or a layer of other type of material, or a structured layer, may be integrated on top of the Ge region 42 up to the thickness of the Si device layer 10. The added (top) layer (10A) may itself be comprised of several sub-layers.

[0225] It should be noted that the configuration of a channel waveguide may be implemented in any one of the semiconductor structure configurations described in Figs. 3A-3B, 4A-4B, 5A-5C, and 6A-6D. In the embodiments including a second electrode (Figs. 3A-3B, 4A-4B, 5A-5C) such configuration can make it easier to integrate the second electrode that requires medium (a single layer, a stack or a photonic structure) which can support the flowing of free charges to create an additional electro-optical effect.

[0226] The Si layer 10A above the Ge region 42 may provide various advantages such as forming a uniform stress of the Ge region. Additional advantages may include uniform and symmetric structuring of the Ge medium within the Si layer, and uniform and symmetric flow of current through, or from, the Ge medium upon applied voltage to create the EO effect needed in any of the configurations described in the present disclosure.

[0227] Furthermore, the configuration of a channel waveguide may also serve as an optical active component in architectures of multi-layer circuits or 3D circuits. The top layer 10A can shield the Ge medium from direct contact of the second circuit’s layer that may come above it, but at the same time, keep a uniform Si thickness layer without height mismatch at the Ge region.

[0228] Fig. 13 exemplifies the electronic device 100 of the present disclosure configured and operable as a photodetector. The semiconductor structure 120 of this device is based on the general structure shown in Fig. 2A. The integrated Ge region 42 is configured as an undoped region or a relatively lightly doped N region, as compared to the highly doped N+region 44 spaced from the integrated Ge region 42 by the second intrinsic region 12.

[0229] By avoiding or reducing the doping in the Ge region 42 inside the trench, the Ge region tends to be more intrinsic, similar in carrier properties to those in the (lightly doped) intrinsic regions II and 12 of the Si device layer 10. When the voltage is set to negative voltage (i.e., reverse biasing a PIN diode), the electronic device of Fig. 13 can convert light into current and thus function as a fully lateral, built inside the chip, optoelectrical converter device (photodetector). As noted above with reference to Fig. 2B, describing the configuration of the semiconductor structure 120 as a light emitter, here as well, the electric field under reverse bias can be stronger for a lesser applied voltage compared to the same Si PIN diode without the Ge medium (the Ge has to be slightly doped). Thus, not only that the power consumption can be reduced, but also the responsivity can be larger compared with other typical configurations (e.g. configurations such as placing the Ge on top of the silicon layer or with common vertical designs of a detector).

[0230] During operation of the photodetector, light that is coupled into the Ge waveguide (i.e., the integrated Ge region 42) with wavelengths in Ge and Si-Ge interface bandgaps can be converted to free charged carriers (holes and electrons) and, consequently, to current flowing through the electric contacts ECI and EC2.

[0231] In addition, the light signal entering the Ge waveguide in order to be detected does not suffer from losses by the highly doped Si regions (e.g., regions 30 and / or 44) and the electric (metal) contacts ECI and EC2. Therefore, the responsivity of photodetection, as well as the signal to noise (SNR) ratio can be larger than those of typical reported devices.

[0232] Furthermore, any lateral misalignment between the Si bus waveguide and the photodetector structure waveguide (Ge in trench) (e.g., semiconductor structure 120 of Fig. 13) due to fabrication deviations does not inflict losses resulting from the interaction of the light signal with one of the highly doped Si regions, due to the presence of the Si intrinsic region(s) (e.g., Il and 12).

[0233] Lastly, due to the existence of the Si intrinsic region(s) and integrated Ge region in the silicon device layer, the photodetector of Fig. 13 can support optical signals with a larger wavelength bandwidth (multiple channels) and a larger number of wavelength- guided modes (multi-modes). As mentioned above, the reason is that an optical signal with a longer wavelength or in a higher order mode, has a longer evanescent (tail) field, and the Si intrinsic region(s) can distance and “defend” the signal from being absorbed (e.g., by free carrier absorption) in the highly doped Si regions and electric (metal) contacts. Therefore, the same photodetector can be located on a multi -channel / mode bus for various kinds of optical signal detection (different wavelength, polarization, and propagating mode), all without optical losses and with equal detection efficiency.

[0234] In the following, the advantages of the electronic device utilizing the planar / lateral-type design of the semiconductor structure of the present disclosure are presented and analyzed (termed “Planar Device Schema” in Tables 2-6 below) by comparing it with known in the art vertical and / or semi -vertical designs (termed “Vertical Device Schema” in Tables 2-6 below). Specifically, the placement of the lateral-type semiconductor structures of the present disclosure in-plane with the Si bus has significant advantages. As described above, the term “lateral P+IN+IN+Si-Ge device” used with respect to the electronic device 100 of the present disclosure is meant to highlight the fully planar / lateral -type mutual placement of the integrated Ge region 42 with respect to the respective highly doped P+(Si) region 30 and the highly doped (Si) N+region 44.

[0235] Table 2 compares fabrication aspects of the planar and vertical devices. The advantage of the lateral device of the present disclosure is emphasized because it is integrated natively to the SOI platform which is adopted in today’s industry for integrated optics in Silicon Photonics. Being CMOS compatible in terms of fabrication and design, this structure is fabricated during, and within, the fabrication sequence of the optical filters, modulators, waveguides, detectors and other components of the integrated photonics that comprises single or large-scale photonic integrated circuits in Silicon Photonics.

[0236] Table 2

[0237] Table 3 compares the gain aspects of the planar and vertical devices. An important and significant advantage of the planar device is that the Si-Ge interface area is larger for the lateral (planar) device rather than for the vertical one. Because the interface is also doped and more relaxed in terms of stress, the emitted wavelengths are blue-shifted and lean towards the 1,500 nm. The integrated Ge region emits around the 1,600 nm because the stress (if exists) red-shifts the emission (for tensile strain). Thus, larger active interface length may provide larger power emission at shorter wavelengths, which may be required for various applications. Table 3

[0238] As mentioned in Table 3, controlling the stress of the integrated Ge region provides the ability to modify and shape the energy band gaps, and consequently, to modify properties of the emission (e.g., wavelength). In the lateral schema of the present disclosure, it is possible to externally control the stress on the Ge region via the clad and Ge interface (see, for example, Fig. 5C and description above). In some embodiments, a stress inducing layer, such as Silicon Nitride (SisNQ, can replace the cladding layer of Silicon Dioxide (SiCh) which induces a lesser stress, or a stress- inducing electrode can be placed to dynamically control the stress of the Ge region as described above. A controlled stress of the Ge region can be induced via various (epitaxial) growth techniques, e.g., 2-step growth with different temperatures causing thermal mismatch may induce 0.2-0.3% biaxial strain. For example, epitaxial growth techniques with a stressor cap are known to cause biaxial tensile strain up to 1-1.5%.

[0239] Table 4 compares the loss aspects of the planar and vertical devices. One of the main reasons that the currently reported and demonstrated devices in Si-Ge emitters have not been commercialized so far is that they all reported that active losses due to operation were too high and thus the emitted power was very inefficient. These losses were compared with the total electrical power applied on the circuit and compared to light emitters on-chip in other common platforms such as InP on SOI.

[0240] The main causes for losses in vertical device architectures are due to the electric (metal) contacts and the highly doped regions being in close proximity with the Ge waveguide where the light generates and propagates in. Table 4

[0241] The lateral-type architecture of the electronic devices of the present disclosure reduces these losses dramatically because of the following: (i) the metals plugs and contacts are distanced from the Ge waveguide (e.g., through the predetermined lengths Si and S2 of the respective intrinsic regions II and 12, as well as through and Di and D2) and are placed at different height levels with respect to the integrated Ge region 42, which provides additional distance; and (ii) the highly doped regions of the P+(in particular) and N+are distanced from the Ge waveguide (e.g., through the predetermined lengths Si and S2 of the respective intrinsic regions II and 12).

[0242] As a result, the losses induced on the generated light are caused mainly by the highly doped N+dopants in the Ge medium and the carriers that enter the Ge medium during applied voltage. The carriers’ concentration is estimated to be on a scale of 1018cm'3which is smaller by more than one order of magnitude from the concentration of 7.6* 1019cm'3of N+doped electrons in the Ge medium. The analysis of the inventors showed that a semiconductor structure according to the principles of the present disclosure can reach the performance of other typical platforms for light emission in integrated optics, such as InP platform.

[0243] One of the advantages of the planar / lateral-type architecture of the present disclosure lies in the fact that the equal height between the Ge waveguide and the Si bus, provides the ability to couple the light to the Si bus with minimal losses if any. This is in contrast to known vertical architectures where non-equal height between the Ge waveguide and the Si bus impedes an efficient coupling of the light to the remaining circuits. If the cavity for a laser device is a ring resonator, for example, an anti-symmetric directional coupler can couple 100% of the emitted light into the Si bus without any losses using the planar device of the present disclosure. Such configuration may completely prevent, or at least highly reduce, back reflection to the laser cavity (resonator) due to the coupler unit.

[0244] Table 5 compares light emission aspects of the planar and vertical devices.

[0245] Table 5

[0246] By contrast, in known vertical designs, in particular for photodetectors, where the Ge waveguide is placed above the Si bus, the Si-Ge waveguide is typically a 4 layers structure, which means that the light is coupled between the Ge and Si layers as it propagates in the waveguide. This behavior makes it very hard to couple all the light to the Si bus waveguide when the Ge waveguide structure ends. Note that the Si bus waveguide is not on the same height (or plane) as the Ge waveguide due to the nature of the design (actually, the Ge waveguide is higher than the Si bus). A schematic overview of these differences was discussed in detail above with reference to Figs. 8A and 8B.

[0247] Table 6 compares electrical / thermal aspects of the planar and vertical devices.

[0248] Table 6

[0249] The ability to add an additional (e.g., second) embedded electrode (see for example Figs. 3A-3B, 4A-4C, and 5A-5C) or system that has a direct proximity to the active region, i.e., the integrated Ge region and waveguide, is a decisive advantage. This electrode can provide the capabilities for a diversity of significant usages which the vertical device is lacking. Some of the usages for such an electrode have been described above: direct modulation, wavelength tunability, optical band tunability, increased emitted power, direct TEC and cooling, and a general calibration electrode.

[0250] In the following, the fabrication aspects of the lateral-type architecture and technology related to the electronic devices of the present disclosure are described.

[0251] In general, the various embodiments of the electronic devices of the present disclosure including integrated Ge within the silicon P+IN+IN+(lateral configuration) structures or the P+IN+(semi-lateral configuration) sub-structures, can be manufactured within the standards, but not only, of CMOS technology using traditional fabrication facilities. The SOI substrate can be easily obtained by companies manufacturing such wafers and exist today around the world. The layers thickness of the native oxide 20 and Si device layer 10 may vary according to the applications the devices are used for. Si- based substrates are used extensively in today’s market and can be obtained from the industry worldwide.

[0252] The Si-P+and Si-N+regions (30 and 44, respectively) are heavily doped regions in the Si device layer 10 that have doping concentration in the typical range of 1019- 1020cm'3. Doping the Si device layer can be achieved by standard doping processes and techniques such as: Ion implantation, and Spin on Dopant / Spin on Glass.

[0253] Etching the trench in the Si device layer for the Ge integration can be performed by standard etching processes such as: Dry etch (e.g., RTE, deep RIE, ICP RIE), and Wet etch (e.g., selective wet etchant solutions for silicon medium). The integration of a Ge layer into the Si trench can be obtained by various known techniques such as growths and depositions.

[0254] Growths techniques may include any of the following: Chemical Vapor Deposition (CVD) and sub-families’ methods, Ultrahigh Vacuum CVD (UHV-CVD), Metal Organic CVD (MOCVD), Low Pressure CVD (LPCVD), Rapid Thermal CVD (RTCVD), Reduced Pressure CVD (RPCVD). Additional growths techniques may include Molecular Beam Epitaxy (MBE), and Atomic Layer Deposition (ALD).

[0255] Deposition techniques may include: Sputter deposition. Physical Vapor Deposition (PVD), Thermal evaporation (PVD), Electron Beam (E-Beam) evaporation (PVD), Pulse laser deposition, and Vapor Liquid Solid (VLS) deposition.

[0256] Etching the Ge material after its deposition at places it should be removed can be achieved by standard processes such as any of the following: Dry etch (e.g., RIE, deep RIE, ICP RIE), Wet etch (e.g., selective wet etchant solutions for germanium medium), Chemical Mechanical Planarization (CMP), grinding machine for semiconductors, Ion milling, and Laser milling.

[0257] The Ge-N+region, i.e., the heavily doped Ge medium in region 42, that is integrated into the Si trench in the silicon device layer 10, may have doping concentration in the range of 1019- 1020cm'3. Doping the Ge region 42, which is required in some of the embodiments described above, can be achieved by standard doping processes and techniques such as any of the following: Spin on Dopant / Spin on Glass, In-situ doping (e.g. via CVD or MBE layer growth), and Ion implantation.

[0258] The annealing (thermal treatment), of the Ge region after its deposition, and the annealing of the Si layer after the trench was created, can be performed using any of the following: Rapid Thermal Annealing (RTP), conventional furnaces or machines with internal heating capabilities, and In-situ (e.g. during the CVD or MBE process).

[0259] The clad layer 60 that covers the top of the sample (in some of the embodiments) before or after completing the Ge region creation stage can be achieved by standard deposition processes and techniques such as any of the following: Plasma Enhanced CVD (PECVD), CVD, Sputter deposition, and ALD.

[0260] The metal contacts that are required to allow applying voltage to the semiconductor structures of the present disclosure may be obtained by regular metal contacts in silicon CMOS technology. All of the methods, processes and techniques described so far exist in traditional fabrication facilities. Whether small-size facilities such as those in academic institutes that have the capabilities of fabricating a few prototype units, and up to large-size facilities such as those in the industry, that have the capabilities for a mass production of units.

[0261] Germanium (Ge) can be found today in CMOS foundries as it is commonly used in microelectronic transistors. The formation of a Ge layer into silicon already exists in facilities that support photonics, as in-chip Si-Ge detectors have become widely available.

[0262] The electronic device of the present disclosure can be optimized via the design (architecture), parameters and fabrication process. For the design and parameters optimization, the variations of the following parameters can be considered, for the configurations of e.g., Fig. 2A or Fig. 6A: D [nm] (or Di [nm] and D2 [nm]) being the distance between the edge of the metal plug / contact and the edge of the respective highly doped region in the Si layer; S [nm] (or S1 / S2, where Si=S2=S or Si^Si) being the spaces between the highly doped regions in the Si layer and the integrated Ge region; W [nm] being the width of the integrated Ge region; H [nm] being the height of the integrated Ge region; L [pm] being the length of the structure; Nce+being the doping concentration of electrons in the integrated Ge medium; and the second electrode’s parameters (if exist).

[0263] Figs. 14A to 14D show in a self-explanatory manner variation of the above parameters in the device configuration similar to that of Fig. 2A. Fig. 14A exemplifies variations in the lengths Si [nm] and S2 [nm] of the intrinsic regions II and 12 between the integrated Ge region 42 and the highly doped regions 30 and 44 in the Si device layer 10. As shown in the figure, the configuration can be such that these lengths are practically zero. Fig. 14B exemplifies variations in the distances Di [nm] and D2 [nm] between the edge of the metal contacts ECI and EC2 and the edge of the highly doped regions 30 and 44 in the Si layer 10. Fig. 14C exemplifies variations in the width W [nm] of the integrated Ge region 42. Fig. 14D exemplifies variations in the height H [nm] of the integrated Ge region 42.

[0264] Fabricating a PIN diode with a highly doped Ge region within the intrinsic region of the diode in a silicon device layer is a complicated fabrication process. To prove fabrication feasibility of such devices using CMOS technology and its compatibility with the technology of the electronic devices of the present disclosure, the inventor fabricated a lateral semiconductor structure 120 of the lateral configuration similar to that of Fig. 2A, using standard fabrication facilities under CMOS technology standards. The fabrication was carried on a SOI substrate with typical layers’ properties used in Silicon Photonics. The resulting P+IN+IN+Si-Ge structure is illustrated in Fig. 15. As can be seen from the results presented, it is possible to fabricate the Ge region in the middle of the intrinsic region within the silicon PIN diode. In the figure, the spacings S [nm] (the spacings between the highly doped P+and highly doped N+regions 30 and 44 in the Si device layer 10 and the integrated Ge region 42), is about 4 pm, the width W [nm] of the integrated Ge region 42 is about 2 pm and the height H [nm] of the integrated Ge region 42 is about 180 nm. A high-quality epitaxial Ge region 42 fills the corresponding trench made within the Si device layer 10 with small surface roughness. The clad 60 (covering the Si layer 10 from the top) is SiCh.

[0265] In the fabricated device / structure shown in Fig. 15, there are no defects, or cracks in the layers, or degradation in layers’ quality or unintentional stress in the material that could be observed or recorded in the final version of the fabrication process of the device. Therefore, the process can be considered stable and reproducible in standard CMOS foundries.

[0266] The successful planar integration of the Ge region into the Si device layer within the SOI substrate, along with the highly doped regions at opposite sides thereof (spaced by intrinsic regions of the Si device layer), proves that the technology to fabricate the devices of the present disclosure can be classified as CMOS compatible and feasible to fabricate at mass production. The electronic devices of the present disclosure can thus serve as a practical light source and a light detector component in Silicon Photonics architecture.

[0267] The present disclosure in its another aspect provides a novel electronic device configured and operable as waveguide. Such electronic device includes a silicon device layer on an insulator, and an integrated Ge region at least partially embedded within a portion of the silicon device layer being enclosed between first and second intrinsic regions of the silicon device layer forming a heterostructure Si-Ge waveguide. This is exemplified in Fig. 16.

[0268] Fig. 16 shows an electronic device 200 including a silicon device layer 10 on an insulator 20, and an integrated Ge region 42 at least partially embedded within a portion of the silicon device layer 10. The integrated Ge region 42 is enclosed between first and second intrinsic regions II and 12 of the silicon device layer 10. The electronic device 200 of Fig. 16 may serve as a passive waveguide (through which light propagates in direction d) that supports light propagation similar to a Si bus. In this case, the bus is a heterostructure Si-Ge waveguide.

[0269] In some cases, it may be preferred to continue propagating the emitted light within a Si-Ge bus for further processing. The bus can also form passive components such as an optical coupler unit, e.g. Y-coupler and directional coupler, a resonator filter, and any other component which can be realized monolithically in-chip structure within integrated photonics. The Si-Ge waveguide of the present disclosure can be equal in size to the optical emitter’s waveguide in the P+IN+IN+structure of any one of the structures described above. Therefore, coupling of the emitted light to the Si-Ge bus waveguide is easily achievable.

[0270] In is further aspect the present disclosure provides the semiconductor structure of the generally lateral-type configuration, which may be lateral or semi-lateral configuration as described above, in which the integrated Ge-region is at least partially embedded in the silicon device layer such that at least a bottom surface of the integrated Ge-region forms an interface with an intrinsic region of the silicon device layer. This is illustrated in Fig. 17. In the example of Fig. 17, the semi-lateral configuration is shown, but it should be understood that the same principles can be implemented in the lateral configuration as well.

[0271] As shown in the figure, the semiconductor structure 120 includes a silicon device layer 10 located on top of an insulator (SOI) 20. The insulator 20 is a buried oxide layer which may typically include Silicon Dioxide (SO2) but may also include Silicon Nitride ( Sis N4, SiNx). Other type of insulators or dielectric mediums, such as Indium Tin Oxide (ITO), Silicon Oxynitride (SiON), Silicon Carbide (SiC), Tantalum Pentoxide (Ta2Os), Titanium Dioxide (TiO2), Zinc Oxide (ZnO), and Niobium Pentoxide (bt^Os) may be included as well. The silicon device layer 10 includes a first highly doped P+silicon region 30 and a second highly doped N+region 40, which is spaced from the first highly doped P+silicon region 30 by a first intrinsic region II of the silicon device layer 10. The second highly doped N+region 40 includes an integrated Ge-region 42 which is at least partially embedded in the silicon device layer 10 such that at least a bottom surface BS of the integrated Ge-region 42 forms an interface with an intrinsic region of the silicon device layer 10, i.e., is spaced from the insulator layer 20 by a portion of the silicon device layer 10. The portion of the silicon device layer can serve as a more preferred “seed” layer for Ge growth with respect to the orientation of crystal direction, compared to the orientation growth of the Ge on the Si trench’s sidewalls that might dominate in case no Si portion is left underneath the Ge.

[0272] Furthermore, for applications requiring shorter wavelengths operation (emission / detection), the interface length is increased with the Si portion existing (in total: left and right sidewalls + the bottom width) which results in an increased gain for shorter wavelength.

[0273] In some embodiments, the semiconductor structure 120 further includes a clad 60 on top of the silicon device layer 10.

[0274] It should be noted, although not specifically shown here, that the electronic device utilizing the above-described semiconductor structure of Fig. 17 also includes electric contacts of an electrode arrangement.

[0275] As described above, in semi-latera; configuration, the integrated Ge region 42 by itself forms the second highly doped N+region 40. Accordingly, the electric contacts are associated with the first highly P+doped region 30 and the integrated Ge region 42 presenting the second highly N+doped region 40. In the lateral configuration (although not shown in the figure), the second highly doped N+region 40 is formed by the integrated Ge region 42 and a highly N+doped region (44) spaced from the integrated Ge region 42 by a second intrinsic region (12) of the silicon device layer 10. In the lateral configuration, the integrated Ge region may be substantially undoped, or a relatively lightly N-doped region (as compared to that of region 44), or highly N+doped. In the lateral configuration, the electric contacts are associated with the regions 30 and 44 and in some examples also with the Ge region 42, as described and exemplified above.

[0276] The present invention, in its yet further provides a novel electronic device utilizing a vertical architecture / configuration of a semiconductor structure. In such device, the semiconductor structure includes a silicon P+layer, and a clad on top of the silicon P+layer, where the clad includes an integrated N+doped Ge region directly interfacing with a surface region of the silicon P+layer. The device also includes an electrode formed by an electrical contacts arrangement, where at least one first contact is associated with the silicon P+layer and at least one second contact is associated with the integrated N+doped Ge region.

[0277] As noted above, the lateral-type (planar) configuration of the semiconductor structure of any of Figs. 16 and 17 may also be implemented in any suitable geometry, e.g., closed loop structure such as ring-like structure. This depends inter alia on the specific application of the electronic device.

[0278] In the following, various examples of such electronic devices using Si-Ge heterostructures of the present disclosure are described, based on enhanced architectures of vertical designs.

[0279] Figs. 18A to 18F show schematically general structures of electronic devices, generally designated 400, utilizing the vertical Si-Ge semiconductor structure, generally designated 140, in Si platform according to the present disclosure. To facilitate understanding, the same reference numbers are used to indicate the functionally similar elements in all these examples.

[0280] Fig. 18A shows an electronic device 400 including a semiconductor structure 140 which includes a silicon P+layer 430, and a clad 60 on top of the silicon P+layer 430. The clad 60 includes an integrated N+doped Ge region 142 directly interfacing with a surface region of the silicon P+layer 430. The device 400 also includes electrical contacts arrangement at least partially embedded in the clad 60 and including at least one first contact ECI of a first electrode associated with the silicon P+layer 430 and extending along a bottom surface of the silicon P+layer 430, and at least one second contact EC2 of a second electrode associated with the integrated N+doped Ge region 142. In the nonlimiting example shown in Fig. 18A the second contact EC2 is split into two spaced-apart contacts EC2A and EC2B aligned with opposite edge portions, respectively, of the Ge region 142.

[0281] Fig. 18B shows device 400 generally similar to that of Fig. 18A but in which the semiconductor structure 140 further includes a P+doped region 70A or a N+doped region 70B above the integrated N+doped Ge region 142, thereby forming with the integrated N+doped Ge region 142 a P+N+diode or P+N+N+junction. The electrical contacts arrangement includes the first contact ECI of the first electrode extending along a bottom surface of the silicon P+layer 430. The second contact of the second electrode includes a pair of the second spaced-apart contacts EC2A and EC2B contacting a pair of spaced- apart top surface regions of the P+doped region 70A or the N+doped region 70B.

[0282] The splitting of the top metal electrode into two segments located at the edges of the Ge region 142, in the configurations of Figs. 18A and 18B reduces the optical losses the light will suffer due to proximity of the metal contacts. It is also the main difference between these configurations and known vertical design of emitters. Fig. 18C exemplifies electronic device 400 generally similar to that of Fig. 18A but in which the electrical contacts arrangement includes a pair of the first spaced-apart contacts ECIA and EC1B of the first electrode interfacing / contacting a first pair of spaced-apart surface regions, respectively, of the silicon P+layer 430 at opposite sides of the integrated N+doped Ge region 142 at certain distances therefrom. The second contact of the second electrode EC2 is interfacing / contacting a top surface of the integrated N+doped Ge region 142.

[0283] Fig. 18D exemplifies a generally similar electronic device 400 but in which the semiconductor structure 140 further includes a P+doped region 70A or a N+doped region 70B above the integrated N+doped Ge region 42, thereby forming with the integrated N+doped Ge region 142 a P+N+P+diode or P+N+N+junction. The electrical contacts arrangement includes a pair of the first spaced-apart contacts ECIA and EC1B of the first electrode interfacing / contacting a first pair of spaced-apart surface regions, respectively, of the silicon P+layer 430 at opposite sides of the integrated N+doped Ge region 142 at certain distances therefrom, and the second contact ECI of the second electrode interfacing / contacting a top surface of the P+doped region 70A or the N+region 70B

[0284] In the configurations of Figs. 18C and 18D, the plug and contact metal electrodes design is all planar. The bottom electrode is placed aside the Ge waveguide area, thus reducing the overall resistance due to shorter current path.

[0285] Fig. 18E exemplifies electronic device 400 generally similar to that of Fig. 18D but in which the second contact of the second electrode includes a second pair of the second spaced-apart contacts EC2A and EC2B interfacing / contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region 142.

[0286] Fig. 18F exemplifies electronic device 400 generally similar to Fig. 18E but in which the semiconductor structure 140 further includes a P+doped region 70A or a N+doped region 70B on top of the integrated N+doped Ge region, thereby forming with the integrated N+doped Ge region 42 aP+N+P+diode or P+N+N+junction. The second contact of the second electrode includes a second pair of the second spaced-apart contacts EC2A and EC2B interfacing / contacting a second pair of spaced-apart top surface regions of the P+doped region 70A or the N+doped region 70B. In the configurations of Figs. 18E and 18F, the metal electrodes design is all planar. In addition, the electrode on top of the Ge waveguide is split and set at the edges to reduce the optical losses.

[0287] Reference is made to Figs. 19A to 19H showing various configurations of electronic device, generally designated 500, with a semi-vertical Si-Ge semiconductors structure, generally designated 150, according to some other embodiments of the present disclosure. To facilitate understanding, the same reference numbers are used to indicate the functionally similar elements in all these examples.

[0288] Fig. 19A exemplifies electronic device 500 including a semiconductor structure 150 including a silicon P+layer 530, and a clad 60 on top of the silicon P+layer 530. The silicon P+layer 530 includes an integrated N+doped Ge region 242 embedded in the silicon P+layer 530. The semiconductor structure 150 also includes electrical contacts arrangement including at least one first contact ECI of a first electrode associated with the silicon P+layer 530 and at least one second contact EC2 of a second electrode associated with the integrated N+doped Ge region 242. In the non-limiting example shown in Fig. 19A, the first contact ECI of a first electrode is interfacing / contacting a bottom surface of the silicon P+layer 530.

[0289] Fig. 19B exemplifies a generally similar electronic device 500 but in which the semiconductor structure 150 further includes either one of a P+region 70A or a N+region 70B on top of the integrated N+doped Ge region 242, thereby forming with the integrated N+doped Ge region 242 either one of a P+N+diode or P+N+N+junction. The second contact EC2 of the second electrode interfaces / contacts a top surface of either one of P+region 70 A or the N+region 70B.

[0290] In the configurations of Figs. 19A and 19B, the Ge waveguide is placed in the highly doped Si bulk 530, consequently, increasing the perimeter size of the Si-Ge interface and enabling placing the Ge region / waveguide at the same height as the Si bus. It should be noted that the Si bus might need to be on another chip, since creating a Si bus on a highly doped bulk Si might result in an increased optical loss of the light propagating in this bus.

[0291] Fig. 19C exemplifies electronic device 500 generally similar to that of Fig. 19A but in which the electrical contacts arrangement includes a pair of the first spaced-apart contacts ECIA and EC1B of the first electrode at least partially embedded in the clad 60 and interfacing / contacting a first pair of spaced-apart surface regions, respectively, of the silicon P+layer 530 at opposite sides of the integrated N+doped Ge region 242 at certain distances therefrom. The second contact EC2 of the second electrode is at least partially embedded in the clad 60 and interfaces / contacts a top surface of the integrated N+ doped Ge region 242.

[0292] Fig. 19D shows electronic device 500 generally similar to that of Fig. 19C but in which the semiconductor structure 150 further includes either one of a P+region 70A or a N+region 70B on top of the integrated N+ doped Ge region 242, thereby forming with the integrated N+doped Ge region 242 either one of a P+N+diode or P+N+N+junction. The second contact EC2 of the second electrode interfaces / contacts a top surface of either one of the P+region 70 A or the N+region 70B.

[0293] In the configurations of Figs. 19C and 19D, the plug and contact metal electrodes design are all planar. The bottom electrode is now placed aside the Ge waveguide area, thus reducing the overall resistance due to shorter current path.

[0294] Fig. 19E exemplifies electronic device 500 generally similar to that of Fig. 19A but in which the electrical contacts arrangement includes the first contact ECI of the first electrode extending along a bottom surface of the silicon P+layer 530 and the second contact of the second electrode includes a second pair of the second spaced-apart contacts EC2A and EC2B interfacing / contacting a second pair of spaced-apart top surface regions of the integrated N+ doped Ge region 242.

[0295] Fig. 19F shows an electronic device 500 generally similar to that of Fig. 19E but in which the semiconductor structure 150 further includes a pair of spaced apart doped regions 70A and 70B embedded in the clad 60 and interfacing with a pair of spaced-apart top regions of the integrated N+doped Ge region 242, each of said pair of the doped regions being configured as a P+region 70A or as a N+region 70B, thereby forming with the integrated N+doped Ge region 242 a pair of P+N+diodes or a pair of P+N+N+junctions. The electrical contacts’ arrangement includes the first contact ECI of the first electrode extending along a bottom surface of the silicon P+layer 530. The second contact of the second electrode includes a second pair of the second spaced-apart contacts, EC2A and EC2B, contacting the pair of the spaced-apart doped regions, 70A and 70B.

[0296] In the configurations of Figs. 19E and 19F, the top metal electrode is split into two segments located at the edges of the Ge medium, thus reducing the optical losses the light will suffer due to proximity to the metal contacts. Fig. 19G shows an electronic device 500 generally similar to Fig. 19E but in which the electrical contacts arrangement includes a first pair of the first spaced-apart contacts ECIA and EC1B of the first electrode interfacing / contacting a first pair of spaced-apart surface regions, respectively, of the silicon P+layer 530 at opposite sides of the integrated N+doped Ge region 242 at certain distances therefrom.

[0297] Fig. 19H shows an electronic device 500 generally similar to Fig. 19G but in which the semiconductor structure 150 further includes either one of a P+region 70A or a N+region 70B on top of the integrated N+doped Ge region 242, thereby forming with the integrated N+doped Ge region 242 either one of a P+N+diode or P+N+N+junction. The second contact of the second electrode includes a second pair of the second spaced- apart contacts EC2A and EC2B interfacing / contacting a second pair of spaced-apart top surface regions of the P+region 70A or the N+region 70B.

[0298] In the configurations of Figs. 19G and 19H, the metal electrodes design is all planar. In addition, the electrode on top of the Ge waveguide is split and set at the edges to reduce the optical losses.

[0299] It should be noted that the vertical-type (semi-vertical) configuration of the semiconductor structure of any of the examples described above can be implemented in any suitable geometry, e.g., closed loop structure such as ring-like structure. This depends inter alia on the specific application of the electronic device.

[0300] Various configurations of resonators and couplers can be integrated using vertical type (semi-vertical) configuration of the semiconductor structures of Figs. 18A to 18F and 19A to 19H, in which a planar cavity can be formed to support lasing at specific wavelengths. For the semi-vertical structures of Figs. 19A to 19H, there is an advantage of the Ge waveguide emitter being at the same planar level as the Si bus. This provides the ability to fully couple the emitted light to the bus with lesser optical losses.

[0301] The electronic devices based on the vertical and semi-vertical configurations of Figs. 18A - 18F and 19A - 19H can be used to perform any of the following: (i) broadband optical sources (e.g., Light Emitting Diode (LED); (ii) coherent light source (e.g., Laser); (iii) Single Photon (SP) light emitter; (iv) Optical Amplifier (OA); and (v) various passive / active components (waveguide, filters, modulators, etc.).

Claims

CLAIMS:

1. An electronic device comprising a semiconductor structure comprising a silicon device layer located on top of an insulator, said silicon device layer comprising: a first highly doped P+silicon region and a second highly doped N+region, which is spaced from the first highly doped P+silicon region by a first intrinsic region of the silicon device layer, and which comprises an integrated Ge-region at least partially embedded in the silicon device layer.

2. The electronic device according to claim 1, wherein said semiconductor structure further comprises a clad on top of the silicon device layer.

3. The electronic device according to claim 1 or 2, further comprising electric contacts of an electrode arrangement, said electric contacts comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region.

4. The electronic device according to any one of the preceding claims, wherein said integrated Ge region has one of the following configurations: is a substantially undoped region, is a relatively lightly N-doped region, is a highly doped N+region, and has a tensile and / or compressive stress.

5. The electronic device according to any one of the preceding claims, wherein said silicon device layer further comprises a second intrinsic region, and wherein the second region comprises a silicon region, being said highly doped N+region, and comprises said integrated Ge region which is separated from said highly doped N+region by said second intrinsic region, such that said first intrinsic region and said second intrinsic region are located at opposite sides of said integrated Ge region6. The electronic device according to claim 5, comprising electric contacts of an electrode arrangement, said electric contacts comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, said first intrinsic region and said second intrinsic region having a predetermined first length Si and a predetermined second length S2, respectively.

7. The electronic device according to claim 6, wherein said predetermined lengths Si and S2 are substantially the same.

8. The electronic device according to claim 6, wherein said predetermined lengths Si and S2 are different.

9. The electronic device according to anyone of claims 5 to 8, wherein said integrated Ge region is configured as substantially undoped or relatively lightly doped N, the device being therefore configured as a P+ININ+Si-Ge heterostructure.

10. The electronic device according to anyone of claims 5 to 8, wherein said integrated Ge region is configured as a highly doped N+region and / or having the tensile and / or compressive stress, the device being therefore configured as a P+IN+IN+Si-Ge heterostructure.

11. The electronic device according to anyone of claims 5 to 10, comprising electric contacts of an electrode arrangement, said electric contacts comprising first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, and a third contact of a second electrode, said third contact being associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer.

12. The electronic device according to claim 11, wherein said third contact directly interfaces a top surface of the integrated Ge region.

13. The electronic device according to claim 11, wherein said third contact is spaced from the integrated Ge region by a portion of the clad.

14. The electronic device according to any one of claims 11 to 13, wherein said third contact is configured as a split contact formed by first and second spaced-apart electrode elements of the second electrode aligned with opposite edges, respectively, of the integrated Ge region.

15. The electronic device according to claim 13, wherein said third contact is configured as a split contact formed by first and second spaced-apart electrode elements of the second electrode aligned with opposite edges, respectively, of the integrated Ge region, said portion of the clad comprising P+doped region and N+doped region aligned with, respectively, said opposite edges of the integrated Ge region, thereby forming with said integrated Ge region first P+N+junction and second N+N+junction, respectively.

16. The electronic device according to claim 13, wherein said portion of the clad comprises a P+doped region or a N+doped region, forming with said integrated Ge region a P+N+diode or N+N+junction, respectively.

17. The electronic device according to any one of claims 1 to 4, wherein said second region comprises said integrated Ge region being the highly doped N+Ge region, the device comprising electric contacts of an electrode arrangement, said electric contactscomprising first and second contacts of a first electrode being associated with, respectively, said first highly doped P+region and said integrated Ge region, thereby forming a P+IN+Si-Ge heterostructure operable as a diode.

18. The electronic device according to claim 17, wherein said second contact is located at least partially in a clad, extending on top of the silicon device layer, and being aligned with the integrated Ge region in a substantially symmetrical configuration with respect to said integrated Ge region, such that said second contact is substantially identically spaced from opposite edges of the integrated Ge region.

19. The electronic device according to claim 17, wherein said second contact is located at least partially in a clad, extending on top of the silicon device layer, and being aligned with the integrated Ge region in a substantially asymmetrical configuration with respect to edges of said integrated Ge region, such that second contact is aligned with an edge of the integrated Ge region further from said first intrinsic region.

20. The electronic device according to claim 18 or 19, wherein the second contact directly interfaces with said integrated Ge region.

21. The electronic device according to claim 18 or 19, wherein the second contact is spaced from said integrated Ge region by a portion of the clad.

22. The electronic device according to claim 21, wherein said portion of the clad comprises a P+doped region or a N+doped region, forming with said N+doped integrated Ge region a P+N+or N+N+junction, respectively.

23. The electronic device according to any one of the preceding claims, wherein the integrated Ge region is configured with one or more of the following characteristics: highly N+doping, tensile stress, and compressive stress, defining an energy band profile of the integrated Ge region.

24. The electronic device according to claim 23, wherein the energy band profile of the integrated Ge region provides direct gap light emission within the integrated Ge region upon application of an electric field via electric contacts comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region.

25. The electronic device according to claim 23, configured and operable as a broadband optical source device emitting light in a range of 1,400 - 13,000 nm.

26. The electronic device according to claim 23, further comprising a resonator located in a light propagating direction, confined within the integrated Ge region the device being operable as a coherent optical source device.

27. The electronic device according to 23, configured and operable as an optical amplifier by setting a voltage around a lasing threshold voltage applied to the semiconductor structure via electrical contacts thereby amplifying external light being coupled to the integrated Ge region.

28. The electronic device according to 23, configured and operable as an electroabsorption modulator.

29. The electronic device according to claim 24, wherein the electrodes arrangement further comprises a third contact of a second electrode being associated with the integrated Ge region and located on top thereof being at least partially in a clad on top of the silicon device layer, said second electrode being configured and operable as a thermo- optical electrode heater, inducing a change in refractive index of the integrated Ge region by induced heating, thereby affecting a power of said direct gap light emission at a specific wavelength.

30. The electronic device according to any one of claims 11 to 13, configured and operable as a photonic junction field-effect transistor (P-JFET) with the integrated Ge region operating as a gate.

31. The electronic device according to claim 14, configured and operable as a photonic junction field-effect transistor (P-JFET) with a gate on the integrated Ge region and independent carrier injection into the integrated Ge medium through said first and second electrode elements of the second electrode.

32. The electronic device according to claim 30 or 31 configured and operable as an optical amplifier.

33. The electronic device according to claim 30 or 31 configured and operable as a high-power light emitter by providing extra carriers via the second electrode.

34. The electronic device according to any one of claims 11 to 13, configured and operable to provide direct gap light emission within the integrated Ge region upon application of an electric field via the first and second electric contacts of the first electrode, the second electrode being configured and operable as a stress-inducing electrode on the integrated Ge region, thereby affecting an energy band gap of theintegrated Ge region, and thereby affecting one or more properties of light emission in the integrated Ge region.

35. The electronic device according to claim 34, wherein said second electrode comprises one or more of the following: a piezoelectric compound configured and operable to create stress under applied electrical power, Micro-Electro-Mechanical Systems (MEMS), polymers known to create stress under applied el ectri cal / optical power.

36. The electronic device according to any one of claims 11 to 13, configured and operable to provide direct gap light emission within the integrated Ge region upon application of an electric field via the first and second electric contacts of the first electrode, said second electrode being configured and operable as a thermo-electric- cooler (TEC), configured and operable to regulate a temperature within and in the vicinity of the integrated GE region.

37. The electronic device according to claim 5, wherein the integrated Ge region has at least one of the following configurations: a highly doped N+Ge region, has a tensile stress, has compressive stress affecting an energy band gap of the integrated Ge region, and wherein electric contacts of an electrode arrangement are provided comprising at least first and second contacts of a first electrode being associated with said first highly doped P+region and said N+region of the second region, said semiconductor structure being configured such that said integrated Ge region is fully embedded in the silicon device layer, and is operable as a channel waveguide for propagating light being confined within said integrated Ge region.

38. The electronic device according to claim 6, wherein said integrated Ge region is configured as an undoped or a relatively lightly doped N region, as compared to said highly doped N+region spaced from the integrated Ge region by the second intrinsic region, the device being operable as a photodetector.

39. An electronic device comprising a silicon device layer on an insulator, and an integrated Ge region at least partially embedded within a portion of said silicon device layer being enclosed between first and second intrinsic regions of said silicon device layer thereby forming a heterostructure Si-Ge waveguide.

40. An electronic device comprising a semiconductor structure comprising a silicon device layer located on top of an insulator, said silicon device layer comprising: a first highly doped P+silicon region and a second region which comprises a highly doped N+region, wherein said second region comprises an integrated Ge-region at least partially embedded in the silicon device layer such that at least a bottom surface of said integrated Ge-region forms an interface with an intrinsic region of the silicon device layer.

41. An electronic device comprising: a semiconductor structure comprising: a silicon P+layer, and a clad on top of the silicon P+layer, said clad comprising an integrated N+doped Ge region directly interfacing with a surface region of the silicon P+layer; and an electrode comprising an electrical contacts arrangement, at least one first contact of said electric contacts arrangement being associated with the silicon P+layer and at least one second contact of said electric contacts arrangement being associated with the integrated N+doped Ge region.

42. The electronic device according to claim 41, wherein said electrical contacts arrangement comprises a pair of spaced-apart first contacts of the electrode contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact contacting a top surface of the integrated N+doped Ge region.

43. The electronic device according to claim 41, wherein: said semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+P+diode or P+N+N+junction; and said electrical contacts arrangement comprises a pair of spaced-apart first contacts of the electrode contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom, and said at least second contact of contacting a top surface of the P+doped region or the N+doped region.

44. The electronic device according to claim 41, wherein said electrical contacts arrangement comprises a first pair of spaced-apart first contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprises a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

45. The electronic device according to claim 41, wherein:said semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+P+ diode or P+N+N+junction; and said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact of comprises a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the P+doped region or the N+doped region.

46. The electronic device according to claim 41, wherein said electrical contacts arrangement comprises: said at least one first contact extending along a bottom surface of the silicon P+layer; and said second contact of said electric contacts arrangement comprising a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

47. The electronic device according to claim 41, wherein: said semiconductor structure further comprises a P+doped region or a N+doped region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: said at least one first contact extending along a bottom surface of the silicon P+layer; and said second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced- apart top surface regions of the P+doped region or the N+doped region.

48. An electronic device comprising: a semiconductor structure comprising: a silicon P+layer, and a clad on top of the silicon P+layer, said silicon P+layer comprising an integrated N+doped Ge region embedded in said silicon P+layer; and an electrode comprising an electrical contacts arrangement, at least one first contact of said electrical contact arrangement associated with the silicon P+layer and at least one second contact of said electrical contacts arrangement associated with the integrated N+doped Ge region.

49. The electronic device according to claim 48, wherein:said electrical contacts arrangement comprises: a pair of spaced-apart contacts of the at least one first contact at least partially embedded in the clad and contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact at least partially embedded in the clad and contacting a top surface of the integrated N+doped Ge region.

50. The electronic device according to claim 48, wherein: said semiconductor structure further comprises either one of a P+region or an N+region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises a pair of spaced-apart contacts of the at least one first contact at least partially embedded in the clad and contacting a pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said second contact contacting a top surface of either one of the P+region or the N+region.

51. The electronic device according to claim 48, wherein said electrical contacts arrangement comprises: the at least one first contact contacting a bottom surface of said silicon P+layer; and the at least one second contact contacting a top surface of the integrated N+doped Ge region.

52. The electronic device according to claim 48, wherein: said semiconductor structure further comprises either one of a P+region or an N+region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: the at least one first contact of the contacting a bottom surface of said silicon P+layer; and the at least one second contact of the second electrode contacting a top surface of said either one of the silicon / polysilicon P+region or the silicon / polysilicon N+region.

53. The electronic device according to claim 48, wherein said electrical contacts arrangement comprises: said at least one first contact comprising the first contact extending along a bottom surface of the silicon P+layer; andsaid at least one second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the integrated N+doped Ge region.

54. The electronic device according to claim 48, wherein: said semiconductor structure further comprises a pair of spaced apart doped regions embedded in the clad and interfacing with a pair of spaced-apart top regions of said integrated N+doped Ge region, each of said pair of the doped regions being configured as a P+region or as an N+region, thereby forming with said integrated N+doped Ge region a pair of P+N+diodes or a pair of P+N+N+junctions; and said electrical contacts arrangement comprises: said at least one first contact of comprising the first contact extending along a bottom surface of the silicon P+layer; and said at least one second contact comprising a pair of spaced-apart contacts contacting said pair of the spaced-apart doped regions.

55. The electronic device according to claim 48, wherein said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprises a second pair of spaced-apart contacts contacting a second pair of space-apart top surface regions of the integrated N+doped Ge region.

56. The electronic device according to claim 48, wherein: said semiconductor structure further comprises either one of a silicon / poly silicon P+region or a silicon / poly silicon N+region on top of said integrated N+doped Ge region, thereby forming with said integrated N+doped Ge region either one of a P+N+diode or P+N+N+junction; and said electrical contacts arrangement comprises: a first pair of spaced-apart contacts of the electrode contacting a first pair of spaced-apart surface regions, respectively, of said silicon P+layer at opposite sides of said integrated N+doped Ge region at certain distances therefrom; and said at least one second contact comprising a second pair of spaced-apart contacts contacting a second pair of spaced-apart top surface regions of the silicon / poly silicon P+region or the silicon / poly silicon N+region.

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